NAND: Add 16bit NAND support for the NDFC

This patch adds support for 16 bit NAND devices attached to the NDFC on ppc4xx processors. Two config entries were added: CONFIG_SYS_NDFC_16 - Setting this tells the NDFC that a 16 bit device is attached. CONFIG_SYS_NDFC_EBC0_CFG - This is for the External Bus Controller configuration register. Also, a new ndfc_read_byte() function was added which does not first convert the data to little endian. The NAND SPL was also modified to do 16bit bad block testing when a 16 bit chip is being used. Signed-off-by: Alex Waterman <awaterman@dawning.com> Signed-off-by: Scott Wood <scottwood@freescale.com>

NAND: Add 16bit NAND support for the NDFC
This patch adds support for 16 bit NAND devices attached to the NDFC on ppc4xx processors. Two config entries were added: CONFIG_SYS_NDFC_16 - Setting this tells the NDFC that a 16 bit device is attached. CONFIG_SYS_NDFC_EBC0_CFG - This is for the External Bus Controller configuration register. Also, a new ndfc_read_byte() function was added which does not first convert the data to little endian. The NAND SPL was also modified to do 16bit bad block testing when a 16 bit chip is being used. Signed-off-by: Alex Waterman <awaterman@dawning.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Alex Waterman · Scott Wood
1 parent c9494866df
Showing 3 changed files with 45 additions and 7 deletions Side-by-side Diff
README
drivers/mtd/nand/ndfc.c
nand_spl/nand_boot.c
@@ -2917,6 +2917,14 @@
 - CONFIG_SYS_SRIOn_MEM_SIZE:
 		Size of SRIO port 'n' memory region
  
+- CONFIG_SYS_NDFC_16
+		Defined to tell the NDFC that the NAND chip is using a
+		16 bit bus.
+
+- CONFIG_SYS_NDFC_EBC0_CFG
+		Sets the EBC0_CFG register for the NDFC. If not defined
+		a default value will be used.
+
 - CONFIG_SPD_EEPROM
 		Get DDR timing information from an I2C EEPROM. Common
 		with pluggable memory modules such as SODIMMs
@@ -37,6 +37,13 @@
 #include <asm/io.h>
 #include <asm/ppc4xx.h>
  
+#ifndef CONFIG_SYS_NAND_BCR
+#define CONFIG_SYS_NAND_BCR 0x80002222
+#endif
+#ifndef CONFIG_SYS_NDFC_EBC0_CFG
+#define CONFIG_SYS_NDFC_EBC0_CFG 0xb8400000
+#endif
+
 /*
  * We need to store the info, which chip-select (CS) is used for the
  * chip number. For example on Sequoia NAND chip #0 uses
  
  
@@ -140,12 +147,25 @@
  
 	return 0;
 }
-#endif /* #ifndef CONFIG_NAND_SPL */
  
-#ifndef CONFIG_SYS_NAND_BCR
-#define CONFIG_SYS_NAND_BCR 0x80002222
+/*
+ * Read a byte from the NDFC.
+ */
+static uint8_t ndfc_read_byte(struct mtd_info *mtd)
+{
+
+	struct nand_chip *chip = mtd->priv;
+
+#ifdef CONFIG_SYS_NDFC_16BIT
+	return (uint8_t) readw(chip->IO_ADDR_R);
+#else
+	return readb(chip->IO_ADDR_R);
 #endif
  
+}
+
+#endif /* #ifndef CONFIG_NAND_SPL */
+
 void board_nand_select_device(struct nand_chip *nand, int chip)
 {
 	/*
  
  
@@ -198,16 +218,21 @@
 	nand->ecc.bytes = 3;
 	nand->select_chip = ndfc_select_chip;
  
+#ifdef CONFIG_SYS_NDFC_16BIT
+	nand->options |= NAND_BUSWIDTH_16;
+#endif
+
 #ifndef CONFIG_NAND_SPL
 	nand->write_buf  = ndfc_write_buf;
 	nand->verify_buf = ndfc_verify_buf;
+	nand->read_byte = ndfc_read_byte;
  
 	chip++;
 #else
 	/*
 	 * Setup EBC (CS0 only right now)
 	 */
-	mtebc(EBC0_CFG, 0xb8400000);
+	mtebc(EBC0_CFG, CONFIG_SYS_NDFC_EBC0_CFG);
  
 	mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR);
 	mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP);
@@ -122,10 +122,15 @@
 	nand_command(mtd, block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
  
 	/*
-	 * Read one byte
+	 * Read one byte (or two if it's a 16 bit chip).
 	 */
-	if (readb(this->IO_ADDR_R) != 0xff)
-		return 1;
+	if (this->options & NAND_BUSWIDTH_16) {
+		if (readw(this->IO_ADDR_R) != 0xffff)
+			return 1;
+	} else {
+		if (readb(this->IO_ADDR_R) != 0xff)
+			return 1;
+	}
  
 	return 0;
 }
...	...	@@ -2917,6 +2917,14 @@
2917	2917	- CONFIG_SYS_SRIOn_MEM_SIZE:
2918	2918	Size of SRIO port 'n' memory region
2919	2919
	2920	+- CONFIG_SYS_NDFC_16
	2921	+ Defined to tell the NDFC that the NAND chip is using a
	2922	+ 16 bit bus.
	2923	+
	2924	+- CONFIG_SYS_NDFC_EBC0_CFG
	2925	+ Sets the EBC0_CFG register for the NDFC. If not defined
	2926	+ a default value will be used.
	2927	+
2920	2928	- CONFIG_SPD_EEPROM
2921	2929	Get DDR timing information from an I2C EEPROM. Common
2922	2930	with pluggable memory modules such as SODIMMs
...	...	@@ -37,6 +37,13 @@
37	37	#include <asm/io.h>
38	38	#include <asm/ppc4xx.h>
39	39
	40	+#ifndef CONFIG_SYS_NAND_BCR
	41	+#define CONFIG_SYS_NAND_BCR 0x80002222
	42	+#endif
	43	+#ifndef CONFIG_SYS_NDFC_EBC0_CFG
	44	+#define CONFIG_SYS_NDFC_EBC0_CFG 0xb8400000
	45	+#endif
	46	+
40	47	/*
41	48	* We need to store the info, which chip-select (CS) is used for the
42	49	* chip number. For example on Sequoia NAND chip #0 uses
43	50
44	51
...	...	@@ -140,12 +147,25 @@
140	147
141	148	return 0;
142	149	}
143		-#endif /* #ifndef CONFIG_NAND_SPL */
144	150
145		-#ifndef CONFIG_SYS_NAND_BCR
146		-#define CONFIG_SYS_NAND_BCR 0x80002222
	151	+/*
	152	+ * Read a byte from the NDFC.
	153	+ */
	154	+static uint8_t ndfc_read_byte(struct mtd_info *mtd)
	155	+{
	156	+
	157	+ struct nand_chip *chip = mtd->priv;
	158	+
	159	+#ifdef CONFIG_SYS_NDFC_16BIT
	160	+ return (uint8_t) readw(chip->IO_ADDR_R);
	161	+#else
	162	+ return readb(chip->IO_ADDR_R);
147	163	#endif
148	164
	165	+}
	166	+
	167	+#endif /* #ifndef CONFIG_NAND_SPL */
	168	+
149	169	void board_nand_select_device(struct nand_chip *nand, int chip)
150	170	{
151	171	/*
152	172
153	173
...	...	@@ -198,16 +218,21 @@
198	218	nand->ecc.bytes = 3;
199	219	nand->select_chip = ndfc_select_chip;
200	220
	221	+#ifdef CONFIG_SYS_NDFC_16BIT
	222	+ nand->options \|= NAND_BUSWIDTH_16;
	223	+#endif
	224	+
201	225	#ifndef CONFIG_NAND_SPL
202	226	nand->write_buf = ndfc_write_buf;
203	227	nand->verify_buf = ndfc_verify_buf;
	228	+ nand->read_byte = ndfc_read_byte;
204	229
205	230	chip++;
206	231	#else
207	232	/*
208	233	* Setup EBC (CS0 only right now)
209	234	*/
210		- mtebc(EBC0_CFG, 0xb8400000);
	235	+ mtebc(EBC0_CFG, CONFIG_SYS_NDFC_EBC0_CFG);
211	236
212	237	mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR);
213	238	mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP);
...	...	@@ -122,10 +122,15 @@
122	122	nand_command(mtd, block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
123	123
124	124	/*
125		- * Read one byte
	125	+ * Read one byte (or two if it's a 16 bit chip).
126	126	*/
127		- if (readb(this->IO_ADDR_R) != 0xff)
128		- return 1;
	127	+ if (this->options & NAND_BUSWIDTH_16) {
	128	+ if (readw(this->IO_ADDR_R) != 0xffff)
	129	+ return 1;
	130	+ } else {
	131	+ if (readb(this->IO_ADDR_R) != 0xff)
	132	+ return 1;
	133	+ }
129	134
130	135	return 0;
131	136	}