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Commit ed247f487e603512f5901f2cec25db018649c05e

Authored by wdenk 2002-10-08 05:58:02 +0800

1 parent 324f6cfd12

Exists in master and in 54 other branches

Initial revision

Showing 4 changed files with 1395 additions and 0 deletions Side-by-side Diff

board/netvia/config.mk
board/netvia/flash.c
cpu/mpc8xx/scc.c
include/flash.h

board/netvia/config.mk

Diff comments View file @ ed247f4

	1	+#
	2	+# (C) Copyright 2000
	3	+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+#
	5	+# See file CREDITS for list of people who contributed to this
	6	+# project.
	7	+#
	8	+# This program is free software; you can redistribute it and/or
	9	+# modify it under the terms of the GNU General Public License as
	10	+# published by the Free Software Foundation; either version 2 of
	11	+# the License, or (at your option) any later version.
	12	+#
	13	+# This program is distributed in the hope that it will be useful,
	14	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+# GNU General Public License for more details.
	17	+#
	18	+# You should have received a copy of the GNU General Public License
	19	+# along with this program; if not, write to the Free Software
	20	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+# MA 02111-1307 USA
	22	+#
	23	+
	24	+#
	25	+# netVia Boards
	26	+#
	27	+
	28	+TEXT_BASE = 0x40000000

board/netvia/flash.c

Diff comments View file @ ed247f4

	1	+/*
	2	+ * (C) Copyright 2000
	3	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+#include <common.h>
	25	+#include <mpc8xx.h>
	26	+
	27	+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
	28	+
	29	+/*-----------------------------------------------------------------------
	30	+ * Functions
	31	+ */
	32	+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
	33	+static int write_byte(flash_info_t * info, ulong dest, uchar data);
	34	+static void flash_get_offsets(ulong base, flash_info_t * info);
	35	+
	36	+/*-----------------------------------------------------------------------
	37	+ */
	38	+
	39	+unsigned long flash_init(void)
	40	+{
	41	+ volatile immap_t immap = (immap_t ) CFG_IMMR;
	42	+ volatile memctl8xx_t *memctl = &immap->im_memctl;
	43	+ unsigned long size;
	44	+ int i;
	45	+
	46	+ /* Init: no FLASHes known */
	47	+ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
	48	+ flash_info[i].flash_id = FLASH_UNKNOWN;
	49	+ }
	50	+
	51	+ /* Static FLASH Bank configuration here - FIXME XXX */
	52	+
	53	+ size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
	54	+
	55	+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
	56	+ printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size, size << 20);
	57	+ }
	58	+
	59	+ /* Remap FLASH according to real size */
	60	+ memctl->memc_or0 = CFG_OR_TIMING_FLASH \| (-size & 0xFFFF8000);
	61	+ memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) \| (memctl->memc_br0 & ~(BR_BA_MSK));
	62	+
	63	+ /* Re-do sizing to get full correct info */
	64	+ size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]);
	65	+
	66	+ flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]);
	67	+
	68	+ /* monitor protection ON by default */
	69	+ flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE, CFG_FLASH_BASE + CFG_MONITOR_LEN - 1, &flash_info[0]);
	70	+
	71	+ flash_info[0].size = size;
	72	+
	73	+ return (size);
	74	+}
	75	+
	76	+/*-----------------------------------------------------------------------
	77	+ */
	78	+static void flash_get_offsets(ulong base, flash_info_t * info)
	79	+{
	80	+ int i;
	81	+
	82	+ /* set up sector start address table */
	83	+ if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
	84	+ for (i = 0; i < info->sector_count; i++) {
	85	+ info->start[i] = base + (i * 0x00010000);
	86	+ }
	87	+ } else if (info->flash_id & FLASH_BTYPE) {
	88	+ /* set sector offsets for bottom boot block type */
	89	+ info->start[0] = base + 0x00000000;
	90	+ info->start[1] = base + 0x00004000;
	91	+ info->start[2] = base + 0x00006000;
	92	+ info->start[3] = base + 0x00008000;
	93	+ for (i = 4; i < info->sector_count; i++) {
	94	+ info->start[i] = base + (i * 0x00010000) - 0x00030000;
	95	+ }
	96	+ } else {
	97	+ /* set sector offsets for top boot block type */
	98	+ i = info->sector_count - 1;
	99	+ info->start[i--] = base + info->size - 0x00004000;
	100	+ info->start[i--] = base + info->size - 0x00006000;
	101	+ info->start[i--] = base + info->size - 0x00008000;
	102	+ for (; i >= 0; i--) {
	103	+ info->start[i] = base + i * 0x00010000;
	104	+ }
	105	+ }
	106	+
	107	+}
	108	+
	109	+/*-----------------------------------------------------------------------
	110	+ */
	111	+void flash_print_info(flash_info_t * info)
	112	+{
	113	+ int i;
	114	+
	115	+ if (info->flash_id == FLASH_UNKNOWN) {
	116	+ printf("missing or unknown FLASH type\n");
	117	+ return;
	118	+ }
	119	+
	120	+ switch (info->flash_id & FLASH_VENDMASK) {
	121	+ case FLASH_MAN_AMD:
	122	+ printf("AMD ");
	123	+ break;
	124	+ case FLASH_MAN_FUJ:
	125	+ printf("FUJITSU ");
	126	+ break;
	127	+ case FLASH_MAN_MX:
	128	+ printf("MXIC ");
	129	+ break;
	130	+ default:
	131	+ printf("Unknown Vendor ");
	132	+ break;
	133	+ }
	134	+
	135	+ switch (info->flash_id & FLASH_TYPEMASK) {
	136	+ case FLASH_AM040:
	137	+ printf("AM29LV040B (4 Mbit, bottom boot sect)\n");
	138	+ break;
	139	+ case FLASH_AM400B:
	140	+ printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
	141	+ break;
	142	+ case FLASH_AM400T:
	143	+ printf("AM29LV400T (4 Mbit, top boot sector)\n");
	144	+ break;
	145	+ case FLASH_AM800B:
	146	+ printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
	147	+ break;
	148	+ case FLASH_AM800T:
	149	+ printf("AM29LV800T (8 Mbit, top boot sector)\n");
	150	+ break;
	151	+ case FLASH_AM160B:
	152	+ printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
	153	+ break;
	154	+ case FLASH_AM160T:
	155	+ printf("AM29LV160T (16 Mbit, top boot sector)\n");
	156	+ break;
	157	+ case FLASH_AM320B:
	158	+ printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
	159	+ break;
	160	+ case FLASH_AM320T:
	161	+ printf("AM29LV320T (32 Mbit, top boot sector)\n");
	162	+ break;
	163	+ default:
	164	+ printf("Unknown Chip Type\n");
	165	+ break;
	166	+ }
	167	+
	168	+ printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
	169	+
	170	+ printf(" Sector Start Addresses:");
	171	+ for (i = 0; i < info->sector_count; ++i) {
	172	+ if ((i % 5) == 0)
	173	+ printf("\n ");
	174	+ printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " ");
	175	+ }
	176	+ printf("\n");
	177	+}
	178	+
	179	+/*-----------------------------------------------------------------------
	180	+ */
	181	+
	182	+
	183	+/*-----------------------------------------------------------------------
	184	+ */
	185	+
	186	+/*
	187	+ * The following code cannot be run from FLASH!
	188	+ */
	189	+
	190	+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
	191	+{
	192	+ short i;
	193	+ uchar mid;
	194	+ uchar pid;
	195	+ vu_char caddr = (vu_char ) addr;
	196	+ ulong base = (ulong) addr;
	197	+
	198	+
	199	+ /* Write auto select command: read Manufacturer ID */
	200	+ caddr[0x0555] = 0xAA;
	201	+ caddr[0x02AA] = 0x55;
	202	+ caddr[0x0555] = 0x90;
	203	+
	204	+ mid = caddr[0];
	205	+ switch (mid) {
	206	+ case (AMD_MANUFACT & 0xFF):
	207	+ info->flash_id = FLASH_MAN_AMD;
	208	+ break;
	209	+ case (FUJ_MANUFACT & 0xFF):
	210	+ info->flash_id = FLASH_MAN_FUJ;
	211	+ break;
	212	+ case (MX_MANUFACT & 0xFF):
	213	+ info->flash_id = FLASH_MAN_MX;
	214	+ break;
	215	+ case (STM_MANUFACT & 0xFF):
	216	+ info->flash_id = FLASH_MAN_STM;
	217	+ break;
	218	+ default:
	219	+ info->flash_id = FLASH_UNKNOWN;
	220	+ info->sector_count = 0;
	221	+ info->size = 0;
	222	+ return (0); /* no or unknown flash */
	223	+ }
	224	+
	225	+ pid = caddr[1]; /* device ID */
	226	+ switch (pid) {
	227	+ case (AMD_ID_LV400T & 0xFF):
	228	+ info->flash_id += FLASH_AM400T;
	229	+ info->sector_count = 11;
	230	+ info->size = 0x00080000;
	231	+ break; /* => 512 kB */
	232	+
	233	+ case (AMD_ID_LV400B & 0xFF):
	234	+ info->flash_id += FLASH_AM400B;
	235	+ info->sector_count = 11;
	236	+ info->size = 0x00080000;
	237	+ break; /* => 512 kB */
	238	+
	239	+ case (AMD_ID_LV800T & 0xFF):
	240	+ info->flash_id += FLASH_AM800T;
	241	+ info->sector_count = 19;
	242	+ info->size = 0x00100000;
	243	+ break; /* => 1 MB */
	244	+
	245	+ case (AMD_ID_LV800B & 0xFF):
	246	+ info->flash_id += FLASH_AM800B;
	247	+ info->sector_count = 19;
	248	+ info->size = 0x00100000;
	249	+ break; /* => 1 MB */
	250	+
	251	+ case (AMD_ID_LV160T & 0xFF):
	252	+ info->flash_id += FLASH_AM160T;
	253	+ info->sector_count = 35;
	254	+ info->size = 0x00200000;
	255	+ break; /* => 2 MB */
	256	+
	257	+ case (AMD_ID_LV160B & 0xFF):
	258	+ info->flash_id += FLASH_AM160B;
	259	+ info->sector_count = 35;
	260	+ info->size = 0x00200000;
	261	+ break; /* => 2 MB */
	262	+
	263	+ case (AMD_ID_LV040B & 0xFF):
	264	+ info->flash_id += FLASH_AM040;
	265	+ info->sector_count = 8;
	266	+ info->size = 0x00080000;
	267	+ break;
	268	+
	269	+ case (STM_ID_M29W040B & 0xFF):
	270	+ info->flash_id += FLASH_AM040;
	271	+ info->sector_count = 8;
	272	+ info->size = 0x00080000;
	273	+ break;
	274	+
	275	+#if 0 /* enable when device IDs are available */
	276	+ case (AMD_ID_LV320T & 0xFF):
	277	+ info->flash_id += FLASH_AM320T;
	278	+ info->sector_count = 67;
	279	+ info->size = 0x00400000;
	280	+ break; /* => 4 MB */
	281	+
	282	+ case (AMD_ID_LV320B & 0xFF):
	283	+ info->flash_id += FLASH_AM320B;
	284	+ info->sector_count = 67;
	285	+ info->size = 0x00400000;
	286	+ break; /* => 4 MB */
	287	+#endif
	288	+ default:
	289	+ info->flash_id = FLASH_UNKNOWN;
	290	+ return (0); /* => no or unknown flash */
	291	+
	292	+ }
	293	+
	294	+ printf(" ");
	295	+ /* set up sector start address table */
	296	+ if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
	297	+ for (i = 0; i < info->sector_count; i++) {
	298	+ info->start[i] = base + (i * 0x00010000);
	299	+ }
	300	+ } else if (info->flash_id & FLASH_BTYPE) {
	301	+ /* set sector offsets for bottom boot block type */
	302	+ info->start[0] = base + 0x00000000;
	303	+ info->start[1] = base + 0x00004000;
	304	+ info->start[2] = base + 0x00006000;
	305	+ info->start[3] = base + 0x00008000;
	306	+ for (i = 4; i < info->sector_count; i++) {
	307	+ info->start[i] = base + (i * 0x00010000) - 0x00030000;
	308	+ }
	309	+ } else {
	310	+ /* set sector offsets for top boot block type */
	311	+ i = info->sector_count - 1;
	312	+ info->start[i--] = base + info->size - 0x00004000;
	313	+ info->start[i--] = base + info->size - 0x00006000;
	314	+ info->start[i--] = base + info->size - 0x00008000;
	315	+ for (; i >= 0; i--) {
	316	+ info->start[i] = base + i * 0x00010000;
	317	+ }
	318	+ }
	319	+
	320	+ /* check for protected sectors */
	321	+ for (i = 0; i < info->sector_count; i++) {
	322	+ /* read sector protection: D0 = 1 if protected */
	323	+ caddr = (volatile unsigned char *)(info->start[i]);
	324	+ info->protect[i] = caddr[2] & 1;
	325	+ }
	326	+
	327	+ /*
	328	+ * Prevent writes to uninitialized FLASH.
	329	+ */
	330	+ if (info->flash_id != FLASH_UNKNOWN) {
	331	+ caddr = (vu_char *) info->start[0];
	332	+
	333	+ caddr[0x0555] = 0xAA;
	334	+ caddr[0x02AA] = 0x55;
	335	+ caddr[0x0555] = 0xF0;
	336	+
	337	+ udelay(20000);
	338	+ }
	339	+
	340	+ return (info->size);
	341	+}
	342	+
	343	+
	344	+/*-----------------------------------------------------------------------
	345	+ */
	346	+
	347	+int flash_erase(flash_info_t * info, int s_first, int s_last)
	348	+{
	349	+ vu_char addr = (vu_char ) (info->start[0]);
	350	+ int flag, prot, sect, l_sect;
	351	+ ulong start, now, last;
	352	+
	353	+ if ((s_first < 0) \|\| (s_first > s_last)) {
	354	+ if (info->flash_id == FLASH_UNKNOWN) {
	355	+ printf("- missing\n");
	356	+ } else {
	357	+ printf("- no sectors to erase\n");
	358	+ }
	359	+ return 1;
	360	+ }
	361	+
	362	+ if ((info->flash_id == FLASH_UNKNOWN) \|\|
	363	+ (info->flash_id > FLASH_AMD_COMP)) {
	364	+ printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
	365	+ return 1;
	366	+ }
	367	+
	368	+ prot = 0;
	369	+ for (sect = s_first; sect <= s_last; ++sect) {
	370	+ if (info->protect[sect]) {
	371	+ prot++;
	372	+ }
	373	+ }
	374	+
	375	+ if (prot) {
	376	+ printf("- Warning: %d protected sectors will not be erased!\n", prot);
	377	+ } else {
	378	+ printf("\n");
	379	+ }
	380	+
	381	+ l_sect = -1;
	382	+
	383	+ /* Disable interrupts which might cause a timeout here */
	384	+ flag = disable_interrupts();
	385	+
	386	+ addr[0x0555] = 0xAA;
	387	+ addr[0x02AA] = 0x55;
	388	+ addr[0x0555] = 0x80;
	389	+ addr[0x0555] = 0xAA;
	390	+ addr[0x02AA] = 0x55;
	391	+
	392	+ /* Start erase on unprotected sectors */
	393	+ for (sect = s_first; sect <= s_last; sect++) {
	394	+ if (info->protect[sect] == 0) { /* not protected */
	395	+ addr = (vu_char *) (info->start[sect]);
	396	+ addr[0] = 0x30;
	397	+ l_sect = sect;
	398	+ }
	399	+ }
	400	+
	401	+ /* re-enable interrupts if necessary */
	402	+ if (flag)
	403	+ enable_interrupts();
	404	+
	405	+ /* wait at least 80us - let's wait 1 ms */
	406	+ udelay(1000);
	407	+
	408	+ /*
	409	+ * We wait for the last triggered sector
	410	+ */
	411	+ if (l_sect < 0)
	412	+ goto DONE;
	413	+
	414	+ start = get_timer(0);
	415	+ last = start;
	416	+ addr = (vu_char *) (info->start[l_sect]);
	417	+ while ((addr[0] & 0x80) != 0x80) {
	418	+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
	419	+ printf("Timeout\n");
	420	+ return 1;
	421	+ }
	422	+ /* show that we're waiting */
	423	+ if ((now - last) > 1000) { /* every second */
	424	+ putc('.');
	425	+ last = now;
	426	+ }
	427	+ }
	428	+
	429	+ DONE:
	430	+ /* reset to read mode */
	431	+ addr = (vu_char *) info->start[0];
	432	+ addr[0] = 0xF0; /* reset bank */
	433	+
	434	+ printf(" done\n");
	435	+ return 0;
	436	+}
	437	+
	438	+/*-----------------------------------------------------------------------
	439	+ * Copy memory to flash, returns:
	440	+ * 0 - OK
	441	+ * 1 - write timeout
	442	+ * 2 - Flash not erased
	443	+ */
	444	+
	445	+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
	446	+{
	447	+ int rc;
	448	+
	449	+ while (cnt > 0) {
	450	+ if ((rc = write_byte(info, addr++, *src++)) != 0) {
	451	+ return (rc);
	452	+ }
	453	+ --cnt;
	454	+ }
	455	+
	456	+ return (0);
	457	+}
	458	+
	459	+/*-----------------------------------------------------------------------
	460	+ * Write a word to Flash, returns:
	461	+ * 0 - OK
	462	+ * 1 - write timeout
	463	+ * 2 - Flash not erased
	464	+ */
	465	+static int write_byte(flash_info_t * info, ulong dest, uchar data)
	466	+{
	467	+ vu_char addr = (vu_char ) (info->start[0]);
	468	+ ulong start;
	469	+ int flag;
	470	+
	471	+ /* Check if Flash is (sufficiently) erased */
	472	+ if ((((vu_char ) dest) & data) != data) {
	473	+ return (2);
	474	+ }
	475	+ /* Disable interrupts which might cause a timeout here */
	476	+ flag = disable_interrupts();
	477	+
	478	+ addr[0x0555] = 0xAA;
	479	+ addr[0x02AA] = 0x55;
	480	+ addr[0x0555] = 0xA0;
	481	+
	482	+ ((vu_char ) dest) = data;
	483	+
	484	+ /* re-enable interrupts if necessary */
	485	+ if (flag)
	486	+ enable_interrupts();
	487	+
	488	+ /* data polling for D7 */
	489	+ start = get_timer(0);
	490	+ while ((((vu_char ) dest) & 0x80) != (data & 0x80)) {
	491	+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
	492	+ return (1);
	493	+ }
	494	+ }
	495	+ return (0);
	496	+}
	497	+
	498	+/*-----------------------------------------------------------------------
	499	+ */

cpu/mpc8xx/scc.c

Diff comments View file @ ed247f4

	1	+/*
	2	+ * File: scc.c
	3	+ * Description:
	4	+ * Basic ET HW initialization and packet RX/TX routines
	5	+ *
	6	+ * NOTE <<<IMPORTANT: PLEASE READ>>>:
	7	+ * Do not cache Rx/Tx buffers!
	8	+ */
	9	+
	10	+/*
	11	+ * MPC823 <-> MC68160 Connections:
	12	+ *
	13	+ * Setup MPC823 to work with MC68160 Enhanced Ethernet
	14	+ * Serial Tranceiver as follows:
	15	+ *
	16	+ * MPC823 Signal MC68160 Comments
	17	+ * ------ ------ ------- --------
	18	+ * PA-12 ETHTX --------> TX Eth. Port Transmit Data
	19	+ * PB-18 E_TENA --------> TENA Eth. Transmit Port Enable
	20	+ * PA-5 ETHTCK <-------- TCLK Eth. Port Transmit Clock
	21	+ * PA-13 ETHRX <-------- RX Eth. Port Receive Data
	22	+ * PC-8 E_RENA <-------- RENA Eth. Receive Enable
	23	+ * PA-6 ETHRCK <-------- RCLK Eth. Port Receive Clock
	24	+ * PC-9 E_CLSN <-------- CLSN Eth. Port Collision Indication
	25	+ *
	26	+ * FADS Board Signal MC68160 Comments
	27	+ * ----------------- ------- --------
	28	+ * (BCSR1) ETHEN* --------> CS2 Eth. Port Enable
	29	+ * (BSCR4) TPSQEL* --------> TPSQEL Twisted Pair Signal Quality Error Test Enable
	30	+ * (BCSR4) TPFLDL* --------> TPFLDL Twisted Pair Full-Duplex
	31	+ * (BCSR4) ETHLOOP --------> LOOP Eth. Port Diagnostic Loop-Back
	32	+ *
	33	+ */
	34	+
	35	+#include <common.h>
	36	+#include <malloc.h>
	37	+#include <commproc.h>
	38	+#include <net.h>
	39	+#include <command.h>
	40	+
	41	+#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(SCC_ENET)
	42	+
	43	+/* Ethernet Transmit and Receive Buffers */
	44	+#define DBUF_LENGTH 1520
	45	+
	46	+#define TX_BUF_CNT 2
	47	+
	48	+#define TOUT_LOOP 100
	49	+
	50	+static char txbuf[DBUF_LENGTH];
	51	+
	52	+static uint rxIdx; /* index of the current RX buffer */
	53	+static uint txIdx; /* index of the current TX buffer */
	54	+
	55	+/*
	56	+ * SCC Ethernet Tx and Rx buffer descriptors allocated at the
	57	+ * immr->udata_bd address on Dual-Port RAM
	58	+ * Provide for Double Buffering
	59	+ */
	60	+
	61	+typedef volatile struct CommonBufferDescriptor {
	62	+ cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
	63	+ cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
	64	+} RTXBD;
	65	+
	66	+static RTXBD *rtx;
	67	+
	68	+static int scc_send(struct eth_device* dev, volatile void *packet, int length);
	69	+static int scc_recv(struct eth_device* dev);
	70	+static int scc_init (struct eth_device* dev, bd_t * bd);
	71	+static void scc_halt(struct eth_device* dev);
	72	+
	73	+int scc_initialize(bd_t *bis)
	74	+{
	75	+ struct eth_device* dev;
	76	+
	77	+ dev = (struct eth_device) malloc(sizeof dev);
	78	+
	79	+ sprintf(dev->name, "SCC ETHERNET");
	80	+ dev->iobase = 0;
	81	+ dev->priv = 0;
	82	+ dev->init = scc_init;
	83	+ dev->halt = scc_halt;
	84	+ dev->send = scc_send;
	85	+ dev->recv = scc_recv;
	86	+
	87	+ eth_register(dev);
	88	+
	89	+ return 1;
	90	+}
	91	+
	92	+static int scc_send(struct eth_device* dev, volatile void *packet, int length)
	93	+{
	94	+ int i, j=0;
	95	+#if 0
	96	+ volatile char in, out;
	97	+#endif
	98	+
	99	+ /* section 16.9.23.3
	100	+ * Wait for ready
	101	+ */
	102	+#if 0
	103	+ while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY);
	104	+ out = (char *)(rtx->txbd[txIdx].cbd_bufaddr);
	105	+ in = packet;
	106	+ for(i = 0; i < length; i++) {
	107	+ out++ = in++;
	108	+ }
	109	+ rtx->txbd[txIdx].cbd_datlen = length;
	110	+ rtx->txbd[txIdx].cbd_sc \|= (BD_ENET_TX_READY \| BD_ENET_TX_LAST);
	111	+ while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) j++;
	112	+
	113	+#ifdef ET_DEBUG
	114	+ printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc);
	115	+#endif
	116	+ i = (rtx->txbd[txIdx++].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */;
	117	+
	118	+ /* wrap around buffer index when necessary */
	119	+ if (txIdx >= TX_BUF_CNT) txIdx = 0;
	120	+#endif
	121	+
	122	+ while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
	123	+ udelay (1); /* will also trigger Wd if needed */
	124	+ j++;
	125	+ }
	126	+ if (j>=TOUT_LOOP) printf("TX not ready\n");
	127	+ rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
	128	+ rtx->txbd[txIdx].cbd_datlen = length;
	129	+ rtx->txbd[txIdx].cbd_sc \|= (BD_ENET_TX_READY \| BD_ENET_TX_LAST \|BD_ENET_TX_WRAP);
	130	+ while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
	131	+ udelay (1); /* will also trigger Wd if needed */
	132	+ j++;
	133	+ }
	134	+ if (j>=TOUT_LOOP) printf("TX timeout\n");
	135	+#ifdef ET_DEBUG
	136	+ printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc);
	137	+#endif
	138	+ i = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */;
	139	+ return i;
	140	+}
	141	+
	142	+static int scc_recv(struct eth_device* dev)
	143	+{
	144	+ int length;
	145	+
	146	+ for (;;) {
	147	+ /* section 16.9.23.2 */
	148	+ if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
	149	+ length = -1;
	150	+ break; /* nothing received - leave for() loop */
	151	+ }
	152	+
	153	+ length = rtx->rxbd[rxIdx].cbd_datlen;
	154	+
	155	+ if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
	156	+#ifdef ET_DEBUG
	157	+ printf("err: %x\n", rtx->rxbd[rxIdx].cbd_sc);
	158	+#endif
	159	+ } else {
	160	+ /* Pass the packet up to the protocol layers. */
	161	+ NetReceive(NetRxPackets[rxIdx], length - 4);
	162	+ }
	163	+
	164	+
	165	+ /* Give the buffer back to the SCC. */
	166	+ rtx->rxbd[rxIdx].cbd_datlen = 0;
	167	+
	168	+ /* wrap around buffer index when necessary */
	169	+ if ((rxIdx + 1) >= PKTBUFSRX) {
	170	+ rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP \| BD_ENET_RX_EMPTY);
	171	+ rxIdx = 0;
	172	+ } else {
	173	+ rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
	174	+ rxIdx++;
	175	+ }
	176	+ }
	177	+ return length;
	178	+}
	179	+
	180	+/**************************************************************
	181	+ *
	182	+ * SCC Ethernet Initialization Routine
	183	+ *
	184	+ *************************************************************/
	185	+
	186	+static int scc_init(struct eth_device* dev, bd_t *bis)
	187	+{
	188	+
	189	+ int i;
	190	+ scc_enet_t *pram_ptr;
	191	+
	192	+ volatile immap_t immr = (immap_t )CFG_IMMR;
	193	+
	194	+#if defined(CONFIG_FADS)
	195	+#if defined(CONFIG_MPC860T)
	196	+ /* The FADS860T doesn't use the MODEM_EN or DATA_VOICE signals. */
	197	+ ((uint ) BCSR4) &= ~BCSR4_ETHLOOP;
	198	+ ((uint ) BCSR4) \|= BCSR4_TFPLDL\|BCSR4_TPSQEL;
	199	+ ((uint ) BCSR1) &= ~BCSR1_ETHEN;
	200	+#else
	201	+ ((uint ) BCSR4) &= ~(BCSR4_ETHLOOP\|BCSR4_MODEM_EN);
	202	+ ((uint ) BCSR4) \|= BCSR4_TFPLDL\|BCSR4_TPSQEL\|BCSR4_DATA_VOICE;
	203	+ ((uint ) BCSR1) &= ~BCSR1_ETHEN;
	204	+#endif
	205	+#endif
	206	+
	207	+ pram_ptr = (scc_enet_t *)&(immr->im_cpm.cp_dparam[PROFF_ENET]);
	208	+
	209	+ rxIdx = 0;
	210	+ txIdx = 0;
	211	+
	212	+#ifdef CFG_ALLOC_DPRAM
	213	+ rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
	214	+ dpram_alloc_align(sizeof(RTXBD), 8));
	215	+#else
	216	+ rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
	217	+#endif /* 0 */
	218	+
	219	+#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
	220	+ /* Configure port A pins for Txd and Rxd.
	221	+ */
	222	+ immr->im_ioport.iop_papar \|= (PA_ENET_RXD \| PA_ENET_TXD);
	223	+ immr->im_ioport.iop_padir &= ~(PA_ENET_RXD \| PA_ENET_TXD);
	224	+ immr->im_ioport.iop_paodr &= ~PA_ENET_TXD;
	225	+#elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))
	226	+ /* Configure port B pins for Txd and Rxd.
	227	+ */
	228	+ immr->im_cpm.cp_pbpar \|= (PB_ENET_RXD \| PB_ENET_TXD);
	229	+ immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD \| PB_ENET_TXD);
	230	+ immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD;
	231	+#else
	232	+#error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined
	233	+#endif
	234	+
	235	+#if defined(PC_ENET_LBK)
	236	+ /* Configure port C pins to disable External Loopback
	237	+ */
	238	+ immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
	239	+ immr->im_ioport.iop_pcdir \|= PC_ENET_LBK;
	240	+ immr->im_ioport.iop_pcso &= ~PC_ENET_LBK;
	241	+ immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */
	242	+#endif /* PC_ENET_LBK */
	243	+
	244	+ /* Configure port C pins to enable CLSN and RENA.
	245	+ */
	246	+ immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN \| PC_ENET_RENA);
	247	+ immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN \| PC_ENET_RENA);
	248	+ immr->im_ioport.iop_pcso \|= (PC_ENET_CLSN \| PC_ENET_RENA);
	249	+
	250	+ /* Configure port A for TCLK and RCLK.
	251	+ */
	252	+ immr->im_ioport.iop_papar \|= (PA_ENET_TCLK \| PA_ENET_RCLK);
	253	+ immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK \| PA_ENET_RCLK);
	254	+
	255	+ /*
	256	+ * Configure Serial Interface clock routing -- see section 16.7.5.3
	257	+ * First, clear all SCC bits to zero, then set the ones we want.
	258	+ */
	259	+
	260	+ immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK;
	261	+ immr->im_cpm.cp_sicr \|= SICR_ENET_CLKRT;
	262	+
	263	+
	264	+ /*
	265	+ * Initialize SDCR -- see section 16.9.23.7
	266	+ * SDMA configuration register
	267	+ */
	268	+ immr->im_siu_conf.sc_sdcr = 0x01;
	269	+
	270	+
	271	+ /*
	272	+ * Setup SCC Ethernet Parameter RAM
	273	+ */
	274	+
	275	+ pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */
	276	+ pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */
	277	+
	278	+ pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */
	279	+
	280	+ pram_ptr->sen_genscc.scc_rbase = (unsigned int)(&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */
	281	+ pram_ptr->sen_genscc.scc_tbase = (unsigned int)(&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */
	282	+
	283	+ /*
	284	+ * Setup Receiver Buffer Descriptors (13.14.24.18)
	285	+ * Settings:
	286	+ * Empty, Wrap
	287	+ */
	288	+
	289	+ for (i = 0; i < PKTBUFSRX; i++)
	290	+ {
	291	+ rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
	292	+ rtx->rxbd[i].cbd_datlen = 0; /* Reset */
	293	+ rtx->rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
	294	+ }
	295	+
	296	+ rtx->rxbd[PKTBUFSRX - 1].cbd_sc \|= BD_ENET_RX_WRAP;
	297	+
	298	+ /*
	299	+ * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
	300	+ * Settings:
	301	+ * Add PADs to Short FRAMES, Wrap, Last, Tx CRC
	302	+ */
	303	+
	304	+ for (i = 0; i < TX_BUF_CNT; i++)
	305	+ {
	306	+ rtx->txbd[i].cbd_sc = (BD_ENET_TX_PAD \| BD_ENET_TX_LAST \| BD_ENET_TX_TC);
	307	+ rtx->txbd[i].cbd_datlen = 0; /* Reset */
	308	+ rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
	309	+ }
	310	+
	311	+ rtx->txbd[TX_BUF_CNT - 1].cbd_sc \|= BD_ENET_TX_WRAP;
	312	+
	313	+ /*
	314	+ * Enter Command: Initialize Rx Params for SCC
	315	+ */
	316	+
	317	+ do { /* Spin until ready to issue command */
	318	+ __asm__ ("eieio");
	319	+ } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
	320	+ /* Issue command */
	321	+ immr->im_cpm.cp_cpcr = ((CPM_CR_INIT_RX << 8) \| (CPM_CR_ENET << 4) \| CPM_CR_FLG);
	322	+ do { /* Spin until command processed */
	323	+ __asm__ ("eieio");
	324	+ } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
	325	+
	326	+ /*
	327	+ * Ethernet Specific Parameter RAM
	328	+ * see table 13-16, pg. 660,
	329	+ * pg. 681 (example with suggested settings)
	330	+ */
	331	+
	332	+ pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */
	333	+ pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */
	334	+ pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
	335	+ pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */
	336	+ pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */
	337	+ pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */
	338	+
	339	+ pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */
	340	+ pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
	341	+ pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */
	342	+
	343	+ pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
	344	+ pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */
	345	+
	346	+ pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
	347	+ pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
	348	+ pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
	349	+ pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */
	350	+
	351	+#define ea eth_get_dev()->enetaddr
	352	+ pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
	353	+ pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
	354	+ pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
	355	+#undef ea
	356	+
	357	+ pram_ptr->sen_pper = 0x0; /* Persistence (unused) */
	358	+ pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */
	359	+ pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */
	360	+ pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */
	361	+ pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */
	362	+ pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */
	363	+ pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */
	364	+ pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */
	365	+
	366	+ /*
	367	+ * Enter Command: Initialize Tx Params for SCC
	368	+ */
	369	+
	370	+ do { /* Spin until ready to issue command */
	371	+ __asm__ ("eieio");
	372	+ } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
	373	+ /* Issue command */
	374	+ immr->im_cpm.cp_cpcr = ((CPM_CR_INIT_TX << 8) \| (CPM_CR_ENET << 4) \| CPM_CR_FLG);
	375	+ do { /* Spin until command processed */
	376	+ __asm__ ("eieio");
	377	+ } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
	378	+
	379	+ /*
	380	+ * Mask all Events in SCCM - we use polling mode
	381	+ */
	382	+ immr->im_cpm.cp_scc[SCC_ENET].scc_sccm = 0;
	383	+
	384	+ /*
	385	+ * Clear Events in SCCE -- Clear bits by writing 1's
	386	+ */
	387	+
	388	+ immr->im_cpm.cp_scc[SCC_ENET].scc_scce = ~(0x0);
	389	+
	390	+
	391	+ /*
	392	+ * Initialize GSMR High 32-Bits
	393	+ * Settings: Normal Mode
	394	+ */
	395	+
	396	+ immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrh = 0;
	397	+
	398	+ /*
	399	+ * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive
	400	+ * Settings:
	401	+ * TCI = Invert
	402	+ * TPL = 48 bits
	403	+ * TPP = Repeating 10's
	404	+ * MODE = Ethernet
	405	+ */
	406	+
	407	+ immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl = ( SCC_GSMRL_TCI \| \
	408	+ SCC_GSMRL_TPL_48 \| \
	409	+ SCC_GSMRL_TPP_10 \| \
	410	+ SCC_GSMRL_MODE_ENET);
	411	+
	412	+ /*
	413	+ * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4
	414	+ */
	415	+
	416	+ immr->im_cpm.cp_scc[SCC_ENET].scc_dsr = 0xd555;
	417	+
	418	+ /*
	419	+ * Initialize the PSMR
	420	+ * Settings:
	421	+ * CRC = 32-Bit CCITT
	422	+ * NIB = Begin searching for SFD 22 bits after RENA
	423	+ * FDE = Full Duplex Enable
	424	+ * LPB = Loopback Enable (Needed when FDE is set)
	425	+ * BRO = Reject broadcast packets
	426	+ * PROMISCOUS = Catch all packets regardless of dest. MAC adress
	427	+ */
	428	+ immr->im_cpm.cp_scc[SCC_ENET].scc_psmr = SCC_PSMR_ENCRC \|
	429	+ SCC_PSMR_NIB22 \|
	430	+#if defined(CONFIG_SCC_ENET_FULL_DUPLEX)
	431	+ SCC_PSMR_FDE \|
	432	+ SCC_PSMR_LPB \|
	433	+#endif
	434	+#if defined(CONFIG_SCC_ENET_NO_BROADCAST)
	435	+ SCC_PSMR_BRO \|
	436	+#endif
	437	+#if defined(CONFIG_SCC_ENET_PROMISCOUS)
	438	+ SCC_PSMR_PRO \|
	439	+#endif
	440	+ 0;
	441	+
	442	+ /*
	443	+ * Configure Ethernet TENA Signal
	444	+ */
	445	+
	446	+#if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA))
	447	+ immr->im_ioport.iop_pcpar \|= PC_ENET_TENA;
	448	+ immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA;
	449	+#elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA))
	450	+ immr->im_cpm.cp_pbpar \|= PB_ENET_TENA;
	451	+ immr->im_cpm.cp_pbdir \|= PB_ENET_TENA;
	452	+#else
	453	+#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
	454	+#endif
	455	+
	456	+#if defined(CONFIG_ADS) && defined(CONFIG_MPC860)
	457	+ /*
	458	+ * Port C is used to control the PHY,MC68160.
	459	+ */
	460	+ immr->im_ioport.iop_pcdir \|=
	461	+ (PC_ENET_ETHLOOP \| PC_ENET_TPFLDL \| PC_ENET_TPSQEL);
	462	+
	463	+ immr->im_ioport.iop_pcdat \|= PC_ENET_TPFLDL;
	464	+ immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP \| PC_ENET_TPSQEL);
	465	+ ((uint ) BCSR1) &= ~BCSR1_ETHEN;
	466	+#endif /* MPC860ADS */
	467	+
	468	+#if defined(CONFIG_AMX860)
	469	+ /*
	470	+ * Port B is used to control the PHY,MC68160.
	471	+ */
	472	+ immr->im_cpm.cp_pbdir \|=
	473	+ (PB_ENET_ETHLOOP \| PB_ENET_TPFLDL \| PB_ENET_TPSQEL);
	474	+
	475	+ immr->im_cpm.cp_pbdat \|= PB_ENET_TPFLDL;
	476	+ immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP \| PB_ENET_TPSQEL);
	477	+
	478	+ immr->im_ioport.iop_pddir \|= PD_ENET_ETH_EN;
	479	+ immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN;
	480	+#endif /* AMX860 */
	481	+
	482	+#ifdef CONFIG_RPXCLASSIC
	483	+ ((uchar )BCSR0) &= ~BCSR0_ETHLPBK;
	484	+ ((uchar )BCSR0) \|= (BCSR0_ETHEN \| BCSR0_COLTEST \| BCSR0_FULLDPLX);
	485	+#endif
	486	+
	487	+#ifdef CONFIG_RPXLITE
	488	+ ((uchar )BCSR0) \|= BCSR0_ETHEN ;
	489	+#endif
	490	+
	491	+#ifdef CONFIG_MBX
	492	+ board_ether_init();
	493	+#endif
	494	+
	495	+#if defined(CONFIG_NETVIA)
	496	+#if defined(PB_ENET_PDN)
	497	+ immr->im_cpm.cp_pbpar &= ~PB_ENET_PDN;
	498	+ immr->im_cpm.cp_pbdir \|= PB_ENET_PDN;
	499	+ immr->im_cpm.cp_pbdat \|= PB_ENET_PDN;
	500	+#elif defined(PC_ENET_PDN)
	501	+ immr->im_cpm.cp_pcpar &= ~PC_ENET_PDN;
	502	+ immr->im_cpm.cp_pcdir \|= PC_ENET_PDN;
	503	+ immr->im_cpm.cp_pcdat \|= PC_ENET_PDN;
	504	+#endif
	505	+#endif
	506	+
	507	+ /*
	508	+ * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
	509	+ */
	510	+
	511	+ immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl \|= (SCC_GSMRL_ENR \| SCC_GSMRL_ENT);
	512	+
	513	+ /*
	514	+ * Work around transmit problem with first eth packet
	515	+ */
	516	+#if defined (CONFIG_FADS)
	517	+ udelay(10000); /* wait 10 ms */
	518	+#elif defined (CONFIG_AMX860) \|\| defined(CONFIG_RPXCLASSIC)
	519	+ udelay(100000); /* wait 100 ms */
	520	+#endif
	521	+
	522	+ return 1;
	523	+}
	524	+
	525	+
	526	+
	527	+static void scc_halt(struct eth_device* dev)
	528	+{
	529	+ volatile immap_t immr = (immap_t )CFG_IMMR;
	530	+ immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &= ~(SCC_GSMRL_ENR \| SCC_GSMRL_ENT);
	531	+}
	532	+
	533	+#if 0
	534	+void restart(void)
	535	+{
	536	+ volatile immap_t immr = (immap_t )CFG_IMMR;
	537	+ immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl \|= (SCC_GSMRL_ENR \| SCC_GSMRL_ENT);
	538	+}
	539	+#endif
	540	+
	541	+#endif /* CFG_CMD_NET, SCC_ENET */

include/flash.h

Diff comments View file @ ed247f4

	1	+/*
	2	+ * (C) Copyright 2000, 2001
	3	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+#ifndef _FLASH_H_
	25	+#define _FLASH_H_
	26	+
	27	+#ifndef CFG_NO_FLASH
	28	+/*-----------------------------------------------------------------------
	29	+ * FLASH Info: contains chip specific data, per FLASH bank
	30	+ */
	31	+
	32	+typedef struct {
	33	+ ulong size; /* total bank size in bytes */
	34	+ ushort sector_count; /* number of erase units */
	35	+ ulong flash_id; /* combined device & manufacturer code */
	36	+ ulong start[CFG_MAX_FLASH_SECT]; /* physical sector start addresses */
	37	+ uchar protect[CFG_MAX_FLASH_SECT]; /* sector protection status */
	38	+#ifdef CFG_FLASH_CFI
	39	+ uchar portwidth; /* the width of the port */
	40	+ uchar chipwidth; /* the width of the chip */
	41	+ ushort buffer_size; /* # of bytes in write buffer */
	42	+ ulong erase_blk_tout; /* maximum block erase timeout */
	43	+ ulong write_tout; /* maximum write timeout */
	44	+ ulong buffer_write_tout; /* maximum buffer write timeout */
	45	+
	46	+#endif
	47	+} flash_info_t;
	48	+
	49	+/*
	50	+ * Values for the width of the port
	51	+ */
	52	+#define FLASH_CFI_8BIT 0x01
	53	+#define FLASH_CFI_16BIT 0x02
	54	+#define FLASH_CFI_32BIT 0x04
	55	+#define FLASH_CFI_64BIT 0x08
	56	+/*
	57	+ * Values for the width of the chip
	58	+ */
	59	+#define FLASH_CFI_BY8 0x01
	60	+#define FLASH_CFI_BY16 0x02
	61	+#define FLASH_CFI_BY32 0x04
	62	+#define FLASH_CFI_BY64 0x08
	63	+
	64	+/* Prototypes */
	65	+
	66	+extern unsigned long flash_init (void);
	67	+extern void flash_print_info (flash_info_t *);
	68	+extern int flash_erase (flash_info_t *, int, int);
	69	+extern int flash_sect_erase (ulong addr_first, ulong addr_last);
	70	+extern int flash_sect_protect (int flag, ulong addr_first, ulong addr_last);
	71	+
	72	+/* common/flash.c */
	73	+extern void flash_protect (int flag, ulong from, ulong to, flash_info_t *info);
	74	+extern int flash_write (uchar *, ulong, ulong);
	75	+extern flash_info_t *addr2info (ulong);
	76	+extern int write_buff (flash_info_t info, uchar src, ulong addr, ulong cnt);
	77	+
	78	+/* board/?/flash.c */
	79	+#if defined(CFG_FLASH_PROTECTION)
	80	+extern int flash_real_protect(flash_info_t *info, long sector, int prot);
	81	+#endif /* CFG_FLASH_PROTECTION */
	82	+
	83	+/*-----------------------------------------------------------------------
	84	+ * return codes from flash_write():
	85	+ */
	86	+#define ERR_OK 0
	87	+#define ERR_TIMOUT 1
	88	+#define ERR_NOT_ERASED 2
	89	+#define ERR_PROTECTED 4
	90	+#define ERR_INVAL 8
	91	+#define ERR_ALIGN 16
	92	+#define ERR_UNKNOWN_FLASH_VENDOR 32
	93	+#define ERR_UNKNOWN_FLASH_TYPE 64
	94	+#define ERR_PROG_ERROR 128
	95	+
	96	+/*-----------------------------------------------------------------------
	97	+ * Protection Flags for flash_protect():
	98	+ */
	99	+#define FLAG_PROTECT_SET 0x01
	100	+#define FLAG_PROTECT_CLEAR 0x02
	101	+
	102	+/*-----------------------------------------------------------------------
	103	+ * Device IDs
	104	+ */
	105	+
	106	+#define AMD_MANUFACT 0x00010001 /* AMD manuf. ID in D23..D16, D7..D0 */
	107	+#define FUJ_MANUFACT 0x00040004 /* FUJITSU manuf. ID in D23..D16, D7..D0 */
	108	+#define STM_MANUFACT 0x00200020 /* STM (Thomson) manuf. ID in D23.. -"- */
	109	+#define SST_MANUFACT 0x00BF00BF /* SST manuf. ID in D23..D16, D7..D0 */
	110	+#define MT_MANUFACT 0x00890089 /* MT manuf. ID in D23..D16, D7..D0 */
	111	+#define INTEL_MANUFACT 0x00890089 /* INTEL manuf. ID in D23..D16, D7..D0 */
	112	+#define INTEL_ALT_MANU 0x00B000B0 /* alternate INTEL namufacturer ID */
	113	+#define MX_MANUFACT 0x00C200C2 /* MXIC manuf. ID in D23..D16, D7..D0 */
	114	+
	115	+ /* Micron Technologies (INTEL compat.) */
	116	+#define MT_ID_28F400_T 0x44704470 /* 28F400B3 ID ( 4 M, top boot sector) */
	117	+#define MT_ID_28F400_B 0x44714471 /* 28F400B3 ID ( 4 M, bottom boot sect) */
	118	+
	119	+#define AMD_ID_LV040B 0x4F /* 29LV040B ID */
	120	+ /* 4 Mbit, 512K x 8, */
	121	+ /* 8 64K x 8 uniform sectors */
	122	+
	123	+#define AMD_ID_F040B 0xA4 /* 29F040B ID */
	124	+ /* 4 Mbit, 512K x 8, */
	125	+ /* 8 64K x 8 uniform sectors */
	126	+#define STM_ID_M29W040B 0xE3 /* M29W040B ID */
	127	+ /* 4 Mbit, 512K x 8, */
	128	+ /* 8 64K x 8 uniform sectors */
	129	+#define AMD_ID_F080B 0xD5 /* 29F080 ID ( 1 M) */
	130	+#define AMD_ID_F016D 0xAD /* 29F016 ID ( 2 M x 8) */
	131	+#define AMD_ID_F032B 0x41 /* 29F032 ID ( 4 M x 8) */
	132	+#define AMD_ID_LV116DT 0xC7 /* 29LV116DT ( 2 M x 8, top boot sect) */
	133	+
	134	+#define AMD_ID_LV400T 0x22B922B9 /* 29LV400T ID ( 4 M, top boot sector) */
	135	+#define AMD_ID_LV400B 0x22BA22BA /* 29LV400B ID ( 4 M, bottom boot sect) */
	136	+
	137	+#define AMD_ID_LV033C 0xA3 /* 29LV033C ID ( 4M x 8 ) */
	138	+
	139	+#define AMD_ID_LV800T 0x22DA22DA /* 29LV800T ID ( 8 M, top boot sector) */
	140	+#define AMD_ID_LV800B 0x225B225B /* 29LV800B ID ( 8 M, bottom boot sect) */
	141	+
	142	+#define AMD_ID_LV160T 0x22C422C4 /* 29LV160T ID (16 M, top boot sector) */
	143	+#define AMD_ID_LV160B 0x22492249 /* 29LV160B ID (16 M, bottom boot sect) */
	144	+
	145	+#define AMD_ID_LV320T 0x22F622F6 /* 29LV320T ID (32 M, top boot sector) */
	146	+#define AMD_ID_LV320B 0x22F922F9 /* 29LV320B ID (32 M, bottom boot sect) */
	147	+
	148	+#define AMD_ID_DL322T 0x22552255 /* 29DL322T ID (32 M, top boot sector) */
	149	+#define AMD_ID_DL322B 0x22562256 /* 29DL322B ID (32 M, bottom boot sect) */
	150	+#define AMD_ID_DL323T 0x22502250 /* 29DL323T ID (32 M, top boot sector) */
	151	+#define AMD_ID_DL323B 0x22532253 /* 29DL323B ID (32 M, bottom boot sect) */
	152	+#define AMD_ID_DL324T 0x225C225C /* 29DL324T ID (32 M, top boot sector) */
	153	+#define AMD_ID_DL324B 0x225F225F /* 29DL324B ID (32 M, bottom boot sect) */
	154	+
	155	+#define AMD_ID_DL640 0x227E227E /* 29DL640D ID (64 M, dual boot sectors)*/
	156	+#define AMD_ID_LV640U 0x22D722D7 /* 29LV640U ID (64 M, uniform sectors) */
	157	+
	158	+#define SST_ID_xF200A 0x27892789 /* 39xF200A ID ( 2M = 128K x 16 ) */
	159	+#define SST_ID_xF400A 0x27802780 /* 39xF400A ID ( 4M = 256K x 16 ) */
	160	+#define SST_ID_xF800A 0x27812781 /* 39xF800A ID ( 8M = 512K x 16 ) */
	161	+#define SST_ID_xF160A 0x27822782 /* 39xF800A ID (16M = 1M x 16 ) */
	162	+
	163	+#define STM_ID_F040B 0xE2 /* M29F040B ID ( 4M = 512K x 8 ) */
	164	+ /* 8 64K x 8 uniform sectors */
	165	+
	166	+#define STM_ID_x800AB 0x005B005B /* M29W800AB ID (8M = 512K x 16 ) */
	167	+#define STM_ID_29W320DT 0x22CA22CA /* M29W320DT ID (32 M, top boot sector) */
	168	+#define STM_ID_29W320DB 0x22CB22CB /* M29W320DB ID (32 M, bottom boot sect) */
	169	+#define STM_ID_29W040B 0x00E300E3 /* M29W040B ID (4M = 512K x 8) */
	170	+
	171	+#define INTEL_ID_28F016S 0x66a066a0 /* 28F016S[VS] ID (16M = 512k x 16) */
	172	+#define INTEL_ID_28F800B3T 0x88928892 /* 8M = 512K x 16 top boot sector */
	173	+#define INTEL_ID_28F800B3B 0x88938893 /* 8M = 512K x 16 bottom boot sector */
	174	+#define INTEL_ID_28F160B3T 0x88908890 /* 16M = 1M x 16 top boot sector */
	175	+#define INTEL_ID_28F160B3B 0x88918891 /* 16M = 1M x 16 bottom boot sector */
	176	+#define INTEL_ID_28F320B3T 0x88968896 /* 32M = 2M x 16 top boot sector */
	177	+#define INTEL_ID_28F320B3B 0x88978897 /* 32M = 2M x 16 bottom boot sector */
	178	+#define INTEL_ID_28F640B3T 0x88988898 /* 64M = 4M x 16 top boot sector */
	179	+#define INTEL_ID_28F640B3B 0x88998899 /* 64M = 4M x 16 bottom boot sector */
	180	+#define INTEL_ID_28F160F3B 0x88F488F4 /* 16M = 1M x 16 bottom boot sector */
	181	+
	182	+#define INTEL_ID_28F800C3T 0x88C088C0 /* 8M = 512K x 16 top boot sector */
	183	+#define INTEL_ID_28F800C3B 0x88C188C1 /* 8M = 512K x 16 bottom boot sector */
	184	+#define INTEL_ID_28F160C3T 0x88C288C2 /* 16M = 1M x 16 top boot sector */
	185	+#define INTEL_ID_28F160C3B 0x88C388C3 /* 16M = 1M x 16 bottom boot sector */
	186	+#define INTEL_ID_28F320C3T 0x88C488C4 /* 32M = 2M x 16 top boot sector */
	187	+#define INTEL_ID_28F320C3B 0x88C588C5 /* 32M = 2M x 16 bottom boot sector */
	188	+#define INTEL_ID_28F640C3T 0x88CC88CC /* 64M = 4M x 16 top boot sector */
	189	+#define INTEL_ID_28F640C3B 0x88CD88CD /* 64M = 4M x 16 bottom boot sector */
	190	+
	191	+#define INTEL_ID_28F128J3 0x89189818 /* 16M = 8M x 16 x 128 */
	192	+#define INTEL_ID_28F640J5 0x00150015 /* 64M = 128K x 64 */
	193	+#define INTEL_ID_28F320J3A 0x00160016 /* 32M = 128K x 32 */
	194	+#define INTEL_ID_28F640J3A 0x00170017 /* 64M = 128K x 64 */
	195	+#define INTEL_ID_28F128J3A 0x00180018 /* 128M = 128K x 128 */
	196	+
	197	+#define INTEL_ID_28F160S3 0x00D000D0 /* 16M = 512K x 32 (64kB x 32) */
	198	+#define INTEL_ID_28F320S3 0x00D400D4 /* 32M = 512K x 64 (64kB x 64) */
	199	+
	200	+/* Note that the Sharp 28F016SC is compatible with the Intel E28F016SC */
	201	+#define SHARP_ID_28F016SCL 0xAAAAAAAA /* LH28F016SCT-L95 2Mx8, 32 64k blocks */
	202	+#define SHARP_ID_28F016SCZ 0xA0A0A0A0 /* LH28F016SCT-Z4 2Mx8, 32 64k blocks */
	203	+#define SHARP_ID_28F008SC 0xA6A6A6A6 /* LH28F008SCT-L12 1Mx8, 16 64k blocks */
	204	+ /* LH28F008SCR-L85 1Mx8, 16 64k blocks */
	205	+
	206	+/*-----------------------------------------------------------------------
	207	+ * Internal FLASH identification codes
	208	+ *
	209	+ * Be careful when adding new type! Odd numbers are "bottom boot sector" types!
	210	+ */
	211	+
	212	+#define FLASH_AM040 0x0001 /* AMD Am29F040B, Am29LV040B
	213	+ * Bright Micro BM29F040
	214	+ * Fujitsu MBM29F040A
	215	+ * STM M29W040B
	216	+ * SGS Thomson M29F040B
	217	+ * 8 64K x 8 uniform sectors
	218	+ */
	219	+#define FLASH_AM400T 0x0002 /* AMD AM29LV400 */
	220	+#define FLASH_AM400B 0x0003
	221	+#define FLASH_AM800T 0x0004 /* AMD AM29LV800 */
	222	+#define FLASH_AM800B 0x0005
	223	+#define FLASH_AM116DT 0x0026 /* AMD AM29LV116DT (2Mx8bit) */
	224	+#define FLASH_AM160T 0x0006 /* AMD AM29LV160 */
	225	+#define FLASH_AM160LV 0x0046 /* AMD29LV160DB (2M = 2Mx8bit ) */
	226	+#define FLASH_AM160B 0x0007
	227	+#define FLASH_AM320T 0x0008 /* AMD AM29LV320 */
	228	+#define FLASH_AM320B 0x0009
	229	+
	230	+#define FLASH_AMDL322T 0x0010 /* AMD AM29DL322 */
	231	+#define FLASH_AMDL322B 0x0011
	232	+#define FLASH_AMDL323T 0x0012 /* AMD AM29DL323 */
	233	+#define FLASH_AMDL323B 0x0013
	234	+#define FLASH_AMDL324T 0x0014 /* AMD AM29DL324 */
	235	+#define FLASH_AMDL324B 0x0015
	236	+
	237	+#define FLASH_AMDL640 0x0016 /* AMD AM29DL640D */
	238	+#define FLASH_AMD016 0x0018 /* AMD AM29F016D */
	239	+
	240	+#define FLASH_SST200A 0x0040 /* SST 39xF200A ID ( 2M = 128K x 16 ) */
	241	+#define FLASH_SST400A 0x0042 /* SST 39xF400A ID ( 4M = 256K x 16 ) */
	242	+#define FLASH_SST800A 0x0044 /* SST 39xF800A ID ( 8M = 512K x 16 ) */
	243	+#define FLASH_SST160A 0x0046 /* SST 39xF160A ID ( 16M = 1M x 16 ) */
	244	+
	245	+#define FLASH_STM800AB 0x0051 /* STM M29WF800AB ( 8M = 512K x 16 ) */
	246	+#define FLASH_STMW320DT 0x0052 /* STM M29W320DT (32 M, top boot sector) */
	247	+#define FLASH_STMW320DB 0x0053 /* STM M29W320DB (32 M, bottom boot sect)*/
	248	+#define FLASH_STM320DB 0x00CB /* STM M29W320DB (4M = 64K x 64, bottom)*/
	249	+#define FLASH_STM800DT 0x00D7 /* STM M29W800DT (1M = 64K x 16, top) */
	250	+#define FLASH_STM800DB 0x005B /* STM M29W800DB (1M = 64K x 16, bottom)*/
	251	+
	252	+#define FLASH_28F400_T 0x0062 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */
	253	+#define FLASH_28F400_B 0x0063 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */
	254	+
	255	+#define FLASH_INTEL800T 0x0074 /* INTEL 28F800B3T ( 8M = 512K x 16 ) */
	256	+#define FLASH_INTEL800B 0x0075 /* INTEL 28F800B3B ( 8M = 512K x 16 ) */
	257	+#define FLASH_INTEL160T 0x0076 /* INTEL 28F160B3T ( 16M = 1 M x 16 ) */
	258	+#define FLASH_INTEL160B 0x0077 /* INTEL 28F160B3B ( 16M = 1 M x 16 ) */
	259	+#define FLASH_INTEL320T 0x0078 /* INTEL 28F320B3T ( 32M = 2 M x 16 ) */
	260	+#define FLASH_INTEL320B 0x0079 /* INTEL 28F320B3B ( 32M = 2 M x 16 ) */
	261	+#define FLASH_INTEL640T 0x007A /* INTEL 28F320B3T ( 64M = 4 M x 16 ) */
	262	+#define FLASH_INTEL640B 0x007B /* INTEL 28F320B3B ( 64M = 4 M x 16 ) */
	263	+
	264	+#define FLASH_28F320J3A 0x007C /* INTEL 28F320J3A ( 32M = 128K x 32) */
	265	+#define FLASH_28F640J3A 0x007D /* INTEL 28F640J3A ( 64M = 128K x 64) */
	266	+#define FLASH_28F128J3A 0x007E /* INTEL 28F128J3A (128M = 128K x 128) */
	267	+
	268	+#define FLASH_28F008S5 0x0080 /* Intel 28F008S5 ( 1M = 64K x 16 ) */
	269	+#define FLASH_28F016SV 0x0081 /* Intel 28F016SV ( 16M = 512k x 32 ) */
	270	+#define FLASH_28F800_B 0x0083 /* Intel E28F800B ( 1M = ? ) */
	271	+#define FLASH_AM29F800B 0x0084 /* AMD Am29F800BB ( 1M = ? ) */
	272	+#define FLASH_28F320J5 0x0085 /* Intel 28F320J5 ( 4M = 128K x 32 ) */
	273	+#define FLASH_28F160S3 0x0086 /* Intel 28F160S3 ( 16M = 512K x 32 ) */
	274	+#define FLASH_28F320S3 0x0088 /* Intel 28F320S3 ( 32M = 512K x 64 ) */
	275	+#define FLASH_AM640U 0x0090 /* AMD Am29LV640U ( 64M = 4M x 16 ) */
	276	+#define FLASH_AM033C 0x0091 /* AMD AM29LV033 ( 32M = 4M x 8 ) */
	277	+#define FLASH_LH28F016SCT 0x0092 /* Sharp 28F016SCT ( 8 Meg Flash SIMM ) */
	278	+#define FLASH_28F160F3B 0x0093 /* Intel 28F160F3B ( 16M = 1M x 16 ) */
	279	+
	280	+#define FLASH_28F640J5 0x0099 /* INTEL 28F640J5 ( 64M = 128K x 64) */
	281	+
	282	+#define FLASH_28F800C3T 0x009A /* Intel 28F800C3T ( 8M = 512K x 16 ) */
	283	+#define FLASH_28F800C3B 0x009B /* Intel 28F800C3B ( 8M = 512K x 16 ) */
	284	+#define FLASH_28F160C3T 0x009C /* Intel 28F160C3T ( 16M = 1M x 16 ) */
	285	+#define FLASH_28F160C3B 0x009D /* Intel 28F160C3B ( 16M = 1M x 16 ) */
	286	+#define FLASH_28F320C3T 0x009E /* Intel 28F320C3T ( 32M = 2M x 16 ) */
	287	+#define FLASH_28F320C3B 0x009F /* Intel 28F320C3B ( 32M = 2M x 16 ) */
	288	+#define FLASH_28F640C3T 0x00A0 /* Intel 28F640C3T ( 64M = 4M x 16 ) */
	289	+#define FLASH_28F640C3B 0x00A1 /* Intel 28F640C3B ( 64M = 4M x 16 ) */
	290	+
	291	+#define FLASH_UNKNOWN 0xFFFF /* unknown flash type */
	292	+
	293	+
	294	+/* manufacturer offsets
	295	+ */
	296	+#define FLASH_MAN_AMD 0x00000000 /* AMD */
	297	+#define FLASH_MAN_FUJ 0x00010000 /* Fujitsu */
	298	+#define FLASH_MAN_BM 0x00020000 /* Bright Microelectronics */
	299	+#define FLASH_MAN_MX 0x00030000 /* MXIC */
	300	+#define FLASH_MAN_STM 0x00040000
	301	+#define FLASH_MAN_SST 0x00100000
	302	+#define FLASH_MAN_INTEL 0x00300000
	303	+#define FLASH_MAN_MT 0x00400000
	304	+#define FLASH_MAN_SHARP 0x00500000
	305	+
	306	+
	307	+#define FLASH_TYPEMASK 0x0000FFFF /* extract FLASH type information */
	308	+#define FLASH_VENDMASK 0xFFFF0000 /* extract FLASH vendor information */
	309	+
	310	+#define FLASH_AMD_COMP 0x000FFFFF /* Up to this ID, FLASH is compatible */
	311	+ /* with AMD, Fujitsu and SST */
	312	+ /* (JEDEC standard commands ?) */
	313	+
	314	+#define FLASH_BTYPE 0x0001 /* mask for bottom boot sector type */
	315	+
	316	+/*-----------------------------------------------------------------------
	317	+ * Timeout constants:
	318	+ *
	319	+ * We can't find any specifications for maximum chip erase times,
	320	+ * so these values are guestimates.
	321	+ */
	322	+#define FLASH_ERASE_TIMEOUT 120000 /* timeout for erasing in ms */
	323	+#define FLASH_WRITE_TIMEOUT 500 /* timeout for writes in ms */
	324	+
	325	+#endif /* !CFG_NO_FLASH */
	326	+
	327	+#endif /* _FLASH_H_ */