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Commit ed90d2c87158e5114b6009fa95bb6417e4b27b3e

Authored by Vivek Mahajan
Committed by Wolfgang Denk
1 parent cfd39cdf94
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

mpc8xxx: USB: Relocates ehci-fsl.h to include/usb 

The following patch moves 8xxx-specifc USB #defines from
drivers/usb/host/ehci-fsl.h to include/usb.

Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Remy Bohmer <linux@bohmer.net>

Showing 3 changed files with 87 additions and 87 deletions Side-by-side Diff

drivers/usb/host/ehci-fsl.c
Diff comments   View file @ ed90d2c
... ... @@ -27,7 +27,7 @@
27 27 #include <asm/bitops.h>
28 28  
29 29 #include "ehci.h"
30   -#include "ehci-fsl.h"
  30 +#include <usb/ehci-fsl.h>
31 31 #include "ehci-core.h"
32 32  
33 33 /*
drivers/usb/host/ehci-fsl.h
View file @ ed90d2c
1   -/*
2   - * Copyright (c) 2005 freescale semiconductor
3   - * Copyright (c) 2005 MontaVista Software
4   - * Copyright (c) 2008 Excito Elektronik i Sk=E5ne AB
5   - *
6   - * This program is free software; you can redistribute it and/or
7   - * modify it under the terms of the GNU General Public License as
8   - * published by the Free Software Foundation; either version 2 of
9   - * the License, or (at your option) any later version.
10   - *
11   - * This program is distributed in the hope that it will be useful,
12   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
13   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14   - * GNU General Public License for more details.
15   - *
16   - * You should have received a copy of the GNU General Public License
17   - * along with this program; if not, write to the Free Software
18   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19   - * MA 02111-1307 USA
20   - */
21   -
22   -#ifndef _EHCI_FSL_H
23   -#define _EHCI_FSL_H
24   -
25   -/* Global offsets */
26   -#define FSL_SKIP_PCI 0x100
27   -
28   -/* offsets for the non-ehci registers in the FSL SOC USB controller */
29   -#define FSL_SOC_USB_ULPIVP 0x170
30   -#define FSL_SOC_USB_PORTSC1 0x184
31   -#define PORT_PTS_MSK (3 << 30)
32   -#define PORT_PTS_UTMI (0 << 30)
33   -#define PORT_PTS_ULPI (2 << 30)
34   -#define PORT_PTS_SERIAL (3 << 30)
35   -#define PORT_PTS_PTW (1 << 28)
36   -
37   -/* USBMODE Register bits */
38   -#define CM_IDLE (0 << 0)
39   -#define CM_RESERVED (1 << 0)
40   -#define CM_DEVICE (2 << 0)
41   -#define CM_HOST (3 << 0)
42   -#define USBMODE_RESERVED_2 (0 << 2)
43   -#define SLOM (1 << 3)
44   -#define SDIS (1 << 4)
45   -
46   -/* CONTROL Register bits */
47   -#define ULPI_INT_EN (1 << 0)
48   -#define WU_INT_EN (1 << 1)
49   -#define USB_EN (1 << 2)
50   -#define LSF_EN (1 << 3)
51   -#define KEEP_OTG_ON (1 << 4)
52   -#define OTG_PORT (1 << 5)
53   -#define REFSEL_12MHZ (0 << 6)
54   -#define REFSEL_16MHZ (1 << 6)
55   -#define REFSEL_48MHZ (2 << 6)
56   -#define PLL_RESET (1 << 8)
57   -#define UTMI_PHY_EN (1 << 9)
58   -#define PHY_CLK_SEL_UTMI (0 << 10)
59   -#define PHY_CLK_SEL_ULPI (1 << 10)
60   -#define CLKIN_SEL_USB_CLK (0 << 11)
61   -#define CLKIN_SEL_USB_CLK2 (1 << 11)
62   -#define CLKIN_SEL_SYS_CLK (2 << 11)
63   -#define CLKIN_SEL_SYS_CLK2 (3 << 11)
64   -#define RESERVED_18 (0 << 13)
65   -#define RESERVED_17 (0 << 14)
66   -#define RESERVED_16 (0 << 15)
67   -#define WU_INT (1 << 16)
68   -#define PHY_CLK_VALID (1 << 17)
69   -
70   -#define FSL_SOC_USB_PORTSC2 0x188
71   -#define FSL_SOC_USB_USBMODE 0x1a8
72   -#define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */
73   -#define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */
74   -#define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */
75   -#define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */
76   -#define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
77   -#define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
78   -#define SNOOP_SIZE_2GB 0x1e
79   -
80   -/* System Clock Control Register */
81   -#define MPC83XX_SCCR_USB_MASK 0x00f00000
82   -#define MPC83XX_SCCR_USB_DRCM_11 0x00300000
83   -#define MPC83XX_SCCR_USB_DRCM_01 0x00100000
84   -#define MPC83XX_SCCR_USB_DRCM_10 0x00200000
85   -
86   -#endif /* _EHCI_FSL_H */
include/usb/ehci-fsl.h
Diff comments   View file @ ed90d2c
  1 +/*
  2 + * Copyright (c) 2005 freescale semiconductor
  3 + * Copyright (c) 2005 MontaVista Software
  4 + * Copyright (c) 2008 Excito Elektronik i Sk=E5ne AB
  5 + *
  6 + * This program is free software; you can redistribute it and/or
  7 + * modify it under the terms of the GNU General Public License as
  8 + * published by the Free Software Foundation; either version 2 of
  9 + * the License, or (at your option) any later version.
  10 + *
  11 + * This program is distributed in the hope that it will be useful,
  12 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14 + * GNU General Public License for more details.
  15 + *
  16 + * You should have received a copy of the GNU General Public License
  17 + * along with this program; if not, write to the Free Software
  18 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19 + * MA 02111-1307 USA
  20 + */
  21 +
  22 +#ifndef _EHCI_FSL_H
  23 +#define _EHCI_FSL_H
  24 +
  25 +/* Global offsets */
  26 +#define FSL_SKIP_PCI 0x100
  27 +
  28 +/* offsets for the non-ehci registers in the FSL SOC USB controller */
  29 +#define FSL_SOC_USB_ULPIVP 0x170
  30 +#define FSL_SOC_USB_PORTSC1 0x184
  31 +#define PORT_PTS_MSK (3 << 30)
  32 +#define PORT_PTS_UTMI (0 << 30)
  33 +#define PORT_PTS_ULPI (2 << 30)
  34 +#define PORT_PTS_SERIAL (3 << 30)
  35 +#define PORT_PTS_PTW (1 << 28)
  36 +
  37 +/* USBMODE Register bits */
  38 +#define CM_IDLE (0 << 0)
  39 +#define CM_RESERVED (1 << 0)
  40 +#define CM_DEVICE (2 << 0)
  41 +#define CM_HOST (3 << 0)
  42 +#define USBMODE_RESERVED_2 (0 << 2)
  43 +#define SLOM (1 << 3)
  44 +#define SDIS (1 << 4)
  45 +
  46 +/* CONTROL Register bits */
  47 +#define ULPI_INT_EN (1 << 0)
  48 +#define WU_INT_EN (1 << 1)
  49 +#define USB_EN (1 << 2)
  50 +#define LSF_EN (1 << 3)
  51 +#define KEEP_OTG_ON (1 << 4)
  52 +#define OTG_PORT (1 << 5)
  53 +#define REFSEL_12MHZ (0 << 6)
  54 +#define REFSEL_16MHZ (1 << 6)
  55 +#define REFSEL_48MHZ (2 << 6)
  56 +#define PLL_RESET (1 << 8)
  57 +#define UTMI_PHY_EN (1 << 9)
  58 +#define PHY_CLK_SEL_UTMI (0 << 10)
  59 +#define PHY_CLK_SEL_ULPI (1 << 10)
  60 +#define CLKIN_SEL_USB_CLK (0 << 11)
  61 +#define CLKIN_SEL_USB_CLK2 (1 << 11)
  62 +#define CLKIN_SEL_SYS_CLK (2 << 11)
  63 +#define CLKIN_SEL_SYS_CLK2 (3 << 11)
  64 +#define RESERVED_18 (0 << 13)
  65 +#define RESERVED_17 (0 << 14)
  66 +#define RESERVED_16 (0 << 15)
  67 +#define WU_INT (1 << 16)
  68 +#define PHY_CLK_VALID (1 << 17)
  69 +
  70 +#define FSL_SOC_USB_PORTSC2 0x188
  71 +#define FSL_SOC_USB_USBMODE 0x1a8
  72 +#define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */
  73 +#define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */
  74 +#define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */
  75 +#define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */
  76 +#define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
  77 +#define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
  78 +#define SNOOP_SIZE_2GB 0x1e
  79 +
  80 +/* System Clock Control Register */
  81 +#define MPC83XX_SCCR_USB_MASK 0x00f00000
  82 +#define MPC83XX_SCCR_USB_DRCM_11 0x00300000
  83 +#define MPC83XX_SCCR_USB_DRCM_01 0x00100000
  84 +#define MPC83XX_SCCR_USB_DRCM_10 0x00200000
  85 +
  86 +#endif /* _EHCI_FSL_H */