Commit ed9c9059f22f2ee1ada4dbc4603f3688bd70e37c

Authored by Jagan Teki
Committed by Philipp Tomsich
1 parent e05b4a4fa8

rockchip: rk3399: Add Orangepi RK3399 support

Add initial support for Orangepi RK3399 board.

Specification
- Rockchip RK3399
- 2GB/4GB DDR3
- 16GB eMMC
- SD card slot
- RTL8211E 1Gbps
- AP6356S WiFI/BT
- HDMI In/Out, DP, MIPI DSI/CSI
- Mini PCIe
- Sensors, Keys etc
- DC12V-2A and DC5V-2A

Commit details about Linux DTS sync:
"arm64: dts: rockchip: Add support for the Orange Pi RK3399"
(sha1: d3e71487a790979057c0fdbf32f85033639c16e6)

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Showing 5 changed files with 861 additions and 0 deletions Side-by-side Diff

arch/arm/dts/Makefile
... ... @@ -74,6 +74,7 @@
74 74 rk3288-fennec.dtb \
75 75 rk3288-firefly.dtb \
76 76 rk3288-miqi.dtb \
  77 + rk3399-orangepi.dtb \
77 78 rk3288-phycore-rdk.dtb \
78 79 rk3288-popmetal.dtb \
79 80 rk3288-rock2-square.dtb \
arch/arm/dts/rk3399-orangepi-u-boot.dtsi
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
  4 + */
  5 +
  6 +#include "rk3399-u-boot.dtsi"
  7 +#include "rk3399-sdram-ddr3-1333.dtsi"
arch/arm/dts/rk3399-orangepi.dts
  1 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2 +/*
  3 + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
  4 + */
  5 +
  6 +/dts-v1/;
  7 +
  8 +#include "dt-bindings/pwm/pwm.h"
  9 +#include "dt-bindings/input/input.h"
  10 +#include "rk3399.dtsi"
  11 +#include "rk3399-opp.dtsi"
  12 +
  13 +/ {
  14 + model = "Orange Pi RK3399 Board";
  15 + compatible = "rockchip,rk3399-orangepi", "rockchip,rk3399";
  16 +
  17 + chosen {
  18 + stdout-path = "serial2:1500000n8";
  19 + };
  20 +
  21 + clkin_gmac: external-gmac-clock {
  22 + compatible = "fixed-clock";
  23 + clock-frequency = <125000000>;
  24 + clock-output-names = "clkin_gmac";
  25 + #clock-cells = <0>;
  26 + };
  27 +
  28 + adc-keys {
  29 + compatible = "adc-keys";
  30 + io-channels = <&saradc 1>;
  31 + io-channel-names = "buttons";
  32 + keyup-threshold-microvolt = <1800000>;
  33 + poll-interval = <100>;
  34 +
  35 + button-up {
  36 + label = "Volume Up";
  37 + linux,code = <KEY_VOLUMEUP>;
  38 + press-threshold-microvolt = <100000>;
  39 + };
  40 +
  41 + button-down {
  42 + label = "Volume Down";
  43 + linux,code = <KEY_VOLUMEDOWN>;
  44 + press-threshold-microvolt = <300000>;
  45 + };
  46 +
  47 + back {
  48 + label = "Back";
  49 + linux,code = <KEY_BACK>;
  50 + press-threshold-microvolt = <985000>;
  51 + };
  52 +
  53 + menu {
  54 + label = "Menu";
  55 + linux,code = <KEY_MENU>;
  56 + press-threshold-microvolt = <1314000>;
  57 + };
  58 + };
  59 +
  60 + dc_12v: dc-12v {
  61 + compatible = "regulator-fixed";
  62 + regulator-name = "dc_12v";
  63 + regulator-always-on;
  64 + regulator-boot-on;
  65 + regulator-min-microvolt = <12000000>;
  66 + regulator-max-microvolt = <12000000>;
  67 + };
  68 +
  69 + keys: gpio-keys {
  70 + compatible = "gpio-keys";
  71 + autorepeat;
  72 +
  73 + power {
  74 + debounce-interval = <100>;
  75 + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
  76 + label = "GPIO Power";
  77 + linux,code = <KEY_POWER>;
  78 + linux,input-type = <1>;
  79 + pinctrl-names = "default";
  80 + pinctrl-0 = <&pwr_btn>;
  81 + wakeup-source;
  82 + };
  83 + };
  84 +
  85 + sdio_pwrseq: sdio-pwrseq {
  86 + compatible = "mmc-pwrseq-simple";
  87 + clocks = <&rk808 1>;
  88 + clock-names = "ext_clock";
  89 + pinctrl-names = "default";
  90 + pinctrl-0 = <&wifi_reg_on_h>;
  91 + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
  92 + };
  93 +
  94 + /* switched by pmic_sleep */
  95 + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
  96 + compatible = "regulator-fixed";
  97 + regulator-name = "vcc1v8_s3";
  98 + regulator-always-on;
  99 + regulator-boot-on;
  100 + regulator-min-microvolt = <1800000>;
  101 + regulator-max-microvolt = <1800000>;
  102 + vin-supply = <&vcc_1v8>;
  103 + };
  104 +
  105 + vcc3v0_sd: vcc3v0-sd {
  106 + compatible = "regulator-fixed";
  107 + enable-active-high;
  108 + gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
  109 + pinctrl-names = "default";
  110 + pinctrl-0 = <&sdmmc0_pwr_h>;
  111 + regulator-boot-on;
  112 + regulator-max-microvolt = <3000000>;
  113 + regulator-min-microvolt = <3000000>;
  114 + regulator-name = "vcc3v0_sd";
  115 + vin-supply = <&vcc3v3_sys>;
  116 + };
  117 +
  118 + vcc3v3_sys: vcc3v3-sys {
  119 + compatible = "regulator-fixed";
  120 + regulator-name = "vcc3v3_sys";
  121 + regulator-always-on;
  122 + regulator-boot-on;
  123 + regulator-min-microvolt = <3300000>;
  124 + regulator-max-microvolt = <3300000>;
  125 + vin-supply = <&vcc_sys>;
  126 + };
  127 +
  128 + vcc5v0_host: vcc5v0-host-regulator {
  129 + compatible = "regulator-fixed";
  130 + enable-active-high;
  131 + gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
  132 + pinctrl-names = "default";
  133 + pinctrl-0 = <&vcc5v0_host_en>;
  134 + regulator-name = "vcc5v0_host";
  135 + regulator-always-on;
  136 + vin-supply = <&vcc_sys>;
  137 + };
  138 +
  139 + vcc5v0_typec0: vcc5v0-typec0-regulator {
  140 + compatible = "regulator-fixed";
  141 + enable-active-high;
  142 + gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
  143 + pinctrl-names = "default";
  144 + pinctrl-0 = <&vcc5v0_typec0_en>;
  145 + regulator-name = "vcc5v0_typec0";
  146 + vin-supply = <&vcc_sys>;
  147 + };
  148 +
  149 + vcc_sys: vcc-sys {
  150 + compatible = "regulator-fixed";
  151 + regulator-name = "vcc_sys";
  152 + regulator-always-on;
  153 + regulator-boot-on;
  154 + regulator-min-microvolt = <5000000>;
  155 + regulator-max-microvolt = <5000000>;
  156 + vin-supply = <&dc_12v>;
  157 + };
  158 +
  159 + vdd_log: vdd-log {
  160 + compatible = "pwm-regulator";
  161 + pwms = <&pwm2 0 25000 1>;
  162 + regulator-name = "vdd_log";
  163 + regulator-always-on;
  164 + regulator-boot-on;
  165 + regulator-min-microvolt = <800000>;
  166 + regulator-max-microvolt = <1400000>;
  167 + vin-supply = <&vcc_sys>;
  168 + };
  169 +};
  170 +
  171 +&cpu_l0 {
  172 + cpu-supply = <&vdd_cpu_l>;
  173 +};
  174 +
  175 +&cpu_l1 {
  176 + cpu-supply = <&vdd_cpu_l>;
  177 +};
  178 +
  179 +&cpu_l2 {
  180 + cpu-supply = <&vdd_cpu_l>;
  181 +};
  182 +
  183 +&cpu_l3 {
  184 + cpu-supply = <&vdd_cpu_l>;
  185 +};
  186 +
  187 +&cpu_b0 {
  188 + cpu-supply = <&vdd_cpu_b>;
  189 +};
  190 +
  191 +&cpu_b1 {
  192 + cpu-supply = <&vdd_cpu_b>;
  193 +};
  194 +
  195 +&emmc_phy {
  196 + status = "okay";
  197 +};
  198 +
  199 +&gmac {
  200 + assigned-clocks = <&cru SCLK_RMII_SRC>;
  201 + assigned-clock-parents = <&clkin_gmac>;
  202 + clock_in_out = "input";
  203 + phy-supply = <&vcc3v3_s3>;
  204 + phy-mode = "rgmii";
  205 + pinctrl-names = "default";
  206 + pinctrl-0 = <&rgmii_pins>;
  207 + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
  208 + snps,reset-active-low;
  209 + snps,reset-delays-us = <0 10000 50000>;
  210 + tx_delay = <0x28>;
  211 + rx_delay = <0x11>;
  212 + status = "okay";
  213 +};
  214 +
  215 +&gpu {
  216 + mali-supply = <&vdd_gpu>;
  217 + status = "okay";
  218 +};
  219 +
  220 +&hdmi {
  221 + ddc-i2c-bus = <&i2c3>;
  222 + status = "okay";
  223 +};
  224 +
  225 +&hdmi_sound {
  226 + status = "okay";
  227 +};
  228 +
  229 +&i2c0 {
  230 + clock-frequency = <400000>;
  231 + i2c-scl-rising-time-ns = <168>;
  232 + i2c-scl-falling-time-ns = <4>;
  233 + status = "okay";
  234 +
  235 + rk808: pmic@1b {
  236 + compatible = "rockchip,rk808";
  237 + reg = <0x1b>;
  238 + interrupt-parent = <&gpio1>;
  239 + interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
  240 + #clock-cells = <1>;
  241 + clock-output-names = "rtc_clko_soc", "rtc_clko_wifi";
  242 + pinctrl-names = "default";
  243 + pinctrl-0 = <&pmic_int_l>;
  244 + rockchip,system-power-controller;
  245 + wakeup-source;
  246 +
  247 + vcc1-supply = <&vcc3v3_sys>;
  248 + vcc2-supply = <&vcc3v3_sys>;
  249 + vcc3-supply = <&vcc3v3_sys>;
  250 + vcc4-supply = <&vcc3v3_sys>;
  251 + vcc6-supply = <&vcc3v3_sys>;
  252 + vcc7-supply = <&vcc3v3_sys>;
  253 + vcc8-supply = <&vcc3v3_sys>;
  254 + vcc9-supply = <&vcc3v3_sys>;
  255 + vcc10-supply = <&vcc3v3_sys>;
  256 + vcc11-supply = <&vcc3v3_sys>;
  257 + vcc12-supply = <&vcc3v3_sys>;
  258 + vddio-supply = <&vcc_3v0>;
  259 +
  260 + regulators {
  261 + vdd_center: DCDC_REG1 {
  262 + regulator-name = "vdd_center";
  263 + regulator-always-on;
  264 + regulator-boot-on;
  265 + regulator-min-microvolt = <700000>;
  266 + regulator-max-microvolt = <1500000>;
  267 + regulator-ramp-delay = <6001>;
  268 + regulator-state-mem {
  269 + regulator-off-in-suspend;
  270 + };
  271 + };
  272 +
  273 + vdd_cpu_l: DCDC_REG2 {
  274 + regulator-name = "vdd_cpu_l";
  275 + regulator-always-on;
  276 + regulator-boot-on;
  277 + regulator-min-microvolt = <700000>;
  278 + regulator-max-microvolt = <1500000>;
  279 + regulator-ramp-delay = <6001>;
  280 + regulator-state-mem {
  281 + regulator-off-in-suspend;
  282 + };
  283 + };
  284 +
  285 + vcc_ddr: DCDC_REG3 {
  286 + regulator-name = "vcc_ddr";
  287 + regulator-always-on;
  288 + regulator-boot-on;
  289 + regulator-state-mem {
  290 + regulator-on-in-suspend;
  291 + };
  292 + };
  293 +
  294 + vcc_1v8: DCDC_REG4 {
  295 + regulator-name = "vcc_1v8";
  296 + regulator-always-on;
  297 + regulator-boot-on;
  298 + regulator-min-microvolt = <1800000>;
  299 + regulator-max-microvolt = <3300000>;
  300 + regulator-state-mem {
  301 + regulator-on-in-suspend;
  302 + regulator-suspend-microvolt = <1800000>;
  303 + };
  304 + };
  305 +
  306 + vcc1v8_dvp: LDO_REG1 {
  307 + regulator-name = "vcc1v8_dvp";
  308 + regulator-always-on;
  309 + regulator-boot-on;
  310 + regulator-min-microvolt = <1800000>;
  311 + regulator-max-microvolt = <3400000>;
  312 + regulator-state-mem {
  313 + regulator-off-in-suspend;
  314 + };
  315 + };
  316 +
  317 + vcc3v0_tp: LDO_REG2 {
  318 + regulator-name = "vcc3v0_tp";
  319 + regulator-always-on;
  320 + regulator-boot-on;
  321 + regulator-min-microvolt = <1800000>;
  322 + regulator-max-microvolt = <3400000>;
  323 + regulator-state-mem {
  324 + regulator-off-in-suspend;
  325 + };
  326 + };
  327 +
  328 + vcc1v8_pmupll: LDO_REG3 {
  329 + regulator-name = "vcc1v8_pmupll";
  330 + regulator-always-on;
  331 + regulator-boot-on;
  332 + regulator-min-microvolt = <800000>;
  333 + regulator-max-microvolt = <2500000>;
  334 + regulator-state-mem {
  335 + regulator-on-in-suspend;
  336 + regulator-suspend-microvolt = <1800000>;
  337 + };
  338 + };
  339 +
  340 + vcc_sdio: LDO_REG4 {
  341 + regulator-name = "vcc_sdio";
  342 + regulator-always-on;
  343 + regulator-boot-on;
  344 + regulator-min-microvolt = <1800000>;
  345 + regulator-max-microvolt = <3400000>;
  346 + regulator-state-mem {
  347 + regulator-on-in-suspend;
  348 + regulator-suspend-microvolt = <3000000>;
  349 + };
  350 + };
  351 +
  352 + vcca3v0_codec: LDO_REG5 {
  353 + regulator-name = "vcca3v0_codec";
  354 + regulator-always-on;
  355 + regulator-boot-on;
  356 + regulator-min-microvolt = <1800000>;
  357 + regulator-max-microvolt = <3400000>;
  358 + regulator-state-mem {
  359 + regulator-off-in-suspend;
  360 + };
  361 + };
  362 +
  363 + vcc_1v5: LDO_REG6 {
  364 + regulator-name = "vcc_1v5";
  365 + regulator-always-on;
  366 + regulator-boot-on;
  367 + regulator-min-microvolt = <800000>;
  368 + regulator-max-microvolt = <2500000>;
  369 + regulator-state-mem {
  370 + regulator-on-in-suspend;
  371 + regulator-suspend-microvolt = <1500000>;
  372 + };
  373 + };
  374 +
  375 + vcca1v8_codec: LDO_REG7 {
  376 + regulator-name = "vcca1v8_codec";
  377 + regulator-always-on;
  378 + regulator-boot-on;
  379 + regulator-min-microvolt = <800000>;
  380 + regulator-max-microvolt = <2500000>;
  381 + regulator-state-mem {
  382 + regulator-off-in-suspend;
  383 + };
  384 + };
  385 +
  386 + vcc_3v0: LDO_REG8 {
  387 + regulator-name = "vcc_3v0";
  388 + regulator-always-on;
  389 + regulator-boot-on;
  390 + regulator-min-microvolt = <1800000>;
  391 + regulator-max-microvolt = <3400000>;
  392 + regulator-state-mem {
  393 + regulator-on-in-suspend;
  394 + regulator-suspend-microvolt = <3000000>;
  395 + };
  396 + };
  397 +
  398 + vcc3v3_s3: SWITCH_REG1 {
  399 + regulator-name = "vcc3v3_s3";
  400 + regulator-always-on;
  401 + regulator-boot-on;
  402 + regulator-state-mem {
  403 + regulator-off-in-suspend;
  404 + };
  405 + };
  406 +
  407 + vcc3v3_s0: SWITCH_REG2 {
  408 + regulator-name = "vcc3v3_s0";
  409 + regulator-always-on;
  410 + regulator-boot-on;
  411 + regulator-state-mem {
  412 + regulator-off-in-suspend;
  413 + };
  414 + };
  415 + };
  416 + };
  417 +
  418 + vdd_cpu_b: regulator@40 {
  419 + compatible = "silergy,syr827";
  420 + reg = <0x40>;
  421 + fcs,suspend-voltage-selector = <1>;
  422 + regulator-name = "vdd_cpu_b";
  423 + regulator-min-microvolt = <712500>;
  424 + regulator-max-microvolt = <1500000>;
  425 + regulator-ramp-delay = <1000>;
  426 + regulator-always-on;
  427 + regulator-boot-on;
  428 + vin-supply = <&vcc3v3_sys>;
  429 +
  430 + regulator-state-mem {
  431 + regulator-off-in-suspend;
  432 + };
  433 + };
  434 +
  435 + vdd_gpu: regulator@41 {
  436 + compatible = "silergy,syr828";
  437 + reg = <0x41>;
  438 + fcs,suspend-voltage-selector = <1>;
  439 + regulator-name = "vdd_gpu";
  440 + regulator-min-microvolt = <712500>;
  441 + regulator-max-microvolt = <1500000>;
  442 + regulator-ramp-delay = <1000>;
  443 + regulator-always-on;
  444 + regulator-boot-on;
  445 + vin-supply = <&vcc3v3_sys>;
  446 +
  447 + regulator-state-mem {
  448 + regulator-off-in-suspend;
  449 + };
  450 + };
  451 +};
  452 +
  453 +&i2c1 {
  454 + i2c-scl-rising-time-ns = <450>;
  455 + i2c-scl-falling-time-ns = <15>;
  456 + status = "okay";
  457 +};
  458 +
  459 +&i2c3 {
  460 + i2c-scl-rising-time-ns = <450>;
  461 + i2c-scl-falling-time-ns = <15>;
  462 + status = "okay";
  463 +};
  464 +
  465 +&i2c4 {
  466 + clock-frequency = <400000>;
  467 + i2c-scl-rising-time-ns = <450>;
  468 + i2c-scl-falling-time-ns = <15>;
  469 + status = "okay";
  470 +
  471 + ak09911@c {
  472 + compatible = "asahi-kasei,ak09911";
  473 + reg = <0x0c>;
  474 + vdd-supply = <&vcc3v3_s3>;
  475 + };
  476 +
  477 + mpu6500@68 {
  478 + compatible = "invensense,mpu6500";
  479 + reg = <0x68>;
  480 + interrupt-parent = <&gpio1>;
  481 + interrupts = <RK_PC6 IRQ_TYPE_EDGE_RISING>;
  482 + pinctrl-names = "default";
  483 + pinctrl-0 = <&gsensor_int_l>;
  484 + vddio-supply = <&vcc3v3_s3>;
  485 + };
  486 +
  487 + lsm6ds3@6a {
  488 + compatible = "st,lsm6ds3";
  489 + reg = <0x6a>;
  490 + interrupt-parent = <&gpio1>;
  491 + interrupts = <RK_PD0 IRQ_TYPE_EDGE_RISING>;
  492 + pinctrl-names = "default";
  493 + pinctrl-0 = <&gyr_int_l>;
  494 + vdd-supply = <&vcc3v3_s3>;
  495 + vddio-supply = <&vcc3v3_s3>;
  496 + };
  497 +
  498 + cm32181@10 {
  499 + compatible = "capella,cm32181";
  500 + reg = <0x10>;
  501 + interrupt-parent = <&gpio4>;
  502 + interrupts = <RK_PD0 IRQ_TYPE_EDGE_RISING>;
  503 + pinctrl-names = "default";
  504 + pinctrl-0 = <&light_int_l>;
  505 + vdd-supply = <&vcc3v3_s3>;
  506 + };
  507 +};
  508 +
  509 +&io_domains {
  510 + status = "okay";
  511 + bt656-supply = <&vcc_3v0>;
  512 + audio-supply = <&vcca1v8_codec>;
  513 + sdmmc-supply = <&vcc_sdio>;
  514 + gpio1830-supply = <&vcc_3v0>;
  515 +};
  516 +
  517 +&pmu_io_domains {
  518 + status = "okay";
  519 + pmu1830-supply = <&vcc_3v0>;
  520 +};
  521 +
  522 +&pinctrl {
  523 + buttons {
  524 + pwr_btn: pwr-btn {
  525 + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
  526 + };
  527 + };
  528 +
  529 + pmic {
  530 + pmic_int_l: pmic-int-l {
  531 + rockchip,pins =
  532 + <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
  533 + };
  534 + };
  535 +
  536 + sd {
  537 + sdmmc0_pwr_h: sdmmc0-pwr-h {
  538 + rockchip,pins =
  539 + <RK_GPIO0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
  540 + };
  541 + };
  542 +
  543 + usb2 {
  544 + vcc5v0_host_en: vcc5v0-host-en {
  545 + rockchip,pins =
  546 + <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
  547 + };
  548 +
  549 + vcc5v0_typec0_en: vcc5v0-typec0-en {
  550 + rockchip,pins =
  551 + <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
  552 + };
  553 + };
  554 +
  555 + sdio-pwrseq {
  556 + wifi_reg_on_h: wifi-reg-on-h {
  557 + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
  558 + };
  559 + };
  560 +
  561 + wifi {
  562 + wifi_host_wake_l: wifi-host-wake-l {
  563 + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
  564 + };
  565 + };
  566 +
  567 + bluetooth {
  568 + bt_reg_on_h: bt-enable-h {
  569 + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
  570 + };
  571 +
  572 + bt_host_wake_l: bt-host-wake-l {
  573 + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
  574 + };
  575 +
  576 + bt_wake_l: bt-wake-l {
  577 + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
  578 + };
  579 + };
  580 +
  581 + mpu6500 {
  582 + gsensor_int_l: gsensor-int-l {
  583 + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
  584 + };
  585 + };
  586 +
  587 + lsm6ds3 {
  588 + gyr_int_l: gyr-int-l {
  589 + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
  590 + };
  591 + };
  592 +
  593 + cm32181 {
  594 + light_int_l: light-int-l {
  595 + rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
  596 + };
  597 + };
  598 +};
  599 +
  600 +&pwm0 {
  601 + status = "okay";
  602 +};
  603 +
  604 +&pwm2 {
  605 + status = "okay";
  606 +};
  607 +
  608 +&saradc {
  609 + vref-supply = <&vcca1v8_s3>;
  610 + status = "okay";
  611 +};
  612 +
  613 +&sdhci {
  614 + bus-width = <8>;
  615 + mmc-hs400-1_8v;
  616 + mmc-hs400-enhanced-strobe;
  617 + non-removable;
  618 + status = "okay";
  619 +};
  620 +
  621 +&sdio0 {
  622 + bus-width = <4>;
  623 + cap-sd-highspeed;
  624 + cap-sdio-irq;
  625 + clock-frequency = <50000000>;
  626 + disable-wp;
  627 + keep-power-in-suspend;
  628 + max-frequency = <50000000>;
  629 + mmc-pwrseq = <&sdio_pwrseq>;
  630 + non-removable;
  631 + pinctrl-names = "default";
  632 + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
  633 + sd-uhs-sdr104;
  634 + status = "okay";
  635 +
  636 + brcmf: wifi@1 {
  637 + compatible = "brcm,bcm4329-fmac";
  638 + interrupt-parent = <&gpio0>;
  639 + interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
  640 + interrupt-names = "host-wake";
  641 + pinctrl-names = "default";
  642 + pinctrl-0 = <&wifi_host_wake_l>;
  643 + };
  644 +};
  645 +
  646 +&sdmmc {
  647 + bus-width = <4>;
  648 + cap-mmc-highspeed;
  649 + cap-sd-highspeed;
  650 + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
  651 + clock-frequency = <150000000>;
  652 + disable-wp;
  653 + max-frequency = <150000000>;
  654 + pinctrl-names = "default";
  655 + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
  656 + vmmc-supply = <&vcc3v0_sd>;
  657 + vqmmc-supply = <&vcc_sdio>;
  658 + status = "okay";
  659 +};
  660 +
  661 +&tcphy0 {
  662 + status = "okay";
  663 +};
  664 +
  665 +&tcphy1 {
  666 + status = "okay";
  667 +};
  668 +
  669 +&tsadc {
  670 + rockchip,hw-tshut-mode = <1>;
  671 + rockchip,hw-tshut-polarity = <1>;
  672 + status = "okay";
  673 +};
  674 +
  675 +&u2phy0 {
  676 + status = "okay";
  677 +
  678 + u2phy0_otg: otg-port {
  679 + phy-supply = <&vcc5v0_typec0>;
  680 + status = "okay";
  681 + };
  682 +
  683 + u2phy0_host: host-port {
  684 + phy-supply = <&vcc5v0_host>;
  685 + status = "okay";
  686 + };
  687 +};
  688 +
  689 +&u2phy1 {
  690 + status = "okay";
  691 +
  692 + u2phy1_otg: otg-port {
  693 + status = "okay";
  694 + };
  695 +
  696 + u2phy1_host: host-port {
  697 + phy-supply = <&vcc5v0_host>;
  698 + status = "okay";
  699 + };
  700 +};
  701 +
  702 +&uart0 {
  703 + pinctrl-names = "default";
  704 + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
  705 + status = "okay";
  706 +
  707 + bluetooth {
  708 + compatible = "brcm,bcm43438-bt";
  709 + clocks = <&rk808 1>;
  710 + clock-names = "ext_clock";
  711 + device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
  712 + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
  713 + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
  714 + pinctrl-names = "default";
  715 + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>;
  716 + };
  717 +};
  718 +
  719 +&uart2 {
  720 + status = "okay";
  721 +};
  722 +
  723 +&usb_host0_ehci {
  724 + status = "okay";
  725 +};
  726 +
  727 +&usb_host0_ohci {
  728 + status = "okay";
  729 +};
  730 +
  731 +&usb_host1_ehci {
  732 + status = "okay";
  733 +};
  734 +
  735 +&usb_host1_ohci {
  736 + status = "okay";
  737 +};
  738 +
  739 +&usbdrd3_0 {
  740 + status = "okay";
  741 +};
  742 +
  743 +&usbdrd_dwc3_0 {
  744 + status = "okay";
  745 + dr_mode = "otg";
  746 +};
  747 +
  748 +&usbdrd3_1 {
  749 + status = "okay";
  750 +};
  751 +
  752 +&usbdrd_dwc3_1 {
  753 + status = "okay";
  754 + dr_mode = "host";
  755 +};
  756 +
  757 +&vopb {
  758 + status = "okay";
  759 +};
  760 +
  761 +&vopb_mmu {
  762 + status = "okay";
  763 +};
  764 +
  765 +&vopl {
  766 + status = "okay";
  767 +};
  768 +
  769 +&vopl_mmu {
  770 + status = "okay";
  771 +};
board/rockchip/evb_rk3399/MAINTAINERS
... ... @@ -5,4 +5,11 @@
5 5 F: include/configs/evb_rk3399.h
6 6 F: configs/evb-rk3399_defconfig
7 7 F: configs/firefly-rk3399_defconfig
  8 +
  9 +ORANGEPI-RK3399
  10 +M: Jagan Teki <jagan@amarulasolutions.com>
  11 +S: Maintained
  12 +F: configs/orangepi-rk3399_defconfig
  13 +F: arch/arm/dts/rk3399-u-boot.dtsi
  14 +F: arch/arm/dts/rk3399-orangepi-u-boot.dtsi
configs/orangepi-rk3399_defconfig
  1 +CONFIG_ARM=y
  2 +CONFIG_ARCH_ROCKCHIP=y
  3 +CONFIG_SYS_TEXT_BASE=0x00200000
  4 +CONFIG_SPL_LIBCOMMON_SUPPORT=y
  5 +CONFIG_SPL_LIBGENERIC_SUPPORT=y
  6 +CONFIG_SYS_MALLOC_F_LEN=0x4000
  7 +CONFIG_ROCKCHIP_RK3399=y
  8 +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
  9 +CONFIG_DEBUG_UART_BASE=0xFF1A0000
  10 +CONFIG_DEBUG_UART_CLOCK=24000000
  11 +CONFIG_SPL_STACK_R_ADDR=0x80000
  12 +CONFIG_DEBUG_UART=y
  13 +CONFIG_NR_DRAM_BANKS=1
  14 +CONFIG_FIT=y
  15 +CONFIG_SPL_LOAD_FIT=y
  16 +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
  17 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb"
  18 +# CONFIG_DISPLAY_CPUINFO is not set
  19 +CONFIG_DISPLAY_BOARDINFO_LATE=y
  20 +CONFIG_SPL_STACK_R=y
  21 +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
  22 +CONFIG_SPL_ATF=y
  23 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
  24 +CONFIG_CMD_BOOTZ=y
  25 +CONFIG_CMD_GPT=y
  26 +CONFIG_CMD_MMC=y
  27 +CONFIG_CMD_SF=y
  28 +CONFIG_CMD_USB=y
  29 +# CONFIG_CMD_SETEXPR is not set
  30 +CONFIG_CMD_TIME=y
  31 +CONFIG_SPL_OF_CONTROL=y
  32 +CONFIG_DEFAULT_DEVICE_TREE="rk3399-orangepi"
  33 +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
  34 +CONFIG_ENV_IS_IN_MMC=y
  35 +CONFIG_REGMAP=y
  36 +CONFIG_SPL_REGMAP=y
  37 +CONFIG_SYSCON=y
  38 +CONFIG_SPL_SYSCON=y
  39 +CONFIG_CLK=y
  40 +CONFIG_SPL_CLK=y
  41 +CONFIG_ROCKCHIP_GPIO=y
  42 +CONFIG_SYS_I2C_ROCKCHIP=y
  43 +CONFIG_MMC_DW=y
  44 +CONFIG_MMC_DW_ROCKCHIP=y
  45 +CONFIG_MMC_SDHCI=y
  46 +CONFIG_MMC_SDHCI_ROCKCHIP=y
  47 +CONFIG_DM_ETH=y
  48 +CONFIG_ETH_DESIGNWARE=y
  49 +CONFIG_GMAC_ROCKCHIP=y
  50 +CONFIG_PINCTRL=y
  51 +CONFIG_SPL_PINCTRL=y
  52 +CONFIG_DM_PMIC=y
  53 +CONFIG_PMIC_RK8XX=y
  54 +CONFIG_REGULATOR_PWM=y
  55 +CONFIG_DM_REGULATOR_FIXED=y
  56 +CONFIG_REGULATOR_RK8XX=y
  57 +CONFIG_PWM_ROCKCHIP=y
  58 +CONFIG_RAM=y
  59 +CONFIG_SPL_RAM=y
  60 +CONFIG_BAUDRATE=1500000
  61 +CONFIG_DEBUG_UART_SHIFT=2
  62 +CONFIG_SYSRESET=y
  63 +CONFIG_USB=y
  64 +CONFIG_USB_XHCI_HCD=y
  65 +CONFIG_USB_XHCI_DWC3=y
  66 +CONFIG_USB_EHCI_HCD=y
  67 +CONFIG_USB_EHCI_GENERIC=y
  68 +CONFIG_USB_HOST_ETHER=y
  69 +CONFIG_USB_ETHER_ASIX=y
  70 +CONFIG_USB_ETHER_ASIX88179=y
  71 +CONFIG_USB_ETHER_MCS7830=y
  72 +CONFIG_USB_ETHER_RTL8152=y
  73 +CONFIG_USB_ETHER_SMSC95XX=y
  74 +CONFIG_USE_TINY_PRINTF=y
  75 +CONFIG_ERRNO_STR=y