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Commit ee7d755a58403fe342a97e40c3e64184d0197992

Authored by Simon Glass
Committed by Tom Warren
1 parent d2f906500e
Exists in v2017.01-smarct4x and in 30 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

tegra: dts: Sync tegra20.dtsi with Linux v4.4 

This file has changed quite a bit since it was set up. Sync it back with
Linux v4.4. Adjust the users slightly to cope with the changes:

- the host1x node is now called host1x@50000000
- we need a clocks node to provide the clk32k_in phandle
- active usb nodes need status = "okay"
- active i2c nodes need status = "okay"

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

Showing 12 changed files with 560 additions and 271 deletions Side-by-side Diff

arch/arm/dts/tegra20-colibri.dts
Diff comments   View file @ ee7d755
... ... @@ -20,7 +20,7 @@
20 20 sdhci0 = "/sdhci@c8000600";
21 21 };
22 22  
23   - host1x {
  23 + host1x@50000000 {
24 24 status = "okay";
25 25 dc@54200000 {
26 26 status = "okay";
27 27  
28 28  
... ... @@ -32,16 +32,19 @@
32 32 };
33 33  
34 34 usb@c5000000 {
  35 + statuc = "okay";
35 36 dr_mode = "otg";
36 37 };
37 38  
38 39 usb@c5004000 {
  40 + statuc = "okay";
39 41 /* VBUS_LAN */
40 42 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
41 43 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
42 44 };
43 45  
44 46 usb@c5008000 {
  47 + statuc = "okay";
45 48 /* USBH_PEN */
46 49 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
47 50 };
... ... @@ -86,6 +89,19 @@
86 89 status = "okay";
87 90 bus-width = <4>;
88 91 cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
  92 + };
  93 +
  94 + clocks {
  95 + compatible = "simple-bus";
  96 + #address-cells = <1>;
  97 + #size-cells = <0>;
  98 +
  99 + clk32k_in: clock@0 {
  100 + compatible = "fixed-clock";
  101 + reg=<0>;
  102 + #clock-cells = <0>;
  103 + clock-frequency = <32768>;
  104 + };
89 105 };
90 106  
91 107 lcd_panel: panel {
arch/arm/dts/tegra20-harmony.dts
Diff comments   View file @ ee7d755
... ... @@ -21,7 +21,7 @@
21 21 reg = <0x00000000 0x40000000>;
22 22 };
23 23  
24   - host1x {
  24 + host1x@50000000 {
25 25 status = "okay";
26 26 dc@54200000 {
27 27 status = "okay";
28 28  
29 29  
... ... @@ -46,30 +46,15 @@
46 46 };
47 47 };
48 48  
49   - i2c@7000c000 {
50   - status = "disabled";
51   - };
52   -
53   - i2c@7000c400 {
54   - status = "disabled";
55   - };
56   -
57   - i2c@7000c500 {
58   - status = "disabled";
59   - };
60   -
61   - i2c@7000d000 {
62   - status = "disabled";
63   - };
64   -
65   - usb@c5000000 {
66   - status = "disabled";
67   - };
68   -
69 49 usb@c5004000 {
  50 + statuc = "okay";
70 51 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 0>;
71 52 };
72 53  
  54 + usb@c5008000 {
  55 + status = "okay";
  56 + };
  57 +
73 58 sdhci@c8000200 {
74 59 status = "okay";
75 60 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
... ... @@ -84,6 +69,19 @@
84 69 wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
85 70 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
86 71 bus-width = <8>;
  72 + };
  73 +
  74 + clocks {
  75 + compatible = "simple-bus";
  76 + #address-cells = <1>;
  77 + #size-cells = <0>;
  78 +
  79 + clk32k_in: clock@0 {
  80 + compatible = "fixed-clock";
  81 + reg=<0>;
  82 + #clock-cells = <0>;
  83 + clock-frequency = <32768>;
  84 + };
87 85 };
88 86  
89 87 lcd_panel: panel {
arch/arm/dts/tegra20-medcom-wide.dts
Diff comments   View file @ ee7d755
... ... @@ -19,7 +19,7 @@
19 19 reg = <0x00000000 0x20000000>;
20 20 };
21 21  
22   - host1x {
  22 + host1x@50000000 {
23 23 status = "okay";
24 24  
25 25 dc@54200000 {
... ... @@ -36,28 +36,8 @@
36 36 clock-frequency = <216000000>;
37 37 };
38 38  
39   - i2c@7000c000 {
40   - status = "disabled";
41   - };
42   -
43   - i2c@7000c400 {
44   - status = "disabled";
45   - };
46   -
47   - i2c@7000c500 {
48   - status = "disabled";
49   - };
50   -
51   - i2c@7000d000 {
52   - status = "disabled";
53   - };
54   -
55   - usb@c5000000 {
56   - status = "disabled";
57   - };
58   -
59   - usb@c5004000 {
60   - status = "disabled";
  39 + usb@c5008000 {
  40 + status = "okay";
61 41 };
62 42  
63 43 lcd_panel: panel {
arch/arm/dts/tegra20-paz00.dts
Diff comments   View file @ ee7d755
... ... @@ -20,7 +20,7 @@
20 20 reg = <0x00000000 0x20000000>;
21 21 };
22 22  
23   - host1x {
  23 + host1x@50000000 {
24 24 status = "okay";
25 25 dc@54200000 {
26 26 status = "okay";
27 27  
... ... @@ -35,30 +35,10 @@
35 35 clock-frequency = < 216000000 >;
36 36 };
37 37  
38   - i2c@7000c000 {
39   - status = "disabled";
  38 + usb@c5008000 {
  39 + status = "okay";
40 40 };
41 41  
42   - i2c@7000c400 {
43   - status = "disabled";
44   - };
45   -
46   - i2c@7000c500 {
47   - status = "disabled";
48   - };
49   -
50   - i2c@7000d000 {
51   - status = "disabled";
52   - };
53   -
54   - usb@c5000000 {
55   - status = "disabled";
56   - };
57   -
58   - usb@c5004000 {
59   - status = "disabled";
60   - };
61   -
62 42 sdhci@c8000000 {
63 43 status = "okay";
64 44 cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
... ... @@ -70,6 +50,19 @@
70 50 sdhci@c8000600 {
71 51 status = "okay";
72 52 bus-width = <8>;
  53 + };
  54 +
  55 + clocks {
  56 + compatible = "simple-bus";
  57 + #address-cells = <1>;
  58 + #size-cells = <0>;
  59 +
  60 + clk32k_in: clock@0 {
  61 + compatible = "fixed-clock";
  62 + reg=<0>;
  63 + #clock-cells = <0>;
  64 + clock-frequency = <32768>;
  65 + };
73 66 };
74 67  
75 68 lcd_panel: panel {
arch/arm/dts/tegra20-plutux.dts
Diff comments   View file @ ee7d755
... ... @@ -38,13 +38,5 @@
38 38 i2c@7000d000 {
39 39 status = "disabled";
40 40 };
41   -
42   - usb@c5000000 {
43   - status = "disabled";
44   - };
45   -
46   - usb@c5004000 {
47   - status = "disabled";
48   - };
49 41 };
arch/arm/dts/tegra20-seaboard.dts
Diff comments   View file @ ee7d755
... ... @@ -31,7 +31,7 @@
31 31 reg = < 0x00000000 0x40000000 >;
32 32 };
33 33  
34   - host1x {
  34 + host1x@50000000 {
35 35 status = "okay";
36 36 dc@54200000 {
37 37 status = "okay";
... ... @@ -44,6 +44,7 @@
44 44  
45 45 /* This is not used in U-Boot, but is expected to be in kernel .dts */
46 46 i2c@7000d000 {
  47 + status = "okay";
47 48 clock-frequency = <100000>;
48 49 pmic@34 {
49 50 compatible = "ti,tps6586x";
50 51  
51 52  
52 53  
... ... @@ -75,18 +76,21 @@
75 76 };
76 77  
77 78 i2c@7000c000 {
  79 + status = "okay";
78 80 clock-frequency = <100000>;
79 81 };
80 82  
81 83 i2c@7000c400 {
82   - status = "disabled";
  84 + status = "okay";
83 85 };
84 86  
85 87 i2c@7000c500 {
  88 + status = "okay";
86 89 clock-frequency = <100000>;
87 90 };
88 91  
89 92 kbc@7000e200 {
  93 + status = "okay";
90 94 linux,keymap = <0x00020011 0x0003001f 0x0004001e 0x0005002c
91 95 0x000701d0 0x0107007d 0x02060064 0x02070038 0x03000006
92 96 0x03010005 0x03020013 0x03030012 0x03040021 0x03050020
... ... @@ -114,6 +118,8 @@
114 118 };
115 119  
116 120 emc@7000f400 {
  121 + #address-cells = <1>;
  122 + #size-cells = <0>;
117 123 emc-table@190000 {
118 124 reg = < 190000 >;
119 125 compatible = "nvidia,tegra20-emc-table";
... ... @@ -151,6 +157,7 @@
151 157 };
152 158  
153 159 usb@c5000000 {
  160 + status = "okay";
154 161 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
155 162 dr_mode = "otg";
156 163 };
... ... @@ -159,6 +166,10 @@
159 166 status = "disabled";
160 167 };
161 168  
  169 + usb@c5008000 {
  170 + status = "okay";
  171 + };
  172 +
162 173 sdhci@c8000400 {
163 174 status = "okay";
164 175 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
... ... @@ -170,6 +181,19 @@
170 181 sdhci@c8000600 {
171 182 status = "okay";
172 183 bus-width = <8>;
  184 + };
  185 +
  186 + clocks {
  187 + compatible = "simple-bus";
  188 + #address-cells = <1>;
  189 + #size-cells = <0>;
  190 +
  191 + clk32k_in: clock@0 {
  192 + compatible = "fixed-clock";
  193 + reg=<0>;
  194 + #clock-cells = <0>;
  195 + clock-frequency = <32768>;
  196 + };
173 197 };
174 198  
175 199 lcd_panel: panel {
arch/arm/dts/tegra20-tamonten.dtsi
Diff comments   View file @ ee7d755
... ... @@ -8,7 +8,7 @@
8 8 reg = <0x00000000 0x20000000>;
9 9 };
10 10  
11   - host1x {
  11 + host1x@50000000 {
12 12 hdmi {
13 13 vdd-supply = <&hdmi_vdd_reg>;
14 14 pll-supply = <&hdmi_pll_reg>;
... ... @@ -481,6 +481,19 @@
481 481 wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
482 482 bus-width = <4>;
483 483 status = "okay";
  484 + };
  485 +
  486 + clocks {
  487 + compatible = "simple-bus";
  488 + #address-cells = <1>;
  489 + #size-cells = <0>;
  490 +
  491 + clk32k_in: clock@0 {
  492 + compatible = "fixed-clock";
  493 + reg=<0>;
  494 + #clock-cells = <0>;
  495 + clock-frequency = <32768>;
  496 + };
484 497 };
485 498  
486 499 regulators {
arch/arm/dts/tegra20-tec.dts
Diff comments   View file @ ee7d755
... ... @@ -19,7 +19,7 @@
19 19 reg = <0x00000000 0x20000000>;
20 20 };
21 21  
22   - host1x {
  22 + host1x@50000000 {
23 23 status = "okay";
24 24  
25 25 dc@54200000 {
... ... @@ -49,14 +49,6 @@
49 49 };
50 50  
51 51 i2c@7000d000 {
52   - status = "disabled";
53   - };
54   -
55   - usb@c5000000 {
56   - status = "disabled";
57   - };
58   -
59   - usb@c5004000 {
60 52 status = "disabled";
61 53 };
62 54  
arch/arm/dts/tegra20-trimslice.dts
Diff comments   View file @ ee7d755
... ... @@ -26,27 +26,11 @@
26 26 clock-frequency = <216000000>;
27 27 };
28 28  
29   - i2c@7000c000 {
30   - status = "disabled";
31   - };
32   -
33 29 spi@7000c380 {
34 30 status = "okay";
35 31 spi-max-frequency = <25000000>;
36 32 };
37 33  
38   - i2c@7000c400 {
39   - status = "disabled";
40   - };
41   -
42   - i2c@7000c500 {
43   - status = "disabled";
44   - };
45   -
46   - i2c@7000d000 {
47   - status = "disabled";
48   - };
49   -
50 34 pcie-controller@80003000 {
51 35 status = "okay";
52 36  
53 37  
... ... @@ -62,13 +46,10 @@
62 46 };
63 47  
64 48 usb@c5000000 {
  49 + status = "okay";
65 50 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
66 51 };
67 52  
68   - usb@c5004000 {
69   - status = "disabled";
70   - };
71   -
72 53 sdhci@c8000000 {
73 54 status = "okay";
74 55 bus-width = <4>;
... ... @@ -79,6 +60,19 @@
79 60 cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
80 61 wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
81 62 bus-width = <4>;
  63 + };
  64 +
  65 + clocks {
  66 + compatible = "simple-bus";
  67 + #address-cells = <1>;
  68 + #size-cells = <0>;
  69 +
  70 + clk32k_in: clock@0 {
  71 + compatible = "fixed-clock";
  72 + reg=<0>;
  73 + #clock-cells = <0>;
  74 + clock-frequency = <32768>;
  75 + };
82 76 };
83 77  
84 78 regulators {
arch/arm/dts/tegra20-ventana.dts
Diff comments   View file @ ee7d755
... ... @@ -20,7 +20,7 @@
20 20 reg = <0x00000000 0x40000000>;
21 21 };
22 22  
23   - host1x {
  23 + host1x@50000000 {
24 24 status = "okay";
25 25 dc@54200000 {
26 26 status = "okay";
27 27  
... ... @@ -35,30 +35,10 @@
35 35 clock-frequency = < 216000000 >;
36 36 };
37 37  
38   - i2c@7000c000 {
39   - status = "disabled";
  38 + usb@c5008000 {
  39 + status = "okay";
40 40 };
41 41  
42   - i2c@7000c400 {
43   - status = "disabled";
44   - };
45   -
46   - i2c@7000c500 {
47   - status = "disabled";
48   - };
49   -
50   - i2c@7000d000 {
51   - status = "disabled";
52   - };
53   -
54   - usb@c5000000 {
55   - status = "disabled";
56   - };
57   -
58   - usb@c5004000 {
59   - status = "disabled";
60   - };
61   -
62 42 sdhci@c8000400 {
63 43 status = "okay";
64 44 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
... ... @@ -70,6 +50,19 @@
70 50 sdhci@c8000600 {
71 51 status = "okay";
72 52 bus-width = <8>;
  53 + };
  54 +
  55 + clocks {
  56 + compatible = "simple-bus";
  57 + #address-cells = <1>;
  58 + #size-cells = <0>;
  59 +
  60 + clk32k_in: clock@0 {
  61 + compatible = "fixed-clock";
  62 + reg=<0>;
  63 + #clock-cells = <0>;
  64 + clock-frequency = <32768>;
  65 + };
73 66 };
74 67  
75 68 lcd_panel: panel {
arch/arm/dts/tegra20-whistler.dts
Diff comments   View file @ ee7d755
... ... @@ -26,19 +26,8 @@
26 26 clock-frequency = < 216000000 >;
27 27 };
28 28  
29   - i2c@7000c000 {
30   - status = "disabled";
31   - };
32   -
33   - i2c@7000c400 {
34   - status = "disabled";
35   - };
36   -
37   - i2c@7000c500 {
38   - status = "disabled";
39   - };
40   -
41 29 i2c@7000d000 {
  30 + status = "okay";
42 31 clock-frequency = <100000>;
43 32  
44 33 pmic@3c {
45 34  
... ... @@ -56,14 +45,10 @@
56 45 };
57 46 };
58 47  
59   - usb@c5000000 {
60   - status = "disabled";
  48 + usb@c5008000 {
  49 + status = "okay";
61 50 };
62 51  
63   - usb@c5004000 {
64   - status = "disabled";
65   - };
66   -
67 52 sdhci@c8000400 {
68 53 status = "okay";
69 54 wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
... ... @@ -74,5 +59,19 @@
74 59 status = "okay";
75 60 bus-width = <8>;
76 61 };
  62 +
  63 + clocks {
  64 + compatible = "simple-bus";
  65 + #address-cells = <1>;
  66 + #size-cells = <0>;
  67 +
  68 + clk32k_in: clock@0 {
  69 + compatible = "fixed-clock";
  70 + reg=<0>;
  71 + #clock-cells = <0>;
  72 + clock-frequency = <32768>;
  73 + };
  74 + };
  75 +
77 76 };
arch/arm/dts/tegra20.dtsi
Diff comments   View file @ ee7d755
1 1 #include <dt-bindings/clock/tegra20-car.h>
2 2 #include <dt-bindings/gpio/tegra-gpio.h>
  3 +#include <dt-bindings/pinctrl/pinctrl-tegra.h>
3 4 #include <dt-bindings/interrupt-controller/arm-gic.h>
4 5  
5 6 #include "skeleton.dtsi"
6 7  
7 8 / {
8 9 compatible = "nvidia,tegra20";
9   - interrupt-parent = <&intc>;
  10 + interrupt-parent = <&lic>;
10 11  
11   - host1x {
  12 + host1x@50000000 {
12 13 compatible = "nvidia,tegra20-host1x", "simple-bus";
13 14 reg = <0x50000000 0x00024000>;
14   - interrupts = <0 65 0x04 /* mpcore syncpt */
15   - 0 67 0x04>; /* mpcore general */
16   - status = "disabled";
  15 + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  16 + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  17 + clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
  18 + resets = <&tegra_car 28>;
  19 + reset-names = "host1x";
17 20  
18 21 #address-cells = <1>;
19 22 #size-cells = <1>;
20 23  
21 24 ranges = <0x54000000 0x54000000 0x04000000>;
22 25  
23   - /* video-encoding/decoding */
24   - mpe {
  26 + mpe@54040000 {
  27 + compatible = "nvidia,tegra20-mpe";
25 28 reg = <0x54040000 0x00040000>;
26   - interrupts = <0 68 0x04>;
27   - status = "disabled";
  29 + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
  30 + clocks = <&tegra_car TEGRA20_CLK_MPE>;
  31 + resets = <&tegra_car 60>;
  32 + reset-names = "mpe";
28 33 };
29 34  
30   - /* video input */
31   - vi {
  35 + vi@54080000 {
  36 + compatible = "nvidia,tegra20-vi";
32 37 reg = <0x54080000 0x00040000>;
33   - interrupts = <0 69 0x04>;
34   - status = "disabled";
  38 + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
  39 + clocks = <&tegra_car TEGRA20_CLK_VI>;
  40 + resets = <&tegra_car 20>;
  41 + reset-names = "vi";
35 42 };
36 43  
37   - /* EPP */
38   - epp {
  44 + epp@540c0000 {
  45 + compatible = "nvidia,tegra20-epp";
39 46 reg = <0x540c0000 0x00040000>;
40   - interrupts = <0 70 0x04>;
41   - status = "disabled";
  47 + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
  48 + clocks = <&tegra_car TEGRA20_CLK_EPP>;
  49 + resets = <&tegra_car 19>;
  50 + reset-names = "epp";
42 51 };
43 52  
44   - /* ISP */
45   - isp {
  53 + isp@54100000 {
  54 + compatible = "nvidia,tegra20-isp";
46 55 reg = <0x54100000 0x00040000>;
47   - interrupts = <0 71 0x04>;
48   - status = "disabled";
  56 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  57 + clocks = <&tegra_car TEGRA20_CLK_ISP>;
  58 + resets = <&tegra_car 23>;
  59 + reset-names = "isp";
49 60 };
50 61  
51   - /* 2D engine */
52   - gr2d {
  62 + gr2d@54140000 {
  63 + compatible = "nvidia,tegra20-gr2d";
53 64 reg = <0x54140000 0x00040000>;
54   - interrupts = <0 72 0x04>;
55   - status = "disabled";
  65 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  66 + clocks = <&tegra_car TEGRA20_CLK_GR2D>;
  67 + resets = <&tegra_car 21>;
  68 + reset-names = "2d";
56 69 };
57 70  
58   - /* 3D engine */
59   - gr3d {
  71 + gr3d@54180000 {
  72 + compatible = "nvidia,tegra20-gr3d";
60 73 reg = <0x54180000 0x00040000>;
61   - status = "disabled";
  74 + clocks = <&tegra_car TEGRA20_CLK_GR3D>;
  75 + resets = <&tegra_car 24>;
  76 + reset-names = "3d";
62 77 };
63 78  
64   - /* display controllers */
65 79 dc@54200000 {
66 80 compatible = "nvidia,tegra20-dc";
67 81 reg = <0x54200000 0x00040000>;
68   - interrupts = <0 73 0x04>;
69   - status = "disabled";
  82 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  83 + clocks = <&tegra_car TEGRA20_CLK_DISP1>,
  84 + <&tegra_car TEGRA20_CLK_PLL_P>;
  85 + clock-names = "dc", "parent";
  86 + resets = <&tegra_car 27>;
  87 + reset-names = "dc";
70 88  
  89 + nvidia,head = <0>;
  90 +
71 91 rgb {
72 92 status = "disabled";
73 93 };
74 94  
75 95  
76 96  
77 97  
78 98  
79 99  
80 100  
81 101  
82 102  
83 103  
84 104  
85 105  
86 106  
87 107  
88 108  
... ... @@ -76,71 +96,140 @@
76 96 dc@54240000 {
77 97 compatible = "nvidia,tegra20-dc";
78 98 reg = <0x54240000 0x00040000>;
79   - interrupts = <0 74 0x04>;
80   - status = "disabled";
  99 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  100 + clocks = <&tegra_car TEGRA20_CLK_DISP2>,
  101 + <&tegra_car TEGRA20_CLK_PLL_P>;
  102 + clock-names = "dc", "parent";
  103 + resets = <&tegra_car 26>;
  104 + reset-names = "dc";
81 105  
  106 + nvidia,head = <1>;
  107 +
82 108 rgb {
83 109 status = "disabled";
84 110 };
85 111 };
86 112  
87   - /* outputs */
88   - hdmi {
  113 + hdmi@54280000 {
89 114 compatible = "nvidia,tegra20-hdmi";
90 115 reg = <0x54280000 0x00040000>;
91   - interrupts = <0 75 0x04>;
  116 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  117 + clocks = <&tegra_car TEGRA20_CLK_HDMI>,
  118 + <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
  119 + clock-names = "hdmi", "parent";
  120 + resets = <&tegra_car 51>;
  121 + reset-names = "hdmi";
92 122 status = "disabled";
93 123 };
94 124  
95   - tvo {
  125 + tvo@542c0000 {
96 126 compatible = "nvidia,tegra20-tvo";
97 127 reg = <0x542c0000 0x00040000>;
98   - interrupts = <0 76 0x04>;
  128 + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
  129 + clocks = <&tegra_car TEGRA20_CLK_TVO>;
99 130 status = "disabled";
100 131 };
101 132  
102   - dsi {
  133 + dsi@54300000 {
103 134 compatible = "nvidia,tegra20-dsi";
104 135 reg = <0x54300000 0x00040000>;
  136 + clocks = <&tegra_car TEGRA20_CLK_DSI>;
  137 + resets = <&tegra_car 48>;
  138 + reset-names = "dsi";
105 139 status = "disabled";
106 140 };
107 141 };
108 142  
  143 + timer@50040600 {
  144 + compatible = "arm,cortex-a9-twd-timer";
  145 + interrupt-parent = <&intc>;
  146 + reg = <0x50040600 0x20>;
  147 + interrupts = <GIC_PPI 13
  148 + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  149 + clocks = <&tegra_car TEGRA20_CLK_TWD>;
  150 + };
  151 +
109 152 intc: interrupt-controller@50041000 {
110   - compatible = "nvidia,tegra20-gic";
  153 + compatible = "arm,cortex-a9-gic";
  154 + reg = <0x50041000 0x1000
  155 + 0x50040100 0x0100>;
111 156 interrupt-controller;
112   - #interrupt-cells = <1>;
113   - reg = < 0x50041000 0x1000 >,
114   - < 0x50040100 0x0100 >;
  157 + #interrupt-cells = <3>;
  158 + interrupt-parent = <&intc>;
115 159 };
116 160  
  161 + cache-controller@50043000 {
  162 + compatible = "arm,pl310-cache";
  163 + reg = <0x50043000 0x1000>;
  164 + arm,data-latency = <5 5 2>;
  165 + arm,tag-latency = <4 4 2>;
  166 + cache-unified;
  167 + cache-level = <2>;
  168 + };
  169 +
  170 + lic: interrupt-controller@60004000 {
  171 + compatible = "nvidia,tegra20-ictlr";
  172 + reg = <0x60004000 0x100>,
  173 + <0x60004100 0x50>,
  174 + <0x60004200 0x50>,
  175 + <0x60004300 0x50>;
  176 + interrupt-controller;
  177 + #interrupt-cells = <3>;
  178 + interrupt-parent = <&intc>;
  179 + };
  180 +
  181 + timer@60005000 {
  182 + compatible = "nvidia,tegra20-timer";
  183 + reg = <0x60005000 0x60>;
  184 + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  185 + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
  186 + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
  187 + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
  188 + clocks = <&tegra_car TEGRA20_CLK_TIMER>;
  189 + };
  190 +
117 191 tegra_car: clock@60006000 {
118 192 compatible = "nvidia,tegra20-car";
119 193 reg = <0x60006000 0x1000>;
120 194 #clock-cells = <1>;
  195 + #reset-cells = <1>;
121 196 };
122 197  
123   - apbdma: dma {
  198 + flow-controller@60007000 {
  199 + compatible = "nvidia,tegra20-flowctrl";
  200 + reg = <0x60007000 0x1000>;
  201 + };
  202 +
  203 + apbdma: dma@6000a000 {
124 204 compatible = "nvidia,tegra20-apbdma";
125 205 reg = <0x6000a000 0x1200>;
126   - interrupts = <0 104 0x04
127   - 0 105 0x04
128   - 0 106 0x04
129   - 0 107 0x04
130   - 0 108 0x04
131   - 0 109 0x04
132   - 0 110 0x04
133   - 0 111 0x04
134   - 0 112 0x04
135   - 0 113 0x04
136   - 0 114 0x04
137   - 0 115 0x04
138   - 0 116 0x04
139   - 0 117 0x04
140   - 0 118 0x04
141   - 0 119 0x04>;
  206 + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
  207 + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
  208 + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
  209 + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
  210 + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
  211 + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
  212 + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
  213 + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
  214 + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
  215 + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
  216 + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
  217 + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
  218 + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
  219 + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
  220 + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
  221 + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
  222 + clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
  223 + resets = <&tegra_car 34>;
  224 + reset-names = "dma";
  225 + #dma-cells = <1>;
142 226 };
143 227  
  228 + ahb@6000c000 {
  229 + compatible = "nvidia,tegra20-ahb";
  230 + reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */
  231 + };
  232 +
144 233 gpio: gpio@6000d000 {
145 234 compatible = "nvidia,tegra20-gpio";
146 235 reg = <0x6000d000 0x1000>;
147 236  
148 237  
149 238  
150 239  
151 240  
152 241  
153 242  
154 243  
... ... @@ -155,41 +244,73 @@
155 244 gpio-controller;
156 245 #interrupt-cells = <2>;
157 246 interrupt-controller;
  247 + /*
  248 + gpio-ranges = <&pinmux 0 0 224>;
  249 + */
158 250 };
159 251  
160   - pinmux: pinmux@70000000 {
  252 + apbmisc@70000800 {
  253 + compatible = "nvidia,tegra20-apbmisc";
  254 + reg = <0x70000800 0x64 /* Chip revision */
  255 + 0x70000008 0x04>; /* Strapping options */
  256 + };
  257 +
  258 + pinmux: pinmux@70000014 {
161 259 compatible = "nvidia,tegra20-pinmux";
162   - reg = < 0x70000014 0x10 /* Tri-state registers */
163   - 0x70000080 0x20 /* Mux registers */
164   - 0x700000a0 0x14 /* Pull-up/down registers */
165   - 0x70000868 0xa8 >; /* Pad control registers */
  260 + reg = <0x70000014 0x10 /* Tri-state registers */
  261 + 0x70000080 0x20 /* Mux registers */
  262 + 0x700000a0 0x14 /* Pull-up/down registers */
  263 + 0x70000868 0xa8>; /* Pad control registers */
166 264 };
167 265  
168 266 das@70000c00 {
169   - #address-cells = <1>;
170   - #size-cells = <0>;
171 267 compatible = "nvidia,tegra20-das";
172 268 reg = <0x70000c00 0x80>;
173 269 };
174 270  
175   - i2s@70002800 {
176   - #address-cells = <1>;
177   - #size-cells = <0>;
  271 + tegra_ac97: ac97@70002000 {
  272 + compatible = "nvidia,tegra20-ac97";
  273 + reg = <0x70002000 0x200>;
  274 + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
  275 + clocks = <&tegra_car TEGRA20_CLK_AC97>;
  276 + resets = <&tegra_car 3>;
  277 + reset-names = "ac97";
  278 + dmas = <&apbdma 12>, <&apbdma 12>;
  279 + dma-names = "rx", "tx";
  280 + status = "disabled";
  281 + };
  282 +
  283 + tegra_i2s1: i2s@70002800 {
178 284 compatible = "nvidia,tegra20-i2s";
179 285 reg = <0x70002800 0x200>;
180   - interrupts = < 45 >;
181   - dma-channel = < 2 >;
  286 + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
  287 + clocks = <&tegra_car TEGRA20_CLK_I2S1>;
  288 + resets = <&tegra_car 11>;
  289 + reset-names = "i2s";
  290 + dmas = <&apbdma 2>, <&apbdma 2>;
  291 + dma-names = "rx", "tx";
  292 + status = "disabled";
182 293 };
183 294  
184   - i2s@70002a00 {
185   - #address-cells = <1>;
186   - #size-cells = <0>;
  295 + tegra_i2s2: i2s@70002a00 {
187 296 compatible = "nvidia,tegra20-i2s";
188 297 reg = <0x70002a00 0x200>;
189   - interrupts = < 35 >;
190   - dma-channel = < 1 >;
  298 + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  299 + clocks = <&tegra_car TEGRA20_CLK_I2S2>;
  300 + resets = <&tegra_car 18>;
  301 + reset-names = "i2s";
  302 + dmas = <&apbdma 1>, <&apbdma 1>;
  303 + dma-names = "rx", "tx";
  304 + status = "disabled";
191 305 };
192 306  
  307 + /*
  308 + * There are two serial driver i.e. 8250 based simple serial
  309 + * driver and APB DMA based serial driver for higher baudrate
  310 + * and performace. To enable the 8250 based driver, the compatible
  311 + * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
  312 + * driver, the comptible is "nvidia,tegra20-hsuart".
  313 + */
193 314 uarta: serial@70006000 {
194 315 compatible = "nvidia,tegra20-uart";
195 316 reg = <0x70006000 0x40>;
196 317  
197 318  
198 319  
199 320  
200 321  
201 322  
202 323  
203 324  
204 325  
205 326  
206 327  
207 328  
... ... @@ -266,58 +387,95 @@
266 387 compatible = "nvidia,tegra20-pwm";
267 388 reg = <0x7000a000 0x100>;
268 389 #pwm-cells = <2>;
  390 + clocks = <&tegra_car TEGRA20_CLK_PWM>;
  391 + resets = <&tegra_car 17>;
  392 + reset-names = "pwm";
  393 + status = "disabled";
269 394 };
270 395  
  396 + rtc@7000e000 {
  397 + compatible = "nvidia,tegra20-rtc";
  398 + reg = <0x7000e000 0x100>;
  399 + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
  400 + clocks = <&tegra_car TEGRA20_CLK_RTC>;
  401 + };
  402 +
271 403 i2c@7000c000 {
  404 + compatible = "nvidia,tegra20-i2c";
  405 + reg = <0x7000c000 0x100>;
  406 + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
272 407 #address-cells = <1>;
273 408 #size-cells = <0>;
274   - compatible = "nvidia,tegra20-i2c";
275   - reg = <0x7000C000 0x100>;
276   - interrupts = < 70 >;
277   - /* PERIPH_ID_I2C1, PLL_P_OUT3 */
278   - clocks = <&tegra_car 12>, <&tegra_car 124>;
  409 + clocks = <&tegra_car TEGRA20_CLK_I2C1>,
  410 + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
  411 + clock-names = "div-clk", "fast-clk";
  412 + resets = <&tegra_car 12>;
  413 + reset-names = "i2c";
  414 + dmas = <&apbdma 21>, <&apbdma 21>;
  415 + dma-names = "rx", "tx";
  416 + status = "disabled";
279 417 };
280 418  
281 419 spi@7000c380 {
282 420 compatible = "nvidia,tegra20-sflash";
283 421 reg = <0x7000c380 0x80>;
284   - interrupts = <0 39 0x04>;
285   - nvidia,dma-request-selector = <&apbdma 11>;
  422 + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
286 423 #address-cells = <1>;
287 424 #size-cells = <0>;
  425 + clocks = <&tegra_car TEGRA20_CLK_SPI>;
  426 + resets = <&tegra_car 43>;
  427 + reset-names = "spi";
  428 + dmas = <&apbdma 11>, <&apbdma 11>;
  429 + dma-names = "rx", "tx";
288 430 status = "disabled";
289   - /* PERIPH_ID_SPI1, PLLP_OUT0 */
290   - clocks = <&tegra_car 43>;
291 431 };
292 432  
293 433 i2c@7000c400 {
  434 + compatible = "nvidia,tegra20-i2c";
  435 + reg = <0x7000c400 0x100>;
  436 + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
294 437 #address-cells = <1>;
295 438 #size-cells = <0>;
296   - compatible = "nvidia,tegra20-i2c";
297   - reg = <0x7000C400 0x100>;
298   - interrupts = < 116 >;
299   - /* PERIPH_ID_I2C2, PLL_P_OUT3 */
300   - clocks = <&tegra_car 54>, <&tegra_car 124>;
  439 + clocks = <&tegra_car TEGRA20_CLK_I2C2>,
  440 + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
  441 + clock-names = "div-clk", "fast-clk";
  442 + resets = <&tegra_car 54>;
  443 + reset-names = "i2c";
  444 + dmas = <&apbdma 22>, <&apbdma 22>;
  445 + dma-names = "rx", "tx";
  446 + status = "disabled";
301 447 };
302 448  
303 449 i2c@7000c500 {
  450 + compatible = "nvidia,tegra20-i2c";
  451 + reg = <0x7000c500 0x100>;
  452 + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
304 453 #address-cells = <1>;
305 454 #size-cells = <0>;
306   - compatible = "nvidia,tegra20-i2c";
307   - reg = <0x7000C500 0x100>;
308   - interrupts = < 124 >;
309   - /* PERIPH_ID_I2C3, PLL_P_OUT3 */
310   - clocks = <&tegra_car 67>, <&tegra_car 124>;
  455 + clocks = <&tegra_car TEGRA20_CLK_I2C3>,
  456 + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
  457 + clock-names = "div-clk", "fast-clk";
  458 + resets = <&tegra_car 67>;
  459 + reset-names = "i2c";
  460 + dmas = <&apbdma 23>, <&apbdma 23>;
  461 + dma-names = "rx", "tx";
  462 + status = "disabled";
311 463 };
312 464  
313 465 i2c@7000d000 {
  466 + compatible = "nvidia,tegra20-i2c-dvc";
  467 + reg = <0x7000d000 0x200>;
  468 + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
314 469 #address-cells = <1>;
315 470 #size-cells = <0>;
316   - compatible = "nvidia,tegra20-i2c-dvc";
317   - reg = <0x7000D000 0x200>;
318   - interrupts = < 85 >;
319   - /* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */
320   - clocks = <&tegra_car 47>, <&tegra_car 124>;
  471 + clocks = <&tegra_car TEGRA20_CLK_DVC>,
  472 + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
  473 + clock-names = "div-clk", "fast-clk";
  474 + resets = <&tegra_car 47>;
  475 + reset-names = "i2c";
  476 + dmas = <&apbdma 24>, <&apbdma 24>;
  477 + dma-names = "rx", "tx";
  478 + status = "disabled";
321 479 };
322 480  
323 481 spi@7000d400 {
324 482  
325 483  
326 484  
327 485  
... ... @@ -376,19 +534,52 @@
376 534 status = "disabled";
377 535 };
378 536  
379   -
380 537 kbc@7000e200 {
381 538 compatible = "nvidia,tegra20-kbc";
382   - reg = <0x7000e200 0x0078>;
  539 + reg = <0x7000e200 0x100>;
  540 + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
  541 + clocks = <&tegra_car TEGRA20_CLK_KBC>;
  542 + resets = <&tegra_car 36>;
  543 + reset-names = "kbc";
  544 + status = "disabled";
383 545 };
384 546  
385   - emc@7000f400 {
386   - #address-cells = < 1 >;
387   - #size-cells = < 0 >;
  547 + pmc@7000e400 {
  548 + compatible = "nvidia,tegra20-pmc";
  549 + reg = <0x7000e400 0x400>;
  550 + clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
  551 + clock-names = "pclk", "clk32k_in";
  552 + };
  553 +
  554 + memory-controller@7000f000 {
  555 + compatible = "nvidia,tegra20-mc";
  556 + reg = <0x7000f000 0x024
  557 + 0x7000f03c 0x3c4>;
  558 + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  559 + };
  560 +
  561 + iommu@7000f024 {
  562 + compatible = "nvidia,tegra20-gart";
  563 + reg = <0x7000f024 0x00000018 /* controller registers */
  564 + 0x58000000 0x02000000>; /* GART aperture */
  565 + };
  566 +
  567 + memory-controller@7000f400 {
388 568 compatible = "nvidia,tegra20-emc";
389 569 reg = <0x7000f400 0x200>;
  570 + #address-cells = <1>;
  571 + #size-cells = <0>;
390 572 };
391 573  
  574 + fuse@7000f800 {
  575 + compatible = "nvidia,tegra20-efuse";
  576 + reg = <0x7000f800 0x400>;
  577 + clocks = <&tegra_car TEGRA20_CLK_FUSE>;
  578 + clock-names = "fuse";
  579 + resets = <&tegra_car 39>;
  580 + reset-names = "fuse";
  581 + };
  582 +
392 583 pcie-controller@80003000 {
393 584 compatible = "nvidia,tegra20-pcie";
394 585 device_type = "pci";
395 586  
... ... @@ -416,9 +607,12 @@
416 607  
417 608 clocks = <&tegra_car TEGRA20_CLK_PEX>,
418 609 <&tegra_car TEGRA20_CLK_AFI>,
419   - <&tegra_car TEGRA20_CLK_PCIE_XCLK>,
420 610 <&tegra_car TEGRA20_CLK_PLL_E>;
421   - clock-names = "pex", "afi", "pcie_xclk", "pll_e";
  611 + clock-names = "pex", "afi", "pll_e";
  612 + resets = <&tegra_car 70>,
  613 + <&tegra_car 72>,
  614 + <&tegra_car 74>;
  615 + reset-names = "pex", "afi", "pcie_x";
422 616 status = "disabled";
423 617  
424 618 pci@1,0 {
425 619  
426 620  
427 621  
428 622  
429 623  
430 624  
431 625  
432 626  
433 627  
434 628  
435 629  
436 630  
437 631  
438 632  
... ... @@ -451,58 +645,159 @@
451 645 usb@c5000000 {
452 646 compatible = "nvidia,tegra20-ehci", "usb-ehci";
453 647 reg = <0xc5000000 0x4000>;
454   - interrupts = < 52 >;
  648 + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
455 649 phy_type = "utmi";
456   - clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */
457 650 nvidia,has-legacy-mode;
  651 + clocks = <&tegra_car TEGRA20_CLK_USBD>;
  652 + resets = <&tegra_car 22>;
  653 + reset-names = "usb";
  654 + nvidia,needs-double-reset;
  655 + nvidia,phy = <&phy1>;
  656 + status = "disabled";
458 657 };
459 658  
  659 + phy1: usb-phy@c5000000 {
  660 + compatible = "nvidia,tegra20-usb-phy";
  661 + reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
  662 + phy_type = "utmi";
  663 + clocks = <&tegra_car TEGRA20_CLK_USBD>,
  664 + <&tegra_car TEGRA20_CLK_PLL_U>,
  665 + <&tegra_car TEGRA20_CLK_CLK_M>,
  666 + <&tegra_car TEGRA20_CLK_USBD>;
  667 + clock-names = "reg", "pll_u", "timer", "utmi-pads";
  668 + resets = <&tegra_car 22>, <&tegra_car 22>;
  669 + reset-names = "usb", "utmi-pads";
  670 + nvidia,has-legacy-mode;
  671 + nvidia,hssync-start-delay = <9>;
  672 + nvidia,idle-wait-delay = <17>;
  673 + nvidia,elastic-limit = <16>;
  674 + nvidia,term-range-adj = <6>;
  675 + nvidia,xcvr-setup = <9>;
  676 + nvidia,xcvr-lsfslew = <1>;
  677 + nvidia,xcvr-lsrslew = <1>;
  678 + nvidia,has-utmi-pad-registers;
  679 + status = "disabled";
  680 + };
  681 +
460 682 usb@c5004000 {
461 683 compatible = "nvidia,tegra20-ehci", "usb-ehci";
462 684 reg = <0xc5004000 0x4000>;
463   - interrupts = < 53 >;
  685 + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
464 686 phy_type = "ulpi";
465   - clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
  687 + clocks = <&tegra_car TEGRA20_CLK_USB2>;
  688 + resets = <&tegra_car 58>;
  689 + reset-names = "usb";
  690 + nvidia,phy = <&phy2>;
  691 + status = "disabled";
466 692 };
467 693  
  694 + phy2: usb-phy@c5004000 {
  695 + compatible = "nvidia,tegra20-usb-phy";
  696 + reg = <0xc5004000 0x4000>;
  697 + phy_type = "ulpi";
  698 + clocks = <&tegra_car TEGRA20_CLK_USB2>,
  699 + <&tegra_car TEGRA20_CLK_PLL_U>,
  700 + <&tegra_car TEGRA20_CLK_CDEV2>;
  701 + clock-names = "reg", "pll_u", "ulpi-link";
  702 + resets = <&tegra_car 58>, <&tegra_car 22>;
  703 + reset-names = "usb", "utmi-pads";
  704 + status = "disabled";
  705 + };
  706 +
468 707 usb@c5008000 {
469 708 compatible = "nvidia,tegra20-ehci", "usb-ehci";
470 709 reg = <0xc5008000 0x4000>;
471   - interrupts = < 129 >;
  710 + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
472 711 phy_type = "utmi";
473   - clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */
  712 + clocks = <&tegra_car TEGRA20_CLK_USB3>;
  713 + resets = <&tegra_car 59>;
  714 + reset-names = "usb";
  715 + nvidia,phy = <&phy3>;
  716 + status = "disabled";
474 717 };
475 718  
  719 + phy3: usb-phy@c5008000 {
  720 + compatible = "nvidia,tegra20-usb-phy";
  721 + reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
  722 + phy_type = "utmi";
  723 + clocks = <&tegra_car TEGRA20_CLK_USB3>,
  724 + <&tegra_car TEGRA20_CLK_PLL_U>,
  725 + <&tegra_car TEGRA20_CLK_CLK_M>,
  726 + <&tegra_car TEGRA20_CLK_USBD>;
  727 + clock-names = "reg", "pll_u", "timer", "utmi-pads";
  728 + resets = <&tegra_car 59>, <&tegra_car 22>;
  729 + reset-names = "usb", "utmi-pads";
  730 + nvidia,hssync-start-delay = <9>;
  731 + nvidia,idle-wait-delay = <17>;
  732 + nvidia,elastic-limit = <16>;
  733 + nvidia,term-range-adj = <6>;
  734 + nvidia,xcvr-setup = <9>;
  735 + nvidia,xcvr-lsfslew = <2>;
  736 + nvidia,xcvr-lsrslew = <2>;
  737 + status = "disabled";
  738 + };
  739 +
476 740 sdhci@c8000000 {
477 741 compatible = "nvidia,tegra20-sdhci";
478 742 reg = <0xc8000000 0x200>;
479   - interrupts = <0 14 0x04>;
480   - clocks = <&tegra_car 14>;
  743 + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
  744 + clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
  745 + resets = <&tegra_car 14>;
  746 + reset-names = "sdhci";
481 747 status = "disabled";
482 748 };
483 749  
484 750 sdhci@c8000200 {
485 751 compatible = "nvidia,tegra20-sdhci";
486 752 reg = <0xc8000200 0x200>;
487   - interrupts = <0 15 0x04>;
488   - clocks = <&tegra_car 9>;
  753 + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
  754 + clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
  755 + resets = <&tegra_car 9>;
  756 + reset-names = "sdhci";
489 757 status = "disabled";
490 758 };
491 759  
492 760 sdhci@c8000400 {
493 761 compatible = "nvidia,tegra20-sdhci";
494 762 reg = <0xc8000400 0x200>;
495   - interrupts = <0 19 0x04>;
496   - clocks = <&tegra_car 69>;
  763 + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
  764 + clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
  765 + resets = <&tegra_car 69>;
  766 + reset-names = "sdhci";
497 767 status = "disabled";
498 768 };
499 769  
500 770 sdhci@c8000600 {
501 771 compatible = "nvidia,tegra20-sdhci";
502 772 reg = <0xc8000600 0x200>;
503   - interrupts = <0 31 0x04>;
504   - clocks = <&tegra_car 15>;
  773 + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  774 + clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
  775 + resets = <&tegra_car 15>;
  776 + reset-names = "sdhci";
505 777 status = "disabled";
  778 + };
  779 +
  780 + cpus {
  781 + #address-cells = <1>;
  782 + #size-cells = <0>;
  783 +
  784 + cpu@0 {
  785 + device_type = "cpu";
  786 + compatible = "arm,cortex-a9";
  787 + reg = <0>;
  788 + };
  789 +
  790 + cpu@1 {
  791 + device_type = "cpu";
  792 + compatible = "arm,cortex-a9";
  793 + reg = <1>;
  794 + };
  795 + };
  796 +
  797 + pmu {
  798 + compatible = "arm,cortex-a9-pmu";
  799 + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
  800 + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
506 801 };
507 802 };