Eric Lee / smarc-uboot

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Commit ee8d037ce7b5ece66d085c0e6b7793e6e3fbef5b

Authored by Masahiro Yamada
1 parent 609bf92411
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

ARM: uniphier: remove SPL support for ARMv8 SoCs 

It has been a while since ARM Trusted Firmware supported UniPhier SoC
family.  U-Boot SPL was intended as a temporary loader that runs in
secure world.  It is a maintenance headache to support two different
boot mechanisms.  Secure firmware is realm of ARM Trusted Firmware
and now U-Boot only serves as a non-secure boot loader for UniPhier
ARMv8 SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Showing 36 changed files with 45 additions and 2145 deletions Side-by-side Diff

arch/arm/dts/uniphier-ld11-global.dts
Diff comments   View file @ ee8d037
... ... @@ -68,13 +68,4 @@
68 68 &usb2 {
69 69 status = "okay";
70 70 };
71   -
72   -/* for U-Boot only */
73   -&serial0 {
74   - u-boot,dm-pre-reloc;
75   -};
76   -
77   -&pinctrl_uart0 {
78   - u-boot,dm-pre-reloc;
79   -};
arch/arm/dts/uniphier-ld11-ref.dts
Diff comments   View file @ ee8d037
... ... @@ -62,13 +62,4 @@
62 62 &usb2 {
63 63 status = "okay";
64 64 };
65   -
66   -/* for U-Boot only */
67   -&serial0 {
68   - u-boot,dm-pre-reloc;
69   -};
70   -
71   -&pinctrl_uart0 {
72   - u-boot,dm-pre-reloc;
73   -};
arch/arm/dts/uniphier-ld11.dtsi
Diff comments   View file @ ee8d037
... ... @@ -109,7 +109,6 @@
109 109 #address-cells = <1>;
110 110 #size-cells = <1>;
111 111 ranges = <0 0 0 0xffffffff>;
112   - u-boot,dm-pre-reloc;
113 112  
114 113 serial0: serial@54006800 {
115 114 compatible = "socionext,uniphier-uart";
116 115  
... ... @@ -343,11 +342,9 @@
343 342 compatible = "socionext,uniphier-ld11-soc-glue",
344 343 "simple-mfd", "syscon";
345 344 reg = <0x5f800000 0x2000>;
346   - u-boot,dm-pre-reloc;
347 345  
348 346 pinctrl: pinctrl {
349 347 compatible = "socionext,uniphier-ld11-pinctrl";
350   - u-boot,dm-pre-reloc;
351 348 };
352 349 };
353 350  
arch/arm/dts/uniphier-ld20-global.dts
Diff comments   View file @ ee8d037
... ... @@ -50,13 +50,4 @@
50 50 &i2c0 {
51 51 status = "okay";
52 52 };
53   -
54   -/* for U-Boot only */
55   -&serial0 {
56   - u-boot,dm-pre-reloc;
57   -};
58   -
59   -&pinctrl_uart0 {
60   - u-boot,dm-pre-reloc;
61   -};
arch/arm/dts/uniphier-ld20-ref.dts
Diff comments   View file @ ee8d037
... ... @@ -50,13 +50,4 @@
50 50 &i2c0 {
51 51 status = "okay";
52 52 };
53   -
54   -/* for U-Boot only */
55   -&serial0 {
56   - u-boot,dm-pre-reloc;
57   -};
58   -
59   -&pinctrl_uart0 {
60   - u-boot,dm-pre-reloc;
61   -};
arch/arm/dts/uniphier-ld20.dtsi
Diff comments   View file @ ee8d037
... ... @@ -178,7 +178,6 @@
178 178 #address-cells = <1>;
179 179 #size-cells = <1>;
180 180 ranges = <0 0 0 0xffffffff>;
181   - u-boot,dm-pre-reloc;
182 181  
183 182 serial0: serial@54006800 {
184 183 compatible = "socionext,uniphier-uart";
185 184  
... ... @@ -378,11 +377,9 @@
378 377 compatible = "socionext,uniphier-ld20-soc-glue",
379 378 "simple-mfd", "syscon";
380 379 reg = <0x5f800000 0x2000>;
381   - u-boot,dm-pre-reloc;
382 380  
383 381 pinctrl: pinctrl {
384 382 compatible = "socionext,uniphier-ld20-pinctrl";
385   - u-boot,dm-pre-reloc;
386 383 };
387 384 };
388 385  
arch/arm/mach-uniphier/Kconfig
Diff comments   View file @ ee8d037
... ... @@ -10,14 +10,6 @@
10 10 select ARMV7_NONSEC
11 11 select ARCH_SUPPORT_PSCI
12 12  
13   -config ARCH_UNIPHIER_64BIT
14   - bool
15   - select ARM64
16   - select CMD_UNZIP
17   - select SPL_SEPARATE_BSS if SPL
18   - select ARMV8_MULTIENTRY if SPL
19   - select ARMV8_SPIN_TABLE if SPL
20   -
21 13 choice
22 14 prompt "UniPhier SoC select"
23 15 default ARCH_UNIPHIER_PRO4
24 16  
... ... @@ -38,18 +30,11 @@
38 30 bool "UniPhier Pro5/PXs2/LD6b SoCs"
39 31 select ARCH_UNIPHIER_32BIT
40 32  
41   -config ARCH_UNIPHIER_LD11_SINGLE
42   - bool "UniPhier LD11 SoC"
43   - select ARCH_UNIPHIER_64BIT
44   -
45   -config ARCH_UNIPHIER_LD20_SINGLE
46   - bool "UniPhier LD20 SoC"
47   - select ARCH_UNIPHIER_64BIT
48   -
49 33 config ARCH_UNIPHIER_V8_MULTI
50 34 bool "UniPhier V8 SoCs"
51 35 depends on !SPL
52   - select ARCH_UNIPHIER_64BIT
  36 + select ARM64
  37 + select CMD_UNZIP
53 38  
54 39 endchoice
55 40  
56 41  
... ... @@ -79,13 +64,13 @@
79 64 default y
80 65  
81 66 config ARCH_UNIPHIER_LD11
82   - bool "Enable UniPhier LD11 SoC support" if ARCH_UNIPHIER_V8_MULTI
83   - depends on ARCH_UNIPHIER_LD11_SINGLE || ARCH_UNIPHIER_V8_MULTI
  67 + bool "Enable UniPhier LD11 SoC support"
  68 + depends on ARCH_UNIPHIER_V8_MULTI
84 69 default y
85 70  
86 71 config ARCH_UNIPHIER_LD20
87   - bool "Enable UniPhier LD20 SoC support" if ARCH_UNIPHIER_V8_MULTI
88   - depends on ARCH_UNIPHIER_LD20_SINGLE || ARCH_UNIPHIER_V8_MULTI
  72 + bool "Enable UniPhier LD20 SoC support"
  73 + depends on ARCH_UNIPHIER_V8_MULTI
89 74 select OF_BOARD_SETUP
90 75 default y
91 76  
arch/arm/mach-uniphier/arm64/Makefile
Diff comments   View file @ ee8d037
... ... @@ -2,15 +2,6 @@
2 2 # SPDX-License-Identifier: GPL-2.0+
3 3 #
4 4  
5   -ifdef CONFIG_SPL_BUILD
6   -obj-y += timer.o
7   -else
8 5 obj-y += mem_map.o
9   -ifdef CONFIG_ARMV8_MULTIENTRY
10   -obj-y += smp.o smp_kick_cpus.o
11   -obj-$(CONFIG_ARCH_UNIPHIER_LD20) += arm-cci500.o
12   -else
13 6 obj-$(CONFIG_ARCH_UNIPHIER_LD20) += lowlevel_init.o
14   -endif
15   -endif
arch/arm/mach-uniphier/arm64/arm-cci500.c
View file @ ee8d037
1   -/*
2   - * Initialization of ARM Corelink CCI-500 Cache Coherency Interconnect
3   - *
4   - * Copyright (C) 2016 Socionext Inc.
5   - * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6   - *
7   - * SPDX-License-Identifier: GPL-2.0+
8   - */
9   -
10   -#include <linux/bitops.h>
11   -#include <linux/io.h>
12   -#include <linux/sizes.h>
13   -
14   -#include "../init.h"
15   -
16   -#define CCI500_BASE 0x5FD00000
17   -#define CCI500_SLAVE_OFFSET 0x1000
18   -
19   -#define CCI500_SNOOP_CTRL
20   -#define CCI500_SNOOP_CTRL_EN_DVM BIT(1)
21   -#define CCI500_SNOOP_CTRL_EN_SNOOP BIT(0)
22   -
23   -void cci500_init(unsigned int nr_slaves)
24   -{
25   - unsigned long slave_base = CCI500_BASE + CCI500_SLAVE_OFFSET;
26   - int i;
27   -
28   - for (i = 0; i < nr_slaves; i++) {
29   - void __iomem *base;
30   - u32 tmp;
31   -
32   - base = ioremap(slave_base, SZ_4K);
33   -
34   - tmp = readl(base);
35   - tmp |= CCI500_SNOOP_CTRL_EN_DVM | CCI500_SNOOP_CTRL_EN_SNOOP;
36   - writel(tmp, base);
37   -
38   - iounmap(base);
39   -
40   - slave_base += CCI500_SLAVE_OFFSET;
41   - }
42   -}
arch/arm/mach-uniphier/arm64/smp.S
View file @ ee8d037
1   -/*
2   - * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#include <linux/linkage.h>
8   -
9   -ENTRY(uniphier_smp_setup)
10   - mrs x0, s3_1_c15_c2_1 /* CPUECTLR_EL1 */
11   - orr x0, x0, #(1 << 6) /* SMPEN */
12   - msr s3_1_c15_c2_1, x0
13   - ret
14   -ENDPROC(uniphier_smp_setup)
15   -
16   -ENTRY(uniphier_secondary_startup)
17   - bl uniphier_smp_setup
18   - b _start
19   -ENDPROC(uniphier_secondary_startup)
arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
View file @ ee8d037
1   -/*
2   - * Copyright (C) 2016 Socionext Inc.
3   - * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <linux/io.h>
9   -#include <linux/sizes.h>
10   -
11   -#include "../init.h"
12   -
13   -#define UNIPHIER_SMPCTRL_ROM_RSV0 0x59801200
14   -
15   -void uniphier_smp_setup(void);
16   -void uniphier_secondary_startup(void);
17   -
18   -void uniphier_smp_kick_all_cpus(void)
19   -{
20   - void __iomem *rom_boot_rsv0;
21   -
22   - rom_boot_rsv0 = ioremap(UNIPHIER_SMPCTRL_ROM_RSV0, SZ_8);
23   -
24   - writeq((u64)uniphier_secondary_startup, rom_boot_rsv0);
25   -
26   - iounmap(rom_boot_rsv0);
27   -
28   - uniphier_smp_setup();
29   -
30   - asm("dsb ishst\n" /* Ensure the write to ROM_RSV0 is visible */
31   - "sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */
32   -}
arch/arm/mach-uniphier/arm64/timer.c
View file @ ee8d037
1   -/*
2   - * Copyright (C) 2016 Socionext Inc.
3   - * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <linux/bitops.h>
9   -#include <linux/io.h>
10   -#include <linux/sizes.h>
11   -
12   -#define CNT_CONTROL_BASE 0x60E00000
13   -
14   -#define CNTCR 0x000
15   -#define CNTCR_EN BIT(0)
16   -
17   -/* setup ARMv8 Generic Timer */
18   -int timer_init(void)
19   -{
20   - void __iomem *base;
21   - u32 tmp;
22   -
23   - base = ioremap(CNT_CONTROL_BASE, SZ_4K);
24   -
25   - /*
26   - * Note:
27   - * In a system that implements both Secure and Non-secure states,
28   - * this register is only writable in Secure state.
29   - */
30   - tmp = readl(base + CNTCR);
31   - tmp |= CNTCR_EN;
32   - writel(tmp, base + CNTCR);
33   -
34   - iounmap(base);
35   -
36   - return 0;
37   -}
arch/arm/mach-uniphier/board_init.c
Diff comments   View file @ ee8d037
... ... @@ -73,9 +73,6 @@
73 73 writel(0x0000b500, 0x6184e024);
74 74 writel(0x00000001, 0x6184e000);
75 75 }
76   -#ifdef CONFIG_ARMV8_MULTIENTRY
77   - cci500_init(2);
78   -#endif
79 76 }
80 77 #endif
81 78  
... ... @@ -229,12 +226,6 @@
229 226 led_puts("U5");
230 227  
231 228 support_card_late_init();
232   -
233   - led_puts("U6");
234   -
235   -#ifdef CONFIG_ARMV8_MULTIENTRY
236   - uniphier_smp_kick_all_cpus();
237   -#endif
238 229  
239 230 led_puts("Uboo");
240 231  
arch/arm/mach-uniphier/boards.c
Diff comments   View file @ ee8d037
... ... @@ -140,69 +140,6 @@
140 140 };
141 141 #endif
142 142  
143   -#if defined(CONFIG_ARCH_UNIPHIER_LD11)
144   -static const struct uniphier_board_data uniphier_ld11_data = {
145   - .dram_freq = 1600,
146   - .dram_ch[0] = {
147   - .size = 0x20000000,
148   - .width = 16,
149   - },
150   - .dram_ch[1] = {
151   - .size = 0x20000000,
152   - .width = 16,
153   - },
154   -};
155   -#endif
156   -
157   -#if defined(CONFIG_ARCH_UNIPHIER_LD20)
158   -static const struct uniphier_board_data uniphier_ld20_ref_data = {
159   - .dram_freq = 1866,
160   - .dram_ch[0] = {
161   - .size = 0x40000000,
162   - .width = 32,
163   - },
164   - .dram_ch[1] = {
165   - .size = 0x40000000,
166   - .width = 32,
167   - },
168   - .dram_ch[2] = {
169   - .size = 0x40000000,
170   - .width = 32,
171   - },
172   - .flags = UNIPHIER_BD_BOARD_LD20_REF,
173   -};
174   -
175   -static const struct uniphier_board_data uniphier_ld20_data = {
176   - .dram_freq = 1866,
177   - .dram_ch[0] = {
178   - .size = 0x40000000,
179   - .width = 32,
180   - },
181   - .dram_ch[1] = {
182   - .size = 0x40000000,
183   - .width = 32,
184   - },
185   - .dram_ch[2] = {
186   - .size = 0x40000000,
187   - .width = 32,
188   - },
189   - .flags = UNIPHIER_BD_BOARD_LD20_GLOBAL,
190   -};
191   -
192   -static const struct uniphier_board_data uniphier_ld21_data = {
193   - .dram_freq = 1866,
194   - .dram_ch[0] = {
195   - .size = 0x20000000,
196   - .width = 32,
197   - },
198   - .dram_ch[1] = {
199   - .size = 0x40000000,
200   - .width = 32,
201   - },
202   - .flags = UNIPHIER_BD_DRAM_SPARSE | UNIPHIER_BD_BOARD_LD21_GLOBAL,
203   -};
204   -#endif
205   -
206 143 struct uniphier_board_id {
207 144 const char *compatible;
208 145 const struct uniphier_board_data *param;
... ... @@ -231,14 +168,6 @@
231 168 #endif
232 169 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
233 170 { "socionext,uniphier-ld6b", &uniphier_ld6b_data, },
234   -#endif
235   -#if defined(CONFIG_ARCH_UNIPHIER_LD11)
236   - { "socionext,uniphier-ld11", &uniphier_ld11_data, },
237   -#endif
238   -#if defined(CONFIG_ARCH_UNIPHIER_LD20)
239   - { "socionext,uniphier-ld21", &uniphier_ld21_data, },
240   - { "socionext,uniphier-ld20-ref", &uniphier_ld20_ref_data, },
241   - { "socionext,uniphier-ld20", &uniphier_ld20_data, },
242 171 #endif
243 172 };
244 173  
arch/arm/mach-uniphier/boot-device/Makefile
Diff comments   View file @ ee8d037
... ... @@ -14,8 +14,4 @@
14 14 obj-$(CONFIG_ARCH_UNIPHIER_LD11) += boot-device-ld11.o
15 15 obj-$(CONFIG_ARCH_UNIPHIER_LD20) += boot-device-ld11.o
16 16 obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += boot-device-pxs3.o
17   -
18   -ifdef CONFIG_SPL_BUILD
19   -obj-$(CONFIG_SPL_BOARD_LOAD_IMAGE) += spl_board.o
20   -endif
arch/arm/mach-uniphier/boot-device/spl_board.c
View file @ ee8d037
1   -/*
2   - * Copyright (C) 2017 Socionext Inc.
3   - * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <spl.h>
10   -#include <linux/bitops.h>
11   -#include <linux/compat.h>
12   -#include <linux/io.h>
13   -#include <asm/processor.h>
14   -
15   -#include "../soc-info.h"
16   -
17   -#define MMC_CMD_SWITCH 6
18   -#define MMC_CMD_SELECT_CARD 7
19   -#define MMC_CMD_SEND_CSD 9
20   -#define MMC_CMD_READ_MULTIPLE_BLOCK 18
21   -
22   -#define EXT_CSD_PART_CONF 179 /* R/W */
23   -
24   -#define MMC_RSP_PRESENT BIT(0)
25   -#define MMC_RSP_136 BIT(1) /* 136 bit response */
26   -#define MMC_RSP_CRC BIT(2) /* expect valid crc */
27   -#define MMC_RSP_BUSY BIT(3) /* card may send busy */
28   -#define MMC_RSP_OPCODE BIT(4) /* response contains opcode */
29   -
30   -#define MMC_RSP_NONE (0)
31   -#define MMC_RSP_R1 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
32   -#define MMC_RSP_R1b (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | \
33   - MMC_RSP_BUSY)
34   -#define MMC_RSP_R2 (MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC)
35   -#define MMC_RSP_R3 (MMC_RSP_PRESENT)
36   -#define MMC_RSP_R4 (MMC_RSP_PRESENT)
37   -#define MMC_RSP_R5 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
38   -#define MMC_RSP_R6 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
39   -#define MMC_RSP_R7 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
40   -
41   -#define SDHCI_DMA_ADDRESS 0x00
42   -#define SDHCI_BLOCK_SIZE 0x04
43   -#define SDHCI_MAKE_BLKSZ(dma, blksz) ((((dma) & 0x7) << 12) | ((blksz) & 0xFFF))
44   -#define SDHCI_BLOCK_COUNT 0x06
45   -#define SDHCI_ARGUMENT 0x08
46   -#define SDHCI_TRANSFER_MODE 0x0C
47   -#define SDHCI_TRNS_DMA BIT(0)
48   -#define SDHCI_TRNS_BLK_CNT_EN BIT(1)
49   -#define SDHCI_TRNS_ACMD12 BIT(2)
50   -#define SDHCI_TRNS_READ BIT(4)
51   -#define SDHCI_TRNS_MULTI BIT(5)
52   -#define SDHCI_COMMAND 0x0E
53   -#define SDHCI_CMD_RESP_MASK 0x03
54   -#define SDHCI_CMD_CRC 0x08
55   -#define SDHCI_CMD_INDEX 0x10
56   -#define SDHCI_CMD_DATA 0x20
57   -#define SDHCI_CMD_ABORTCMD 0xC0
58   -#define SDHCI_CMD_RESP_NONE 0x00
59   -#define SDHCI_CMD_RESP_LONG 0x01
60   -#define SDHCI_CMD_RESP_SHORT 0x02
61   -#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
62   -#define SDHCI_MAKE_CMD(c, f) ((((c) & 0xff) << 8) | ((f) & 0xff))
63   -#define SDHCI_RESPONSE 0x10
64   -#define SDHCI_HOST_CONTROL 0x28
65   -#define SDHCI_CTRL_DMA_MASK 0x18
66   -#define SDHCI_CTRL_SDMA 0x00
67   -#define SDHCI_BLOCK_GAP_CONTROL 0x2A
68   -#define SDHCI_SOFTWARE_RESET 0x2F
69   -#define SDHCI_RESET_CMD 0x02
70   -#define SDHCI_RESET_DATA 0x04
71   -#define SDHCI_INT_STATUS 0x30
72   -#define SDHCI_INT_RESPONSE BIT(0)
73   -#define SDHCI_INT_DATA_END BIT(1)
74   -#define SDHCI_INT_ERROR BIT(15)
75   -#define SDHCI_SIGNAL_ENABLE 0x38
76   -
77   -/* RCA assigned by Boot ROM */
78   -#define UNIPHIER_EMMC_RCA 0x1000
79   -
80   -struct uniphier_mmc_cmd {
81   - unsigned int cmdidx;
82   - unsigned int resp_type;
83   - unsigned int cmdarg;
84   - unsigned int is_data;
85   -};
86   -
87   -static int uniphier_emmc_send_cmd(void __iomem *host_base,
88   - struct uniphier_mmc_cmd *cmd)
89   -{
90   - u32 mode = 0;
91   - u32 mask = SDHCI_INT_RESPONSE;
92   - u32 stat, flags;
93   -
94   - writel(U32_MAX, host_base + SDHCI_INT_STATUS);
95   - writel(0, host_base + SDHCI_SIGNAL_ENABLE);
96   - writel(cmd->cmdarg, host_base + SDHCI_ARGUMENT);
97   -
98   - if (cmd->is_data)
99   - mode = SDHCI_TRNS_DMA | SDHCI_TRNS_BLK_CNT_EN |
100   - SDHCI_TRNS_ACMD12 | SDHCI_TRNS_READ |
101   - SDHCI_TRNS_MULTI;
102   -
103   - writew(mode, host_base + SDHCI_TRANSFER_MODE);
104   -
105   - if (!(cmd->resp_type & MMC_RSP_PRESENT))
106   - flags = SDHCI_CMD_RESP_NONE;
107   - else if (cmd->resp_type & MMC_RSP_136)
108   - flags = SDHCI_CMD_RESP_LONG;
109   - else if (cmd->resp_type & MMC_RSP_BUSY)
110   - flags = SDHCI_CMD_RESP_SHORT_BUSY;
111   - else
112   - flags = SDHCI_CMD_RESP_SHORT;
113   -
114   - if (cmd->resp_type & MMC_RSP_CRC)
115   - flags |= SDHCI_CMD_CRC;
116   - if (cmd->resp_type & MMC_RSP_OPCODE)
117   - flags |= SDHCI_CMD_INDEX;
118   - if (cmd->is_data)
119   - flags |= SDHCI_CMD_DATA;
120   -
121   - if (cmd->resp_type & MMC_RSP_BUSY || cmd->is_data)
122   - mask |= SDHCI_INT_DATA_END;
123   -
124   - writew(SDHCI_MAKE_CMD(cmd->cmdidx, flags), host_base + SDHCI_COMMAND);
125   -
126   - do {
127   - stat = readl(host_base + SDHCI_INT_STATUS);
128   - if (stat & SDHCI_INT_ERROR)
129   - return -EIO;
130   -
131   - } while ((stat & mask) != mask);
132   -
133   - return 0;
134   -}
135   -
136   -static int uniphier_emmc_switch_part(void __iomem *host_base, int part_num)
137   -{
138   - struct uniphier_mmc_cmd cmd = {};
139   -
140   - cmd.cmdidx = MMC_CMD_SWITCH;
141   - cmd.resp_type = MMC_RSP_R1b;
142   - cmd.cmdarg = (EXT_CSD_PART_CONF << 16) | (part_num << 8) | (3 << 24);
143   -
144   - return uniphier_emmc_send_cmd(host_base, &cmd);
145   -}
146   -
147   -static int uniphier_emmc_is_over_2gb(void __iomem *host_base)
148   -{
149   - struct uniphier_mmc_cmd cmd = {};
150   - u32 csd40, csd72; /* CSD[71:40], CSD[103:72] */
151   - int ret;
152   -
153   - cmd.cmdidx = MMC_CMD_SEND_CSD;
154   - cmd.resp_type = MMC_RSP_R2;
155   - cmd.cmdarg = UNIPHIER_EMMC_RCA << 16;
156   -
157   - ret = uniphier_emmc_send_cmd(host_base, &cmd);
158   - if (ret)
159   - return ret;
160   -
161   - csd40 = readl(host_base + SDHCI_RESPONSE + 4);
162   - csd72 = readl(host_base + SDHCI_RESPONSE + 8);
163   -
164   - return !(~csd40 & 0xffc00380) && !(~csd72 & 0x3);
165   -}
166   -
167   -static int uniphier_emmc_load_image(void __iomem *host_base, u32 dev_addr,
168   - unsigned long load_addr, u32 block_cnt)
169   -{
170   - struct uniphier_mmc_cmd cmd = {};
171   - u8 tmp;
172   -
173   - WARN_ON(load_addr >> 32);
174   -
175   - writel(load_addr, host_base + SDHCI_DMA_ADDRESS);
176   - writew(SDHCI_MAKE_BLKSZ(7, 512), host_base + SDHCI_BLOCK_SIZE);
177   - writew(block_cnt, host_base + SDHCI_BLOCK_COUNT);
178   -
179   - tmp = readb(host_base + SDHCI_HOST_CONTROL);
180   - tmp &= ~SDHCI_CTRL_DMA_MASK;
181   - tmp |= SDHCI_CTRL_SDMA;
182   - writeb(tmp, host_base + SDHCI_HOST_CONTROL);
183   -
184   - tmp = readb(host_base + SDHCI_BLOCK_GAP_CONTROL);
185   - tmp &= ~1; /* clear Stop At Block Gap Request */
186   - writeb(tmp, host_base + SDHCI_BLOCK_GAP_CONTROL);
187   -
188   - cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
189   - cmd.resp_type = MMC_RSP_R1;
190   - cmd.cmdarg = dev_addr;
191   - cmd.is_data = 1;
192   -
193   - return uniphier_emmc_send_cmd(host_base, &cmd);
194   -}
195   -
196   -static int spl_board_load_image(struct spl_image_info *spl_image,
197   - struct spl_boot_device *bootdev)
198   -{
199   - u32 dev_addr = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
200   - void __iomem *host_base = (void __iomem *)0x5a000200;
201   - struct uniphier_mmc_cmd cmd = {};
202   - int ret;
203   -
204   - /*
205   - * deselect card before SEND_CSD command.
206   - * Do not check the return code. It fails, but it is OK.
207   - */
208   - cmd.cmdidx = MMC_CMD_SELECT_CARD;
209   - cmd.resp_type = MMC_RSP_R1;
210   -
211   - uniphier_emmc_send_cmd(host_base, &cmd); /* CMD7 (arg=0) */
212   -
213   - /* reset CMD Line */
214   - writeb(SDHCI_RESET_CMD | SDHCI_RESET_DATA,
215   - host_base + SDHCI_SOFTWARE_RESET);
216   - while (readb(host_base + SDHCI_SOFTWARE_RESET))
217   - cpu_relax();
218   -
219   - ret = uniphier_emmc_is_over_2gb(host_base);
220   - if (ret < 0)
221   - return ret;
222   - if (ret) {
223   - debug("card is block addressing\n");
224   - } else {
225   - debug("card is byte addressing\n");
226   - dev_addr *= 512;
227   - }
228   -
229   - cmd.cmdarg = UNIPHIER_EMMC_RCA << 16;
230   -
231   - /* select card again */
232   - ret = uniphier_emmc_send_cmd(host_base, &cmd);
233   - if (ret)
234   - printf("failed to select card\n");
235   -
236   - /* Switch to Boot Partition 1 */
237   - ret = uniphier_emmc_switch_part(host_base, 1);
238   - if (ret)
239   - printf("failed to switch partition\n");
240   -
241   - ret = uniphier_emmc_load_image(host_base, dev_addr,
242   - CONFIG_SYS_TEXT_BASE, 1);
243   - if (ret) {
244   - printf("failed to load image\n");
245   - return ret;
246   - }
247   -
248   - ret = spl_parse_image_header(spl_image, (void *)CONFIG_SYS_TEXT_BASE);
249   - if (ret)
250   - return ret;
251   -
252   - ret = uniphier_emmc_load_image(host_base, dev_addr,
253   - spl_image->load_addr,
254   - spl_image->size / 512);
255   - if (ret) {
256   - printf("failed to load image\n");
257   - return ret;
258   - }
259   -
260   - return 0;
261   -}
262   -SPL_LOAD_IMAGE_METHOD("eMMC", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
arch/arm/mach-uniphier/clk/Makefile
Diff comments   View file @ ee8d037
... ... @@ -11,8 +11,6 @@
11 11 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-early-sld3.o clk-dram-pro5.o dpll-pro5.o
12 12 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-early-sld3.o clk-dram-pxs2.o dpll-pxs2.o
13 13 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-early-sld3.o clk-dram-pxs2.o dpll-pxs2.o
14   -obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-early-ld11.o clk-dram-ld11.o dpll-ld11.o
15   -obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-early-ld11.o clk-dram-ld20.o dpll-ld20.o
16 14  
17 15 else
18 16  
arch/arm/mach-uniphier/clk/clk-dram-ld11.c
View file @ ee8d037
1   -/*
2   - * Copyright (C) 2016-2017 Socionext Inc.
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#include <linux/io.h>
8   -
9   -#include "../init.h"
10   -#include "../sc64-regs.h"
11   -
12   -void uniphier_ld11_dram_clk_init(void)
13   -{
14   - u32 tmp;
15   -
16   - /* deassert reset */
17   - tmp = readl(SC_RSTCTRL7);
18   - tmp |= SC_RSTCTRL7_UMC31 | SC_RSTCTRL7_UMC30;
19   - writel(tmp, SC_RSTCTRL7);
20   -
21   - /* provide clocks */
22   - tmp = readl(SC_CLKCTRL7);
23   - tmp |= SC_CLKCTRL7_UMC31 | SC_CLKCTRL7_UMC30;
24   - writel(tmp, SC_CLKCTRL7);
25   -}
arch/arm/mach-uniphier/clk/clk-dram-ld20.c
View file @ ee8d037
1   -/*
2   - * Copyright (C) 2016-2017 Socionext Inc.
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#include <linux/io.h>
8   -
9   -#include "../init.h"
10   -#include "../sc64-regs.h"
11   -
12   -void uniphier_ld20_dram_clk_init(void)
13   -{
14   - u32 tmp;
15   -
16   - /* deassert reset */
17   - tmp = readl(SC_RSTCTRL7);
18   - tmp |= SC_RSTCTRL7_UMCSB | SC_RSTCTRL7_UMCA2 | SC_RSTCTRL7_UMCA1 |
19   - SC_RSTCTRL7_UMCA0 | SC_RSTCTRL7_UMC32 | SC_RSTCTRL7_UMC31 |
20   - SC_RSTCTRL7_UMC30;
21   - writel(tmp, SC_RSTCTRL7);
22   -
23   - /* provide clocks */
24   - tmp = readl(SC_CLKCTRL7);
25   - tmp |= SC_CLKCTRL7_UMCSB | SC_CLKCTRL7_UMC32 | SC_CLKCTRL7_UMC31 |
26   - SC_CLKCTRL7_UMC30;
27   - writel(tmp, SC_CLKCTRL7);
28   -}
arch/arm/mach-uniphier/clk/clk-early-ld11.c
View file @ ee8d037
1   -/*
2   - * Copyright (C) 2016-2017 Socionext Inc.
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#include <linux/io.h>
8   -
9   -#include "../init.h"
10   -#include "../sc64-regs.h"
11   -
12   -void uniphier_ld11_early_clk_init(void)
13   -{
14   - u32 tmp;
15   -
16   - /* provide clocks */
17   - tmp = readl(SC_CLKCTRL4);
18   - tmp |= SC_CLKCTRL4_PERI;
19   - writel(tmp, SC_CLKCTRL4);
20   -}
arch/arm/mach-uniphier/clk/dpll-ld11.c
View file @ ee8d037
1   -/*
2   - * Copyright (C) 2016 Socionext Inc.
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#include "../init.h"
8   -#include "../sc64-regs.h"
9   -#include "pll.h"
10   -
11   -int uniphier_ld11_dpll_init(const struct uniphier_board_data *bd)
12   -{
13   - uniphier_ld20_sscpll_init(SC_DPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
14   -
15   - return 0;
16   -}
arch/arm/mach-uniphier/clk/dpll-ld20.c
View file @ ee8d037
1   -/*
2   - * Copyright (C) 2016 Socionext Inc.
3   - * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include "../init.h"
9   -#include "../sc64-regs.h"
10   -#include "pll.h"
11   -
12   -int uniphier_ld20_dpll_init(const struct uniphier_board_data *bd)
13   -{
14   - uniphier_ld20_sscpll_init(SC_DPLL0CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
15   - uniphier_ld20_sscpll_init(SC_DPLL1CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
16   - uniphier_ld20_sscpll_init(SC_DPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
17   -
18   - return 0;
19   -}
arch/arm/mach-uniphier/dram/Makefile
Diff comments   View file @ ee8d037
... ... @@ -14,8 +14,6 @@
14 14 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += umc-pro5.o
15 15 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += umc-pxs2.o
16 16 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += umc-pxs2.o
17   -obj-$(CONFIG_ARCH_UNIPHIER_LD11) += umc-ld11.o
18   -obj-$(CONFIG_ARCH_UNIPHIER_LD20) += umc-ld20.o
19 17  
20 18 else
21 19  
arch/arm/mach-uniphier/dram/ddruqphy-regs.h
View file @ ee8d037
1   -/*
2   - * Copyright (C) 2016 Socionext Inc.
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#ifndef _DDRUQPHY_REGS_H
8   -#define _DDRUQPHY_REGS_H
9   -
10   -#include <linux/bitops.h>
11   -
12   -#define PHY_REG_SHIFT 2
13   -#define PHY_SLV_DLY_WIDTH 6
14   -#define PHY_BITLVL_DLY_WIDTH 6
15   -#define PHY_MAS_DLY_WIDTH 8
16   -
17   -#define PHY_SCL_START (0x40 << (PHY_REG_SHIFT))
18   -#define PHY_SCL_START_GO_DONE BIT(28)
19   -#define PHY_SCL_DATA_0 (0x41 << (PHY_REG_SHIFT))
20   -#define PHY_SCL_DATA_1 (0x42 << (PHY_REG_SHIFT))
21   -#define PHY_SCL_LATENCY (0x43 << (PHY_REG_SHIFT))
22   -#define PHY_SCL_CONFIG_1 (0x46 << (PHY_REG_SHIFT))
23   -#define PHY_SCL_CONFIG_2 (0x47 << (PHY_REG_SHIFT))
24   -#define PHY_PAD_CTRL (0x48 << (PHY_REG_SHIFT))
25   -#define PHY_DLL_RECALIB (0x49 << (PHY_REG_SHIFT))
26   -#define PHY_DLL_RECALIB_TRIM_MASK GENMASK(PHY_SLV_DLY_WIDTH - 1, 0)
27   -#define PHY_DLL_RECALIB_INCR BIT(27)
28   -#define PHY_DLL_ADRCTRL (0x4A << (PHY_REG_SHIFT))
29   -#define PHY_DLL_ADRCTRL_TRIM_MASK GENMASK(PHY_SLV_DLY_WIDTH - 1, 0)
30   -#define PHY_DLL_ADRCTRL_INCR BIT(9)
31   -#define PHY_DLL_ADRCTRL_MDL_SHIFT 24
32   -#define PHY_DLL_ADRCTRL_MDL_MASK (GENMASK(PHY_MAS_DLY_WIDTH - 1, 0) << \
33   - PHY_DLL_ADRCTRL_MDL_SHIFT)
34   -#define PHY_LANE_SEL (0x4B << (PHY_REG_SHIFT))
35   -#define PHY_LANE_SEL_LANE_SHIFT 0
36   -#define PHY_LANE_SEL_LANE_WIDTH 8
37   -#define PHY_LANE_SEL_BIT_SHIFT 8
38   -#define PHY_LANE_SEL_BIT_WIDTH 4
39   -#define PHY_DLL_TRIM_1 (0x4C << (PHY_REG_SHIFT))
40   -#define PHY_DLL_TRIM_2 (0x4D << (PHY_REG_SHIFT))
41   -#define PHY_DLL_TRIM_3 (0x4E << (PHY_REG_SHIFT))
42   -#define PHY_SCL_MAIN_CLK_DELTA (0x50 << (PHY_REG_SHIFT))
43   -#define PHY_WRLVL_AUTOINC_TRIM (0x53 << (PHY_REG_SHIFT))
44   -#define PHY_WRLVL_DYN_ODT (0x54 << (PHY_REG_SHIFT))
45   -#define PHY_WRLVL_ON_OFF (0x55 << (PHY_REG_SHIFT))
46   -#define PHY_UNQ_ANALOG_DLL_1 (0x57 << (PHY_REG_SHIFT))
47   -#define PHY_UNQ_ANALOG_DLL_2 (0x58 << (PHY_REG_SHIFT))
48   -#define PHY_DLL_INCR_TRIM_1 (0x59 << (PHY_REG_SHIFT))
49   -#define PHY_DLL_INCR_TRIM_3 (0x5A << (PHY_REG_SHIFT))
50   -#define PHY_SCL_CONFIG_3 (0x5B << (PHY_REG_SHIFT))
51   -#define PHY_UNIQUIFY_TSMC_IO_1 (0x5C << (PHY_REG_SHIFT))
52   -#define PHY_SCL_START_ADDR (0x62 << (PHY_REG_SHIFT))
53   -#define PHY_IP_DQ_DQS_BITWISE_TRIM (0x65 << (PHY_REG_SHIFT))
54   -#define PHY_IP_DQ_DQS_BITWISE_TRIM_MASK \
55   - GENMASK(PHY_BITLVL_DLY_WIDTH - 1, 0)
56   -#define PHY_IP_DQ_DQS_BITWISE_TRIM_INC \
57   - BIT(PHY_BITLVL_DLY_WIDTH)
58   -#define PHY_IP_DQ_DQS_BITWISE_TRIM_OVERRIDE \
59   - BIT(PHY_BITLVL_DLY_WIDTH + 1)
60   -#define PHY_DSCL_CNT (0x67 << (PHY_REG_SHIFT))
61   -#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM (0x68 << (PHY_REG_SHIFT))
62   -#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_MASK \
63   - GENMASK(PHY_BITLVL_DLY_WIDTH - 1, 0)
64   -#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_INC \
65   - BIT(PHY_BITLVL_DLY_WIDTH)
66   -#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_OVERRIDE \
67   - BIT(PHY_BITLVL_DLY_WIDTH + 1)
68   -#define PHY_DLL_TRIM_CLK (0x69 << (PHY_REG_SHIFT))
69   -#define PHY_DLL_TRIM_CLK_MASK GENMASK(PHY_SLV_DLY_WIDTH, 0)
70   -#define PHY_DLL_TRIM_CLK_INCR BIT(PHY_SLV_DLY_WIDTH + 1)
71   -#define PHY_DYNAMIC_BIT_LVL (0x6B << (PHY_REG_SHIFT))
72   -#define PHY_SCL_WINDOW_TRIM (0x6D << (PHY_REG_SHIFT))
73   -#define PHY_DISABLE_GATING_FOR_SCL (0x6E << (PHY_REG_SHIFT))
74   -#define PHY_SCL_CONFIG_4 (0x6F << (PHY_REG_SHIFT))
75   -#define PHY_DYNAMIC_WRITE_BIT_LVL (0x70 << (PHY_REG_SHIFT))
76   -#define PHY_VREF_TRAINING (0x72 << (PHY_REG_SHIFT))
77   -#define PHY_SCL_GATE_TIMING (0x78 << (PHY_REG_SHIFT))
78   -
79   -#endif /* _DDRUQPHY_REGS_H */
arch/arm/mach-uniphier/dram/umc-ld11.c
View file @ ee8d037
1   -/*
2   - * Copyright (C) 2016 Socionext Inc.
3   - */
4   -
5   -#include <common.h>
6   -#include <linux/io.h>
7   -#include <linux/sizes.h>
8   -#include <asm/processor.h>
9   -
10   -#include "../init.h"
11   -#include "ddrphy-regs.h"
12   -#include "umc64-regs.h"
13   -
14   -#define DDR_FREQ 1600
15   -
16   -#define DRAM_CH_NR 2
17   -#define RANK_BLOCKS_TR 2
18   -
19   -enum dram_freq {
20   - DRAM_FREQ_1600M,
21   - DRAM_FREQ_NR,
22   -};
23   -
24   -enum dram_size {
25   - DRAM_SZ_256M,
26   - DRAM_SZ_512M,
27   - DRAM_SZ_NR,
28   -};
29   -
30   -/* PHY */
31   -static const int rof_pos_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} };
32   -static const int rof_neg_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} };
33   -static const int rof_pos_shift[RANK_BLOCKS_TR][2] = { {-35, -35}, {-35, -35} };
34   -static const int rof_neg_shift[RANK_BLOCKS_TR][2] = { {-17, -17}, {-17, -17} };
35   -static const int tof_shift[RANK_BLOCKS_TR][2] = { {-50, -50}, {-50, -50} };
36   -
37   -/* Register address */
38   -#define PHY_ZQ0CR1 0x00000184
39   -#define PHY_ZQ1CR1 0x00000194
40   -#define PHY_ZQ2CR1 0x000001A4
41   -#define PHY_DX0GCR 0x000001C0
42   -#define PHY_DX0GTR 0x000001F0
43   -#define PHY_DX1GCR 0x00000200
44   -#define PHY_DX1GTR 0x00000230
45   -#define PHY_DX2GCR 0x00000240
46   -#define PHY_DX2GTR 0x00000270
47   -#define PHY_DX3GCR 0x00000280
48   -#define PHY_DX3GTR 0x000002B0
49   -
50   -#define PHY_DXMDLR(dx) (0x000001EC + 0x40 * (dx))
51   -#define PHY_DXLCDLR0(dx) (0x000001E0 + 0x40 * (dx))
52   -#define PHY_DXLCDLR1(dx) (0x000001E4 + 0x40 * (dx))
53   -#define PHY_DXLCDLR2(dx) (0x000001E8 + 0x40 * (dx))
54   -#define PHY_DXBDLR1(dx) (0x000001D0 + 0x40 * (dx))
55   -#define PHY_DXBDLR2(dx) (0x000001D4 + 0x40 * (dx))
56   -
57   -/* MASK */
58   -#define PHY_ACBD_MASK 0x00FC0000
59   -#define PHY_CK0BD_MASK 0x0000003F
60   -#define PHY_CK1BD_MASK 0x00000FC0
61   -#define PHY_IPRD_MASK 0x000000FF
62   -#define PHY_WLD_MASK(rank) (0xFF << (8 * (rank)))
63   -#define PHY_DQSGD_MASK(rank) (0xFF << (8 * (rank)))
64   -#define PHY_DQSGX_MASK BIT(6)
65   -#define PHY_DSWBD_MASK 0x3F000000 /* bit[29:24] */
66   -#define PHY_DSDQOE_MASK 0x00000FFF
67   -
68   -static void ddrphy_maskwritel(u32 data, u32 mask, void __iomem *addr)
69   -{
70   - u32 value;
71   -
72   - value = (readl(addr) & ~(mask)) | (data & mask);
73   - writel(value, addr);
74   -}
75   -
76   -static u32 ddrphy_maskreadl(u32 mask, void __iomem *addr)
77   -{
78   - return readl(addr) & mask;
79   -}
80   -
81   -/* step of 0.5T for PUB-byte */
82   -static u8 ddrphy_get_mdl(int dx, void __iomem *phy_base)
83   -{
84   - return ddrphy_maskreadl(PHY_IPRD_MASK, phy_base + PHY_DXMDLR(dx));
85   -}
86   -
87   -/* Calculating step for PUB-byte */
88   -static int ddrphy_hpstep(int delay, int dx, void __iomem *phy_base)
89   -{
90   - return delay * ddrphy_get_mdl(dx, phy_base) * DDR_FREQ / 1000000;
91   -}
92   -
93   -static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable)
94   -{
95   - u32 tmp;
96   -
97   - tmp = readl(phy_base + PHY_PGCR1);
98   -
99   - if (enable)
100   - tmp &= ~PHY_PGCR1_INHVT;
101   - else
102   - tmp |= PHY_PGCR1_INHVT;
103   -
104   - writel(tmp, phy_base + PHY_PGCR1);
105   -
106   - if (!enable) {
107   - while (!(readl(phy_base + PHY_PGSR1) & PHY_PGSR1_VTSTOP))
108   - cpu_relax();
109   - }
110   -}
111   -
112   -static void ddrphy_set_ckoffset_qoffset(int delay_ckoffset0, int delay_ckoffset1,
113   - int delay_qoffset, int enable,
114   - void __iomem *phy_base)
115   -{
116   - u8 ck_step0, ck_step1; /* ckoffset_step for clock */
117   - u8 q_step; /* qoffset_step for clock */
118   - int dx;
119   -
120   - dx = 2; /* use dx2 in sLD11 */
121   -
122   - ck_step0 = ddrphy_hpstep(delay_ckoffset0, dx, phy_base); /* CK-Offset */
123   - ck_step1 = ddrphy_hpstep(delay_ckoffset1, dx, phy_base); /* CK-Offset */
124   - q_step = ddrphy_hpstep(delay_qoffset, dx, phy_base); /* Q-Offset */
125   -
126   - ddrphy_vt_ctrl(phy_base, 0);
127   -
128   - /* Q->[23:18], CK1->[11:6], CK0->bit[5:0] */
129   - if (enable == 1)
130   - ddrphy_maskwritel((q_step << 18) + (ck_step1 << 6) + ck_step0,
131   - PHY_ACBD_MASK | PHY_CK1BD_MASK | PHY_CK0BD_MASK,
132   - phy_base + PHY_ACBDLR);
133   -
134   - ddrphy_vt_ctrl(phy_base, 1);
135   -}
136   -
137   -static void ddrphy_set_wl_delay_dx(int dx, int r0_delay, int r1_delay,
138   - int enable, void __iomem *phy_base)
139   -{
140   - int rank;
141   - int delay_wl[4];
142   - u32 wl_mask = 0; /* WriteLeveling's Mask */
143   - u32 wl_value = 0; /* WriteLeveling's Value */
144   -
145   - delay_wl[0] = r0_delay & 0xfff;
146   - delay_wl[1] = r1_delay & 0xfff;
147   - delay_wl[2] = 0;
148   - delay_wl[3] = 0;
149   -
150   - ddrphy_vt_ctrl(phy_base, 0);
151   -
152   - for (rank = 0; rank < 4; rank++) {
153   - wl_mask |= PHY_WLD_MASK(rank);
154   - /* WriteLeveling's delay */
155   - wl_value |= ddrphy_hpstep(delay_wl[rank], dx, phy_base) << (8 * rank);
156   - }
157   -
158   - if (enable == 1)
159   - ddrphy_maskwritel(wl_value, wl_mask, phy_base + PHY_DXLCDLR0(dx));
160   -
161   - ddrphy_vt_ctrl(phy_base, 1);
162   -}
163   -
164   -static void ddrphy_set_dqsg_delay_dx(int dx, int r0_delay, int r1_delay,
165   - int enable, void __iomem *phy_base)
166   -{
167   - int rank;
168   - int delay_dqsg[4];
169   - u32 dqsg_mask = 0; /* DQSGating_LCDL_delay's Mask */
170   - u32 dqsg_value = 0; /* DQSGating_LCDL_delay's Value */
171   -
172   - delay_dqsg[0] = r0_delay;
173   - delay_dqsg[1] = r1_delay;
174   - delay_dqsg[2] = 0;
175   - delay_dqsg[3] = 0;
176   -
177   - ddrphy_vt_ctrl(phy_base, 0);
178   -
179   - for (rank = 0; rank < 4; rank++) {
180   - dqsg_mask |= PHY_DQSGD_MASK(rank);
181   - /* DQSGating's delay */
182   - dqsg_value |= ddrphy_hpstep(delay_dqsg[rank], dx, phy_base) << (8 * rank);
183   - }
184   -
185   - if (enable == 1)
186   - ddrphy_maskwritel(dqsg_value, dqsg_mask, phy_base + PHY_DXLCDLR2(dx));
187   -
188   - ddrphy_vt_ctrl(phy_base, 1);
189   -}
190   -
191   -static void ddrphy_set_dswb_delay_dx(int dx, int delay, int enable, void __iomem *phy_base)
192   -{
193   - u8 dswb_step;
194   -
195   - ddrphy_vt_ctrl(phy_base, 0);
196   -
197   - dswb_step = ddrphy_hpstep(delay, dx, phy_base); /* DQS-BDL's delay */
198   -
199   - if (enable == 1)
200   - ddrphy_maskwritel(dswb_step << 24, PHY_DSWBD_MASK, phy_base + PHY_DXBDLR1(dx));
201   -
202   - ddrphy_vt_ctrl(phy_base, 1);
203   -}
204   -
205   -static void ddrphy_set_oe_delay_dx(int dx, int dqs_delay, int dq_delay,
206   - int enable, void __iomem *phy_base)
207   -{
208   - u8 dqs_oe_step, dq_oe_step;
209   - u32 wdata;
210   -
211   - ddrphy_vt_ctrl(phy_base, 0);
212   -
213   - /* OE(DQS,DQ) */
214   - dqs_oe_step = ddrphy_hpstep(dqs_delay, dx, phy_base); /* DQS-oe's delay */
215   - dq_oe_step = ddrphy_hpstep(dq_delay, dx, phy_base); /* DQ-oe's delay */
216   - wdata = ((dq_oe_step<<6) + dqs_oe_step) & 0xFFF;
217   -
218   - if (enable == 1)
219   - ddrphy_maskwritel(wdata, PHY_DSDQOE_MASK, phy_base + PHY_DXBDLR2(dx));
220   -
221   - ddrphy_vt_ctrl(phy_base, 1);
222   -}
223   -
224   -static void ddrphy_ext_dqsgt(void __iomem *phy_base)
225   -{
226   - /* Extend DQSGating_window min:+1T max:+1T */
227   - ddrphy_maskwritel(PHY_DQSGX_MASK, PHY_DQSGX_MASK, phy_base + PHY_DSGCR);
228   -}
229   -
230   -static void ddrphy_shift_tof_hws(void __iomem *phy_base, const int shift[][2])
231   -{
232   - int dx, block, byte;
233   - u32 lcdlr1, wdqd;
234   -
235   - ddrphy_vt_ctrl(phy_base, 0);
236   -
237   - for (block = 0; block < RANK_BLOCKS_TR; block++) {
238   - for (byte = 0; byte < 2; byte++) {
239   - dx = block * 2 + byte;
240   - lcdlr1 = readl(phy_base + PHY_DXLCDLR1(dx));
241   - wdqd = lcdlr1 & 0xff;
242   - wdqd = clamp(wdqd + ddrphy_hpstep(shift[block][byte], dx, phy_base),
243   - 0U, 0xffU);
244   - lcdlr1 = (lcdlr1 & ~0xff) | wdqd;
245   - writel(lcdlr1, phy_base + PHY_DXLCDLR1(dx));
246   - readl(phy_base + PHY_DXLCDLR1(dx)); /* relax */
247   - }
248   - }
249   -
250   - ddrphy_vt_ctrl(phy_base, 1);
251   -}
252   -
253   -static void ddrphy_shift_rof_hws(void __iomem *phy_base, const int pos_shift[][2],
254   - const int neg_shift[][2])
255   -{
256   - int dx, block, byte;
257   - u32 lcdlr1, rdqsd, rdqnsd;
258   -
259   - ddrphy_vt_ctrl(phy_base, 0);
260   -
261   - for (block = 0; block < RANK_BLOCKS_TR; block++) {
262   - for (byte = 0; byte < 2; byte++) {
263   - dx = block * 2 + byte;
264   - lcdlr1 = readl(phy_base + PHY_DXLCDLR1(dx));
265   -
266   - /* DQS LCDL RDQNSD->[23:16] RDQSD->[15:8] */
267   - rdqsd = (lcdlr1 >> 8) & 0xff;
268   - rdqnsd = (lcdlr1 >> 16) & 0xff;
269   - rdqsd = clamp(rdqsd + ddrphy_hpstep(pos_shift[block][byte], dx, phy_base),
270   - 0U, 0xffU);
271   - rdqnsd = clamp(rdqnsd + ddrphy_hpstep(neg_shift[block][byte], dx, phy_base),
272   - 0U, 0xffU);
273   - lcdlr1 = (lcdlr1 & ~(0xffff << 8)) | (rdqsd << 8) | (rdqnsd << 16);
274   - writel(lcdlr1, phy_base + PHY_DXLCDLR1(dx));
275   - readl(phy_base + PHY_DXLCDLR1(dx)); /* relax */
276   - }
277   - }
278   -
279   - ddrphy_vt_ctrl(phy_base, 1);
280   -}
281   -
282   -static void ddrphy_boot_run_hws(void __iomem *phy_base)
283   -{
284   - /* Hard Training for DIO */
285   - writel(0x0000f401, phy_base + PHY_PIR);
286   - while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
287   - cpu_relax();
288   -}
289   -
290   -static void ddrphy_training(void __iomem *phy_base)
291   -{
292   - /* DIO roffset shift before hard training */
293   - ddrphy_shift_rof_hws(phy_base, rof_pos_shift_pre, rof_neg_shift_pre);
294   -
295   - /* Hard Training for each CH */
296   - ddrphy_boot_run_hws(phy_base);
297   -
298   - /* DIO toffset shift after training */
299   - ddrphy_shift_tof_hws(phy_base, tof_shift);
300   -
301   - /* DIO roffset shift after training */
302   - ddrphy_shift_rof_hws(phy_base, rof_pos_shift, rof_neg_shift);
303   -
304   - /* Extend DQSGating window min:+1T max:+1T */
305   - ddrphy_ext_dqsgt(phy_base);
306   -}
307   -
308   -static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq)
309   -{
310   - writel(0x40000000, phy_base + PHY_PIR);
311   - writel(0x0300C4F1, phy_base + PHY_PGCR1);
312   - writel(0x0C807D04, phy_base + PHY_PTR0);
313   - writel(0x27100578, phy_base + PHY_PTR1);
314   - writel(0x00083DEF, phy_base + PHY_PTR2);
315   - writel(0x12061A80, phy_base + PHY_PTR3);
316   - writel(0x08027100, phy_base + PHY_PTR4);
317   - writel(0x9D9CBB66, phy_base + PHY_DTPR0);
318   - writel(0x1a878400, phy_base + PHY_DTPR1);
319   - writel(0x50025200, phy_base + PHY_DTPR2);
320   - writel(0xF004641A, phy_base + PHY_DSGCR);
321   - writel(0x0000040B, phy_base + PHY_DCR);
322   - writel(0x00000d71, phy_base + PHY_MR0);
323   - writel(0x00000006, phy_base + PHY_MR1);
324   - writel(0x00000098, phy_base + PHY_MR2);
325   - writel(0x00000000, phy_base + PHY_MR3);
326   -
327   - while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
328   - cpu_relax();
329   -
330   - writel(0x00000059, phy_base + PHY_ZQ0CR1);
331   - writel(0x00000019, phy_base + PHY_ZQ1CR1);
332   - writel(0x00000019, phy_base + PHY_ZQ2CR1);
333   - writel(0x30FC6C20, phy_base + PHY_PGCR2);
334   -
335   - ddrphy_set_ckoffset_qoffset(119, 0, 0, 1, phy_base);
336   - ddrphy_set_wl_delay_dx(0, 220, 220, 1, phy_base);
337   - ddrphy_set_wl_delay_dx(1, 160, 160, 1, phy_base);
338   - ddrphy_set_wl_delay_dx(2, 190, 190, 1, phy_base);
339   - ddrphy_set_wl_delay_dx(3, 150, 150, 1, phy_base);
340   - ddrphy_set_dqsg_delay_dx(0, 750, 750, 1, phy_base);
341   - ddrphy_set_dqsg_delay_dx(1, 750, 750, 1, phy_base);
342   - ddrphy_set_dqsg_delay_dx(2, 750, 750, 1, phy_base);
343   - ddrphy_set_dqsg_delay_dx(3, 750, 750, 1, phy_base);
344   - ddrphy_set_dswb_delay_dx(0, 0, 1, phy_base);
345   - ddrphy_set_dswb_delay_dx(1, 0, 1, phy_base);
346   - ddrphy_set_dswb_delay_dx(2, 0, 1, phy_base);
347   - ddrphy_set_dswb_delay_dx(3, 0, 1, phy_base);
348   - ddrphy_set_oe_delay_dx(0, 0, 0, 1, phy_base);
349   - ddrphy_set_oe_delay_dx(1, 0, 0, 1, phy_base);
350   - ddrphy_set_oe_delay_dx(2, 0, 0, 1, phy_base);
351   - ddrphy_set_oe_delay_dx(3, 0, 0, 1, phy_base);
352   -
353   - writel(0x44000E81, phy_base + PHY_DX0GCR);
354   - writel(0x44000E81, phy_base + PHY_DX1GCR);
355   - writel(0x44000E81, phy_base + PHY_DX2GCR);
356   - writel(0x44000E81, phy_base + PHY_DX3GCR);
357   - writel(0x00055002, phy_base + PHY_DX0GTR);
358   - writel(0x00055002, phy_base + PHY_DX1GTR);
359   - writel(0x00055010, phy_base + PHY_DX2GTR);
360   - writel(0x00055010, phy_base + PHY_DX3GTR);
361   - writel(0x930035C7, phy_base + PHY_DTCR);
362   - writel(0x00000003, phy_base + PHY_PIR);
363   - readl(phy_base + PHY_PIR);
364   - while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
365   - cpu_relax();
366   -
367   - writel(0x00000181, phy_base + PHY_PIR);
368   - readl(phy_base + PHY_PIR);
369   - while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
370   - cpu_relax();
371   -
372   - writel(0x44181884, phy_base + PHY_DXCCR);
373   - writel(0x00000001, phy_base + PHY_GPR1);
374   -}
375   -
376   -/* UMC */
377   -static const u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060B0B1C};
378   -static const u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x27201806};
379   -static const u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00120B04};
380   -static const u32 umc_cmdctle[DRAM_FREQ_NR] = {0x00680607};
381   -static const u32 umc_cmdctlf[DRAM_FREQ_NR] = {0x02000200};
382   -static const u32 umc_cmdctlg[DRAM_FREQ_NR] = {0x08080808};
383   -
384   -static const u32 umc_rdatactl[DRAM_FREQ_NR] = {0x00000810};
385   -static const u32 umc_wdatactl[DRAM_FREQ_NR] = {0x00000004};
386   -static const u32 umc_odtctl[DRAM_FREQ_NR] = {0x02000002};
387   -static const u32 umc_acssetb[DRAM_CH_NR] = {0x00000200, 0x00000203};
388   -
389   -static const u32 umc_memconfch[DRAM_FREQ_NR] = {0x00023605};
390   -
391   -static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
392   - unsigned long size, int ch)
393   -{
394   - /* Wait for PHY Init Complete */
395   - writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
396   - writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB);
397   - writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC);
398   - writel(umc_cmdctle[freq], dc_base + UMC_CMDCTLE);
399   - writel(umc_cmdctlf[freq], dc_base + UMC_CMDCTLF);
400   - writel(umc_cmdctlg[freq], dc_base + UMC_CMDCTLG);
401   -
402   - writel(umc_rdatactl[freq], dc_base + UMC_RDATACTL_D0);
403   - writel(umc_rdatactl[freq], dc_base + UMC_RDATACTL_D1);
404   -
405   - writel(umc_wdatactl[freq], dc_base + UMC_WDATACTL_D0);
406   - writel(umc_wdatactl[freq], dc_base + UMC_WDATACTL_D1);
407   -
408   - writel(umc_odtctl[freq], dc_base + UMC_ODTCTL_D0);
409   - writel(umc_odtctl[freq], dc_base + UMC_ODTCTL_D1);
410   -
411   - writel(0x00000003, dc_base + UMC_ACSSETA);
412   - writel(0x00000103, dc_base + UMC_FLOWCTLG);
413   - writel(umc_acssetb[ch], dc_base + UMC_ACSSETB);
414   - writel(0x02020200, dc_base + UMC_SPCSETB);
415   - writel(umc_memconfch[freq], dc_base + UMC_MEMCONFCH);
416   - writel(0x00000002, dc_base + UMC_ACFETCHCTRL);
417   -
418   - return 0;
419   -}
420   -
421   -static int umc_ch_init(void __iomem *umc_ch_base,
422   - enum dram_freq freq, unsigned long size, int ch)
423   -{
424   - void __iomem *dc_base = umc_ch_base;
425   -
426   - return umc_dc_init(dc_base, freq, size, ch);
427   -}
428   -
429   -static void um_init(void __iomem *um_base)
430   -{
431   - writel(0x00000001, um_base + UMC_SIORST);
432   - writel(0x00000001, um_base + UMC_VO0RST);
433   - writel(0x00000001, um_base + UMC_VPERST);
434   - writel(0x00000001, um_base + UMC_RGLRST);
435   - writel(0x00000001, um_base + UMC_A2DRST);
436   - writel(0x00000001, um_base + UMC_DMDRST);
437   -}
438   -
439   -int uniphier_ld11_umc_init(const struct uniphier_board_data *bd)
440   -{
441   - void __iomem *um_base = (void __iomem *)0x5B800000;
442   - void __iomem *umc_ch_base = (void __iomem *)0x5BC00000;
443   - void __iomem *phy_base = (void __iomem *)0x5BC01000;
444   - enum dram_freq freq;
445   - int ch, ret;
446   -
447   - switch (bd->dram_freq) {
448   - case 1600:
449   - freq = DRAM_FREQ_1600M;
450   - break;
451   - default:
452   - pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
453   - return -EINVAL;
454   - }
455   -
456   - writel(0x00000101, umc_ch_base + UMC_DIOCTLA);
457   - while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
458   - cpu_relax();
459   -
460   - writel(0x00000000, umc_ch_base + UMC_DIOCTLA);
461   - writel(0x00000001, umc_ch_base + UMC_DEBUGC);
462   - writel(0x00000101, umc_ch_base + UMC_DIOCTLA);
463   -
464   - writel(0x00000100, umc_ch_base + UMC_INITSET);
465   - while (readl(umc_ch_base + UMC_INITSTAT) & BIT(8))
466   - cpu_relax();
467   -
468   - writel(0x00000100, umc_ch_base + 0x00200000 + UMC_INITSET);
469   - while (readl(umc_ch_base + 0x00200000 + UMC_INITSTAT) & BIT(8))
470   - cpu_relax();
471   -
472   - ddrphy_init(phy_base, freq);
473   -
474   - for (ch = 0; ch < DRAM_CH_NR; ch++) {
475   - unsigned long size = bd->dram_ch[ch].size;
476   - unsigned int width = bd->dram_ch[ch].width;
477   -
478   - ret = umc_ch_init(umc_ch_base, freq, size / (width / 16), ch);
479   - if (ret) {
480   - pr_err("failed to initialize UMC ch%d\n", ch);
481   - return ret;
482   - }
483   -
484   - umc_ch_base += 0x00200000;
485   - }
486   - ddrphy_training(phy_base);
487   -
488   - um_init(um_base);
489   -
490   - return 0;
491   -}
arch/arm/mach-uniphier/dram/umc-ld20.c
View file @ ee8d037
1   -/*
2   - * Copyright (C) 2016-2017 Socionext Inc.
3   - *
4   - * based on commit 5ffd75ecd4929f22361ef65a35f0331d2fbc0f35 of Diag
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#include <common.h>
10   -#include <linux/bitops.h>
11   -#include <linux/compat.h>
12   -#include <linux/errno.h>
13   -#include <linux/io.h>
14   -#include <linux/sizes.h>
15   -#include <asm/processor.h>
16   -
17   -#include "../init.h"
18   -#include "ddruqphy-regs.h"
19   -#include "umc64-regs.h"
20   -
21   -#define DRAM_CH_NR 3
22   -
23   -enum dram_freq {
24   - DRAM_FREQ_1866M,
25   - DRAM_FREQ_NR,
26   -};
27   -
28   -enum dram_size {
29   - DRAM_SZ_256M,
30   - DRAM_SZ_512M,
31   - DRAM_SZ_NR,
32   -};
33   -
34   -enum dram_board { /* board type */
35   - DRAM_BOARD_LD20_REF, /* LD20 reference */
36   - DRAM_BOARD_LD20_GLOBAL, /* LD20 TV */
37   - DRAM_BOARD_LD20_C1, /* LD20 TV C1 */
38   - DRAM_BOARD_LD21_REF, /* LD21 reference */
39   - DRAM_BOARD_LD21_GLOBAL, /* LD21 TV */
40   - DRAM_BOARD_NR,
41   -};
42   -
43   -/* PHY */
44   -static const int ddrphy_adrctrl[DRAM_BOARD_NR][DRAM_CH_NR] = {
45   - {268 - 262, 268 - 263, 268 - 378}, /* LD20 reference */
46   - {268 - 262, 268 - 263, 268 - 378}, /* LD20 TV */
47   - {268 - 262, 268 - 263, 268 - 378}, /* LD20 TV C1 */
48   - {268 - 212, 268 - 268, /* No CH2 */}, /* LD21 reference */
49   - {268 - 212, 268 - 268, /* No CH2 */}, /* LD21 TV */
50   -};
51   -
52   -static const int ddrphy_dlltrimclk[DRAM_BOARD_NR][DRAM_CH_NR] = {
53   - {268, 268, 268}, /* LD20 reference */
54   - {268, 268, 268}, /* LD20 TV */
55   - {189, 189, 189}, /* LD20 TV C1 */
56   - {268, 268 + 252, /* No CH2 */}, /* LD21 reference */
57   - {268, 268 + 202, /* No CH2 */}, /* LD21 TV */
58   -};
59   -
60   -static const int ddrphy_dllrecalib[DRAM_BOARD_NR][DRAM_CH_NR] = {
61   - {268 - 378, 268 - 263, 268 - 378}, /* LD20 reference */
62   - {268 - 378, 268 - 263, 268 - 378}, /* LD20 TV */
63   - {268 - 378, 268 - 263, 268 - 378}, /* LD20 TV C1 */
64   - {268 - 212, 268 - 536, /* No CH2 */}, /* LD21 reference */
65   - {268 - 212, 268 - 536, /* No CH2 */}, /* LD21 TV */
66   -};
67   -
68   -static const u32 ddrphy_phy_pad_ctrl[DRAM_BOARD_NR][DRAM_CH_NR] = {
69   - {0x50B840B1, 0x50B840B1, 0x50B840B1}, /* LD20 reference */
70   - {0x50BB40B1, 0x50BB40B1, 0x50BB40B1}, /* LD20 TV */
71   - {0x50BB40B1, 0x50BB40B1, 0x50BB40B1}, /* LD20 TV C1 */
72   - {0x50BB40B4, 0x50B840B1, /* No CH2 */}, /* LD21 reference */
73   - {0x50BB40B4, 0x50B840B1, /* No CH2 */}, /* LD21 TV */
74   -};
75   -
76   -static const u32 ddrphy_scl_gate_timing[DRAM_CH_NR] = {
77   - 0x00000140, 0x00000180, 0x00000140
78   -};
79   -
80   -static const short ddrphy_op_dq_shift_val_ld20[DRAM_CH_NR][32] = {
81   - {
82   - 2, 1, 0, 1, 2, 1, 1, 1,
83   - 2, 1, 1, 2, 1, 1, 1, 1,
84   - 1, 2, 1, 1, 1, 2, 1, 1,
85   - 2, 2, 0, 1, 1, 2, 2, 1,
86   - },
87   - {
88   - 1, 1, 0, 1, 2, 2, 1, 1,
89   - 1, 1, 1, 1, 1, 1, 1, 1,
90   - 1, 1, 0, 0, 1, 1, 0, 0,
91   - 0, 1, 1, 1, 2, 1, 2, 1,
92   - },
93   - {
94   - 2, 2, 0, 2, 1, 1, 2, 1,
95   - 1, 1, 0, 1, 1, -1, 1, 1,
96   - 2, 2, 2, 2, 1, 1, 1, 1,
97   - 1, 1, 1, 0, 2, 2, 1, 2,
98   - },
99   -};
100   -
101   -static const short ddrphy_op_dq_shift_val_ld21[DRAM_CH_NR][32] = {
102   - {
103   - 1, 1, 0, 1, 1, 1, 1, 1,
104   - 1, 0, 0, 0, 1, 1, 0, 2,
105   - 1, 1, 0, 0, 1, 1, 1, 1,
106   - 1, 0, 0, 0, 1, 0, 0, 1,
107   - },
108   - { 1, 0, 2, 1, 1, 1, 1, 0,
109   - 1, 0, 0, 1, 0, 1, 0, 0,
110   - 1, 0, 1, 0, 1, 1, 1, 0,
111   - 1, 1, 1, 1, 0, 1, 0, 0,
112   - },
113   - /* No CH2 */
114   -};
115   -
116   -static const short (* const ddrphy_op_dq_shift_val[DRAM_BOARD_NR])[32] = {
117   - ddrphy_op_dq_shift_val_ld20, /* LD20 reference */
118   - ddrphy_op_dq_shift_val_ld20, /* LD20 TV */
119   - ddrphy_op_dq_shift_val_ld20, /* LD20 TV C */
120   - ddrphy_op_dq_shift_val_ld21, /* LD21 reference */
121   - ddrphy_op_dq_shift_val_ld21, /* LD21 TV */
122   -};
123   -
124   -static const short ddrphy_ip_dq_shift_val_ld20[DRAM_CH_NR][32] = {
125   - {
126   - 3, 3, 3, 2, 3, 2, 0, 2,
127   - 2, 3, 3, 1, 2, 2, 2, 2,
128   - 2, 2, 2, 2, 0, 1, 1, 1,
129   - 2, 2, 2, 2, 3, 0, 2, 2,
130   - },
131   - {
132   - 2, 2, 1, 1, -1, 1, 1, 1,
133   - 2, 0, 2, 2, 2, 1, 0, 2,
134   - 2, 1, 2, 1, 0, 1, 1, 1,
135   - 2, 2, 2, 2, 2, 2, 2, 2,
136   - },
137   - {
138   - 2, 2, 3, 2, 1, 2, 2, 2,
139   - 2, 3, 4, 2, 3, 4, 3, 3,
140   - 2, 2, 1, 2, 1, 1, 1, 1,
141   - 2, 2, 2, 2, 1, 2, 2, 1,
142   - },
143   -};
144   -
145   -static const short ddrphy_ip_dq_shift_val_ld21[DRAM_CH_NR][32] = {
146   - {
147   - 2, 2, 2, 2, 1, 2, 2, 2,
148   - 2, 3, 3, 2, 2, 2, 2, 2,
149   - 2, 1, 2, 2, 1, 1, 1, 1,
150   - 2, 2, 2, 3, 1, 2, 2, 2,
151   - },
152   - {
153   - 3, 4, 4, 1, 0, 1, 1, 1,
154   - 1, 2, 1, 2, 2, 3, 3, 2,
155   - 1, 0, 2, 1, 1, 0, 1, 0,
156   - 0, 1, 0, 0, 1, 1, 0, 1,
157   - },
158   - /* No CH2 */
159   -};
160   -
161   -static const short (* const ddrphy_ip_dq_shift_val[DRAM_BOARD_NR])[32] = {
162   - ddrphy_ip_dq_shift_val_ld20, /* LD20 reference */
163   - ddrphy_ip_dq_shift_val_ld20, /* LD20 TV */
164   - ddrphy_ip_dq_shift_val_ld20, /* LD20 TV C */
165   - ddrphy_ip_dq_shift_val_ld21, /* LD21 reference */
166   - ddrphy_ip_dq_shift_val_ld21, /* LD21 TV */
167   -};
168   -
169   -static void ddrphy_select_lane(void __iomem *phy_base, unsigned int lane,
170   - unsigned int bit)
171   -{
172   - WARN_ON(lane >= 1 << PHY_LANE_SEL_LANE_WIDTH);
173   - WARN_ON(bit >= 1 << PHY_LANE_SEL_BIT_WIDTH);
174   -
175   - writel((bit << PHY_LANE_SEL_BIT_SHIFT) |
176   - (lane << PHY_LANE_SEL_LANE_SHIFT),
177   - phy_base + PHY_LANE_SEL);
178   -}
179   -
180   -#define DDRPHY_EFUSEMON (void *)0x5f900118
181   -
182   -static void ddrphy_init(void __iomem *phy_base, enum dram_board board, int ch)
183   -{
184   - writel(0x0C001001, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
185   - while (!(readl(phy_base + PHY_UNIQUIFY_TSMC_IO_1) & BIT(1)))
186   - cpu_relax();
187   -
188   - if (readl(DDRPHY_EFUSEMON) & BIT(ch))
189   - writel(0x00000000, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
190   - else
191   - writel(0x0C001000, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
192   -
193   - writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_3);
194   - writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_1);
195   - ddrphy_select_lane(phy_base, 0, 0);
196   - writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
197   - writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
198   - ddrphy_select_lane(phy_base, 6, 0);
199   - writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
200   - writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
201   - ddrphy_select_lane(phy_base, 12, 0);
202   - writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
203   - writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
204   - ddrphy_select_lane(phy_base, 18, 0);
205   - writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
206   - writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
207   - writel(0x00000001, phy_base + PHY_SCL_WINDOW_TRIM);
208   - writel(0x00000000, phy_base + PHY_UNQ_ANALOG_DLL_1);
209   - writel(ddrphy_phy_pad_ctrl[board][ch], phy_base + PHY_PAD_CTRL);
210   - writel(0x00000070, phy_base + PHY_VREF_TRAINING);
211   - writel(0x01000075, phy_base + PHY_SCL_CONFIG_1);
212   - writel(0x00000501, phy_base + PHY_SCL_CONFIG_2);
213   - writel(0x00000000, phy_base + PHY_SCL_CONFIG_3);
214   - writel(0x000261c0, phy_base + PHY_DYNAMIC_WRITE_BIT_LVL);
215   - writel(0x00000000, phy_base + PHY_SCL_CONFIG_4);
216   - writel(ddrphy_scl_gate_timing[ch], phy_base + PHY_SCL_GATE_TIMING);
217   - writel(0x02a000a0, phy_base + PHY_WRLVL_DYN_ODT);
218   - writel(0x00840004, phy_base + PHY_WRLVL_ON_OFF);
219   - writel(0x0000020d, phy_base + PHY_DLL_ADRCTRL);
220   - ddrphy_select_lane(phy_base, 0, 0);
221   - writel(0x0000008d, phy_base + PHY_DLL_TRIM_CLK);
222   - writel(0xa800100d, phy_base + PHY_DLL_RECALIB);
223   - writel(0x00005076, phy_base + PHY_SCL_LATENCY);
224   -}
225   -
226   -static int ddrphy_to_dly_step(void __iomem *phy_base, unsigned int freq,
227   - int delay)
228   -{
229   - int mdl;
230   -
231   - mdl = (readl(phy_base + PHY_DLL_ADRCTRL) & PHY_DLL_ADRCTRL_MDL_MASK) >>
232   - PHY_DLL_ADRCTRL_MDL_SHIFT;
233   -
234   - return DIV_ROUND_CLOSEST((long)freq * delay * mdl, 2 * 1000000L);
235   -}
236   -
237   -static void ddrphy_set_delay(void __iomem *phy_base, unsigned int reg,
238   - u32 mask, u32 incr, int dly_step)
239   -{
240   - u32 tmp;
241   -
242   - tmp = readl(phy_base + reg);
243   - tmp &= ~mask;
244   - tmp |= min_t(u32, abs(dly_step), mask);
245   -
246   - if (dly_step >= 0)
247   - tmp |= incr;
248   - else
249   - tmp &= ~incr;
250   -
251   - writel(tmp, phy_base + reg);
252   -}
253   -
254   -static void ddrphy_set_dll_recalib(void __iomem *phy_base, int dly_step)
255   -{
256   - ddrphy_set_delay(phy_base, PHY_DLL_RECALIB,
257   - PHY_DLL_RECALIB_TRIM_MASK, PHY_DLL_RECALIB_INCR,
258   - dly_step);
259   -}
260   -
261   -static void ddrphy_set_dll_adrctrl(void __iomem *phy_base, int dly_step)
262   -{
263   - ddrphy_set_delay(phy_base, PHY_DLL_ADRCTRL,
264   - PHY_DLL_ADRCTRL_TRIM_MASK, PHY_DLL_ADRCTRL_INCR,
265   - dly_step);
266   -}
267   -
268   -static void ddrphy_set_dll_trim_clk(void __iomem *phy_base, int dly_step)
269   -{
270   - ddrphy_select_lane(phy_base, 0, 0);
271   -
272   - ddrphy_set_delay(phy_base, PHY_DLL_TRIM_CLK,
273   - PHY_DLL_TRIM_CLK_MASK, PHY_DLL_TRIM_CLK_INCR,
274   - dly_step);
275   -}
276   -
277   -static void ddrphy_init_tail(void __iomem *phy_base, enum dram_board board,
278   - unsigned int freq, int ch)
279   -{
280   - int step;
281   -
282   - step = ddrphy_to_dly_step(phy_base, freq, ddrphy_adrctrl[board][ch]);
283   - ddrphy_set_dll_adrctrl(phy_base, step);
284   -
285   - step = ddrphy_to_dly_step(phy_base, freq, ddrphy_dlltrimclk[board][ch]);
286   - ddrphy_set_dll_trim_clk(phy_base, step);
287   -
288   - step = ddrphy_to_dly_step(phy_base, freq, ddrphy_dllrecalib[board][ch]);
289   - ddrphy_set_dll_recalib(phy_base, step);
290   -}
291   -
292   -static void ddrphy_shift_one_dq(void __iomem *phy_base, unsigned int reg,
293   - u32 mask, u32 incr, short shift_val)
294   -{
295   - u32 tmp;
296   - int val;
297   -
298   - tmp = readl(phy_base + reg);
299   -
300   - val = tmp & mask;
301   - if (!(tmp & incr))
302   - val = -val;
303   -
304   - val += shift_val;
305   -
306   - tmp &= ~(incr | mask);
307   - tmp |= min_t(u32, abs(val), mask);
308   - if (val >= 0)
309   - tmp |= incr;
310   -
311   - writel(tmp, phy_base + reg);
312   -}
313   -
314   -static void ddrphy_shift_dq(void __iomem *phy_base, unsigned int reg,
315   - u32 mask, u32 incr, u32 override,
316   - const short *shift_val_array)
317   -{
318   - u32 tmp;
319   - int dx, bit;
320   -
321   - tmp = readl(phy_base + reg);
322   - tmp |= override;
323   - writel(tmp, phy_base + reg);
324   -
325   - for (dx = 0; dx < 4; dx++) {
326   - for (bit = 0; bit < 8; bit++) {
327   - ddrphy_select_lane(phy_base,
328   - (PHY_BITLVL_DLY_WIDTH + 1) * dx,
329   - bit);
330   -
331   - ddrphy_shift_one_dq(phy_base, reg, mask, incr,
332   - shift_val_array[dx * 8 + bit]);
333   - }
334   - }
335   -
336   - ddrphy_select_lane(phy_base, 0, 0);
337   -}
338   -
339   -static int ddrphy_training(void __iomem *phy_base, enum dram_board board,
340   - int ch)
341   -{
342   - writel(0x0000000f, phy_base + PHY_WRLVL_AUTOINC_TRIM);
343   - writel(0x00010000, phy_base + PHY_DLL_TRIM_2);
344   - writel(0x50000000, phy_base + PHY_SCL_START);
345   -
346   - while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
347   - cpu_relax();
348   -
349   - writel(0x00000000, phy_base + PHY_DISABLE_GATING_FOR_SCL);
350   - writel(0xff00ff00, phy_base + PHY_SCL_DATA_0);
351   - writel(0xff00ff00, phy_base + PHY_SCL_DATA_1);
352   - writel(0xFBF8FFFF, phy_base + PHY_SCL_START_ADDR);
353   - writel(0x11000000, phy_base + PHY_SCL_START);
354   -
355   - while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
356   - cpu_relax();
357   -
358   - writel(0xFBF0FFFF, phy_base + PHY_SCL_START_ADDR);
359   - writel(0x30500000, phy_base + PHY_SCL_START);
360   -
361   - while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
362   - cpu_relax();
363   -
364   - writel(0x00000001, phy_base + PHY_DISABLE_GATING_FOR_SCL);
365   - writel(0x00000010, phy_base + PHY_SCL_MAIN_CLK_DELTA);
366   - writel(0x789b3de0, phy_base + PHY_SCL_DATA_0);
367   - writel(0xf10e4a56, phy_base + PHY_SCL_DATA_1);
368   - writel(0x11000000, phy_base + PHY_SCL_START);
369   -
370   - while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
371   - cpu_relax();
372   -
373   - writel(0x34000000, phy_base + PHY_SCL_START);
374   -
375   - while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
376   - cpu_relax();
377   -
378   - writel(0x00000003, phy_base + PHY_DISABLE_GATING_FOR_SCL);
379   -
380   - writel(0x000261c0, phy_base + PHY_DYNAMIC_WRITE_BIT_LVL);
381   - writel(0x00003270, phy_base + PHY_DYNAMIC_BIT_LVL);
382   - writel(0x011BD0C4, phy_base + PHY_DSCL_CNT);
383   -
384   - /* shift ip_dq trim */
385   - ddrphy_shift_dq(phy_base,
386   - PHY_IP_DQ_DQS_BITWISE_TRIM,
387   - PHY_IP_DQ_DQS_BITWISE_TRIM_MASK,
388   - PHY_IP_DQ_DQS_BITWISE_TRIM_INC,
389   - PHY_IP_DQ_DQS_BITWISE_TRIM_OVERRIDE,
390   - ddrphy_ip_dq_shift_val[board][ch]);
391   -
392   - /* shift op_dq trim */
393   - ddrphy_shift_dq(phy_base,
394   - PHY_OP_DQ_DM_DQS_BITWISE_TRIM,
395   - PHY_OP_DQ_DM_DQS_BITWISE_TRIM_MASK,
396   - PHY_OP_DQ_DM_DQS_BITWISE_TRIM_INC,
397   - PHY_OP_DQ_DM_DQS_BITWISE_TRIM_OVERRIDE,
398   - ddrphy_op_dq_shift_val[board][ch]);
399   -
400   - return 0;
401   -}
402   -
403   -/* UMC */
404   -static const u32 umc_initctla[DRAM_FREQ_NR] = {0x71016D11};
405   -static const u32 umc_initctlb[DRAM_FREQ_NR] = {0x07E390AC};
406   -static const u32 umc_initctlc[DRAM_FREQ_NR] = {0x00FF00FF};
407   -static const u32 umc_drmmr0[DRAM_FREQ_NR] = {0x00000114};
408   -static const u32 umc_drmmr2[DRAM_FREQ_NR] = {0x000002a0};
409   -
410   -static const u32 umc_memconf0a[DRAM_FREQ_NR][DRAM_SZ_NR] = {
411   - /* 256MB 512MB */
412   - {0x00000601, 0x00000801}, /* 1866 MHz */
413   -};
414   -
415   -static const u32 umc_memconf0b[DRAM_FREQ_NR][DRAM_SZ_NR] = {
416   - /* 256MB 512MB */
417   - {0x00000120, 0x00000130}, /* 1866 MHz */
418   -};
419   -
420   -static const u32 umc_memconfch[DRAM_FREQ_NR][DRAM_SZ_NR] = {
421   - /* 256MB 512MB */
422   - {0x00033603, 0x00033803}, /* 1866 MHz */
423   -};
424   -
425   -static const u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20};
426   -static const u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08};
427   -static const u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04};
428   -static const u32 umc_cmdctle[DRAM_FREQ_NR][DRAM_SZ_NR] = {
429   - /* 256MB 512MB */
430   - {0x0049071D, 0x0078071D}, /* 1866 MHz */
431   -};
432   -
433   -static const u32 umc_rdatactl[DRAM_FREQ_NR] = {0x00000610};
434   -static const u32 umc_wdatactl[DRAM_FREQ_NR] = {0x00000204};
435   -static const u32 umc_odtctl[DRAM_FREQ_NR] = {0x02000002};
436   -static const u32 umc_dataset[DRAM_FREQ_NR] = {0x04000000};
437   -
438   -static const u32 umc_flowctla[DRAM_FREQ_NR] = {0x0081E01E};
439   -static const u32 umc_directbusctrla[DRAM_CH_NR] = {
440   - 0x00000000, 0x00000001, 0x00000001
441   -};
442   -
443   -static void umc_poll_phy_init_complete(void __iomem *dc_base)
444   -{
445   - /* Wait for PHY Init Complete */
446   - while (!(readl(dc_base + UMC_DFISTCTLC) & BIT(0)))
447   - cpu_relax();
448   -}
449   -
450   -static int umc_dc_init(void __iomem *dc_base, unsigned int freq,
451   - unsigned long size, int ch)
452   -{
453   - enum dram_freq freq_e;
454   - enum dram_size size_e;
455   -
456   - switch (freq) {
457   - case 1866:
458   - freq_e = DRAM_FREQ_1866M;
459   - break;
460   - default:
461   - pr_err("unsupported DRAM frequency %ud MHz\n", freq);
462   - return -EINVAL;
463   - }
464   -
465   - switch (size) {
466   - case 0:
467   - return 0;
468   - case SZ_256M:
469   - size_e = DRAM_SZ_256M;
470   - break;
471   - case SZ_512M:
472   - size_e = DRAM_SZ_512M;
473   - break;
474   - default:
475   - pr_err("unsupported DRAM size 0x%08lx (per 16bit) for ch%d\n",
476   - size, ch);
477   - return -EINVAL;
478   - }
479   -
480   - writel(0x00000001, dc_base + UMC_DFICSOVRRD);
481   - writel(0x00000000, dc_base + UMC_DFITURNOFF);
482   -
483   - writel(umc_initctla[freq_e], dc_base + UMC_INITCTLA);
484   - writel(umc_initctlb[freq_e], dc_base + UMC_INITCTLB);
485   - writel(umc_initctlc[freq_e], dc_base + UMC_INITCTLC);
486   -
487   - writel(umc_drmmr0[freq_e], dc_base + UMC_DRMMR0);
488   - writel(0x00000004, dc_base + UMC_DRMMR1);
489   - writel(umc_drmmr2[freq_e], dc_base + UMC_DRMMR2);
490   - writel(0x00000000, dc_base + UMC_DRMMR3);
491   -
492   - writel(umc_memconf0a[freq_e][size_e], dc_base + UMC_MEMCONF0A);
493   - writel(umc_memconf0b[freq_e][size_e], dc_base + UMC_MEMCONF0B);
494   - writel(umc_memconfch[freq_e][size_e], dc_base + UMC_MEMCONFCH);
495   - writel(0x00000000, dc_base + UMC_MEMMAPSET);
496   -
497   - writel(umc_cmdctla[freq_e], dc_base + UMC_CMDCTLA);
498   - writel(umc_cmdctlb[freq_e], dc_base + UMC_CMDCTLB);
499   - writel(umc_cmdctlc[freq_e], dc_base + UMC_CMDCTLC);
500   - writel(umc_cmdctle[freq_e][size_e], dc_base + UMC_CMDCTLE);
501   -
502   - writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0);
503   - writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D1);
504   -
505   - writel(umc_wdatactl[freq_e], dc_base + UMC_WDATACTL_D0);
506   - writel(umc_wdatactl[freq_e], dc_base + UMC_WDATACTL_D1);
507   - writel(umc_odtctl[freq_e], dc_base + UMC_ODTCTL_D0);
508   - writel(umc_odtctl[freq_e], dc_base + UMC_ODTCTL_D1);
509   - writel(umc_dataset[freq_e], dc_base + UMC_DATASET);
510   -
511   - writel(0x00400020, dc_base + UMC_DCCGCTL);
512   - writel(0x00000003, dc_base + UMC_ACSSETA);
513   - writel(0x00000103, dc_base + UMC_FLOWCTLG);
514   - writel(0x00010200, dc_base + UMC_ACSSETB);
515   -
516   - writel(umc_flowctla[freq_e], dc_base + UMC_FLOWCTLA);
517   - writel(0x00004444, dc_base + UMC_FLOWCTLC);
518   - writel(0x00000000, dc_base + UMC_DFICUPDCTLA);
519   -
520   - writel(0x00202000, dc_base + UMC_FLOWCTLB);
521   - writel(0x00000000, dc_base + UMC_BSICMAPSET);
522   - writel(0x00000000, dc_base + UMC_ERRMASKA);
523   - writel(0x00000000, dc_base + UMC_ERRMASKB);
524   -
525   - writel(umc_directbusctrla[ch], dc_base + UMC_DIRECTBUSCTRLA);
526   -
527   - writel(0x00000001, dc_base + UMC_INITSET);
528   - /* Wait for PHY Init Complete */
529   - while (readl(dc_base + UMC_INITSTAT) & BIT(0))
530   - cpu_relax();
531   -
532   - writel(0x2A0A0A00, dc_base + UMC_SPCSETB);
533   - writel(0x00000000, dc_base + UMC_DFICSOVRRD);
534   -
535   - return 0;
536   -}
537   -
538   -static int umc_ch_init(void __iomem *umc_ch_base, void __iomem *phy_ch_base,
539   - enum dram_board board, unsigned int freq,
540   - unsigned long size, int ch)
541   -{
542   - void __iomem *dc_base = umc_ch_base + 0x00011000;
543   - void __iomem *phy_base = phy_ch_base;
544   - int ret;
545   -
546   - /* PHY Update Mode (ON) */
547   - writel(0x8000003f, dc_base + UMC_DFIPUPDCTLA);
548   -
549   - /* deassert PHY reset signals */
550   - writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST,
551   - dc_base + UMC_DIOCTLA);
552   -
553   - ddrphy_init(phy_base, board, ch);
554   -
555   - umc_poll_phy_init_complete(dc_base);
556   -
557   - ddrphy_init_tail(phy_base, board, freq, ch);
558   -
559   - ret = umc_dc_init(dc_base, freq, size, ch);
560   - if (ret)
561   - return ret;
562   -
563   - ret = ddrphy_training(phy_base, board, ch);
564   - if (ret)
565   - return ret;
566   -
567   - return 0;
568   -}
569   -
570   -static void um_init(void __iomem *um_base)
571   -{
572   - writel(0x000000ff, um_base + UMC_MBUS0);
573   - writel(0x000000ff, um_base + UMC_MBUS1);
574   - writel(0x000000ff, um_base + UMC_MBUS2);
575   - writel(0x00000001, um_base + UMC_MBUS3);
576   - writel(0x00000001, um_base + UMC_MBUS4);
577   - writel(0x00000001, um_base + UMC_MBUS5);
578   - writel(0x00000001, um_base + UMC_MBUS6);
579   - writel(0x00000001, um_base + UMC_MBUS7);
580   - writel(0x00000001, um_base + UMC_MBUS8);
581   - writel(0x00000001, um_base + UMC_MBUS9);
582   - writel(0x00000001, um_base + UMC_MBUS10);
583   -}
584   -
585   -int uniphier_ld20_umc_init(const struct uniphier_board_data *bd)
586   -{
587   - void __iomem *um_base = (void __iomem *)0x5b600000;
588   - void __iomem *umc_ch_base = (void __iomem *)0x5b800000;
589   - void __iomem *phy_ch_base = (void __iomem *)0x6e200000;
590   - enum dram_board board;
591   - int ch, ret;
592   -
593   - switch (UNIPHIER_BD_BOARD_GET_TYPE(bd->flags)) {
594   - case UNIPHIER_BD_BOARD_LD20_REF:
595   - board = DRAM_BOARD_LD20_REF;
596   - break;
597   - case UNIPHIER_BD_BOARD_LD20_GLOBAL:
598   - board = DRAM_BOARD_LD20_GLOBAL;
599   - break;
600   - case UNIPHIER_BD_BOARD_LD20_C1:
601   - board = DRAM_BOARD_LD20_C1;
602   - break;
603   - case UNIPHIER_BD_BOARD_LD21_REF:
604   - board = DRAM_BOARD_LD21_REF;
605   - break;
606   - case UNIPHIER_BD_BOARD_LD21_GLOBAL:
607   - board = DRAM_BOARD_LD21_GLOBAL;
608   - break;
609   - default:
610   - pr_err("unsupported board type %d\n",
611   - UNIPHIER_BD_BOARD_GET_TYPE(bd->flags));
612   - return -EINVAL;
613   - }
614   -
615   - for (ch = 0; ch < DRAM_CH_NR; ch++) {
616   - unsigned long size = bd->dram_ch[ch].size;
617   - unsigned int width = bd->dram_ch[ch].width;
618   -
619   - if (size) {
620   - ret = umc_ch_init(umc_ch_base, phy_ch_base, board,
621   - bd->dram_freq, size / (width / 16),
622   - ch);
623   - if (ret) {
624   - pr_err("failed to initialize UMC ch%d\n", ch);
625   - return ret;
626   - }
627   - }
628   -
629   - umc_ch_base += 0x00200000;
630   - phy_ch_base += 0x00004000;
631   - }
632   -
633   - um_init(um_base);
634   -
635   - return 0;
636   -}
arch/arm/mach-uniphier/dram/umc64-regs.h
View file @ ee8d037
1   -/*
2   - * Copyright (C) 2016 Socionext Inc.
3   - */
4   -
5   -#ifndef UMC_LD20_REGS_H
6   -#define UMC_LD20_REGS_H
7   -
8   -#define UMC_CMDCTLA 0x00000000
9   -#define UMC_CMDCTLB 0x00000004
10   -#define UMC_CMDCTLC 0x00000008
11   -#define UMC_INITCTLA 0x00000020
12   -#define UMC_INITCTLB 0x00000024
13   -#define UMC_INITCTLC 0x00000028
14   -#define UMC_DRMMR0 0x00000030
15   -#define UMC_DRMMR1 0x00000034
16   -#define UMC_DRMMR2 0x00000038
17   -#define UMC_DRMMR3 0x0000003C
18   -#define UMC_INITSET 0x00000040
19   -#define UMC_INITSTAT 0x00000044
20   -#define UMC_CMDCTLE 0x00000050
21   -#define UMC_CMDCTLF 0x00000054
22   -#define UMC_CMDCTLG 0x00000058
23   -#define UMC_SPCSETB 0x00000084
24   -#define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */
25   -#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */
26   -#define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */
27   -#define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */
28   -#define UMC_ACSSETA 0x000000C0
29   -#define UMC_ACSSETB 0x000000C4
30   -#define UMC_MEMCONF0A 0x00000200
31   -#define UMC_MEMCONF0B 0x00000204
32   -#define UMC_MEMCONFCH 0x00000240
33   -#define UMC_MEMMAPSET 0x00000250
34   -#define UMC_FLOWCTLA 0x00000400
35   -#define UMC_FLOWCTLB 0x00000404
36   -#define UMC_FLOWCTLC 0x00000408
37   -#define UMC_ACFETCHCTRL 0x00000460
38   -#define UMC_FLOWCTLG 0x00000508
39   -#define UMC_RDATACTL_D0 0x00000600
40   -#define UMC_WDATACTL_D0 0x00000604
41   -#define UMC_RDATACTL_D1 0x00000608
42   -#define UMC_WDATACTL_D1 0x0000060C
43   -#define UMC_DATASET 0x00000610
44   -#define UMC_ODTCTL_D0 0x00000618
45   -#define UMC_ODTCTL_D1 0x0000061C
46   -#define UMC_RESPCTL 0x00000624
47   -#define UMC_DIRECTBUSCTRLA 0x00000680
48   -#define UMC_DEBUGC 0x00000718
49   -#define UMC_DCCGCTL 0x00000720
50   -#define UMC_DICGCTLA 0x00000724
51   -#define UMC_DICGCTLB 0x00000728
52   -#define UMC_ERRMASKA 0x00000958
53   -#define UMC_ERRMASKB 0x0000095C
54   -#define UMC_BSICMAPSET 0x00000988
55   -#define UMC_DIOCTLA 0x00000C00
56   -#define UMC_DIOCTLA_CTL_NRST BIT(8) /* ctl_rst_n */
57   -#define UMC_DIOCTLA_CFG_NRST BIT(0) /* cfg_rst_n */
58   -#define UMC_DFISTCTLC 0x00000C18
59   -#define UMC_DFICUPDCTLA 0x00000C20
60   -#define UMC_DFIPUPDCTLA 0x00000C30
61   -#define UMC_DFICSOVRRD 0x00000C84
62   -#define UMC_DFITURNOFF 0x00000C88
63   -
64   -/* UM registers */
65   -#define UMC_MBUS0 0x00080004
66   -#define UMC_MBUS1 0x00081004
67   -#define UMC_MBUS2 0x00082004
68   -#define UMC_MBUS3 0x00000C78
69   -#define UMC_MBUS4 0x00000CF8
70   -#define UMC_MBUS5 0x00000E78
71   -#define UMC_MBUS6 0x00000EF8
72   -#define UMC_MBUS7 0x00001278
73   -#define UMC_MBUS8 0x000012F8
74   -#define UMC_MBUS9 0x00002478
75   -#define UMC_MBUS10 0x000024F8
76   -
77   -/* UMC1 register */
78   -#define UMC_SIORST 0x00000728
79   -#define UMC_VO0RST 0x0000073c
80   -#define UMC_VPERST 0x00000744
81   -#define UMC_RGLRST 0x00000750
82   -#define UMC_A2DRST 0x00000764
83   -#define UMC_DMDRST 0x00000770
84   -
85   -#endif /* UMC_LD20_REGS_H */
arch/arm/mach-uniphier/init.h
Diff comments   View file @ ee8d037
... ... @@ -24,13 +24,6 @@
24 24  
25 25 #define UNIPHIER_BD_DRAM_SPARSE BIT(9)
26 26 #define UNIPHIER_BD_DDR3PLUS BIT(8)
27   -
28   -#define UNIPHIER_BD_BOARD_GET_TYPE(f) ((f) & 0x7)
29   -#define UNIPHIER_BD_BOARD_LD20_REF 0 /* LD20 reference */
30   -#define UNIPHIER_BD_BOARD_LD20_GLOBAL 1 /* LD20 TV Set */
31   -#define UNIPHIER_BD_BOARD_LD20_C1 2 /* LD20 TV Set C1 */
32   -#define UNIPHIER_BD_BOARD_LD21_REF 3 /* LD21 reference */
33   -#define UNIPHIER_BD_BOARD_LD21_GLOBAL 4 /* LD21 TV Set */
34 27 };
35 28  
36 29 const struct uniphier_board_data *uniphier_get_board_param(void);
... ... @@ -41,8 +34,6 @@
41 34 int uniphier_sld8_init(const struct uniphier_board_data *bd);
42 35 int uniphier_pro5_init(const struct uniphier_board_data *bd);
43 36 int uniphier_pxs2_init(const struct uniphier_board_data *bd);
44   -int uniphier_ld11_init(const struct uniphier_board_data *bd);
45   -int uniphier_ld20_init(const struct uniphier_board_data *bd);
46 37  
47 38 #if defined(CONFIG_MICRO_SUPPORT_CARD)
48 39 void uniphier_sbc_init_admulti(void);
49 40  
50 41  
... ... @@ -85,17 +76,12 @@
85 76 int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd);
86 77 int uniphier_pro5_dpll_init(const struct uniphier_board_data *bd);
87 78 int uniphier_pxs2_dpll_init(const struct uniphier_board_data *bd);
88   -int uniphier_ld11_dpll_init(const struct uniphier_board_data *bd);
89   -int uniphier_ld20_dpll_init(const struct uniphier_board_data *bd);
90 79  
91 80 void uniphier_sld3_early_clk_init(void);
92   -void uniphier_ld11_early_clk_init(void);
93 81  
94 82 void uniphier_sld3_dram_clk_init(void);
95 83 void uniphier_pro5_dram_clk_init(void);
96 84 void uniphier_pxs2_dram_clk_init(void);
97   -void uniphier_ld11_dram_clk_init(void);
98   -void uniphier_ld20_dram_clk_init(void);
99 85  
100 86 int uniphier_sld3_umc_init(const struct uniphier_board_data *bd);
101 87 int uniphier_ld4_umc_init(const struct uniphier_board_data *bd);
... ... @@ -103,8 +89,6 @@
103 89 int uniphier_sld8_umc_init(const struct uniphier_board_data *bd);
104 90 int uniphier_pro5_umc_init(const struct uniphier_board_data *bd);
105 91 int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd);
106   -int uniphier_ld20_umc_init(const struct uniphier_board_data *bd);
107   -int uniphier_ld11_umc_init(const struct uniphier_board_data *bd);
108 92  
109 93 void uniphier_sld3_pll_init(void);
110 94 void uniphier_ld4_pll_init(void);
... ... @@ -125,8 +109,6 @@
125 109 int uniphier_have_internal_stm(void);
126 110 int uniphier_boot_from_backend(void);
127 111 int uniphier_pin_init(const char *pinconfig_name);
128   -void uniphier_smp_kick_all_cpus(void);
129   -void cci500_init(unsigned int nr_slaves);
130 112  
131 113 #undef pr_warn
132 114 #define pr_warn(fmt, args...) printf(fmt, ##args)
arch/arm/mach-uniphier/spl_board_init.c
Diff comments   View file @ ee8d037
... ... @@ -97,26 +97,6 @@
97 97 .umc_init = uniphier_pxs2_umc_init,
98 98 },
99 99 #endif
100   -#if defined(CONFIG_ARCH_UNIPHIER_LD11)
101   - {
102   - .soc_id = UNIPHIER_LD11_ID,
103   - .early_clk_init = uniphier_ld11_early_clk_init,
104   - .dpll_init = uniphier_ld11_dpll_init,
105   - .memconf_init = uniphier_memconf_2ch_init,
106   - .dram_clk_init = uniphier_ld11_dram_clk_init,
107   - .umc_init = uniphier_ld11_umc_init,
108   - },
109   -#endif
110   -#if defined(CONFIG_ARCH_UNIPHIER_LD20)
111   - {
112   - .soc_id = UNIPHIER_LD20_ID,
113   - .early_clk_init = uniphier_ld11_early_clk_init,
114   - .dpll_init = uniphier_ld20_dpll_init,
115   - .memconf_init = uniphier_memconf_3ch_init,
116   - .dram_clk_init = uniphier_ld20_dram_clk_init,
117   - .umc_init = uniphier_ld20_umc_init,
118   - },
119   -#endif
120 100 };
121 101 UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_spl_initdata, uniphier_spl_initdata)
122 102  
123 103  
... ... @@ -141,10 +121,8 @@
141 121 if (initdata->bcu_init)
142 122 initdata->bcu_init(bd);
143 123  
144   -
145 124 initdata->early_clk_init();
146 125  
147   -
148 126 #ifdef CONFIG_SPL_SERIAL_SUPPORT
149 127 preloader_console_init();
150 128 #endif
... ... @@ -168,9 +146,5 @@
168 146 pr_err("failed to init DRAM\n");
169 147 hang();
170 148 }
171   -
172   -#ifdef CONFIG_ARM64
173   - dcache_disable();
174   -#endif
175 149 }
configs/uniphier_ld11_defconfig
View file @ ee8d037
1   -CONFIG_ARM=y
2   -CONFIG_ARCH_UNIPHIER=y
3   -CONFIG_SYS_TEXT_BASE=0x84000000
4   -CONFIG_SYS_MALLOC_F_LEN=0x2000
5   -CONFIG_SPL_SERIAL_SUPPORT=y
6   -CONFIG_ARCH_UNIPHIER_LD11_SINGLE=y
7   -CONFIG_MICRO_SUPPORT_CARD=y
8   -CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld11-ref"
9   -# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
10   -CONFIG_SPL=y
11   -CONFIG_SPL_NOR_SUPPORT=y
12   -CONFIG_HUSH_PARSER=y
13   -CONFIG_CMD_CONFIG=y
14   -# CONFIG_CMD_XIMG is not set
15   -# CONFIG_CMD_ENV_EXISTS is not set
16   -CONFIG_CMD_GPT=y
17   -CONFIG_CMD_MMC=y
18   -CONFIG_CMD_I2C=y
19   -CONFIG_CMD_USB=y
20   -# CONFIG_CMD_FPGA is not set
21   -CONFIG_CMD_GPIO=y
22   -CONFIG_CMD_TFTPPUT=y
23   -CONFIG_CMD_PING=y
24   -CONFIG_CMD_CACHE=y
25   -CONFIG_CMD_TIME=y
26   -# CONFIG_CMD_MISC is not set
27   -CONFIG_CMD_FAT=y
28   -# CONFIG_SPL_DOS_PARTITION is not set
29   -# CONFIG_SPL_EFI_PARTITION is not set
30   -CONFIG_NET_RANDOM_ETHADDR=y
31   -CONFIG_SPL_OF_TRANSLATE=y
32   -CONFIG_GPIO_UNIPHIER=y
33   -CONFIG_MISC=y
34   -CONFIG_I2C_EEPROM=y
35   -CONFIG_MMC_SDHCI=y
36   -CONFIG_MMC_SDHCI_SDMA=y
37   -CONFIG_MMC_SDHCI_CADENCE=y
38   -CONFIG_USB=y
39   -CONFIG_USB_EHCI_HCD=y
40   -CONFIG_USB_EHCI_GENERIC=y
41   -CONFIG_USB_STORAGE=y
configs/uniphier_ld20_defconfig
View file @ ee8d037
1   -CONFIG_ARM=y
2   -CONFIG_ARCH_UNIPHIER=y
3   -CONFIG_SYS_TEXT_BASE=0x84000000
4   -CONFIG_SYS_MALLOC_F_LEN=0x2000
5   -CONFIG_SPL_SERIAL_SUPPORT=y
6   -CONFIG_ARCH_UNIPHIER_LD20_SINGLE=y
7   -CONFIG_MICRO_SUPPORT_CARD=y
8   -CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld20-ref"
9   -# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
10   -CONFIG_SPL=y
11   -CONFIG_SPL_NOR_SUPPORT=y
12   -CONFIG_HUSH_PARSER=y
13   -CONFIG_CMD_CONFIG=y
14   -# CONFIG_CMD_XIMG is not set
15   -# CONFIG_CMD_ENV_EXISTS is not set
16   -CONFIG_CMD_GPT=y
17   -CONFIG_CMD_MMC=y
18   -CONFIG_CMD_I2C=y
19   -CONFIG_CMD_USB=y
20   -# CONFIG_CMD_FPGA is not set
21   -CONFIG_CMD_GPIO=y
22   -CONFIG_CMD_TFTPPUT=y
23   -CONFIG_CMD_PING=y
24   -CONFIG_CMD_CACHE=y
25   -CONFIG_CMD_TIME=y
26   -# CONFIG_CMD_MISC is not set
27   -CONFIG_CMD_FAT=y
28   -# CONFIG_SPL_DOS_PARTITION is not set
29   -# CONFIG_SPL_EFI_PARTITION is not set
30   -CONFIG_NET_RANDOM_ETHADDR=y
31   -CONFIG_SPL_OF_TRANSLATE=y
32   -CONFIG_GPIO_UNIPHIER=y
33   -CONFIG_MISC=y
34   -CONFIG_I2C_EEPROM=y
35   -CONFIG_MMC_UNIPHIER=y
36   -CONFIG_MMC_SDHCI=y
37   -CONFIG_MMC_SDHCI_CADENCE=y
38   -CONFIG_USB=y
39   -CONFIG_USB_XHCI_HCD=y
40   -CONFIG_USB_STORAGE=y
... ... @@ -55,11 +55,11 @@
55 55 $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-ld6b-ref
56 56  
57 57 LD11 reference board:
58   - $ make uniphier_ld11_defconfig
59   - $ make CROSS_COMPILE=aarch64-linux-gnu-
  58 + $ make uniphier_v8_defconfig
  59 + $ make CROSS_COMPILE=aarch64-linux-gnu- DEVICE_TREE=uniphier-ld11-ref
60 60  
61 61 LD20 reference board:
62   - $ make uniphier_ld20_defconfig
  62 + $ make uniphier_v8_defconfig
63 63 $ make CROSS_COMPILE=aarch64-linux-gnu-
64 64  
65 65 PXs3 reference board:
drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
Diff comments   View file @ ee8d037
... ... @@ -59,12 +59,12 @@
59 59 UNIPHIER_PINCTRL_GROUP(i2c3),
60 60 UNIPHIER_PINCTRL_GROUP(i2c4),
61 61 UNIPHIER_PINCTRL_GROUP(nand),
62   - UNIPHIER_PINCTRL_GROUP_SPL(system_bus),
63   - UNIPHIER_PINCTRL_GROUP_SPL(system_bus_cs1),
64   - UNIPHIER_PINCTRL_GROUP_SPL(uart0),
65   - UNIPHIER_PINCTRL_GROUP_SPL(uart1),
66   - UNIPHIER_PINCTRL_GROUP_SPL(uart2),
67   - UNIPHIER_PINCTRL_GROUP_SPL(uart3),
  62 + UNIPHIER_PINCTRL_GROUP(system_bus),
  63 + UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
  64 + UNIPHIER_PINCTRL_GROUP(uart0),
  65 + UNIPHIER_PINCTRL_GROUP(uart1),
  66 + UNIPHIER_PINCTRL_GROUP(uart2),
  67 + UNIPHIER_PINCTRL_GROUP(uart3),
68 68 UNIPHIER_PINCTRL_GROUP(usb0),
69 69 UNIPHIER_PINCTRL_GROUP(usb1),
70 70 UNIPHIER_PINCTRL_GROUP(usb2),
... ... @@ -78,11 +78,11 @@
78 78 UNIPHIER_PINMUX_FUNCTION(i2c3),
79 79 UNIPHIER_PINMUX_FUNCTION(i2c4),
80 80 UNIPHIER_PINMUX_FUNCTION(nand),
81   - UNIPHIER_PINMUX_FUNCTION_SPL(system_bus),
82   - UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
83   - UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
84   - UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
85   - UNIPHIER_PINMUX_FUNCTION_SPL(uart3),
  81 + UNIPHIER_PINMUX_FUNCTION(system_bus),
  82 + UNIPHIER_PINMUX_FUNCTION(uart0),
  83 + UNIPHIER_PINMUX_FUNCTION(uart1),
  84 + UNIPHIER_PINMUX_FUNCTION(uart2),
  85 + UNIPHIER_PINMUX_FUNCTION(uart3),
86 86 UNIPHIER_PINMUX_FUNCTION(usb0),
87 87 UNIPHIER_PINMUX_FUNCTION(usb1),
88 88 UNIPHIER_PINMUX_FUNCTION(usb2),
drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
Diff comments   View file @ ee8d037
... ... @@ -69,12 +69,12 @@
69 69 UNIPHIER_PINCTRL_GROUP(i2c4),
70 70 UNIPHIER_PINCTRL_GROUP(nand),
71 71 UNIPHIER_PINCTRL_GROUP(sd),
72   - UNIPHIER_PINCTRL_GROUP_SPL(system_bus),
73   - UNIPHIER_PINCTRL_GROUP_SPL(system_bus_cs1),
74   - UNIPHIER_PINCTRL_GROUP_SPL(uart0),
75   - UNIPHIER_PINCTRL_GROUP_SPL(uart1),
76   - UNIPHIER_PINCTRL_GROUP_SPL(uart2),
77   - UNIPHIER_PINCTRL_GROUP_SPL(uart3),
  72 + UNIPHIER_PINCTRL_GROUP(system_bus),
  73 + UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
  74 + UNIPHIER_PINCTRL_GROUP(uart0),
  75 + UNIPHIER_PINCTRL_GROUP(uart1),
  76 + UNIPHIER_PINCTRL_GROUP(uart2),
  77 + UNIPHIER_PINCTRL_GROUP(uart3),
78 78 UNIPHIER_PINCTRL_GROUP(usb0),
79 79 UNIPHIER_PINCTRL_GROUP(usb1),
80 80 UNIPHIER_PINCTRL_GROUP(usb2),
... ... @@ -91,11 +91,11 @@
91 91 UNIPHIER_PINMUX_FUNCTION(i2c4),
92 92 UNIPHIER_PINMUX_FUNCTION(nand),
93 93 UNIPHIER_PINMUX_FUNCTION(sd),
94   - UNIPHIER_PINMUX_FUNCTION_SPL(system_bus),
95   - UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
96   - UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
97   - UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
98   - UNIPHIER_PINMUX_FUNCTION_SPL(uart3),
  94 + UNIPHIER_PINMUX_FUNCTION(system_bus),
  95 + UNIPHIER_PINMUX_FUNCTION(uart0),
  96 + UNIPHIER_PINMUX_FUNCTION(uart1),
  97 + UNIPHIER_PINMUX_FUNCTION(uart2),
  98 + UNIPHIER_PINMUX_FUNCTION(uart3),
99 99 UNIPHIER_PINMUX_FUNCTION(usb0),
100 100 UNIPHIER_PINMUX_FUNCTION(usb1),
101 101 UNIPHIER_PINMUX_FUNCTION(usb2),
drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c
Diff comments   View file @ ee8d037
... ... @@ -78,12 +78,12 @@
78 78 UNIPHIER_PINCTRL_GROUP(i2c3),
79 79 UNIPHIER_PINCTRL_GROUP(nand),
80 80 UNIPHIER_PINCTRL_GROUP(sd),
81   - UNIPHIER_PINCTRL_GROUP_SPL(system_bus),
82   - UNIPHIER_PINCTRL_GROUP_SPL(system_bus_cs1),
83   - UNIPHIER_PINCTRL_GROUP_SPL(uart0),
84   - UNIPHIER_PINCTRL_GROUP_SPL(uart1),
85   - UNIPHIER_PINCTRL_GROUP_SPL(uart2),
86   - UNIPHIER_PINCTRL_GROUP_SPL(uart3),
  81 + UNIPHIER_PINCTRL_GROUP(system_bus),
  82 + UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
  83 + UNIPHIER_PINCTRL_GROUP(uart0),
  84 + UNIPHIER_PINCTRL_GROUP(uart1),
  85 + UNIPHIER_PINCTRL_GROUP(uart2),
  86 + UNIPHIER_PINCTRL_GROUP(uart3),
87 87 UNIPHIER_PINCTRL_GROUP(usb0),
88 88 UNIPHIER_PINCTRL_GROUP(usb1),
89 89 UNIPHIER_PINCTRL_GROUP(usb2),
... ... @@ -102,11 +102,11 @@
102 102 UNIPHIER_PINMUX_FUNCTION(i2c3),
103 103 UNIPHIER_PINMUX_FUNCTION(nand),
104 104 UNIPHIER_PINMUX_FUNCTION(sd),
105   - UNIPHIER_PINMUX_FUNCTION_SPL(system_bus),
106   - UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
107   - UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
108   - UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
109   - UNIPHIER_PINMUX_FUNCTION_SPL(uart3),
  105 + UNIPHIER_PINMUX_FUNCTION(system_bus),
  106 + UNIPHIER_PINMUX_FUNCTION(uart0),
  107 + UNIPHIER_PINMUX_FUNCTION(uart1),
  108 + UNIPHIER_PINMUX_FUNCTION(uart2),
  109 + UNIPHIER_PINMUX_FUNCTION(uart3),
110 110 UNIPHIER_PINMUX_FUNCTION(usb0),
111 111 UNIPHIER_PINMUX_FUNCTION(usb1),
112 112 UNIPHIER_PINMUX_FUNCTION(usb2),
include/configs/uniphier.h
Diff comments   View file @ ee8d037
... ... @@ -77,17 +77,7 @@
77 77 #define CONFIG_SYS_MMC_ENV_DEV 0
78 78 #define CONFIG_SYS_MMC_ENV_PART 1
79 79  
80   -#ifdef CONFIG_ARMV8_MULTIENTRY
81   -#define CPU_RELEASE_ADDR 0x80000000
82   -#define COUNTER_FREQUENCY 50000000
83   -#define CONFIG_GICV3
84   -#define GICD_BASE 0x5fe00000
85   -#if defined(CONFIG_ARCH_UNIPHIER_LD11)
86   -#define GICR_BASE 0x5fe40000
87   -#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
88   -#define GICR_BASE 0x5fe80000
89   -#endif
90   -#elif !defined(CONFIG_ARM64)
  80 +#if !defined(CONFIG_ARM64)
91 81 /* Time clock 1MHz */
92 82 #define CONFIG_SYS_TIMER_RATE 1000000
93 83 #endif
... ... @@ -134,7 +124,7 @@
134 124  
135 125 #define CONFIG_CMDLINE_EDITING /* add command line history */
136 126  
137   -#if defined(CONFIG_ARM64) && !defined(CONFIG_ARMV8_MULTIENTRY)
  127 +#if defined(CONFIG_ARM64)
138 128 /* ARM Trusted Firmware */
139 129 #define BOOT_IMAGES \
140 130 "second_image=unph_bl.bin\0" \
... ... @@ -262,9 +252,7 @@
262 252 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
263 253  
264 254 /* only for SPL */
265   -#if defined(CONFIG_ARM64)
266   -#define CONFIG_SPL_TEXT_BASE 0x30000000
267   -#elif defined(CONFIG_ARCH_UNIPHIER_SLD3) || \
  255 +#if defined(CONFIG_ARCH_UNIPHIER_SLD3) || \
268 256 defined(CONFIG_ARCH_UNIPHIER_LD4) || \
269 257 defined(CONFIG_ARCH_UNIPHIER_SLD8)
270 258 #define CONFIG_SPL_TEXT_BASE 0x00040000
271 259  
272 260  
... ... @@ -272,18 +260,9 @@
272 260 #define CONFIG_SPL_TEXT_BASE 0x00100000
273 261 #endif
274 262  
275   -#if defined(CONFIG_ARCH_UNIPHIER_LD11)
276   -#define CONFIG_SPL_STACK (0x30014c00)
277   -#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
278   -#define CONFIG_SPL_STACK (0x3001c000)
279   -#else
280 263 #define CONFIG_SPL_STACK (0x00100000)
281   -#endif
282 264  
283 265 #define CONFIG_SPL_FRAMEWORK
284   -#ifdef CONFIG_ARM64
285   -#define CONFIG_SPL_BOARD_LOAD_IMAGE
286   -#endif
287 266  
288 267 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
289 268  
290 269  
... ... @@ -292,16 +271,7 @@
292 271  
293 272 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
294 273 #define CONFIG_SPL_MAX_FOOTPRINT 0x10000
295   -#if defined(CONFIG_ARCH_UNIPHIER_LD20)
296   -#define CONFIG_SPL_MAX_SIZE 0x14000
297   -#else
298 274 #define CONFIG_SPL_MAX_SIZE 0x10000
299   -#endif
300   -#if defined(CONFIG_ARCH_UNIPHIER_LD11)
301   -#define CONFIG_SPL_BSS_START_ADDR 0x30012000
302   -#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
303   -#define CONFIG_SPL_BSS_START_ADDR 0x30016000
304   -#endif
305 275 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000
306 276  
307 277 #define CONFIG_SPL_PAD_TO 0x20000