Eric Lee / smarc-uboot

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Commit f017cd7f71fa98be4b3222a7c314ef000296c51a

Authored by Masahiro Yamada
Committed by Tom Rini
1 parent 79cbecb81b
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

mpc8xx: remove NETVIA board support 

This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Pantelis Antoniou <panto@intracom.gr>

Showing 14 changed files with 1 additions and 1564 deletions Side-by-side Diff

arch/powerpc/cpu/mpc8xx/Kconfig
Diff comments   View file @ f017cd7
... ... @@ -25,9 +25,6 @@
25 25 config TARGET_LWMON
26 26 bool "Support lwmon"
27 27  
28   -config TARGET_NETVIA
29   - bool "Support NETVIA"
30   -
31 28 config TARGET_TQM823L
32 29 bool "Support TQM823L"
33 30  
... ... @@ -71,7 +68,6 @@
71 68 source "board/ip860/Kconfig"
72 69 source "board/ivm/Kconfig"
73 70 source "board/lwmon/Kconfig"
74   -source "board/netvia/Kconfig"
75 71 source "board/tqc/tqm8xx/Kconfig"
76 72  
77 73 endmenu
arch/powerpc/cpu/mpc8xx/scc.c
Diff comments   View file @ f017cd7
... ... @@ -448,26 +448,6 @@
448 448 #error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
449 449 #endif
450 450  
451   -#if defined(CONFIG_NETVIA)
452   -#if defined(PA_ENET_PDN)
453   - immr->im_ioport.iop_papar &= ~PA_ENET_PDN;
454   - immr->im_ioport.iop_padir |= PA_ENET_PDN;
455   - immr->im_ioport.iop_padat |= PA_ENET_PDN;
456   -#elif defined(PB_ENET_PDN)
457   - immr->im_cpm.cp_pbpar &= ~PB_ENET_PDN;
458   - immr->im_cpm.cp_pbdir |= PB_ENET_PDN;
459   - immr->im_cpm.cp_pbdat |= PB_ENET_PDN;
460   -#elif defined(PC_ENET_PDN)
461   - immr->im_ioport.iop_pcpar &= ~PC_ENET_PDN;
462   - immr->im_ioport.iop_pcdir |= PC_ENET_PDN;
463   - immr->im_ioport.iop_pcdat |= PC_ENET_PDN;
464   -#elif defined(PD_ENET_PDN)
465   - immr->im_ioport.iop_pdpar &= ~PD_ENET_PDN;
466   - immr->im_ioport.iop_pddir |= PD_ENET_PDN;
467   - immr->im_ioport.iop_pddat |= PD_ENET_PDN;
468   -#endif
469   -#endif
470   -
471 451 /*
472 452 * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
473 453 */
board/netvia/Kconfig
View file @ f017cd7
1   -if TARGET_NETVIA
2   -
3   -config SYS_BOARD
4   - default "netvia"
5   -
6   -config SYS_CONFIG_NAME
7   - default "NETVIA"
8   -
9   -endif
board/netvia/MAINTAINERS
View file @ f017cd7
1   -NETVIA BOARD
2   -M: Pantelis Antoniou <panto@intracom.gr>
3   -S: Maintained
4   -F: board/netvia/
5   -F: include/configs/NETVIA.h
6   -F: configs/NETVIA_defconfig
7   -F: configs/NETVIA_V2_defconfig
board/netvia/Makefile
View file @ f017cd7
1   -#
2   -# (C) Copyright 2000-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -obj-y = netvia.o flash.o
board/netvia/flash.c
View file @ f017cd7
1   -/*
2   - * (C) Copyright 2000
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <mpc8xx.h>
10   -
11   -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
12   -
13   -/*-----------------------------------------------------------------------
14   - * Functions
15   - */
16   -static ulong flash_get_size(vu_long * addr, flash_info_t * info);
17   -static int write_byte(flash_info_t * info, ulong dest, uchar data);
18   -static void flash_get_offsets(ulong base, flash_info_t * info);
19   -
20   -/*-----------------------------------------------------------------------
21   - */
22   -
23   -unsigned long flash_init(void)
24   -{
25   - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
26   - volatile memctl8xx_t *memctl = &immap->im_memctl;
27   - unsigned long size;
28   - int i;
29   -
30   - /* Init: no FLASHes known */
31   - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
32   - flash_info[i].flash_id = FLASH_UNKNOWN;
33   -
34   - size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
35   -
36   - if (flash_info[0].flash_id == FLASH_UNKNOWN) {
37   - printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size, size << 20);
38   - }
39   -
40   - /* Remap FLASH according to real size */
41   - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
42   - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
43   -
44   - /* Re-do sizing to get full correct info */
45   - size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
46   -
47   - flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
48   -
49   - /* monitor protection ON by default */
50   - flash_protect(FLAG_PROTECT_SET,
51   - CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
52   - &flash_info[0]);
53   -
54   - flash_protect ( FLAG_PROTECT_SET,
55   - CONFIG_ENV_ADDR,
56   - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
57   - &flash_info[0]);
58   -
59   -#ifdef CONFIG_ENV_ADDR_REDUND
60   - flash_protect ( FLAG_PROTECT_SET,
61   - CONFIG_ENV_ADDR_REDUND,
62   - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
63   - &flash_info[0]);
64   -#endif
65   -
66   -
67   - flash_info[0].size = size;
68   -
69   - return (size);
70   -}
71   -
72   -/*-----------------------------------------------------------------------
73   - */
74   -static void flash_get_offsets(ulong base, flash_info_t * info)
75   -{
76   - int i;
77   -
78   - /* set up sector start address table */
79   - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
80   - for (i = 0; i < info->sector_count; i++) {
81   - info->start[i] = base + (i * 0x00010000);
82   - }
83   - } else if (info->flash_id & FLASH_BTYPE) {
84   - /* set sector offsets for bottom boot block type */
85   - info->start[0] = base + 0x00000000;
86   - info->start[1] = base + 0x00004000;
87   - info->start[2] = base + 0x00006000;
88   - info->start[3] = base + 0x00008000;
89   - for (i = 4; i < info->sector_count; i++) {
90   - info->start[i] = base + (i * 0x00010000) - 0x00030000;
91   - }
92   - } else {
93   - /* set sector offsets for top boot block type */
94   - i = info->sector_count - 1;
95   - info->start[i--] = base + info->size - 0x00004000;
96   - info->start[i--] = base + info->size - 0x00006000;
97   - info->start[i--] = base + info->size - 0x00008000;
98   - for (; i >= 0; i--) {
99   - info->start[i] = base + i * 0x00010000;
100   - }
101   - }
102   -
103   -}
104   -
105   -/*-----------------------------------------------------------------------
106   - */
107   -void flash_print_info(flash_info_t * info)
108   -{
109   - int i;
110   -
111   - if (info->flash_id == FLASH_UNKNOWN) {
112   - printf("missing or unknown FLASH type\n");
113   - return;
114   - }
115   -
116   - switch (info->flash_id & FLASH_VENDMASK) {
117   - case FLASH_MAN_AMD:
118   - printf("AMD ");
119   - break;
120   - case FLASH_MAN_FUJ:
121   - printf("FUJITSU ");
122   - break;
123   - case FLASH_MAN_MX:
124   - printf("MXIC ");
125   - break;
126   - default:
127   - printf("Unknown Vendor ");
128   - break;
129   - }
130   -
131   - switch (info->flash_id & FLASH_TYPEMASK) {
132   - case FLASH_AM040:
133   - printf("AM29LV040B (4 Mbit, bottom boot sect)\n");
134   - break;
135   - case FLASH_AM400B:
136   - printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
137   - break;
138   - case FLASH_AM400T:
139   - printf("AM29LV400T (4 Mbit, top boot sector)\n");
140   - break;
141   - case FLASH_AM800B:
142   - printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
143   - break;
144   - case FLASH_AM800T:
145   - printf("AM29LV800T (8 Mbit, top boot sector)\n");
146   - break;
147   - case FLASH_AM160B:
148   - printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
149   - break;
150   - case FLASH_AM160T:
151   - printf("AM29LV160T (16 Mbit, top boot sector)\n");
152   - break;
153   - case FLASH_AM320B:
154   - printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
155   - break;
156   - case FLASH_AM320T:
157   - printf("AM29LV320T (32 Mbit, top boot sector)\n");
158   - break;
159   - default:
160   - printf("Unknown Chip Type\n");
161   - break;
162   - }
163   -
164   - printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
165   -
166   - printf(" Sector Start Addresses:");
167   - for (i = 0; i < info->sector_count; ++i) {
168   - if ((i % 5) == 0)
169   - printf("\n ");
170   - printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " ");
171   - }
172   - printf("\n");
173   -}
174   -
175   -/*-----------------------------------------------------------------------
176   - */
177   -
178   -
179   -/*-----------------------------------------------------------------------
180   - */
181   -
182   -/*
183   - * The following code cannot be run from FLASH!
184   - */
185   -
186   -static ulong flash_get_size(vu_long * addr, flash_info_t * info)
187   -{
188   - short i;
189   - uchar mid;
190   - uchar pid;
191   - vu_char *caddr = (vu_char *) addr;
192   - ulong base = (ulong) addr;
193   -
194   -
195   - /* Write auto select command: read Manufacturer ID */
196   - caddr[0x0555] = 0xAA;
197   - caddr[0x02AA] = 0x55;
198   - caddr[0x0555] = 0x90;
199   -
200   - mid = caddr[0];
201   - switch (mid) {
202   - case (AMD_MANUFACT & 0xFF):
203   - info->flash_id = FLASH_MAN_AMD;
204   - break;
205   - case (FUJ_MANUFACT & 0xFF):
206   - info->flash_id = FLASH_MAN_FUJ;
207   - break;
208   - case (MX_MANUFACT & 0xFF):
209   - info->flash_id = FLASH_MAN_MX;
210   - break;
211   - case (STM_MANUFACT & 0xFF):
212   - info->flash_id = FLASH_MAN_STM;
213   - break;
214   - default:
215   - info->flash_id = FLASH_UNKNOWN;
216   - info->sector_count = 0;
217   - info->size = 0;
218   - return (0); /* no or unknown flash */
219   - }
220   -
221   - pid = caddr[1]; /* device ID */
222   - switch (pid) {
223   - case (AMD_ID_LV400T & 0xFF):
224   - info->flash_id += FLASH_AM400T;
225   - info->sector_count = 11;
226   - info->size = 0x00080000;
227   - break; /* => 512 kB */
228   -
229   - case (AMD_ID_LV400B & 0xFF):
230   - info->flash_id += FLASH_AM400B;
231   - info->sector_count = 11;
232   - info->size = 0x00080000;
233   - break; /* => 512 kB */
234   -
235   - case (AMD_ID_LV800T & 0xFF):
236   - info->flash_id += FLASH_AM800T;
237   - info->sector_count = 19;
238   - info->size = 0x00100000;
239   - break; /* => 1 MB */
240   -
241   - case (AMD_ID_LV800B & 0xFF):
242   - info->flash_id += FLASH_AM800B;
243   - info->sector_count = 19;
244   - info->size = 0x00100000;
245   - break; /* => 1 MB */
246   -
247   - case (AMD_ID_LV160T & 0xFF):
248   - info->flash_id += FLASH_AM160T;
249   - info->sector_count = 35;
250   - info->size = 0x00200000;
251   - break; /* => 2 MB */
252   -
253   - case (AMD_ID_LV160B & 0xFF):
254   - info->flash_id += FLASH_AM160B;
255   - info->sector_count = 35;
256   - info->size = 0x00200000;
257   - break; /* => 2 MB */
258   -
259   - case (AMD_ID_LV040B & 0xFF):
260   - info->flash_id += FLASH_AM040;
261   - info->sector_count = 8;
262   - info->size = 0x00080000;
263   - break;
264   -
265   - case (STM_ID_M29W040B & 0xFF):
266   - info->flash_id += FLASH_AM040;
267   - info->sector_count = 8;
268   - info->size = 0x00080000;
269   - break;
270   -
271   -#if 0 /* enable when device IDs are available */
272   - case (AMD_ID_LV320T & 0xFF):
273   - info->flash_id += FLASH_AM320T;
274   - info->sector_count = 67;
275   - info->size = 0x00400000;
276   - break; /* => 4 MB */
277   -
278   - case (AMD_ID_LV320B & 0xFF):
279   - info->flash_id += FLASH_AM320B;
280   - info->sector_count = 67;
281   - info->size = 0x00400000;
282   - break; /* => 4 MB */
283   -#endif
284   - default:
285   - info->flash_id = FLASH_UNKNOWN;
286   - return (0); /* => no or unknown flash */
287   -
288   - }
289   -
290   - printf(" ");
291   - /* set up sector start address table */
292   - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
293   - for (i = 0; i < info->sector_count; i++) {
294   - info->start[i] = base + (i * 0x00010000);
295   - }
296   - } else if (info->flash_id & FLASH_BTYPE) {
297   - /* set sector offsets for bottom boot block type */
298   - info->start[0] = base + 0x00000000;
299   - info->start[1] = base + 0x00004000;
300   - info->start[2] = base + 0x00006000;
301   - info->start[3] = base + 0x00008000;
302   - for (i = 4; i < info->sector_count; i++) {
303   - info->start[i] = base + (i * 0x00010000) - 0x00030000;
304   - }
305   - } else {
306   - /* set sector offsets for top boot block type */
307   - i = info->sector_count - 1;
308   - info->start[i--] = base + info->size - 0x00004000;
309   - info->start[i--] = base + info->size - 0x00006000;
310   - info->start[i--] = base + info->size - 0x00008000;
311   - for (; i >= 0; i--) {
312   - info->start[i] = base + i * 0x00010000;
313   - }
314   - }
315   -
316   - /* check for protected sectors */
317   - for (i = 0; i < info->sector_count; i++) {
318   - /* read sector protection: D0 = 1 if protected */
319   - caddr = (volatile unsigned char *)(info->start[i]);
320   - info->protect[i] = caddr[2] & 1;
321   - }
322   -
323   - /*
324   - * Prevent writes to uninitialized FLASH.
325   - */
326   - if (info->flash_id != FLASH_UNKNOWN) {
327   - caddr = (vu_char *) info->start[0];
328   -
329   - caddr[0x0555] = 0xAA;
330   - caddr[0x02AA] = 0x55;
331   - caddr[0x0555] = 0xF0;
332   -
333   - udelay(20000);
334   - }
335   -
336   - return (info->size);
337   -}
338   -
339   -
340   -/*-----------------------------------------------------------------------
341   - */
342   -
343   -int flash_erase(flash_info_t * info, int s_first, int s_last)
344   -{
345   - vu_char *addr = (vu_char *) (info->start[0]);
346   - int flag, prot, sect, l_sect;
347   - ulong start, now, last;
348   -
349   - if ((s_first < 0) || (s_first > s_last)) {
350   - if (info->flash_id == FLASH_UNKNOWN) {
351   - printf("- missing\n");
352   - } else {
353   - printf("- no sectors to erase\n");
354   - }
355   - return 1;
356   - }
357   -
358   - if ((info->flash_id == FLASH_UNKNOWN) ||
359   - (info->flash_id > FLASH_AMD_COMP)) {
360   - printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
361   - return 1;
362   - }
363   -
364   - prot = 0;
365   - for (sect = s_first; sect <= s_last; ++sect) {
366   - if (info->protect[sect]) {
367   - prot++;
368   - }
369   - }
370   -
371   - if (prot) {
372   - printf("- Warning: %d protected sectors will not be erased!\n", prot);
373   - } else {
374   - printf("\n");
375   - }
376   -
377   - l_sect = -1;
378   -
379   - /* Disable interrupts which might cause a timeout here */
380   - flag = disable_interrupts();
381   -
382   - addr[0x0555] = 0xAA;
383   - addr[0x02AA] = 0x55;
384   - addr[0x0555] = 0x80;
385   - addr[0x0555] = 0xAA;
386   - addr[0x02AA] = 0x55;
387   -
388   - /* Start erase on unprotected sectors */
389   - for (sect = s_first; sect <= s_last; sect++) {
390   - if (info->protect[sect] == 0) { /* not protected */
391   - addr = (vu_char *) (info->start[sect]);
392   - addr[0] = 0x30;
393   - l_sect = sect;
394   - }
395   - }
396   -
397   - /* re-enable interrupts if necessary */
398   - if (flag)
399   - enable_interrupts();
400   -
401   - /* wait at least 80us - let's wait 1 ms */
402   - udelay(1000);
403   -
404   - /*
405   - * We wait for the last triggered sector
406   - */
407   - if (l_sect < 0)
408   - goto DONE;
409   -
410   - start = get_timer(0);
411   - last = start;
412   - addr = (vu_char *) (info->start[l_sect]);
413   - while ((addr[0] & 0x80) != 0x80) {
414   - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
415   - printf("Timeout\n");
416   - return 1;
417   - }
418   - /* show that we're waiting */
419   - if ((now - last) > 1000) { /* every second */
420   - putc('.');
421   - last = now;
422   - }
423   - }
424   -
425   - DONE:
426   - /* reset to read mode */
427   - addr = (vu_char *) info->start[0];
428   - addr[0] = 0xF0; /* reset bank */
429   -
430   - printf(" done\n");
431   - return 0;
432   -}
433   -
434   -/*-----------------------------------------------------------------------
435   - * Copy memory to flash, returns:
436   - * 0 - OK
437   - * 1 - write timeout
438   - * 2 - Flash not erased
439   - */
440   -
441   -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
442   -{
443   - int rc;
444   -
445   - while (cnt > 0) {
446   - if ((rc = write_byte(info, addr++, *src++)) != 0) {
447   - return (rc);
448   - }
449   - --cnt;
450   - }
451   -
452   - return (0);
453   -}
454   -
455   -/*-----------------------------------------------------------------------
456   - * Write a word to Flash, returns:
457   - * 0 - OK
458   - * 1 - write timeout
459   - * 2 - Flash not erased
460   - */
461   -static int write_byte(flash_info_t * info, ulong dest, uchar data)
462   -{
463   - vu_char *addr = (vu_char *) (info->start[0]);
464   - ulong start;
465   - int flag;
466   -
467   - /* Check if Flash is (sufficiently) erased */
468   - if ((*((vu_char *) dest) & data) != data) {
469   - return (2);
470   - }
471   - /* Disable interrupts which might cause a timeout here */
472   - flag = disable_interrupts();
473   -
474   - addr[0x0555] = 0xAA;
475   - addr[0x02AA] = 0x55;
476   - addr[0x0555] = 0xA0;
477   -
478   - *((vu_char *) dest) = data;
479   -
480   - /* re-enable interrupts if necessary */
481   - if (flag)
482   - enable_interrupts();
483   -
484   - /* data polling for D7 */
485   - start = get_timer(0);
486   - while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
487   - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
488   - return (1);
489   - }
490   - }
491   - return (0);
492   -}
493   -
494   -/*-----------------------------------------------------------------------
495   - */
board/netvia/netvia.c
View file @ f017cd7
1   -/*
2   - * (C) Copyright 2000
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -/*
9   - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
10   - * U-Boot port on NetVia board
11   - */
12   -
13   -#include <common.h>
14   -#include "mpc8xx.h"
15   -
16   -/****************************************************************/
17   -
18   -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
19   -/* last value written to the external register; we cannot read back */
20   -unsigned int last_er_val;
21   -#endif
22   -
23   -/****************************************************************/
24   -
25   -/****************************************************************/
26   -
27   -/* some sane bit macros */
28   -#define _BD(_b) (1U << (31-(_b)))
29   -#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
30   -
31   -#define _BW(_b) (1U << (15-(_b)))
32   -#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
33   -
34   -#define _BB(_b) (1U << (7-(_b)))
35   -#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
36   -
37   -#define _B(_b) _BD(_b)
38   -#define _BR(_l, _h) _BDR(_l, _h)
39   -
40   -/****************************************************************/
41   -
42   -#define _NOT_USED_ 0xFFFFFFFF
43   -
44   -/****************************************************************/
45   -
46   -#define CS_0000 0x00000000
47   -#define CS_0001 0x10000000
48   -#define CS_0010 0x20000000
49   -#define CS_0011 0x30000000
50   -#define CS_0100 0x40000000
51   -#define CS_0101 0x50000000
52   -#define CS_0110 0x60000000
53   -#define CS_0111 0x70000000
54   -#define CS_1000 0x80000000
55   -#define CS_1001 0x90000000
56   -#define CS_1010 0xA0000000
57   -#define CS_1011 0xB0000000
58   -#define CS_1100 0xC0000000
59   -#define CS_1101 0xD0000000
60   -#define CS_1110 0xE0000000
61   -#define CS_1111 0xF0000000
62   -
63   -#define BS_0000 0x00000000
64   -#define BS_0001 0x01000000
65   -#define BS_0010 0x02000000
66   -#define BS_0011 0x03000000
67   -#define BS_0100 0x04000000
68   -#define BS_0101 0x05000000
69   -#define BS_0110 0x06000000
70   -#define BS_0111 0x07000000
71   -#define BS_1000 0x08000000
72   -#define BS_1001 0x09000000
73   -#define BS_1010 0x0A000000
74   -#define BS_1011 0x0B000000
75   -#define BS_1100 0x0C000000
76   -#define BS_1101 0x0D000000
77   -#define BS_1110 0x0E000000
78   -#define BS_1111 0x0F000000
79   -
80   -#define A10_AAAA 0x00000000
81   -#define A10_AAA0 0x00200000
82   -#define A10_AAA1 0x00300000
83   -#define A10_000A 0x00800000
84   -#define A10_0000 0x00A00000
85   -#define A10_0001 0x00B00000
86   -#define A10_111A 0x00C00000
87   -#define A10_1110 0x00E00000
88   -#define A10_1111 0x00F00000
89   -
90   -#define RAS_0000 0x00000000
91   -#define RAS_0001 0x00040000
92   -#define RAS_1110 0x00080000
93   -#define RAS_1111 0x000C0000
94   -
95   -#define CAS_0000 0x00000000
96   -#define CAS_0001 0x00010000
97   -#define CAS_1110 0x00020000
98   -#define CAS_1111 0x00030000
99   -
100   -#define WE_0000 0x00000000
101   -#define WE_0001 0x00004000
102   -#define WE_1110 0x00008000
103   -#define WE_1111 0x0000C000
104   -
105   -#define GPL4_0000 0x00000000
106   -#define GPL4_0001 0x00001000
107   -#define GPL4_1110 0x00002000
108   -#define GPL4_1111 0x00003000
109   -
110   -#define GPL5_0000 0x00000000
111   -#define GPL5_0001 0x00000400
112   -#define GPL5_1110 0x00000800
113   -#define GPL5_1111 0x00000C00
114   -#define LOOP 0x00000080
115   -
116   -#define EXEN 0x00000040
117   -
118   -#define AMX_COL 0x00000000
119   -#define AMX_ROW 0x00000020
120   -#define AMX_MAR 0x00000030
121   -
122   -#define NA 0x00000008
123   -
124   -#define UTA 0x00000004
125   -
126   -#define TODT 0x00000002
127   -
128   -#define LAST 0x00000001
129   -
130   -const uint sdram_table[0x40] = {
131   - /* RSS */
132   - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
133   - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
134   - CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
135   - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
136   - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
137   - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
138   - _NOT_USED_, _NOT_USED_,
139   -
140   - /* RBS */
141   - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
142   - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
143   - CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
144   - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
145   - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
146   - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
147   - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */
148   - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */
149   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
150   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
151   -
152   - /* WSS */
153   - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,
154   - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,
155   - CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA,
156   - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,
157   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
158   -
159   - /* WBS */
160   - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
161   - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
162   - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */
163   - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
164   - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
165   - CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
166   - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
167   - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
168   - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
169   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
170   - _NOT_USED_, _NOT_USED_, _NOT_USED_,
171   -
172   - /* UPT */
173   - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
174   - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | LOOP,
175   - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,
176   - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,
177   - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | LOOP,
178   - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | LAST,
179   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
180   - _NOT_USED_, _NOT_USED_,
181   -
182   - /* EXC */
183   - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,
184   - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,
185   -
186   - /* REG */
187   - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1110 | AMX_MAR,
188   - CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | TODT | LAST,
189   -};
190   -
191   -/* ------------------------------------------------------------------------- */
192   -
193   -
194   -/*
195   - * Check Board Identity:
196   - *
197   - * Test ETX ID string (ETX_xxx...)
198   - *
199   - * Return 1 always.
200   - */
201   -
202   -int checkboard(void)
203   -{
204   -#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
205   - printf ("NETVIA v1\n");
206   -#else
207   - printf ("NETVIA v2+\n");
208   -#endif
209   - return (0);
210   -}
211   -
212   -/* ------------------------------------------------------------------------- */
213   -
214   -/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
215   -#define MAR_SDRAM_INIT 0x000000C8LU
216   -
217   -#define MCR_OP(x) ((unsigned long)((x) & 3) << (31-1))
218   -#define MCR_OP_MASK MCR_OP(3)
219   -
220   -#define MCR_UM(x) ((unsigned long)((x) & 1) << (31 - 8))
221   -#define MCR_UM_MASK MCR_UM(1)
222   -#define MCR_UM_UPMA MCR_UM(0)
223   -#define MCR_UM_UPMB MCR_UM(1)
224   -
225   -#define MCR_MB(x) ((unsigned long)((x) & 7) << (31 - 18))
226   -#define MCR_MB_MASK MCR_MB(7)
227   -#define MCR_MB_CS(x) MCR_MB(x)
228   -
229   -#define MCR_MCLF(x) ((unsigned long)((x) & 15) << (31 - 23))
230   -#define MCR_MCLF_MASK MCR_MCLF(15)
231   -
232   -phys_size_t initdram(int board_type)
233   -{
234   - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
235   - volatile memctl8xx_t *memctl = &immap->im_memctl;
236   - long int size;
237   -
238   - upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint));
239   -
240   - /*
241   - * Preliminary prescaler for refresh
242   - */
243   - memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
244   -
245   - memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
246   -
247   - /*
248   - * Map controller bank 3 to the SDRAM bank at preliminary address.
249   - */
250   - memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
251   - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
252   -
253   - memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & ~MAMR_PTAE; /* no refresh yet */
254   -
255   - udelay(200);
256   -
257   - /* perform SDRAM initialisation sequence */
258   - memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(1) | MCR_MAD(0x3C); /* precharge all */
259   - udelay(1);
260   - memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(0) | MCR_MAD(0x30); /* refresh 16 times(0) */
261   - udelay(1);
262   - memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(1) | MCR_MAD(0x3E); /* exception program (write mar) */
263   - udelay(1);
264   -
265   - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
266   -
267   - udelay(1000);
268   -
269   - memctl->memc_mamr = CONFIG_SYS_MAMR_9COL;
270   -
271   - size = SDRAM_MAX_SIZE;
272   -
273   - udelay(10000);
274   -
275   - return (size);
276   -}
277   -
278   -/* ------------------------------------------------------------------------- */
279   -
280   -int misc_init_r(void)
281   -{
282   -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
283   - last_er_val = 0xffffffff;
284   -#endif
285   - return(0);
286   -}
287   -
288   -/* ------------------------------------------------------------------------- */
289   -
290   -/* GP = general purpose, SP = special purpose (on chip peripheral) */
291   -
292   -/* bits that can have a special purpose or can be configured as inputs/outputs */
293   -#define PA_GP_INMASK 0
294   -#define PA_GP_OUTMASK (_BW(5) | _BWR(14, 15))
295   -#define PA_SP_MASK (_BW(4) | _BWR(6, 13))
296   -#define PA_ODR_VAL 0
297   -#define PA_GP_OUTVAL _BW(5)
298   -#define PA_SP_DIRVAL 0
299   -
300   -#define PB_GP_INMASK _B(28)
301   -#define PB_GP_OUTMASK (_BR(16, 19) | _BR(26, 27) | _BR(29, 31))
302   -#define PB_SP_MASK _BR(22, 25)
303   -#define PB_ODR_VAL 0
304   -#define PB_GP_OUTVAL (_BR(16, 19) | _BR(26, 27) | _BR(29, 31))
305   -#define PB_SP_DIRVAL 0
306   -
307   -#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
308   -
309   -#define PC_GP_INMASK (_BWR(5, 7) | _BWR(9, 10) | _BW(13))
310   -#define PC_GP_OUTMASK _BW(12)
311   -#define PC_SP_MASK (_BW(4) | _BW(8))
312   -#define PC_SOVAL 0
313   -#define PC_INTVAL 0
314   -#define PC_GP_OUTVAL 0
315   -#define PC_SP_DIRVAL 0
316   -
317   -#define PD_GP_INMASK 0
318   -#define PD_GP_OUTMASK _BWR(3, 15)
319   -#define PD_SP_MASK 0
320   -#define PD_GP_OUTVAL (_BW(3) | _BW(5) | _BW(7) | _BWR(8, 15))
321   -#define PD_SP_DIRVAL 0
322   -
323   -#elif CONFIG_NETVIA_VERSION >= 2
324   -
325   -#define PC_GP_INMASK (_BW(5) | _BW(7) | _BWR(9, 11) | _BWR(13, 15))
326   -#define PC_GP_OUTMASK (_BW(6) | _BW(12))
327   -#define PC_SP_MASK (_BW(4) | _BW(8))
328   -#define PC_SOVAL 0
329   -#define PC_INTVAL _BW(7)
330   -#define PC_GP_OUTVAL (_BW(6) | _BW(12))
331   -#define PC_SP_DIRVAL 0
332   -
333   -#define PD_GP_INMASK 0
334   -#define PD_GP_OUTMASK _BWR(3, 15)
335   -#define PD_SP_MASK 0
336   -#define PD_GP_OUTVAL (_BW(3) | _BW(5) | _BW(9) | _BW(11))
337   -#define PD_SP_DIRVAL 0
338   -
339   -#else
340   -#error Unknown NETVIA board version.
341   -#endif
342   -
343   -int board_early_init_f(void)
344   -{
345   - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
346   - volatile iop8xx_t *ioport = &immap->im_ioport;
347   - volatile cpm8xx_t *cpm = &immap->im_cpm;
348   - volatile memctl8xx_t *memctl = &immap->im_memctl;
349   -
350   - /* DSP0 chip select */
351   - memctl->memc_or4 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
352   - memctl->memc_br4 = ((DSP0_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
353   -
354   - /* DSP1 chip select */
355   - memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
356   - memctl->memc_br5 = ((DSP1_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
357   -
358   - /* FPGA chip select */
359   - memctl->memc_or6 = ((0xFFFFFFFFLU & ~(FPGA_SIZE - 1)) | OR_BI | OR_SCY_1_CLK);
360   - memctl->memc_br6 = ((FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
361   -
362   -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
363   - /* NAND chip select */
364   - memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX);
365   - memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
366   -
367   - /* kill this chip select */
368   - memctl->memc_br2 &= ~BR_V; /* invalid */
369   -
370   - /* external reg chip select */
371   - memctl->memc_or7 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK);
372   - memctl->memc_br7 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
373   -#endif
374   -
375   - ioport->iop_padat = PA_GP_OUTVAL;
376   - ioport->iop_paodr = PA_ODR_VAL;
377   - ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL;
378   - ioport->iop_papar = PA_SP_MASK;
379   -
380   - cpm->cp_pbdat = PB_GP_OUTVAL;
381   - cpm->cp_pbodr = PB_ODR_VAL;
382   - cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL;
383   - cpm->cp_pbpar = PB_SP_MASK;
384   -
385   - ioport->iop_pcdat = PC_GP_OUTVAL;
386   - ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL;
387   - ioport->iop_pcso = PC_SOVAL;
388   - ioport->iop_pcint = PC_INTVAL;
389   - ioport->iop_pcpar = PC_SP_MASK;
390   -
391   - ioport->iop_pddat = PD_GP_OUTVAL;
392   - ioport->iop_pddir = PD_GP_OUTMASK | PD_SP_DIRVAL;
393   - ioport->iop_pdpar = PD_SP_MASK;
394   -
395   -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
396   - /* external register init */
397   - *(volatile uint *)ER_BASE = 0xFFFFFFFF;
398   -#endif
399   -
400   - return 0;
401   -}
board/netvia/u-boot.lds.debug
View file @ f017cd7
1   -/*
2   - * (C) Copyright 2000
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -OUTPUT_ARCH(powerpc)
9   -/* Do we need any of these for elf?
10   - __DYNAMIC = 0; */
11   -SECTIONS
12   -{
13   - /* Read-only sections, merged into text segment: */
14   - . = + SIZEOF_HEADERS;
15   - .interp : { *(.interp) }
16   - .hash : { *(.hash) }
17   - .dynsym : { *(.dynsym) }
18   - .dynstr : { *(.dynstr) }
19   - .rel.text : { *(.rel.text) }
20   - .rela.text : { *(.rela.text) }
21   - .rel.data : { *(.rel.data) }
22   - .rela.data : { *(.rela.data) }
23   - .rel.rodata : { *(.rel.rodata) }
24   - .rela.rodata : { *(.rela.rodata) }
25   - .rel.got : { *(.rel.got) }
26   - .rela.got : { *(.rela.got) }
27   - .rel.ctors : { *(.rel.ctors) }
28   - .rela.ctors : { *(.rela.ctors) }
29   - .rel.dtors : { *(.rel.dtors) }
30   - .rela.dtors : { *(.rela.dtors) }
31   - .rel.bss : { *(.rel.bss) }
32   - .rela.bss : { *(.rela.bss) }
33   - .rel.plt : { *(.rel.plt) }
34   - .rela.plt : { *(.rela.plt) }
35   - .init : { *(.init) }
36   - .plt : { *(.plt) }
37   - .text :
38   - {
39   - /* WARNING - the following is hand-optimized to fit within */
40   - /* the sector layout of our flash chips! XXX FIXME XXX */
41   -
42   - arch/powerpc/cpu/mpc8xx/start.o (.text)
43   - common/dlmalloc.o (.text)
44   - lib/vsprintf.o (.text)
45   - lib/crc32.o (.text)
46   -
47   - . = env_offset;
48   - common/env_embedded.o(.text)
49   -
50   - *(.text)
51   - *(.got1)
52   - }
53   - _etext = .;
54   - PROVIDE (etext = .);
55   - .rodata :
56   - {
57   - *(.rodata)
58   - *(.rodata1)
59   - *(.rodata.str1.4)
60   - *(.eh_frame)
61   - }
62   - .fini : { *(.fini) } =0
63   - .ctors : { *(.ctors) }
64   - .dtors : { *(.dtors) }
65   -
66   - /* Read-write section, merged into data segment: */
67   - . = (. + 0x0FFF) & 0xFFFFF000;
68   - _erotext = .;
69   - PROVIDE (erotext = .);
70   - .reloc :
71   - {
72   - *(.got)
73   - _GOT2_TABLE_ = .;
74   - *(.got2)
75   - _FIXUP_TABLE_ = .;
76   - *(.fixup)
77   - }
78   - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
79   - __fixup_entries = (. - _FIXUP_TABLE_)>>2;
80   -
81   - .data :
82   - {
83   - *(.data)
84   - *(.data1)
85   - *(.sdata)
86   - *(.sdata2)
87   - *(.dynamic)
88   - CONSTRUCTORS
89   - }
90   - _edata = .;
91   - PROVIDE (edata = .);
92   -
93   -
94   - . = ALIGN(4);
95   - .u_boot_list : {
96   - KEEP(*(SORT(.u_boot_list*)));
97   - }
98   -
99   -
100   - __start___ex_table = .;
101   - __ex_table : { *(__ex_table) }
102   - __stop___ex_table = .;
103   -
104   - . = ALIGN(4096);
105   - __init_begin = .;
106   - .text.init : { *(.text.init) }
107   - .data.init : { *(.data.init) }
108   - . = ALIGN(4096);
109   - __init_end = .;
110   -
111   - __bss_start = .;
112   - .bss :
113   - {
114   - *(.sbss) *(.scommon)
115   - *(.dynbss)
116   - *(.bss)
117   - *(COMMON)
118   - }
119   - __bss_end = . ;
120   - PROVIDE (end = .);
121   -}
configs/NETVIA_V2_defconfig
View file @ f017cd7
1   -CONFIG_SYS_EXTRA_OPTIONS="NETVIA_VERSION=2"
2   -CONFIG_PPC=y
3   -CONFIG_8xx=y
4   -CONFIG_TARGET_NETVIA=y
configs/NETVIA_defconfig
View file @ f017cd7
1   -CONFIG_SYS_EXTRA_OPTIONS="NETVIA_VERSION=1"
2   -CONFIG_PPC=y
3   -CONFIG_8xx=y
4   -CONFIG_TARGET_NETVIA=y
doc/README.scrapyard
Diff comments   View file @ f017cd7
... ... @@ -12,6 +12,7 @@
12 12  
13 13 Board Arch CPU Commit Removed Last known maintainer/contact
14 14 =================================================================================================
  15 +NETVIA powerpc mpc8xx - - Pantelis Antoniou <panto@intracom.gr>
15 16 R360MPI powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
16 17 RRvision powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
17 18 SPD823TS powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
... ... @@ -594,39 +594,6 @@
594 594 #define SICR_ENET_CLKRT ((uint)0x00250000)
595 595 #endif /* CONFIG_KM8XX */
596 596  
597   -/*** NETVIA *******************************************************/
598   -
599   -#if defined(CONFIG_NETVIA)
600   -/* Bits in parallel I/O port registers that have to be set/cleared
601   - * to configure the pins for SCC2 use.
602   - */
603   -#define PROFF_ENET PROFF_SCC2
604   -#define CPM_CR_ENET CPM_CR_CH_SCC2
605   -#define SCC_ENET 1
606   -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
607   -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
608   -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
609   -#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
610   -
611   -#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
612   -# define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */
613   -#elif CONFIG_NETVIA_VERSION >= 2
614   -# define PC_ENET_PDN ((ushort)0x0008) /* PC 12 */
615   -#endif
616   -
617   -#define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */
618   -
619   -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
620   -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
621   -
622   -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
623   - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
624   - */
625   -#define SICR_ENET_MASK ((uint)0x0000ff00)
626   -#define SICR_ENET_CLKRT ((uint)0x00002f00)
627   -
628   -#endif /* CONFIG_NETVIA */
629   -
630 597 /*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/
631 598  
632 599 #if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
include/configs/NETVIA.h
View file @ f017cd7
1   -/*
2   - * (C) Copyright 2000-2010
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -/*
9   - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
10   - * U-Boot port on NetVia board
11   - */
12   -
13   -#ifndef __CONFIG_H
14   -#define __CONFIG_H
15   -
16   -/*
17   - * High Level Configuration Options
18   - * (easy to change)
19   - */
20   -
21   -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
22   -#define CONFIG_NETVIA 1 /* ...on a NetVia board */
23   -
24   -#define CONFIG_SYS_TEXT_BASE 0x40000000
25   -
26   -#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
27   -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
28   -#undef CONFIG_8xx_CONS_SMC2
29   -#undef CONFIG_8xx_CONS_NONE
30   -#else
31   -#define CONFIG_8xx_CONS_NONE
32   -#define CONFIG_MAX3100_SERIAL
33   -#endif
34   -
35   -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
36   -
37   -#define CONFIG_XIN 10000000
38   -#define CONFIG_8xx_GCLK_FREQ 80000000
39   -
40   -#if 0
41   -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
42   -#else
43   -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
44   -#endif
45   -
46   -#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
47   -
48   -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
49   -
50   -#undef CONFIG_BOOTARGS
51   -#define CONFIG_BOOTCOMMAND \
52   - "tftpboot; " \
53   - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
54   - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
55   - "bootm"
56   -
57   -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
58   -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
59   -
60   -#undef CONFIG_WATCHDOG /* watchdog disabled */
61   -
62   -#define CONFIG_STATUS_LED 1 /* Status LED enabled */
63   -
64   -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
65   -#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
66   -#endif
67   -
68   -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
69   -
70   -/*
71   - * BOOTP options
72   - */
73   -#define CONFIG_BOOTP_SUBNETMASK
74   -#define CONFIG_BOOTP_GATEWAY
75   -#define CONFIG_BOOTP_HOSTNAME
76   -#define CONFIG_BOOTP_BOOTPATH
77   -#define CONFIG_BOOTP_BOOTFILESIZE
78   -#define CONFIG_BOOTP_NISDOMAIN
79   -
80   -
81   -#undef CONFIG_MAC_PARTITION
82   -#undef CONFIG_DOS_PARTITION
83   -
84   -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
85   -
86   -
87   -/*
88   - * Command line configuration.
89   - */
90   -#include <config_cmd_default.h>
91   -
92   -#define CONFIG_CMD_DHCP
93   -#define CONFIG_CMD_PING
94   -
95   -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
96   -/* #define CONFIG_CMD_NAND */ /* disabled */
97   -#endif
98   -
99   -
100   -#define CONFIG_BOARD_EARLY_INIT_F 1
101   -#define CONFIG_MISC_INIT_R
102   -
103   -/*
104   - * Miscellaneous configurable options
105   - */
106   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
107   -#if defined(CONFIG_CMD_KGDB)
108   -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
109   -#else
110   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
111   -#endif
112   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
113   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
114   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
115   -
116   -#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */
117   -#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
118   -
119   -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
120   -
121   -/*
122   - * Low Level Configuration Settings
123   - * (address mappings, register initial values, etc.)
124   - * You should know what you are doing if you make changes here.
125   - */
126   -/*-----------------------------------------------------------------------
127   - * Internal Memory Mapped Register
128   - */
129   -#define CONFIG_SYS_IMMR 0xFF000000
130   -
131   -/*-----------------------------------------------------------------------
132   - * Definitions for initial stack pointer and data area (in DPRAM)
133   - */
134   -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
135   -#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
136   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
137   -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
138   -
139   -/*-----------------------------------------------------------------------
140   - * Start addresses for the final memory configuration
141   - * (Set up by the startup code)
142   - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
143   - */
144   -#define CONFIG_SYS_SDRAM_BASE 0x00000000
145   -#define CONFIG_SYS_FLASH_BASE 0x40000000
146   -#if defined(DEBUG)
147   -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
148   -#else
149   -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
150   -#endif
151   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
152   -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
153   -
154   -/*
155   - * For booting Linux, the board info and command line data
156   - * have to be in the first 8 MB of memory, since this is
157   - * the maximum mapped by the Linux kernel during initialization.
158   - */
159   -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
160   -
161   -/*-----------------------------------------------------------------------
162   - * FLASH organization
163   - */
164   -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
165   -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
166   -
167   -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
168   -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
169   -
170   -#define CONFIG_ENV_IS_IN_FLASH 1
171   -#define CONFIG_ENV_SECT_SIZE 0x10000
172   -
173   -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000)
174   -#define CONFIG_ENV_SIZE 0x4000
175   -
176   -#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000)
177   -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
178   -
179   -/*-----------------------------------------------------------------------
180   - * Cache Configuration
181   - */
182   -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
183   -#if defined(CONFIG_CMD_KGDB)
184   -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
185   -#endif
186   -
187   -/*-----------------------------------------------------------------------
188   - * SYPCR - System Protection Control 11-9
189   - * SYPCR can only be written once after reset!
190   - *-----------------------------------------------------------------------
191   - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
192   - */
193   -#if defined(CONFIG_WATCHDOG)
194   -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
195   - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
196   -#else
197   -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
198   -#endif
199   -
200   -/*-----------------------------------------------------------------------
201   - * SIUMCR - SIU Module Configuration 11-6
202   - *-----------------------------------------------------------------------
203   - * PCMCIA config., multi-function pin tri-state
204   - */
205   -#ifndef CONFIG_CAN_DRIVER
206   -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
207   -#else /* we must activate GPL5 in the SIUMCR for CAN */
208   -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
209   -#endif /* CONFIG_CAN_DRIVER */
210   -
211   -/*-----------------------------------------------------------------------
212   - * TBSCR - Time Base Status and Control 11-26
213   - *-----------------------------------------------------------------------
214   - * Clear Reference Interrupt Status, Timebase freezing enabled
215   - */
216   -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
217   -
218   -/*-----------------------------------------------------------------------
219   - * RTCSC - Real-Time Clock Status and Control Register 11-27
220   - *-----------------------------------------------------------------------
221   - */
222   -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
223   -
224   -/*-----------------------------------------------------------------------
225   - * PISCR - Periodic Interrupt Status and Control 11-31
226   - *-----------------------------------------------------------------------
227   - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
228   - */
229   -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
230   -
231   -/*-----------------------------------------------------------------------
232   - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
233   - *-----------------------------------------------------------------------
234   - * Reset PLL lock status sticky bit, timer expired status bit and timer
235   - * interrupt status bit
236   - *
237   - *
238   - *-----------------------------------------------------------------------
239   - * SCCR - System Clock and reset Control Register 15-27
240   - *-----------------------------------------------------------------------
241   - * Set clock output, timebase and RTC source and divider,
242   - * power management and some other internal clocks
243   - */
244   -
245   -#define SCCR_MASK SCCR_EBDF11
246   -
247   -#if CONFIG_8xx_GCLK_FREQ == 50000000
248   -
249   -#define CONFIG_SYS_PLPRCR ( ((5 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
250   -#define CONFIG_SYS_SCCR (SCCR_TBS | \
251   - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
252   - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
253   - SCCR_DFALCD00)
254   -
255   -#elif CONFIG_8xx_GCLK_FREQ == 80000000
256   -
257   -#define CONFIG_SYS_PLPRCR ( ((8 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
258   -#define CONFIG_SYS_SCCR (SCCR_TBS | \
259   - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
260   - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
261   - SCCR_DFALCD00 | SCCR_EBDF01)
262   -
263   -#endif
264   -
265   -/*-----------------------------------------------------------------------
266   - *
267   - *-----------------------------------------------------------------------
268   - *
269   - */
270   -/*#define CONFIG_SYS_DER 0x2002000F*/
271   -#define CONFIG_SYS_DER 0
272   -
273   -/*
274   - * Init Memory Controller:
275   - *
276   - * BR0/1 and OR0/1 (FLASH)
277   - */
278   -
279   -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
280   -
281   -/* used to re-map FLASH both when starting from SRAM or FLASH:
282   - * restrict access enough to keep SRAM working (if any)
283   - * but not too much to meddle with FLASH accesses
284   - */
285   -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
286   -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
287   -
288   -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
289   -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
290   -
291   -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
292   -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
293   -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
294   -
295   -/*
296   - * BR3 and OR3 (SDRAM)
297   - *
298   - */
299   -#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
300   -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
301   -
302   -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
303   -#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
304   -
305   -#define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
306   -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
307   -
308   -/*
309   - * Memory Periodic Timer Prescaler
310   - */
311   -
312   -/* periodic timer for refresh */
313   -#define CONFIG_SYS_MAMR_PTA 208
314   -
315   -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
316   -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
317   -
318   -/*
319   - * MAMR settings for SDRAM
320   - */
321   -
322   -/* 9 column SDRAM */
323   -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
324   - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
325   - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
326   -
327   -/* Ethernet at SCC2 */
328   -#define CONFIG_SCC2_ENET
329   -
330   -/****************************************************************/
331   -
332   -#define DSP_SIZE 0x00010000 /* 64K */
333   -#define FPGA_SIZE 0x00010000 /* 64K */
334   -
335   -#define DSP0_BASE 0xF1000000
336   -#define DSP1_BASE (DSP0_BASE + DSP_SIZE)
337   -#define FPGA_BASE (DSP1_BASE + DSP_SIZE)
338   -
339   -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
340   -
341   -#define ER_SIZE 0x00010000 /* 64K */
342   -#define ER_BASE (FPGA_BASE + FPGA_SIZE)
343   -
344   -#define NAND_SIZE 0x00010000 /* 64K */
345   -#define NAND_BASE (ER_BASE + ER_SIZE)
346   -
347   -#endif
348   -
349   -/****************************************************************/
350   -
351   -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
352   -
353   -#define STATUS_LED_BIT 0x00000001 /* bit 31 */
354   -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
355   -#define STATUS_LED_STATE STATUS_LED_BLINKING
356   -
357   -#define STATUS_LED_BIT1 0x00000002 /* bit 30 */
358   -#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
359   -#define STATUS_LED_STATE1 STATUS_LED_OFF
360   -
361   -#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
362   -#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
363   -
364   -#endif
365   -
366   -
367   -/*****************************************************************************/
368   -
369   -#ifndef __ASSEMBLY__
370   -
371   -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
372   -
373   -/* LEDs */
374   -
375   -/* last value written to the external register; we cannot read back */
376   -extern unsigned int last_er_val;
377   -
378   -/* led_id_t is unsigned long mask */
379   -typedef unsigned int led_id_t;
380   -
381   -static inline void __led_init(led_id_t mask, int state)
382   -{
383   - unsigned int new_er_val;
384   -
385   - if (state)
386   - new_er_val = last_er_val & ~mask;
387   - else
388   - new_er_val = last_er_val | mask;
389   -
390   - *(volatile unsigned int *)ER_BASE = new_er_val;
391   - last_er_val = new_er_val;
392   -}
393   -
394   -static inline void __led_toggle(led_id_t mask)
395   -{
396   - unsigned int new_er_val;
397   -
398   - new_er_val = last_er_val ^ mask;
399   - *(volatile unsigned int *)ER_BASE = new_er_val;
400   - last_er_val = new_er_val;
401   -}
402   -
403   -static inline void __led_set(led_id_t mask, int state)
404   -{
405   - unsigned int new_er_val;
406   -
407   - if (state)
408   - new_er_val = last_er_val & ~mask;
409   - else
410   - new_er_val = last_er_val | mask;
411   -
412   - *(volatile unsigned int *)ER_BASE = new_er_val;
413   - last_er_val = new_er_val;
414   -}
415   -
416   -/* MAX3100 console */
417   -#define MAX3100_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
418   -#define MAX3100_SPI_RXD_BIT 0x00000008
419   -
420   -#define MAX3100_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
421   -#define MAX3100_SPI_TXD_BIT 0x00000004
422   -
423   -#define MAX3100_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
424   -#define MAX3100_SPI_CLK_BIT 0x00000002
425   -
426   -#define MAX3100_CS_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat)
427   -#define MAX3100_CS_BIT 0x0010
428   -
429   -#endif
430   -
431   -#endif
432   -
433   -/*************************************************************************************************/
434   -
435   -#endif /* __CONFIG_H */
include/status_led.h
Diff comments   View file @ f017cd7
... ... @@ -122,29 +122,6 @@
122 122 * filling this file up with lots of custom board stuff.
123 123 */
124 124  
125   -/***** NetVia ********************************************************/
126   -#elif defined(CONFIG_NETVIA)
127   -
128   -#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
129   -
130   -#define STATUS_LED_PAR im_ioport.iop_pdpar
131   -#define STATUS_LED_DIR im_ioport.iop_pddir
132   -#undef STATUS_LED_ODR
133   -#define STATUS_LED_DAT im_ioport.iop_pddat
134   -
135   -# define STATUS_LED_BIT 0x0080 /* PD.8 */
136   -# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
137   -# define STATUS_LED_STATE STATUS_LED_BLINKING
138   -
139   -# define STATUS_LED_BIT1 0x0040 /* PD.9 */
140   -# define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
141   -# define STATUS_LED_STATE1 STATUS_LED_OFF
142   -
143   -# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
144   -# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
145   -
146   -#endif
147   -
148 125 /***** CMI ********************************************************/
149 126 #elif defined(CONFIG_CMI)
150 127 # define STATUS_LED_DIR im_mios.mios_mpiosm32ddr