Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit f018545ef756c4bc567d1bbf153615833bc590b0

Authored by Ash Charles
Committed by Joe Hershberger
1 parent 21622452f2
Exists in v2017.01-smarct4x and in 25 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2017.01-smarct3x, v2017.01-smarct3x-emmc

net: phy: micrel: center FLP burst timing at 16ms 

Like [1], reset the FLP burst timing for the KSZ9031 to the 16ms
specified by the IEEE802.3 standard from the chip's default of 8ms.

For more details, see the "Auto-Negotiation Timing" section of the
KSZ9031RNX datasheet.

[1] https://patchwork.kernel.org/patch/6558371/

Signed-off-by: Ash Charles <ash.charles@savoirfairelinux.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Showing 2 changed files with 26 additions and 0 deletions Side-by-side Diff

drivers/net/phy/micrel.c
Diff comments   View file @ f018545
... ... @@ -415,11 +415,31 @@
415 415  
416 416 return 0;
417 417 }
  418 +
  419 +static int ksz9031_center_flp_timing(struct phy_device *phydev)
  420 +{
  421 + struct phy_driver *drv = phydev->drv;
  422 + int ret = 0;
  423 +
  424 + if (!drv || !drv->writeext)
  425 + return -EOPNOTSUPP;
  426 +
  427 + ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_LO, 0x1A80);
  428 + if (ret)
  429 + return ret;
  430 +
  431 + ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_HI, 0x6);
  432 + return ret;
  433 +}
418 434 #else
419 435 static int ksz9031_of_config(struct phy_device *phydev)
420 436 {
421 437 return 0;
422 438 }
  439 +static int ksz9031_center_flp_timing(struct phy_device *phydev)
  440 +{
  441 + return 0;
  442 +}
423 443 #endif
424 444  
425 445 /* Accessors to extended registers*/
... ... @@ -470,6 +490,9 @@
470 490 {
471 491 int ret;
472 492 ret = ksz9031_of_config(phydev);
  493 + if (ret)
  494 + return ret;
  495 + ret = ksz9031_center_flp_timing(phydev);
473 496 if (ret)
474 497 return ret;
475 498 return genphy_config(phydev);
... ... @@ -20,6 +20,9 @@
20 20 #define MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW 0x6
21 21 #define MII_KSZ9031_EXT_RGMII_CLOCK_SKEW 0x8
22 22  
  23 +#define MII_KSZ9031_FLP_BURST_TX_LO 0x3
  24 +#define MII_KSZ9031_FLP_BURST_TX_HI 0x4
  25 +
23 26 /* Registers */
24 27 #define MMD_ACCESS_CONTROL 0xd
25 28 #define MMD_ACCESS_REG_DATA 0xe