Eric Lee / smarc-uboot

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Commit f01b631f7d370da1fe59f933f370d6372f4dbd04

Authored by Tom Warren
Committed by Tom Warren
1 parent 6d6c0baebe
Exists in master and in 53 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Tegra30: Add/enable Cardhu build (T30 reference board) 

This build is stripped down. It boots to the command prompt.
GPIO is the only peripheral supported. Others TBD.

include/configs/tegra-common.h now holds common config options
for Tegra SoCs.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>

Showing 9 changed files with 865 additions and 173 deletions Side-by-side Diff

board/nvidia/cardhu/Makefile
Diff comments   View file @ f01b631
  1 +#
  2 +# (C) Copyright 2010-2012
  3 +# NVIDIA Corporation <www.nvidia.com>
  4 +#
  5 +#
  6 +# See file CREDITS for list of people who contributed to this
  7 +# project.
  8 +#
  9 +# This program is free software; you can redistribute it and/or
  10 +# modify it under the terms of the GNU General Public License as
  11 +# published by the Free Software Foundation; either version 2 of
  12 +# the License, or (at your option) any later version.
  13 +#
  14 +# This program is distributed in the hope that it will be useful,
  15 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 +# GNU General Public License for more details.
  18 +#
  19 +# You should have received a copy of the GNU General Public License
  20 +# along with this program; if not, write to the Free Software
  21 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 +# MA 02111-1307 USA
  23 +#
  24 +
  25 +include $(TOPDIR)/config.mk
  26 +
  27 +LIB = $(obj)lib$(BOARD).o
  28 +
  29 +COBJS := $(BOARD).o
  30 +
  31 +SRCS := $(COBJS:.o=.c)
  32 +OBJS := $(addprefix $(obj),$(COBJS))
  33 +
  34 +$(LIB): $(obj).depend $(OBJS)
  35 + $(call cmd_link_o_target, $(OBJS))
  36 +
  37 +#########################################################################
  38 +
  39 +# defines $(obj).depend target
  40 +include $(SRCTREE)/rules.mk
  41 +
  42 +sinclude $(obj).depend
  43 +
  44 +#########################################################################
board/nvidia/cardhu/cardhu.c
Diff comments   View file @ f01b631
  1 +/*
  2 + * (C) Copyright 2010-2012
  3 + * NVIDIA Corporation <www.nvidia.com>
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include <common.h>
  25 +#include <asm/arch/pinmux.h>
  26 +#include "pinmux-config-cardhu.h"
  27 +
  28 +/*
  29 + * Routine: pinmux_init
  30 + * Description: Do individual peripheral pinmux configs
  31 + */
  32 +void pinmux_init(void)
  33 +{
  34 + pinmux_config_table(tegra3_pinmux_common,
  35 + ARRAY_SIZE(tegra3_pinmux_common));
  36 +
  37 + pinmux_config_table(unused_pins_lowpower,
  38 + ARRAY_SIZE(unused_pins_lowpower));
  39 +}
board/nvidia/cardhu/cardhu.c.mmc
Diff comments   View file @ f01b631
  1 +/*
  2 + * (C) Copyright 2010-2012
  3 + * NVIDIA Corporation <www.nvidia.com>
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include <common.h>
  25 +#include <asm/io.h>
  26 +#include <asm/arch/pinmux.h>
  27 +#include "pinmux-config-cardhu.h"
  28 +
  29 +#include <asm/arch/clock.h>
  30 +#include <asm/arch/gp_padctrl.h>
  31 +#include <asm/arch/pmu.h>
  32 +#include <asm/arch/sdmmc.h>
  33 +#include <asm/arch-tegra/mmc.h>
  34 +#include <asm/arch-tegra/tegra_mmc.h>
  35 +#include <mmc.h>
  36 +#include <i2c.h>
  37 +
  38 +/*
  39 + * Routine: pinmux_init
  40 + * Description: Do individual peripheral pinmux configs
  41 + */
  42 +void pinmux_init(void)
  43 +{
  44 + pinmux_config_table(tegra3_pinmux_common,
  45 + ARRAY_SIZE(tegra3_pinmux_common));
  46 +
  47 + pinmux_config_table(unused_pins_lowpower,
  48 + ARRAY_SIZE(unused_pins_lowpower));
  49 +}
  50 +
  51 +#if defined(CONFIG_MMC)
  52 +/*
  53 + * Routine: pin_mux_mmc
  54 + * Description: setup the pin muxes/tristate values for the SDMMC(s)
  55 + */
  56 +static void pin_mux_mmc(void)
  57 +{
  58 +}
  59 +
  60 +/* Do I2C/PMU writes to bring up SD card bus power */
  61 +static void board_sdmmc_voltage_init(void)
  62 +{
  63 + uchar reg, data_buffer[1];
  64 + int i;
  65 +
  66 + i2c_set_bus_num(0); /* PMU is on bus 0 */
  67 +
  68 + data_buffer[0] = 0x65;
  69 + reg = 0x32;
  70 +
  71 + for (i = 0; i < MAX_I2C_RETRY; ++i) {
  72 + if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1))
  73 + udelay(100);
  74 + }
  75 +
  76 + data_buffer[0] = 0x09;
  77 + reg = 0x67;
  78 +
  79 + for (i = 0; i < MAX_I2C_RETRY; ++i) {
  80 + if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1))
  81 + udelay(100);
  82 + }
  83 +}
  84 +
  85 +static void pad_init_mmc(struct tegra_mmc *reg)
  86 +{
  87 + struct apb_misc_gp_ctlr *const gpc =
  88 + (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
  89 + struct sdmmc_ctlr *const sdmmc = (struct sdmmc_ctlr *)reg;
  90 + u32 val, offset = (unsigned int)reg;
  91 + u32 padcfg, padmask;
  92 +
  93 + debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)sdmmc);
  94 +
  95 + /* Set the pad drive strength for SDMMC1 or 3 only */
  96 + if (offset != TEGRA_SDMMC1_BASE && offset != TEGRA_SDMMC3_BASE) {
  97 + debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
  98 + __func__);
  99 + return;
  100 + }
  101 +
  102 + /* Set pads as per T30 TRM, section 24.6.1.2 */
  103 + padcfg = (GP_SDIOCFG_DRVUP_SLWF | GP_SDIOCFG_DRVDN_SLWR | \
  104 + GP_SDIOCFG_DRVUP | GP_SDIOCFG_DRVDN);
  105 + padmask = 0x00000FFF;
  106 + if (offset == TEGRA_SDMMC1_BASE) {
  107 + val = readl(&gpc->sdio1cfg);
  108 + val &= padmask;
  109 + val |= padcfg;
  110 + writel(val, &gpc->sdio1cfg);
  111 + } else { /* SDMMC3 */
  112 + val = readl(&gpc->sdio3cfg);
  113 + val &= padmask;
  114 + val |= padcfg;
  115 + writel(val, &gpc->sdio3cfg);
  116 + }
  117 +
  118 + val = readl(&sdmmc->sdmmc_sdmemcomp_pad_ctrl);
  119 + val &= 0xFFFFFFF0;
  120 + val |= MEMCOMP_PADCTRL_VREF;
  121 + writel(val, &sdmmc->sdmmc_sdmemcomp_pad_ctrl);
  122 +
  123 + val = readl(&sdmmc->sdmmc_auto_cal_config);
  124 + val &= 0xFFFF0000;
  125 + val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
  126 + writel(val, &sdmmc->sdmmc_auto_cal_config);
  127 +}
  128 +
  129 +/* this is a weak define that we are overriding */
  130 +int board_mmc_init(bd_t *bd)
  131 +{
  132 + debug("board_mmc_init called\n");
  133 +
  134 + /* Turn on SD-card bus power */
  135 + board_sdmmc_voltage_init();
  136 +
  137 + /* Set up the SDMMC pads as per the TRM */
  138 + pad_init_mmc((struct tegra_mmc *)TEGRA_SDMMC1_BASE);
  139 +
  140 + /* Enable muxes, etc. for SDMMC controllers */
  141 + pin_mux_mmc();
  142 +
  143 + /* init dev 0 (SDMMC4), ("HSMMC") with 8-bit bus */
  144 + tegra_mmc_init(0, 8, -1, -1);
  145 +
  146 + /* init dev 1 (SDMMC0), ("SDIO") with 8-bit bus */
  147 + tegra_mmc_init(1, 8, -1, -1);
  148 +
  149 + return 0;
  150 +}
  151 +#endif /* MMC */
board/nvidia/cardhu/pinmux-config-cardhu.h
Diff comments   View file @ f01b631
  1 +/*
  2 + * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
  3 + *
  4 + * This program is free software; you can redistribute it and/or modify it
  5 + * under the terms and conditions of the GNU General Public License,
  6 + * version 2, as published by the Free Software Foundation.
  7 + *
  8 + * This program is distributed in the hope it will be useful, but WITHOUT
  9 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  11 + * more details.
  12 + *
  13 + * You should have received a copy of the GNU General Public License
  14 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
  15 + */
  16 +
  17 +#ifndef _PINMUX_CONFIG_CARDHU_H_
  18 +#define _PINMUX_CONFIG_CARDHU_H_
  19 +
  20 +#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \
  21 + { \
  22 + .pingroup = PINGRP_##_pingroup, \
  23 + .func = PMUX_FUNC_##_mux, \
  24 + .pull = PMUX_PULL_##_pull, \
  25 + .tristate = PMUX_TRI_##_tri, \
  26 + .io = PMUX_PIN_##_io, \
  27 + .lock = PMUX_PIN_LOCK_DEFAULT, \
  28 + .od = PMUX_PIN_OD_DEFAULT, \
  29 + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
  30 + }
  31 +
  32 +#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
  33 + { \
  34 + .pingroup = PINGRP_##_pingroup, \
  35 + .func = PMUX_FUNC_##_mux, \
  36 + .pull = PMUX_PULL_##_pull, \
  37 + .tristate = PMUX_TRI_##_tri, \
  38 + .io = PMUX_PIN_##_io, \
  39 + .lock = PMUX_PIN_LOCK_##_lock, \
  40 + .od = PMUX_PIN_OD_##_od, \
  41 + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
  42 + }
  43 +
  44 +#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
  45 + { \
  46 + .pingroup = PINGRP_##_pingroup, \
  47 + .func = PMUX_FUNC_##_mux, \
  48 + .pull = PMUX_PULL_##_pull, \
  49 + .tristate = PMUX_TRI_##_tri, \
  50 + .io = PMUX_PIN_##_io, \
  51 + .lock = PMUX_PIN_LOCK_##_lock, \
  52 + .od = PMUX_PIN_OD_DEFAULT, \
  53 + .ioreset = PMUX_PIN_IO_RESET_##_ioreset \
  54 + }
  55 +
  56 +static struct pingroup_config tegra3_pinmux_common[] = {
  57 + /* SDMMC1 pinmux */
  58 + DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
  59 + DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
  60 + DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT),
  61 + DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT),
  62 + DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT),
  63 + DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT),
  64 +
  65 + /* SDMMC3 pinmux */
  66 + DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
  67 + DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT),
  68 + DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT),
  69 + DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT),
  70 + DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT),
  71 + DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT),
  72 + DEFAULT_PINMUX(SDMMC3_DAT6, RSVD1, NORMAL, NORMAL, INPUT),
  73 + DEFAULT_PINMUX(SDMMC3_DAT7, RSVD1, NORMAL, NORMAL, INPUT),
  74 +
  75 + /* SDMMC4 pinmux */
  76 + LV_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
  77 + LV_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
  78 + LV_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
  79 + LV_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
  80 + LV_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
  81 + LV_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
  82 + LV_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
  83 + LV_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
  84 + LV_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
  85 + LV_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
  86 + LV_PINMUX(SDMMC4_RST_N, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
  87 +
  88 + /* I2C1 pinmux */
  89 + I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
  90 + I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
  91 +
  92 + /* I2C2 pinmux */
  93 + I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
  94 + I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
  95 +
  96 + /* I2C3 pinmux */
  97 + I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
  98 + I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
  99 +
  100 + /* I2C4 pinmux */
  101 + I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
  102 + I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
  103 +
  104 + /* Power I2C pinmux */
  105 + I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
  106 + I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
  107 +
  108 + DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT),
  109 + DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, NORMAL, INPUT),
  110 + DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT),
  111 + DEFAULT_PINMUX(ULPI_DATA3, RSVD1, NORMAL, NORMAL, INPUT),
  112 + DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT),
  113 + DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT),
  114 + DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT),
  115 + DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, OUTPUT),
  116 + DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT),
  117 + DEFAULT_PINMUX(ULPI_DIR, UARTD, NORMAL, NORMAL, INPUT),
  118 + DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT),
  119 + DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, OUTPUT),
  120 + DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT),
  121 + DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT),
  122 + DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT),
  123 + DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT),
  124 + DEFAULT_PINMUX(GPIO_PV2, OWR, NORMAL, NORMAL, OUTPUT),
  125 + DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, OUTPUT),
  126 + DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT),
  127 + DEFAULT_PINMUX(CLK2_REQ, DAP, NORMAL, NORMAL, INPUT),
  128 + DEFAULT_PINMUX(LCD_PWR1, DISPA, NORMAL, NORMAL, INPUT),
  129 + DEFAULT_PINMUX(LCD_PWR2, DISPA, NORMAL, NORMAL, INPUT),
  130 + DEFAULT_PINMUX(LCD_SDIN, DISPA, NORMAL, NORMAL, INPUT),
  131 + DEFAULT_PINMUX(LCD_SDOUT, DISPA, NORMAL, NORMAL, INPUT),
  132 + DEFAULT_PINMUX(LCD_WR_N, DISPA, NORMAL, NORMAL, INPUT),
  133 + DEFAULT_PINMUX(LCD_CS0_N, DISPA, NORMAL, NORMAL, INPUT),
  134 + DEFAULT_PINMUX(LCD_DC0, DISPA, NORMAL, NORMAL, INPUT),
  135 + DEFAULT_PINMUX(LCD_SCK, DISPA, NORMAL, NORMAL, INPUT),
  136 + DEFAULT_PINMUX(LCD_PWR0, DISPA, NORMAL, NORMAL, INPUT),
  137 + DEFAULT_PINMUX(LCD_PCLK, DISPA, NORMAL, NORMAL, INPUT),
  138 + DEFAULT_PINMUX(LCD_DE, DISPA, NORMAL, NORMAL, INPUT),
  139 + DEFAULT_PINMUX(LCD_HSYNC, DISPA, NORMAL, NORMAL, INPUT),
  140 + DEFAULT_PINMUX(LCD_VSYNC, DISPA, NORMAL, NORMAL, INPUT),
  141 + DEFAULT_PINMUX(LCD_D0, DISPA, NORMAL, NORMAL, INPUT),
  142 + DEFAULT_PINMUX(LCD_D1, DISPA, NORMAL, NORMAL, INPUT),
  143 + DEFAULT_PINMUX(LCD_D2, DISPA, NORMAL, NORMAL, INPUT),
  144 + DEFAULT_PINMUX(LCD_D3, DISPA, NORMAL, NORMAL, INPUT),
  145 + DEFAULT_PINMUX(LCD_D4, DISPA, NORMAL, NORMAL, INPUT),
  146 + DEFAULT_PINMUX(LCD_D5, DISPA, NORMAL, NORMAL, INPUT),
  147 + DEFAULT_PINMUX(LCD_D6, DISPA, NORMAL, NORMAL, INPUT),
  148 + DEFAULT_PINMUX(LCD_D7, DISPA, NORMAL, NORMAL, INPUT),
  149 + DEFAULT_PINMUX(LCD_D8, DISPA, NORMAL, NORMAL, INPUT),
  150 + DEFAULT_PINMUX(LCD_D9, DISPA, NORMAL, NORMAL, INPUT),
  151 + DEFAULT_PINMUX(LCD_D10, DISPA, NORMAL, NORMAL, INPUT),
  152 + DEFAULT_PINMUX(LCD_D11, DISPA, NORMAL, NORMAL, INPUT),
  153 + DEFAULT_PINMUX(LCD_D12, DISPA, NORMAL, NORMAL, INPUT),
  154 + DEFAULT_PINMUX(LCD_D13, DISPA, NORMAL, NORMAL, INPUT),
  155 + DEFAULT_PINMUX(LCD_D14, DISPA, NORMAL, NORMAL, INPUT),
  156 + DEFAULT_PINMUX(LCD_D15, DISPA, NORMAL, NORMAL, INPUT),
  157 + DEFAULT_PINMUX(LCD_D16, DISPA, NORMAL, NORMAL, INPUT),
  158 + DEFAULT_PINMUX(LCD_D17, DISPA, NORMAL, NORMAL, INPUT),
  159 + DEFAULT_PINMUX(LCD_D18, DISPA, NORMAL, NORMAL, INPUT),
  160 + DEFAULT_PINMUX(LCD_D19, DISPA, NORMAL, NORMAL, INPUT),
  161 + DEFAULT_PINMUX(LCD_D20, DISPA, NORMAL, NORMAL, INPUT),
  162 + DEFAULT_PINMUX(LCD_D21, DISPA, NORMAL, NORMAL, INPUT),
  163 + DEFAULT_PINMUX(LCD_D22, DISPA, NORMAL, NORMAL, INPUT),
  164 + DEFAULT_PINMUX(LCD_D23, DISPA, NORMAL, NORMAL, INPUT),
  165 + DEFAULT_PINMUX(LCD_CS1_N, DISPA, NORMAL, NORMAL, INPUT),
  166 + DEFAULT_PINMUX(LCD_M1, DISPA, NORMAL, NORMAL, INPUT),
  167 + DEFAULT_PINMUX(LCD_DC1, DISPA, NORMAL, NORMAL, INPUT),
  168 + DEFAULT_PINMUX(CRT_HSYNC, CRT, NORMAL, NORMAL, OUTPUT),
  169 + DEFAULT_PINMUX(CRT_VSYNC, CRT, NORMAL, NORMAL, OUTPUT),
  170 + LV_PINMUX(VI_D0, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
  171 + LV_PINMUX(VI_D1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
  172 + LV_PINMUX(VI_D2, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
  173 + LV_PINMUX(VI_D3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
  174 + LV_PINMUX(VI_D4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
  175 + LV_PINMUX(VI_D5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
  176 + LV_PINMUX(VI_D7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
  177 + LV_PINMUX(VI_D10, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
  178 + LV_PINMUX(VI_MCLK, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
  179 + DEFAULT_PINMUX(UART2_RXD, IRDA, NORMAL, NORMAL, INPUT),
  180 + DEFAULT_PINMUX(UART2_TXD, IRDA, NORMAL, NORMAL, OUTPUT),
  181 + DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT),
  182 + DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT),
  183 + DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
  184 + DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT),
  185 + DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT),
  186 + DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
  187 + DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT),
  188 + DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
  189 + DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, NORMAL, INPUT),
  190 + DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT),
  191 + DEFAULT_PINMUX(GPIO_PU4, PWM1, NORMAL, NORMAL, OUTPUT),
  192 + DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, NORMAL, OUTPUT),
  193 + DEFAULT_PINMUX(GPIO_PU6, RSVD1, NORMAL, NORMAL, INPUT),
  194 + DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT),
  195 + DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT),
  196 + DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
  197 + DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
  198 + DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
  199 + DEFAULT_PINMUX(CLK3_REQ, DEV3, NORMAL, NORMAL, INPUT),
  200 + DEFAULT_PINMUX(GMI_WP_N, GMI, NORMAL, NORMAL, INPUT),
  201 + DEFAULT_PINMUX(GMI_CS2_N, RSVD1, UP, NORMAL, INPUT), /* EN_VDD_BL1 */
  202 + DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */
  203 + DEFAULT_PINMUX(GMI_AD10, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */
  204 + DEFAULT_PINMUX(GMI_A16, SPI4, NORMAL, NORMAL, INPUT),
  205 + DEFAULT_PINMUX(GMI_A17, SPI4, NORMAL, NORMAL, INPUT),
  206 + DEFAULT_PINMUX(GMI_A18, SPI4, NORMAL, NORMAL, INPUT),
  207 + DEFAULT_PINMUX(GMI_A19, SPI4, NORMAL, NORMAL, INPUT),
  208 + DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, UP, NORMAL, INPUT),
  209 + DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT),
  210 + DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT),
  211 + DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, INPUT),
  212 + DEFAULT_PINMUX(GPIO_PBB5, VGP5, NORMAL, NORMAL, INPUT),
  213 + DEFAULT_PINMUX(GPIO_PBB6, VGP6, NORMAL, NORMAL, INPUT),
  214 + DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT),
  215 + DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT),
  216 + DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT),
  217 +
  218 + /* KBC keys */
  219 + DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT),
  220 + DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT),
  221 + DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT),
  222 + DEFAULT_PINMUX(KB_ROW3, KBC, UP, NORMAL, INPUT),
  223 + DEFAULT_PINMUX(KB_ROW4, KBC, UP, NORMAL, INPUT),
  224 + DEFAULT_PINMUX(KB_ROW5, KBC, UP, NORMAL, INPUT),
  225 + DEFAULT_PINMUX(KB_ROW6, KBC, UP, NORMAL, INPUT),
  226 + DEFAULT_PINMUX(KB_ROW7, KBC, UP, NORMAL, INPUT),
  227 + DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
  228 + DEFAULT_PINMUX(KB_ROW9, KBC, UP, NORMAL, INPUT),
  229 + DEFAULT_PINMUX(KB_ROW10, KBC, UP, NORMAL, INPUT),
  230 + DEFAULT_PINMUX(KB_ROW11, KBC, UP, NORMAL, INPUT),
  231 + DEFAULT_PINMUX(KB_ROW12, KBC, UP, NORMAL, INPUT),
  232 + DEFAULT_PINMUX(KB_ROW13, KBC, UP, NORMAL, INPUT),
  233 + DEFAULT_PINMUX(KB_ROW14, KBC, UP, NORMAL, INPUT),
  234 + DEFAULT_PINMUX(KB_ROW15, KBC, UP, NORMAL, INPUT),
  235 + DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT),
  236 + DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT),
  237 + DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT),
  238 + DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, INPUT),
  239 + DEFAULT_PINMUX(KB_COL4, KBC, UP, NORMAL, INPUT),
  240 + DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT),
  241 + DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, INPUT),
  242 + DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, INPUT),
  243 + DEFAULT_PINMUX(GPIO_PV0, RSVD1, UP, NORMAL, INPUT),
  244 +
  245 + DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT),
  246 + DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT),
  247 + DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
  248 + DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT),
  249 + DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT),
  250 + DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT),
  251 + DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT),
  252 + DEFAULT_PINMUX(CLK1_REQ, DAP, NORMAL, NORMAL, INPUT),
  253 + DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT),
  254 + DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT),
  255 + DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT),
  256 + DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT),
  257 + DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT),
  258 + DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
  259 + DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
  260 +
  261 + DEFAULT_PINMUX(SPI2_CS1_N, SPI2, UP, NORMAL, INPUT),
  262 + DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT),
  263 + DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT),
  264 + DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT),
  265 + DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT),
  266 + DEFAULT_PINMUX(PEX_L0_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
  267 + DEFAULT_PINMUX(PEX_L0_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
  268 + DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
  269 + DEFAULT_PINMUX(PEX_WAKE_N, PCIE, NORMAL, NORMAL, INPUT),
  270 + DEFAULT_PINMUX(PEX_L1_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
  271 + DEFAULT_PINMUX(PEX_L1_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
  272 + DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
  273 + DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
  274 + DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
  275 + DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
  276 + DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT),
  277 + DEFAULT_PINMUX(HDMI_INT, RSVD1, NORMAL, TRISTATE, INPUT),
  278 +
  279 + /* GPIOs */
  280 + /* SDMMC1 CD gpio */
  281 + DEFAULT_PINMUX(GMI_IORDY, RSVD1, UP, NORMAL, INPUT),
  282 + /* SDMMC1 WP gpio */
  283 + LV_PINMUX(VI_D11, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE),
  284 +
  285 + /* Touch panel GPIO */
  286 + /* Touch IRQ */
  287 + DEFAULT_PINMUX(GMI_AD12, NAND, UP, NORMAL, INPUT),
  288 +
  289 + /* Touch RESET */
  290 + DEFAULT_PINMUX(GMI_AD14, NAND, NORMAL, NORMAL, OUTPUT),
  291 +
  292 + /* Power rails GPIO */
  293 + DEFAULT_PINMUX(SPI2_SCK, GMI, NORMAL, NORMAL, INPUT),
  294 + DEFAULT_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, INPUT),
  295 + DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
  296 + DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, UP, NORMAL, INPUT),
  297 + DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, UP, NORMAL, INPUT),
  298 +
  299 + LV_PINMUX(VI_D6, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
  300 + LV_PINMUX(VI_D8, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
  301 + LV_PINMUX(VI_D9, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
  302 + LV_PINMUX(VI_PCLK, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE),
  303 + LV_PINMUX(VI_HSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
  304 + LV_PINMUX(VI_VSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
  305 +};
  306 +
  307 +static struct pingroup_config unused_pins_lowpower[] = {
  308 + DEFAULT_PINMUX(GMI_WAIT, NAND, UP, TRISTATE, OUTPUT),
  309 + DEFAULT_PINMUX(GMI_ADV_N, NAND, NORMAL, TRISTATE, OUTPUT),
  310 + DEFAULT_PINMUX(GMI_CLK, NAND, NORMAL, TRISTATE, OUTPUT),
  311 + DEFAULT_PINMUX(GMI_CS3_N, NAND, NORMAL, NORMAL, OUTPUT),
  312 + DEFAULT_PINMUX(GMI_CS7_N, NAND, UP, NORMAL, INPUT),
  313 + DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, TRISTATE, OUTPUT),
  314 + DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, TRISTATE, OUTPUT),
  315 + DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, TRISTATE, OUTPUT),
  316 + DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, TRISTATE, OUTPUT),
  317 + DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, TRISTATE, OUTPUT),
  318 + DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, TRISTATE, OUTPUT),
  319 + DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, TRISTATE, OUTPUT),
  320 + DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, TRISTATE, OUTPUT),
  321 + DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT),
  322 + DEFAULT_PINMUX(GMI_AD11, NAND, NORMAL, NORMAL, OUTPUT),
  323 + DEFAULT_PINMUX(GMI_AD13, NAND, UP, NORMAL, INPUT),
  324 + DEFAULT_PINMUX(GMI_WR_N, NAND, NORMAL, TRISTATE, OUTPUT),
  325 + DEFAULT_PINMUX(GMI_OE_N, NAND, NORMAL, TRISTATE, OUTPUT),
  326 + DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT),
  327 +};
  328 +
  329 +#endif /* _PINMUX_CONFIG_CARDHU_H_ */
... ... @@ -290,6 +290,7 @@
290 290 seaboard arm armv7:arm720t seaboard nvidia tegra20
291 291 ventana arm armv7:arm720t ventana nvidia tegra20
292 292 whistler arm armv7:arm720t whistler nvidia tegra20
  293 +cardhu arm armv7:arm720t cardhu nvidia tegra30
293 294 colibri_t20_iris arm armv7:arm720t colibri_t20_iris toradex tegra20
294 295 u8500_href arm armv7 u8500 st-ericsson u8500
295 296 snowball arm armv7 snowball st-ericsson u8500
include/configs/tegra-common-post.h
Diff comments   View file @ f01b631
... ... @@ -119,33 +119,6 @@
119 119  
120 120 #endif
121 121  
122   -/*
123   - * Memory layout for where various images get loaded by boot scripts:
124   - *
125   - * scriptaddr can be pretty much anywhere that doesn't conflict with something
126   - * else. Put it above BOOTMAPSZ to eliminate conflicts.
127   - *
128   - * kernel_addr_r must be within the first 128M of RAM in order for the
129   - * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
130   - * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
131   - * should not overlap that area, or the kernel will have to copy itself
132   - * somewhere else before decompression. Similarly, the address of any other
133   - * data passed to the kernel shouldn't overlap the start of RAM. Pushing
134   - * this up to 16M allows for a sizable kernel to be decompressed below the
135   - * compressed load address.
136   - *
137   - * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
138   - * the compressed kernel to be up to 16M too.
139   - *
140   - * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
141   - * for the FDT/DTB to be up to 1M, which is hopefully plenty.
142   - */
143   -#define MEM_LAYOUT_ENV_SETTINGS \
144   - "scriptaddr=0x10000000\0" \
145   - "kernel_addr_r=0x01000000\0" \
146   - "fdt_addr_r=0x02000000\0" \
147   - "ramdisk_addr_r=0x02100000\0" \
148   -
149 122 #ifdef CONFIG_TEGRA_KEYBOARD
150 123 #define STDIN_KBD_KBC ",tegra-kbc"
151 124 #else
include/configs/tegra-common.h
Diff comments   View file @ f01b631
  1 +/*
  2 + * (C) Copyright 2010-2012
  3 + * NVIDIA Corporation <www.nvidia.com>
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#ifndef __TEGRA_COMMON_H
  25 +#define __TEGRA_COMMON_H
  26 +#include <asm/sizes.h>
  27 +#include <linux/stringify.h>
  28 +
  29 +/*
  30 + * High Level Configuration Options
  31 + */
  32 +#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
  33 +#define CONFIG_TEGRA /* which is a Tegra generic machine */
  34 +#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
  35 +
  36 +#define CONFIG_SYS_CACHELINE_SIZE 32
  37 +
  38 +#include <asm/arch/tegra.h> /* get chip and board defs */
  39 +
  40 +/*
  41 + * Display CPU and Board information
  42 + */
  43 +#define CONFIG_DISPLAY_CPUINFO
  44 +#define CONFIG_DISPLAY_BOARDINFO
  45 +
  46 +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
  47 +#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
  48 +
  49 +/* Environment */
  50 +#define CONFIG_ENV_VARS_UBOOT_CONFIG
  51 +#define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */
  52 +
  53 +/*
  54 + * Size of malloc() pool
  55 + */
  56 +#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
  57 +
  58 +/*
  59 + * PllX Configuration
  60 + */
  61 +#define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */
  62 +
  63 +#define CONFIG_SYS_NS16550
  64 +#define CONFIG_SYS_NS16550_SERIAL
  65 +#define CONFIG_SYS_NS16550_REG_SIZE (-4)
  66 +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
  67 +
  68 +/*
  69 + * select serial console configuration
  70 + */
  71 +#define CONFIG_CONS_INDEX 1
  72 +
  73 +/* allow to overwrite serial and ethaddr */
  74 +#define CONFIG_ENV_OVERWRITE
  75 +#define CONFIG_BAUDRATE 115200
  76 +
  77 +/* include default commands */
  78 +#include <config_cmd_default.h>
  79 +
  80 +/* remove unused commands */
  81 +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
  82 +#undef CONFIG_CMD_FPGA /* FPGA configuration support */
  83 +#undef CONFIG_CMD_IMI
  84 +#undef CONFIG_CMD_IMLS
  85 +#undef CONFIG_CMD_NFS /* NFS support */
  86 +#undef CONFIG_CMD_NET /* network support */
  87 +
  88 +/* turn on command-line edit/hist/auto */
  89 +#define CONFIG_CMDLINE_EDITING
  90 +#define CONFIG_COMMAND_HISTORY
  91 +#define CONFIG_AUTO_COMPLETE
  92 +
  93 +#define CONFIG_SYS_NO_FLASH
  94 +
  95 +#define CONFIG_CONSOLE_MUX
  96 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV
  97 +#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
  98 +
  99 +/*
  100 + * Miscellaneous configurable options
  101 + */
  102 +#define CONFIG_SYS_LONGHELP /* undef to save memory */
  103 +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
  104 +#define CONFIG_SYS_PROMPT V_PROMPT
  105 +/*
  106 + * Increasing the size of the IO buffer as default nfsargs size is more
  107 + * than 256 and so it is not possible to edit it
  108 + */
  109 +#define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */
  110 +/* Print Buffer Size */
  111 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  112 + sizeof(CONFIG_SYS_PROMPT) + 16)
  113 +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  114 +/* Boot Argument Buffer Size */
  115 +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
  116 +
  117 +#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
  118 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
  119 +
  120 +#define CONFIG_SYS_HZ 1000
  121 +
  122 +/*-----------------------------------------------------------------------
  123 + * Physical Memory Map
  124 + */
  125 +#define CONFIG_NR_DRAM_BANKS 1
  126 +#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
  127 +#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
  128 +
  129 +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
  130 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  131 +
  132 +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
  133 +
  134 +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
  135 +#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
  136 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
  137 + CONFIG_SYS_INIT_RAM_SIZE - \
  138 + GENERATED_GBL_DATA_SIZE)
  139 +
  140 +#define CONFIG_TEGRA_GPIO
  141 +#define CONFIG_CMD_GPIO
  142 +#define CONFIG_CMD_ENTERRCM
  143 +#define CONFIG_CMD_BOOTZ
  144 +
  145 +/* Defines for SPL */
  146 +#define CONFIG_SPL
  147 +#define CONFIG_SPL_FRAMEWORK
  148 +#define CONFIG_SPL_RAM_DEVICE
  149 +#define CONFIG_SPL_BOARD_INIT
  150 +#define CONFIG_SPL_NAND_SIMPLE
  151 +#define CONFIG_SPL_MAX_SIZE (CONFIG_SYS_TEXT_BASE - \
  152 + CONFIG_SPL_TEXT_BASE)
  153 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
  154 +
  155 +#define CONFIG_SPL_LIBCOMMON_SUPPORT
  156 +#define CONFIG_SPL_LIBGENERIC_SUPPORT
  157 +#define CONFIG_SPL_SERIAL_SUPPORT
  158 +#define CONFIG_SPL_GPIO_SUPPORT
  159 +
  160 +#endif /* _TEGRA_COMMON_H_ */
include/configs/tegra20-common.h
Diff comments   View file @ f01b631
... ... @@ -21,81 +21,82 @@
21 21 * MA 02111-1307 USA
22 22 */
23 23  
24   -#ifndef __TEGRA20_COMMON_H
25   -#define __TEGRA20_COMMON_H
26   -#include <asm/sizes.h>
27   -#include <linux/stringify.h>
  24 +#ifndef _TEGRA20_COMMON_H_
  25 +#define _TEGRA20_COMMON_H_
  26 +#include "tegra-common.h"
28 27  
29 28 /*
  29 + * NS16550 Configuration
  30 + */
  31 +#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
  32 +
  33 +/*
30 34 * High Level Configuration Options
31 35 */
32   -#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
33   -#define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */
34   -#define CONFIG_TEGRA /* which is a Tegra generic machine */
35   -#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
  36 +#define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */
36 37  
37   -#define CONFIG_SYS_CACHELINE_SIZE 32
  38 +/* Environment information, boards can override if required */
  39 +#define CONFIG_LOADADDR 0x00408000 /* def. location for kernel */
38 40  
39   -#include <asm/arch/tegra.h> /* get chip and board defs */
  41 +/*
  42 + * Miscellaneous configurable options
  43 + */
  44 +#define CONFIG_SYS_LOAD_ADDR 0x00A00800 /* default */
  45 +#define CONFIG_STACKBASE 0x02800000 /* 40MB */
40 46  
41   -/* Align LCD to 1MB boundary */
42   -#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
  47 +/*-----------------------------------------------------------------------
  48 + * Physical Memory Map
  49 + */
  50 +#define CONFIG_SYS_TEXT_BASE 0x0010E000
43 51  
44 52 /*
45   - * Display CPU and Board information
  53 + * Memory layout for where various images get loaded by boot scripts:
  54 + *
  55 + * scriptaddr can be pretty much anywhere that doesn't conflict with something
  56 + * else. Put it above BOOTMAPSZ to eliminate conflicts.
  57 + *
  58 + * kernel_addr_r must be within the first 128M of RAM in order for the
  59 + * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  60 + * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
  61 + * should not overlap that area, or the kernel will have to copy itself
  62 + * somewhere else before decompression. Similarly, the address of any other
  63 + * data passed to the kernel shouldn't overlap the start of RAM. Pushing
  64 + * this up to 16M allows for a sizable kernel to be decompressed below the
  65 + * compressed load address.
  66 + *
  67 + * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
  68 + * the compressed kernel to be up to 16M too.
  69 + *
  70 + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
  71 + * for the FDT/DTB to be up to 1M, which is hopefully plenty.
46 72 */
47   -#define CONFIG_DISPLAY_CPUINFO
48   -#define CONFIG_DISPLAY_BOARDINFO
  73 +#define MEM_LAYOUT_ENV_SETTINGS \
  74 + "scriptaddr=0x10000000\0" \
  75 + "kernel_addr_r=0x01000000\0" \
  76 + "fdt_addr_r=0x02000000\0" \
  77 + "ramdisk_addr_r=0x02100000\0"
49 78  
50   -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
51   -#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
  79 +/* Defines for SPL */
  80 +#define CONFIG_SPL_TEXT_BASE 0x00108000
  81 +#define CONFIG_SYS_SPL_MALLOC_START 0x00090000
  82 +#define CONFIG_SPL_STACK 0x000ffffc
52 83  
  84 +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds"
  85 +
  86 +/* Align LCD to 1MB boundary */
  87 +#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
  88 +
53 89 #ifdef CONFIG_TEGRA_LP0
54 90 #define TEGRA_LP0_ADDR 0x1C406000
55 91 #define TEGRA_LP0_SIZE 0x2000
56 92 #define TEGRA_LP0_VEC \
57   - "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
  93 + "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
58 94 "@" __stringify(TEGRA_LP0_ADDR) " "
59 95 #else
60 96 #define TEGRA_LP0_VEC
61 97 #endif
62 98  
63   -/* Environment */
64   -#define CONFIG_ENV_VARS_UBOOT_CONFIG
65   -#define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */
66   -
67 99 /*
68   - * Size of malloc() pool
69   - */
70   -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
71   -
72   -/*
73   - * PllX Configuration
74   - */
75   -#define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */
76   -
77   -/*
78   - * NS16550 Configuration
79   - */
80   -#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
81   -
82   -#define CONFIG_SYS_NS16550
83   -#define CONFIG_SYS_NS16550_SERIAL
84   -#define CONFIG_SYS_NS16550_REG_SIZE (-4)
85   -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
86   -
87   -/*
88   - * select serial console configuration
89   - */
90   -#define CONFIG_CONS_INDEX 1
91   -
92   -/* allow to overwrite serial and ethaddr */
93   -#define CONFIG_ENV_OVERWRITE
94   -#define CONFIG_BAUDRATE 115200
95   -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
96   - 115200}
97   -
98   -/*
99 100 * This parameter affects a TXFILLTUNING field that controls how much data is
100 101 * sent to the latency fifo before it is sent to the wire. Without this
101 102 * parameter, the default (2) causes occasional Data Buffer Errors in OUT
102 103  
103 104  
... ... @@ -107,106 +108,14 @@
107 108 /* Total I2C ports on Tegra20 */
108 109 #define TEGRA_I2C_NUM_CONTROLLERS 4
109 110  
110   -/* include default commands */
111   -#include <config_cmd_default.h>
112 111 #define CONFIG_PARTITION_UUIDS
113 112 #define CONFIG_CMD_PART
114 113  
115   -/* remove unused commands */
116   -#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
117   -#undef CONFIG_CMD_FPGA /* FPGA configuration support */
118   -#undef CONFIG_CMD_IMI
119   -#undef CONFIG_CMD_IMLS
120   -#undef CONFIG_CMD_NFS /* NFS support */
121   -#undef CONFIG_CMD_NET /* network support */
122   -
123   -/* turn on command-line edit/hist/auto */
124   -#define CONFIG_CMDLINE_EDITING
125   -#define CONFIG_COMMAND_HISTORY
126   -#define CONFIG_AUTO_COMPLETE
127   -
128   -#define CONFIG_SYS_NO_FLASH
129   -
130   -#define CONFIG_CONSOLE_MUX
131   -#define CONFIG_SYS_CONSOLE_IS_IN_ENV
132   -
133   -#define CONFIG_LOADADDR 0x408000 /* def. location for kernel */
134   -#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
135   -
136   -/*
137   - * Miscellaneous configurable options
138   - */
139   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
140   -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
141   -#define CONFIG_SYS_PROMPT V_PROMPT
142   -/*
143   - * Increasing the size of the IO buffer as default nfsargs size is more
144   - * than 256 and so it is not possible to edit it
145   - */
146   -#define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */
147   -/* Print Buffer Size */
148   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
149   - sizeof(CONFIG_SYS_PROMPT) + 16)
150   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
151   -/* Boot Argument Buffer Size */
152   -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
153   -
154   -#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
155   -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
156   -
157   -#define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */
158   -#define CONFIG_SYS_HZ 1000
159   -
160   -#define CONFIG_STACKBASE 0x2800000 /* 40MB */
161   -
162   -/*-----------------------------------------------------------------------
163   - * Physical Memory Map
164   - */
165   -#define CONFIG_NR_DRAM_BANKS 1
166   -#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
167   -#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
168   -
169   -#define CONFIG_SYS_TEXT_BASE 0x0010c000
170   -#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
171   -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
172   -
173   -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
174   -
175   -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
176   -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
177   -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
178   - CONFIG_SYS_INIT_RAM_SIZE - \
179   - GENERATED_GBL_DATA_SIZE)
180   -
181   -#define CONFIG_TEGRA_GPIO
182   -#define CONFIG_CMD_GPIO
183   -#define CONFIG_CMD_ENTERRCM
184   -#define CONFIG_CMD_BOOTZ
185   -
186   -/* Defines for SPL */
187   -#define CONFIG_SPL
188   -#define CONFIG_SPL_FRAMEWORK
189   -#define CONFIG_SPL_RAM_DEVICE
190   -#define CONFIG_SPL_BOARD_INIT
191   -#define CONFIG_SPL_NAND_SIMPLE
192   -#define CONFIG_SPL_TEXT_BASE 0x00108000
193   -#define CONFIG_SPL_MAX_SIZE (CONFIG_SYS_TEXT_BASE - \
194   - CONFIG_SPL_TEXT_BASE)
195   -#define CONFIG_SYS_SPL_MALLOC_START 0x00090000
196   -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
197   -#define CONFIG_SPL_STACK 0x000ffffc
198   -
199   -#define CONFIG_SPL_LIBCOMMON_SUPPORT
200   -#define CONFIG_SPL_LIBGENERIC_SUPPORT
201   -#define CONFIG_SPL_SERIAL_SUPPORT
202   -#define CONFIG_SPL_GPIO_SUPPORT
203   -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds"
204   -
205 114 #define CONFIG_SYS_NAND_SELF_INIT
206 115 #define CONFIG_SYS_NAND_ONFI_DETECTION
207 116  
208 117 /* Misc utility code */
209 118 #define CONFIG_BOUNCE_BUFFER
210 119  
211   -#endif /* __TEGRA20_COMMON_H */
  120 +#endif /* _TEGRA20_COMMON_H_ */
include/configs/tegra30-common.h
Diff comments   View file @ f01b631
  1 +/*
  2 + * (C) Copyright 2010-2012
  3 + * NVIDIA Corporation <www.nvidia.com>
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#ifndef _TEGRA30_COMMON_H_
  25 +#define _TEGRA30_COMMON_H_
  26 +#include "tegra-common.h"
  27 +
  28 +/*
  29 + * NS16550 Configuration
  30 + */
  31 +#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
  32 +
  33 +/*
  34 + * High Level Configuration Options
  35 + */
  36 +#define CONFIG_TEGRA30 /* in a NVidia Tegra30 core */
  37 +
  38 +/* Environment information, boards can override if required */
  39 +#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
  40 +
  41 +/*
  42 + * Miscellaneous configurable options
  43 + */
  44 +#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */
  45 +#define CONFIG_STACKBASE 0x82800000 /* 40MB */
  46 +
  47 +/*-----------------------------------------------------------------------
  48 + * Physical Memory Map
  49 + */
  50 +#define CONFIG_SYS_TEXT_BASE 0x8010E000
  51 +
  52 +/*
  53 + * Memory layout for where various images get loaded by boot scripts:
  54 + *
  55 + * scriptaddr can be pretty much anywhere that doesn't conflict with something
  56 + * else. Put it above BOOTMAPSZ to eliminate conflicts.
  57 + *
  58 + * kernel_addr_r must be within the first 128M of RAM in order for the
  59 + * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  60 + * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
  61 + * should not overlap that area, or the kernel will have to copy itself
  62 + * somewhere else before decompression. Similarly, the address of any other
  63 + * data passed to the kernel shouldn't overlap the start of RAM. Pushing
  64 + * this up to 16M allows for a sizable kernel to be decompressed below the
  65 + * compressed load address.
  66 + *
  67 + * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
  68 + * the compressed kernel to be up to 16M too.
  69 + *
  70 + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
  71 + * for the FDT/DTB to be up to 1M, which is hopefully plenty.
  72 + */
  73 +#define MEM_LAYOUT_ENV_SETTINGS \
  74 + "scriptaddr=0x90000000\0" \
  75 + "kernel_addr_r=0x81000000\0" \
  76 + "fdt_addr_r=0x82000000\0" \
  77 + "ramdisk_addr_r=0x82100000\0"
  78 +
  79 +/* Defines for SPL */
  80 +#define CONFIG_SPL_TEXT_BASE 0x80108000
  81 +#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
  82 +#define CONFIG_SPL_STACK 0x800ffffc
  83 +
  84 +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra30/u-boot-spl.lds"
  85 +
  86 +#endif /* _TEGRA30_COMMON_H_ */