Eric Lee / smarc-uboot

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Commit f0a2c7b4b64eacd06bb272856bcc056be8719f5a

Authored by Ilko Iliev
Committed by Jean-Christophe PLAGNIOL-VILLARD
1 parent dc39ae9513
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

at91: add support for the PM9263 board of Ronetix GmbH 

The PM9263 board is based on the AT91SAM9263-EK board.

Here is the page on Ronetix website:
http://www.ronetix.at/starter_kit_9263.html

Signed-off-by: Ilko Iliev <iliev@ronetix.at>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Showing 20 changed files with 1397 additions and 59 deletions Side-by-side Diff

... ... @@ -204,6 +204,10 @@
204 204 KUP4K MPC855
205 205 KUP4X MPC859
206 206  
  207 +Ilko Iliev <iliev@ronetix.at>
  208 +
  209 + PM9263 AT91SAM9263
  210 +
207 211 Gary Jennejohn <garyj@denx.de>
208 212  
209 213 quad100hd PPC405EP
... ... @@ -582,6 +582,7 @@
582 582 kb9202 \
583 583 mp2usb \
584 584 m501sk \
  585 + pm9263 \
585 586 "
586 587  
587 588 #########################################################################
... ... @@ -2749,6 +2749,9 @@
2749 2749 fi;
2750 2750 @$(MKCONFIG) -a at91sam9rlek arm arm926ejs at91sam9rlek atmel at91
2751 2751  
  2752 +pm9263_config : unconfig
  2753 + @$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91
  2754 +
2752 2755 ########################################################################
2753 2756 ## ARM Integrator boards - see doc/README-integrator for more info.
2754 2757 integratorap_config \
... ... @@ -3520,6 +3523,7 @@
3520 3523 $(obj)board/armltd/{integratorap,integratorcp}/u-boot.lds \
3521 3524 $(obj)board/bf5{18f,26,27,33,38f,48,61}-ez{brd,kit}/u-boot.lds \
3522 3525 $(obj)board/bf5{33,37}-stamp/u-boot.lds \
  3526 + $(obj)cpu/arm926ejs/at91/u-boot.lds \
3523 3527 $(obj)cpu/blackfin/bootrom-asm-offsets.[chs]
3524 3528 @rm -f $(obj)include/bmp_logo.h
3525 3529 @rm -f $(obj)nand_spl/{u-boot-spl,u-boot-spl.map,System.map}
board/ronetix/pm9263/Makefile
Diff comments   View file @ f0a2c7b
  1 +#
  2 +# (C) Copyright 2003-2008
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# (C) Copyright 2008
  6 +# Stelian Pop <stelian.pop@leadtechdesign.com>
  7 +# Lead Tech Design <www.leadtechdesign.com>
  8 +# Ilko Iliev <www.ronetix.at>
  9 +#
  10 +# See file CREDITS for list of people who contributed to this
  11 +# project.
  12 +#
  13 +# This program is free software; you can redistribute it and/or
  14 +# modify it under the terms of the GNU General Public License as
  15 +# published by the Free Software Foundation; either version 2 of
  16 +# the License, or (at your option) any later version.
  17 +#
  18 +# This program is distributed in the hope that it will be useful,
  19 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21 +# GNU General Public License for more details.
  22 +#
  23 +# You should have received a copy of the GNU General Public License
  24 +# along with this program; if not, write to the Free Software
  25 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26 +# MA 02111-1307 USA
  27 +#
  28 +
  29 +include $(TOPDIR)/config.mk
  30 +
  31 +LIB = $(obj)lib$(BOARD).a
  32 +
  33 +COBJS-y += pm9263.o
  34 +COBJS-y += led.o
  35 +COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
  36 +
  37 +ifndef CONFIG_SKIP_LOWLEVEL_INIT
  38 +SOBJS-y := lowlevel_init.o
  39 +endif
  40 +
  41 +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
  42 +OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS-y))
  43 +SOBJS := $(addprefix $(obj),$(SOBJS-y))
  44 +
  45 +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
  46 + $(AR) $(ARFLAGS) $@ $(OBJS)
  47 +
  48 +clean:
  49 + rm -f $(SOBJS) $(OBJS)
  50 +
  51 +distclean: clean
  52 + rm -f $(LIB) core *.bak $(obj).depend
  53 +
  54 +#########################################################################
  55 +
  56 +# defines $(obj).depend target
  57 +include $(SRCTREE)/rules.mk
  58 +
  59 +sinclude $(obj).depend
  60 +
  61 +#########################################################################
board/ronetix/pm9263/config.mk
Diff comments   View file @ f0a2c7b
  1 +TEXT_BASE = 0x23f00000
board/ronetix/pm9263/led.c
Diff comments   View file @ f0a2c7b
  1 +/*
  2 + * (C) Copyright 2007-2008
  3 + * Stelian Pop <stelian.pop@leadtechdesign.com>
  4 + * Lead Tech Design <www.leadtechdesign.com>
  5 + * Ilko Iliev <www.ronetix.at>
  6 + *
  7 + * See file CREDITS for list of people who contributed to this
  8 + * project.
  9 + *
  10 + * This program is free software; you can redistribute it and/or
  11 + * modify it under the terms of the GNU General Public License as
  12 + * published by the Free Software Foundation; either version 2 of
  13 + * the License, or (at your option) any later version.
  14 + *
  15 + * This program is distributed in the hope that it will be useful,
  16 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18 + * GNU General Public License for more details.
  19 + *
  20 + * You should have received a copy of the GNU General Public License
  21 + * along with this program; if not, write to the Free Software
  22 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 + * MA 02111-1307 USA
  24 + */
  25 +
  26 +#include <common.h>
  27 +#include <asm/arch/at91sam9263.h>
  28 +#include <asm/arch/at91_pmc.h>
  29 +#include <asm/arch/gpio.h>
  30 +#include <asm/arch/io.h>
  31 +
  32 +void coloured_LED_init(void)
  33 +{
  34 + /* Enable clock */
  35 + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOB |
  36 + 1 << AT91SAM9263_ID_PIOCDE);
  37 +
  38 + at91_set_gpio_output(CONFIG_RED_LED, 1);
  39 + at91_set_gpio_output(CONFIG_GREEN_LED, 1);
  40 +
  41 + at91_set_gpio_value(CONFIG_RED_LED, 0);
  42 + at91_set_gpio_value(CONFIG_GREEN_LED, 1);
  43 +}
board/ronetix/pm9263/lowlevel_init.S
Diff comments   View file @ f0a2c7b
  1 +/*
  2 + * Memory Setup stuff - taken from blob memsetup.S
  3 + *
  4 + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
  5 + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
  6 + *
  7 + * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
  8 + * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  9 + *
  10 + * See file CREDITS for list of people who contributed to this
  11 + * project.
  12 + *
  13 + * This program is free software; you can redistribute it and/or
  14 + * modify it under the terms of the GNU General Public License as
  15 + * published by the Free Software Foundation; either version 2 of
  16 + * the License, or (at your option) any later version.
  17 + *
  18 + * This program is distributed in the hope that it will be useful,
  19 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21 + * GNU General Public License for more details.
  22 + *
  23 + * You should have received a copy of the GNU General Public License
  24 + * along with this program; if not, write to the Free Software
  25 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26 + * MA 02111-1307 USA
  27 + */
  28 +
  29 +#include <config.h>
  30 +#include <version.h>
  31 +#include <asm/arch/hardware.h>
  32 +#include <asm/arch/at91_pmc.h>
  33 +#include <asm/arch/at91_pio.h>
  34 +#include <asm/arch/at91_rstc.h>
  35 +#include <asm/arch/at91_wdt.h>
  36 +#include <asm/arch/at91sam9_sdramc.h>
  37 +#include <asm/arch/at91sam9_smc.h>
  38 +#include <asm/arch/at91sam9263_matrix.h>
  39 +
  40 +_TEXT_BASE:
  41 + .word TEXT_BASE
  42 +
  43 +.globl lowlevel_init
  44 +.type lowlevel_init,function
  45 +lowlevel_init:
  46 +
  47 + mov r5, pc /* r5 = POS1 + 4 current */
  48 +POS1:
  49 + ldr r0, =POS1 /* r0 = POS1 compile */
  50 + ldr r2, _TEXT_BASE
  51 + sub r0, r0, r2 /* r0 = POS1-_TEXT_BASE (POS1 relative) */
  52 + sub r5, r5, r0 /* r0 = TEXT_BASE-1 */
  53 + sub r5, r5, #4 /* r1 = text base - current */
  54 +
  55 + /* memory control configuration 1 */
  56 + ldr r0, =SMRDATA
  57 + ldr r2, =SMRDATA1
  58 + ldr r1, _TEXT_BASE
  59 + sub r0, r0, r1
  60 + sub r2, r2, r1
  61 + add r0, r0, r5
  62 + add r2, r2, r5
  63 +0:
  64 + /* the address */
  65 + ldr r1, [r0], #4
  66 + /* the value */
  67 + ldr r3, [r0], #4
  68 + str r3, [r1]
  69 + cmp r2, r0
  70 + bne 0b
  71 +
  72 +/* ----------------------------------------------------------------------------
  73 + * PMC Init Step 1.
  74 + * ----------------------------------------------------------------------------
  75 + * - Check if the PLL is already initialized
  76 + * ----------------------------------------------------------------------------
  77 + */
  78 + ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
  79 + ldr r0, [r1]
  80 + and r0, r0, #3
  81 + cmp r0, #0
  82 + bne PLL_setup_end
  83 +
  84 +/* ---------------------------------------------------------------------------
  85 + * - Enable the Main Oscillator
  86 + * ---------------------------------------------------------------------------
  87 + */
  88 + ldr r1, =(AT91_BASE_SYS + AT91_CKGR_MOR)
  89 + ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR)
  90 + ldr r0, =0x0000FF01
  91 + str r0, [r1] /* Enable main oscillator, OSCOUNT = 0xFF */
  92 +
  93 + /* Reading the PMC Status to detect when the Main Oscillator is enabled */
  94 + mov r4, #AT91_PMC_MOSCS
  95 +MOSCS_Loop:
  96 + ldr r3, [r2]
  97 + and r3, r4, r3
  98 + cmp r3, #AT91_PMC_MOSCS
  99 + bne MOSCS_Loop
  100 +
  101 +/* ----------------------------------------------------------------------------
  102 + * PMC Init Step 2.
  103 + * ----------------------------------------------------------------------------
  104 + * Setup PLLA
  105 + * ----------------------------------------------------------------------------
  106 + */
  107 + ldr r1, =(AT91_BASE_SYS + AT91_CKGR_PLLAR)
  108 + ldr r0, =CONFIG_SYS_PLLAR_VAL
  109 + str r0, [r1]
  110 +
  111 + /* Reading the PMC Status register to detect when the PLLA is locked */
  112 + mov r4, #AT91_PMC_LOCKA
  113 +MOSCS_Loop1:
  114 + ldr r3, [r2]
  115 + and r3, r4, r3
  116 + cmp r3, #AT91_PMC_LOCKA
  117 + bne MOSCS_Loop1
  118 +
  119 +/* ----------------------------------------------------------------------------
  120 + * PMC Init Step 3.
  121 + * ----------------------------------------------------------------------------
  122 + * - Switch on the Main Oscillator 18.432 MHz
  123 + * ----------------------------------------------------------------------------
  124 + */
  125 + ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
  126 +
  127 + /* -Master Clock Controller register PMC_MCKR */
  128 + ldr r0, =CONFIG_SYS_MCKR1_VAL
  129 + str r0, [r1]
  130 +
  131 + /* Reading the PMC Status to detect when the Master clock is ready */
  132 + mov r4, #AT91_PMC_MCKRDY
  133 +MCKRDY_Loop:
  134 + ldr r3, [r2]
  135 + and r3, r4, r3
  136 + cmp r3, #AT91_PMC_MCKRDY
  137 + bne MCKRDY_Loop
  138 +
  139 + ldr r0, =CONFIG_SYS_MCKR2_VAL
  140 + str r0, [r1]
  141 +
  142 + /* Reading the PMC Status to detect when the Master clock is ready */
  143 + mov r4, #AT91_PMC_MCKRDY
  144 +MCKRDY_Loop1:
  145 + ldr r3, [r2]
  146 + and r3, r4, r3
  147 + cmp r3, #AT91_PMC_MCKRDY
  148 + bne MCKRDY_Loop1
  149 +
  150 +PLL_setup_end:
  151 +
  152 +/* ----------------------------------------------------------------------------
  153 + * - memory control configuration 2
  154 + * ----------------------------------------------------------------------------
  155 + */
  156 + ldr r0, =(AT91_BASE_SYS + AT91_SDRAMC_TR)
  157 + ldr r1, [r0]
  158 + cmp r1, #0
  159 + bne SDRAM_setup_end
  160 +
  161 + ldr r0, =SMRDATA1
  162 + ldr r2, =SMRDATA2
  163 + ldr r1, _TEXT_BASE
  164 + sub r0, r0, r1
  165 + sub r2, r2, r1
  166 + add r0, r0, r5
  167 + add r2, r2, r5
  168 +
  169 +2:
  170 + /* the address */
  171 + ldr r1, [r0], #4
  172 + /* the value */
  173 + ldr r3, [r0], #4
  174 + str r3, [r1]
  175 + cmp r2, r0
  176 + bne 2b
  177 +
  178 +SDRAM_setup_end:
  179 + /* everything is fine now */
  180 + mov pc, lr
  181 +
  182 + .ltorg
  183 +
  184 +SMRDATA:
  185 + .word (AT91_BASE_SYS + AT91_WDT_MR)
  186 + .word CONFIG_SYS_WDTC_WDMR_VAL
  187 +
  188 + .word (AT91_BASE_SYS + AT91_PIOD + PIO_PDR)
  189 + .word CONFIG_SYS_PIOD_PDR_VAL1
  190 + .word (AT91_BASE_SYS + AT91_PIOD + PIO_PUDR)
  191 + .word CONFIG_SYS_PIOD_PPUDR_VAL
  192 + .word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR)
  193 + .word CONFIG_SYS_PIOD_PPUDR_VAL
  194 +
  195 + .word (AT91_BASE_SYS + AT91_MATRIX_EBI0CSA)
  196 + .word CONFIG_SYS_MATRIX_EBI0CSA_VAL
  197 + .word (AT91_BASE_SYS + AT91_MATRIX_EBI1CSA)
  198 + .word CONFIG_SYS_MATRIX_EBI1CSA_VAL
  199 +
  200 + /* flash */
  201 + .word (AT91_BASE_SYS + AT91_SMC_MODE(0))
  202 + .word CONFIG_SYS_SMC0_CTRL0_VAL
  203 +
  204 + .word (AT91_BASE_SYS + AT91_SMC_CYCLE(0))
  205 + .word CONFIG_SYS_SMC0_CYCLE0_VAL
  206 +
  207 + .word (AT91_BASE_SYS + AT91_SMC_PULSE(0))
  208 + .word CONFIG_SYS_SMC0_PULSE0_VAL
  209 +
  210 + .word (AT91_BASE_SYS + AT91_SMC_SETUP(0))
  211 + .word CONFIG_SYS_SMC0_SETUP0_VAL
  212 +
  213 + /* PSRAM */
  214 + .word (AT91_BASE_SYS + AT91_SMC1_MODE(0))
  215 + .word CONFIG_SYS_SMC1_CTRL0_VAL
  216 +
  217 + .word (AT91_BASE_SYS + AT91_SMC1_CYCLE(0))
  218 + .word CONFIG_SYS_SMC1_CYCLE0_VAL
  219 +
  220 + .word (AT91_BASE_SYS + AT91_SMC1_PULSE(0))
  221 + .word CONFIG_SYS_SMC1_PULSE0_VAL
  222 +
  223 + .word (AT91_BASE_SYS + AT91_SMC1_SETUP(0))
  224 + .word CONFIG_SYS_SMC1_SETUP0_VAL
  225 +
  226 +SMRDATA1:
  227 + .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
  228 + .word CONFIG_SYS_SDRC_MR_VAL1
  229 + .word (AT91_BASE_SYS + AT91_SDRAMC_TR)
  230 + .word CONFIG_SYS_SDRC_TR_VAL1
  231 + .word (AT91_BASE_SYS + AT91_SDRAMC_CR)
  232 + .word CONFIG_SYS_SDRC_CR_VAL
  233 + .word (AT91_BASE_SYS + AT91_SDRAMC_MDR)
  234 + .word CONFIG_SYS_SDRC_MDR_VAL
  235 + .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
  236 + .word CONFIG_SYS_SDRC_MR_VAL2
  237 + .word AT91_SDRAM_BASE
  238 + .word CONFIG_SYS_SDRAM_VAL1
  239 + .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
  240 + .word CONFIG_SYS_SDRC_MR_VAL3
  241 + .word AT91_SDRAM_BASE
  242 + .word CONFIG_SYS_SDRAM_VAL2
  243 + .word AT91_SDRAM_BASE
  244 + .word CONFIG_SYS_SDRAM_VAL3
  245 + .word AT91_SDRAM_BASE
  246 + .word CONFIG_SYS_SDRAM_VAL4
  247 + .word AT91_SDRAM_BASE
  248 + .word CONFIG_SYS_SDRAM_VAL5
  249 + .word AT91_SDRAM_BASE
  250 + .word CONFIG_SYS_SDRAM_VAL6
  251 + .word AT91_SDRAM_BASE
  252 + .word CONFIG_SYS_SDRAM_VAL7
  253 + .word AT91_SDRAM_BASE
  254 + .word CONFIG_SYS_SDRAM_VAL8
  255 + .word AT91_SDRAM_BASE
  256 + .word CONFIG_SYS_SDRAM_VAL9
  257 + .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
  258 + .word CONFIG_SYS_SDRC_MR_VAL4
  259 + .word AT91_SDRAM_BASE
  260 + .word CONFIG_SYS_SDRAM_VAL10
  261 + .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
  262 + .word CONFIG_SYS_SDRC_MR_VAL5
  263 + .word AT91_SDRAM_BASE
  264 + .word CONFIG_SYS_SDRAM_VAL11
  265 + .word (AT91_BASE_SYS + AT91_SDRAMC_TR)
  266 + .word CONFIG_SYS_SDRC_TR_VAL2
  267 + .word AT91_SDRAM_BASE
  268 + .word CONFIG_SYS_SDRAM_VAL12
  269 + /* User reset enable*/
  270 + .word (AT91_BASE_SYS + AT91_RSTC_MR)
  271 + .word CONFIG_SYS_RSTC_RMR_VAL
  272 +#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
  273 + /* MATRIX_MCFG - REMAP all masters */
  274 + .word (AT91_BASE_SYS + AT91_MATRIX_MCFG0)
  275 + .word 0x1FF
  276 +#endif
  277 +
  278 +SMRDATA2:
  279 + .word 0
board/ronetix/pm9263/partition.c
Diff comments   View file @ f0a2c7b
  1 +/*
  2 + * (C) Copyright 2008
  3 + * Ulf Samuelsson <ulf@atmel.com>
  4 + * Ilko Iliev <www.ronetix.at>
  5 + *
  6 + * This program is free software; you can redistribute it and/or
  7 + * modify it under the terms of the GNU General Public License as
  8 + * published by the Free Software Foundation; either version 2 of
  9 + * the License, or (at your option) any later version.
  10 + *
  11 + * This program is distributed in the hope that it will be useful,
  12 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14 + * GNU General Public License for more details.
  15 + *
  16 + * You should have received a copy of the GNU General Public License
  17 + * along with this program; if not, write to the Free Software
  18 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19 + * MA 02111-1307 USA
  20 + *
  21 + */
  22 +#include <common.h>
  23 +#include <config.h>
  24 +#include <asm/hardware.h>
  25 +#include <dataflash.h>
  26 +
  27 +AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
  28 +
  29 +struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
  30 + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
  31 +};
  32 +
  33 +/*define the area offsets*/
  34 +#ifdef CONFIG_SYS_USE_DATAFLASH
  35 +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
  36 + {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
  37 + {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
  38 + {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
  39 + {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
  40 + {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
  41 +};
  42 +#else
  43 +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
  44 + {0x00000000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, ""},
  45 +};
  46 +
  47 +#endif
board/ronetix/pm9263/pm9263.c
Diff comments   View file @ f0a2c7b
  1 +/*
  2 + * (C) Copyright 2007-2008
  3 + * Stelian Pop <stelian.pop@leadtechdesign.com>
  4 + * Lead Tech Design <www.leadtechdesign.com>
  5 + * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
  6 + * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  7 + *
  8 + * See file CREDITS for list of people who contributed to this
  9 + * project.
  10 + *
  11 + * This program is free software; you can redistribute it and/or
  12 + * modify it under the terms of the GNU General Public License as
  13 + * published by the Free Software Foundation; either version 2 of
  14 + * the License, or (at your option) any later version.
  15 + *
  16 + * This program is distributed in the hope that it will be useful,
  17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19 + * GNU General Public License for more details.
  20 + *
  21 + * You should have received a copy of the GNU General Public License
  22 + * along with this program; if not, write to the Free Software
  23 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 + * MA 02111-1307 USA
  25 + */
  26 +
  27 +#include <common.h>
  28 +#include <asm/sizes.h>
  29 +#include <asm/arch/at91sam9263.h>
  30 +#include <asm/arch/at91sam9263_matrix.h>
  31 +#include <asm/arch/at91sam9_smc.h>
  32 +#include <asm/arch/at91_common.h>
  33 +#include <asm/arch/at91_pmc.h>
  34 +#include <asm/arch/at91_rstc.h>
  35 +#include <asm/arch/clk.h>
  36 +#include <asm/arch/gpio.h>
  37 +#include <asm/arch/io.h>
  38 +#include <asm/arch/hardware.h>
  39 +#include <lcd.h>
  40 +#include <atmel_lcdc.h>
  41 +#include <dataflash.h>
  42 +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  43 +#include <net.h>
  44 +#endif
  45 +#include <netdev.h>
  46 +
  47 +DECLARE_GLOBAL_DATA_PTR;
  48 +
  49 +/* ------------------------------------------------------------------------- */
  50 +/*
  51 + * Miscelaneous platform dependent initialisations
  52 + */
  53 +
  54 +#ifdef CONFIG_CMD_NAND
  55 +static void pm9263_nand_hw_init(void)
  56 +{
  57 + unsigned long csa;
  58 +
  59 + /* Enable CS3 */
  60 + csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
  61 + at91_sys_write(AT91_MATRIX_EBI0CSA,
  62 + csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
  63 +
  64 + /* Configure SMC CS3 for NAND/SmartMedia */
  65 + at91_sys_write(AT91_SMC_SETUP(3),
  66 + AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(1) |
  67 + AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(1));
  68 + at91_sys_write(AT91_SMC_PULSE(3),
  69 + AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
  70 + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
  71 + at91_sys_write(AT91_SMC_CYCLE(3),
  72 + AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
  73 + at91_sys_write(AT91_SMC_MODE(3),
  74 + AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
  75 + AT91_SMC_EXNWMODE_DISABLE |
  76 +#ifdef CONFIG_SYS_NAND_DBW_16
  77 + AT91_SMC_DBW_16 |
  78 +#else /* CONFIG_SYS_NAND_DBW_8 */
  79 + AT91_SMC_DBW_8 |
  80 +#endif
  81 + AT91_SMC_TDF_(2));
  82 +
  83 + /* Configure RDY/BSY */
  84 + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  85 +
  86 + /* Enable NandFlash */
  87 + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  88 +}
  89 +#endif
  90 +
  91 +#ifdef CONFIG_MACB
  92 +static void pm9263_macb_hw_init(void)
  93 +{
  94 + /*
  95 + * PB27 enables the 50MHz oscillator for Ethernet PHY
  96 + * 1 - enable
  97 + * 0 - disable
  98 + */
  99 + at91_set_gpio_output(AT91_PIN_PB27, 1);
  100 + at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */
  101 +
  102 + /* Enable clock */
  103 + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
  104 +
  105 + /*
  106 + * Disable pull-up on:
  107 + * RXDV (PC25) => PHY normal mode (not Test mode)
  108 + * ERX0 (PE25) => PHY ADDR0
  109 + * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
  110 + *
  111 + * PHY has internal pull-down
  112 + */
  113 + writel(pin_to_mask(AT91_PIN_PC25),
  114 + pin_to_controller(AT91_PIN_PC0) + PIO_PUDR);
  115 + writel(pin_to_mask(AT91_PIN_PE25) |
  116 + pin_to_mask(AT91_PIN_PE26),
  117 + pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
  118 +
  119 +
  120 + /* Re-enable pull-up */
  121 + writel(pin_to_mask(AT91_PIN_PC25),
  122 + pin_to_controller(AT91_PIN_PC0) + PIO_PUER);
  123 + writel(pin_to_mask(AT91_PIN_PE25) |
  124 + pin_to_mask(AT91_PIN_PE26),
  125 + pin_to_controller(AT91_PIN_PE0) + PIO_PUER);
  126 +
  127 + at91_macb_hw_init();
  128 +}
  129 +#endif
  130 +
  131 +#ifdef CONFIG_LCD
  132 +vidinfo_t panel_info = {
  133 + vl_col: 240,
  134 + vl_row: 320,
  135 + vl_clk: 4965000,
  136 + vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
  137 + ATMEL_LCDC_INVFRAME_INVERTED,
  138 + vl_bpix: 3,
  139 + vl_tft: 1,
  140 + vl_hsync_len: 5,
  141 + vl_left_margin: 1,
  142 + vl_right_margin:33,
  143 + vl_vsync_len: 1,
  144 + vl_upper_margin:1,
  145 + vl_lower_margin:0,
  146 + mmio: AT91SAM9263_LCDC_BASE,
  147 +};
  148 +
  149 +void lcd_enable(void)
  150 +{
  151 + at91_set_gpio_value(AT91_PIN_PA22, 1); /* power up */
  152 +}
  153 +
  154 +void lcd_disable(void)
  155 +{
  156 + at91_set_gpio_value(AT91_PIN_PA22, 0); /* power down */
  157 +}
  158 +
  159 +#ifdef CONFIG_LCD_IN_PSRAM
  160 +
  161 +#define PSRAM_CRE_PIN AT91_PIN_PB29
  162 +#define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)
  163 +
  164 +/* Initialize the PSRAM memory */
  165 +static int pm9263_lcd_hw_psram_init(void)
  166 +{
  167 + volatile uint16_t x;
  168 +
  169 + /* setup PB29 as output */
  170 + at91_set_gpio_output(PSRAM_CRE_PIN, 1);
  171 +
  172 + at91_set_gpio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */
  173 +
  174 + /* PSRAM: write BCR */
  175 + x = readw(PSRAM_CTRL_REG);
  176 + x = readw(PSRAM_CTRL_REG);
  177 + writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
  178 + writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */
  179 +
  180 + /* write RCR of the PSRAM */
  181 + x = readw(PSRAM_CTRL_REG);
  182 + x = readw(PSRAM_CTRL_REG);
  183 + writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
  184 + /* set RCR; 0x10-async mode,0x90-page mode */
  185 + writew(0x90, PSRAM_CTRL_REG);
  186 +
  187 + /*
  188 + * test to see if the PSRAM is MT45W2M16A or MT45W2M16B
  189 + * MT45W2M16B - CRE must be 0
  190 + * MT45W2M16A - CRE must be 1
  191 + */
  192 + writew(0x1234, PHYS_PSRAM);
  193 + writew(0x5678, PHYS_PSRAM + 2);
  194 +
  195 + /* test if the chip is MT45W2M16B */
  196 + if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) {
  197 + /* try with CRE=1 (MT45W2M16A) */
  198 + at91_set_gpio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
  199 +
  200 + /* write RCR of the PSRAM */
  201 + x = readw(PSRAM_CTRL_REG);
  202 + x = readw(PSRAM_CTRL_REG);
  203 + writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
  204 + /* set RCR;0x10-async mode,0x90-page mode */
  205 + writew(0x90, PSRAM_CTRL_REG);
  206 +
  207 +
  208 + writew(0x1234, PHYS_PSRAM);
  209 + writew(0x5678, PHYS_PSRAM+2);
  210 + if ((readw(PHYS_PSRAM) != 0x1234)
  211 + || (readw(PHYS_PSRAM + 2) != 0x5678))
  212 + return 1;
  213 +
  214 + }
  215 +
  216 + /* Bus matrix */
  217 + at91_sys_write( AT91_MATRIX_PRAS5, AT91_MATRIX_M5PR );
  218 + at91_sys_write( AT91_MATRIX_SCFG5, AT91_MATRIX_ARBT_FIXED_PRIORITY |
  219 + (AT91_MATRIX_FIXED_DEFMSTR & (5 << 18)) |
  220 + AT91_MATRIX_DEFMSTR_TYPE_FIXED |
  221 + (AT91_MATRIX_SLOT_CYCLE & (0x80 << 0)));
  222 +
  223 + return 0;
  224 +}
  225 +#endif
  226 +
  227 +static void pm9263_lcd_hw_init(void)
  228 +{
  229 + at91_set_A_periph(AT91_PIN_PC0, 0); /* LCDVSYNC */
  230 + at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
  231 + at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
  232 + at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
  233 + at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
  234 + at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
  235 + at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
  236 + at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
  237 + at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
  238 + at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
  239 + at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
  240 + at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
  241 + at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
  242 + at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
  243 + at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
  244 + at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
  245 + at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
  246 + at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
  247 + at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
  248 + at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
  249 + at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */
  250 + at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
  251 + at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
  252 +
  253 + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
  254 +
  255 + /* Power Control */
  256 + at91_set_gpio_output(AT91_PIN_PA22, 1);
  257 + at91_set_gpio_value(AT91_PIN_PA22, 0); /* power down */
  258 +
  259 +#ifdef CONFIG_LCD_IN_PSRAM
  260 + /* initialize te PSRAM */
  261 + int stat = pm9263_lcd_hw_psram_init();
  262 +
  263 + gd->fb_base = (stat == 0) ? PHYS_PSRAM : AT91SAM9263_SRAM0_BASE;
  264 +#else
  265 + gd->fb_base = AT91SAM9263_SRAM0_BASE;
  266 +#endif
  267 +
  268 +}
  269 +
  270 +#ifdef CONFIG_LCD_INFO
  271 +#include <nand.h>
  272 +#include <version.h>
  273 +
  274 +extern flash_info_t flash_info[];
  275 +
  276 +void lcd_show_board_info(void)
  277 +{
  278 + ulong dram_size, nand_size, flash_size, dataflash_size;
  279 + int i;
  280 + char temp[32];
  281 +
  282 + lcd_printf ("%s\n", U_BOOT_VERSION);
  283 + lcd_printf ("(C) 2009 Ronetix GmbH\n");
  284 + lcd_printf ("support@ronetix.at\n");
  285 + lcd_printf ("%s CPU at %s MHz",
  286 + AT91_CPU_NAME,
  287 + strmhz(temp, get_cpu_clk_rate()));
  288 +
  289 + dram_size = 0;
  290 + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
  291 + dram_size += gd->bd->bi_dram[i].size;
  292 +
  293 + nand_size = 0;
  294 + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
  295 + nand_size += nand_info[i].size;
  296 +
  297 + flash_size = 0;
  298 + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
  299 + flash_size += flash_info[i].size;
  300 +
  301 + dataflash_size = 0;
  302 + for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
  303 + dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
  304 + dataflash_info[i].Device.pages_size;
  305 +
  306 + lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
  307 + "4 MB PSRAM, %ld MB DataFlash\n",
  308 + dram_size >> 20,
  309 + nand_size >> 20,
  310 + flash_size >> 20,
  311 + dataflash_size >> 20);
  312 +}
  313 +#endif /* CONFIG_LCD_INFO */
  314 +
  315 +#endif /* CONFIG_LCD */
  316 +
  317 +int board_init(void)
  318 +{
  319 + /* Enable Ctrlc */
  320 + console_init_f();
  321 +
  322 + at91_sys_write(AT91_PMC_PCER,
  323 + (1 << AT91SAM9263_ID_PIOA) |
  324 + (1 << AT91SAM9263_ID_PIOCDE) |
  325 + (1 << AT91SAM9263_ID_PIOB));
  326 +
  327 + /* arch number of AT91SAM9263EK-Board */
  328 + gd->bd->bi_arch_number = MACH_TYPE_PM9263;
  329 +
  330 + /* adress of boot parameters */
  331 + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  332 +
  333 + at91_serial_hw_init();
  334 +#ifdef CONFIG_CMD_NAND
  335 + pm9263_nand_hw_init();
  336 +#endif
  337 +#ifdef CONFIG_HAS_DATAFLASH
  338 + at91_spi0_hw_init(1 << 0);
  339 +#endif
  340 +#ifdef CONFIG_MACB
  341 + pm9263_macb_hw_init();
  342 +#endif
  343 +#ifdef CONFIG_USB_OHCI_NEW
  344 + at91_uhp_hw_init();
  345 +#endif
  346 +#ifdef CONFIG_LCD
  347 + pm9263_lcd_hw_init();
  348 +#endif
  349 + return 0;
  350 +}
  351 +
  352 +int dram_init(void)
  353 +{
  354 + gd->bd->bi_dram[0].start = PHYS_SDRAM;
  355 + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
  356 + return 0;
  357 +}
  358 +
  359 +#ifdef CONFIG_RESET_PHY_R
  360 +void reset_phy(void)
  361 +{
  362 +#ifdef CONFIG_MACB
  363 + /*
  364 + * Initialize ethernet HW addr prior to starting Linux,
  365 + * needed for nfsroot
  366 + */
  367 + eth_init(gd->bd);
  368 +#endif
  369 +}
  370 +#endif
  371 +
  372 +int board_eth_init(bd_t *bis)
  373 +{
  374 + int rc = 0;
  375 +#ifdef CONFIG_MACB
  376 + rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x01);
  377 +#endif
  378 + return rc;
  379 +}
  380 +
  381 +#ifdef CONFIG_DISPLAY_BOARDINFO
  382 +int checkboard (void)
  383 +{
  384 + char *ss;
  385 + char buf[32];
  386 +
  387 + printf ("Board : Ronetix PM9263\n");
  388 + printf ("Crystal frequency: %8s MHz\n",
  389 + strmhz(buf, get_main_clk_rate()));
  390 + printf ("CPU clock : %8s MHz\n",
  391 + strmhz(buf, get_cpu_clk_rate()));
  392 + printf ("Master clock : %8s MHz\n",
  393 + strmhz(buf, get_mck_clk_rate()));
  394 +
  395 + switch (gd->fb_base) {
  396 + case PHYS_PSRAM:
  397 + ss = "(PSRAM)";
  398 + break;
  399 +
  400 + case AT91SAM9263_SRAM0_BASE:
  401 + ss = "(Internal SRAM)";
  402 + break;
  403 +
  404 + default:
  405 + ss = "";
  406 + break;
  407 + }
  408 + printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss );
  409 +
  410 + printf ("\n");
  411 + return 0;
  412 +}
  413 +#endif
cpu/arm926ejs/at91/Makefile
Diff comments   View file @ f0a2c7b
... ... @@ -63,10 +63,13 @@
63 63 SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
64 64 OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
65 65  
66   -all: $(obj).depend $(LIB)
  66 +all: $(obj).depend $(LIB) $(obj)u-boot.lds
67 67  
68 68 $(LIB): $(OBJS)
69 69 $(AR) $(ARFLAGS) $@ $(OBJS)
  70 +
  71 +$(obj)u-boot.lds: u-boot.lds.S
  72 + $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -DCONFIG_BOARDDIR=$(BOARDDIR) -P $^ > $@
70 73  
71 74 #########################################################################
72 75  
cpu/arm926ejs/at91/config.mk
Diff comments   View file @ f0a2c7b
1 1 PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,)
2   -LDSCRIPT := $(SRCTREE)/cpu/arm926ejs/at91/u-boot.lds
  2 +LDSCRIPT := $(OBJTREE)/cpu/arm926ejs/at91/u-boot.lds
cpu/arm926ejs/at91/lowlevel_init.S
Diff comments   View file @ f0a2c7b
... ... @@ -30,6 +30,8 @@
30 30 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
31 31  
32 32 .globl lowlevel_init
  33 +.weak lowlevel_init
  34 +.set lowlevel_init,function
33 35 lowlevel_init:
34 36  
35 37 /*
cpu/arm926ejs/at91/u-boot.lds
View file @ f0a2c7b
1   -/*
2   - * (C) Copyright 2002
3   - * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
4   - *
5   - * See file CREDITS for list of people who contributed to this
6   - * project.
7   - *
8   - * This program is free software; you can redistribute it and/or
9   - * modify it under the terms of the GNU General Public License as
10   - * published by the Free Software Foundation; either version 2 of
11   - * the License, or (at your option) any later version.
12   - *
13   - * This program is distributed in the hope that it will be useful,
14   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   - * GNU General Public License for more details.
17   - *
18   - * You should have received a copy of the GNU General Public License
19   - * along with this program; if not, write to the Free Software
20   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   - * MA 02111-1307 USA
22   - */
23   -
24   -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
25   -/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
26   -OUTPUT_ARCH(arm)
27   -ENTRY(_start)
28   -SECTIONS
29   -{
30   - . = 0x00000000;
31   -
32   - . = ALIGN(4);
33   - .text :
34   - {
35   - cpu/arm926ejs/start.o (.text)
36   - *(.text)
37   - }
38   -
39   - . = ALIGN(4);
40   - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
41   -
42   - . = ALIGN(4);
43   - .data : { *(.data) }
44   -
45   - . = ALIGN(4);
46   - .got : { *(.got) }
47   -
48   - . = .;
49   - __u_boot_cmd_start = .;
50   - .u_boot_cmd : { *(.u_boot_cmd) }
51   - __u_boot_cmd_end = .;
52   -
53   - . = ALIGN(4);
54   - __bss_start = .;
55   - .bss : { *(.bss) . = ALIGN(4); }
56   - _end = .;
57   -}
cpu/arm926ejs/at91/u-boot.lds.S
Diff comments   View file @ f0a2c7b
  1 +/*
  2 + * (C) Copyright 2002
  3 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include <config.h>
  25 +
  26 +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
  27 +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
  28 +OUTPUT_ARCH(arm)
  29 +ENTRY(_start)
  30 +SECTIONS
  31 +{
  32 + . = 0x00000000;
  33 +
  34 + . = ALIGN(4);
  35 + .text :
  36 + {
  37 + cpu/arm926ejs/start.o (.text)
  38 +#ifndef CONFIG_SKIP_LOWLEVEL_INIT
  39 + board/CONFIG_BOARDDIR/lowlevel_init.o (.text)
  40 +#endif
  41 + *(.text)
  42 + }
  43 +
  44 + . = ALIGN(4);
  45 + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
  46 +
  47 + . = ALIGN(4);
  48 + .data : { *(.data) }
  49 +
  50 + . = ALIGN(4);
  51 + .got : { *(.got) }
  52 +
  53 + . = .;
  54 + __u_boot_cmd_start = .;
  55 + .u_boot_cmd : { *(.u_boot_cmd) }
  56 + __u_boot_cmd_end = .;
  57 +
  58 + . = ALIGN(4);
  59 + __bss_start = .;
  60 + .bss : { *(.bss) . = ALIGN(4); }
  61 + _end = .;
  62 +}
include/asm-arm/arch-at91/at91sam9263.h
Diff comments   View file @ f0a2c7b
... ... @@ -106,6 +106,7 @@
106 106 #define AT91_USART2 AT91SAM9263_BASE_US2
107 107  
108 108 #define AT91_SMC AT91_SMC0
  109 +#define AT91_SDRAMC AT91_SDRAMC0
109 110  
110 111 /*
111 112 * Internal Memory.
include/asm-arm/arch-at91/at91sam9_sdramc.h
Diff comments   View file @ f0a2c7b
  1 +/*
  2 + * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h]
  3 + *
  4 + * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  5 + * Copyright (C) 2007 Andrew Victor
  6 + * Copyright (C) 2007 Atmel Corporation.
  7 + *
  8 + * SDRAM Controllers (SDRAMC) - System peripherals registers.
  9 + * Based on AT91SAM9261 datasheet revision D.
  10 + *
  11 + * This program is free software; you can redistribute it and/or modify
  12 + * it under the terms of the GNU General Public License as published by
  13 + * the Free Software Foundation; either version 2 of the License, or
  14 + * (at your option) any later version.
  15 + */
  16 +
  17 +#ifndef AT91SAM9_SDRAMC_H
  18 +#define AT91SAM9_SDRAMC_H
  19 +
  20 +/* SDRAM Controller (SDRAMC) registers */
  21 +#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */
  22 +#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
  23 +#define AT91_SDRAMC_MODE_NORMAL 0
  24 +#define AT91_SDRAMC_MODE_NOP 1
  25 +#define AT91_SDRAMC_MODE_PRECHARGE 2
  26 +#define AT91_SDRAMC_MODE_LMR 3
  27 +#define AT91_SDRAMC_MODE_REFRESH 4
  28 +#define AT91_SDRAMC_MODE_EXT_LMR 5
  29 +#define AT91_SDRAMC_MODE_DEEP 6
  30 +
  31 +#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */
  32 +#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
  33 +
  34 +#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */
  35 +#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
  36 +#define AT91_SDRAMC_NC_8 (0 << 0)
  37 +#define AT91_SDRAMC_NC_9 (1 << 0)
  38 +#define AT91_SDRAMC_NC_10 (2 << 0)
  39 +#define AT91_SDRAMC_NC_11 (3 << 0)
  40 +#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
  41 +#define AT91_SDRAMC_NR_11 (0 << 2)
  42 +#define AT91_SDRAMC_NR_12 (1 << 2)
  43 +#define AT91_SDRAMC_NR_13 (2 << 2)
  44 +#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
  45 +#define AT91_SDRAMC_NB_2 (0 << 4)
  46 +#define AT91_SDRAMC_NB_4 (1 << 4)
  47 +#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
  48 +#define AT91_SDRAMC_CAS_1 (1 << 5)
  49 +#define AT91_SDRAMC_CAS_2 (2 << 5)
  50 +#define AT91_SDRAMC_CAS_3 (3 << 5)
  51 +#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */
  52 +#define AT91_SDRAMC_DBW_32 (0 << 7)
  53 +#define AT91_SDRAMC_DBW_16 (1 << 7)
  54 +#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */
  55 +#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */
  56 +#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */
  57 +#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */
  58 +#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
  59 +#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
  60 +
  61 +#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */
  62 +#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
  63 +#define AT91_SDRAMC_LPCB_DISABLE 0
  64 +#define AT91_SDRAMC_LPCB_SELF_REFRESH 1
  65 +#define AT91_SDRAMC_LPCB_POWER_DOWN 2
  66 +#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
  67 +#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
  68 +#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
  69 +#define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */
  70 +#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
  71 +#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12)
  72 +#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
  73 +#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
  74 +
  75 +#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */
  76 +#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */
  77 +#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */
  78 +#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */
  79 +#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
  80 +
  81 +#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */
  82 +#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
  83 +#define AT91_SDRAMC_MD_SDRAM 0
  84 +#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
  85 +
  86 +
  87 +#endif
include/asm-arm/arch-at91/hardware.h
Diff comments   View file @ f0a2c7b
... ... @@ -48,6 +48,23 @@
48 48 #error "Unsupported AT91 processor"
49 49 #endif
50 50  
  51 +/* External Memory Map */
  52 +#define AT91_CHIPSELECT_0 0x10000000
  53 +#define AT91_CHIPSELECT_1 0x20000000
  54 +#define AT91_CHIPSELECT_2 0x30000000
  55 +#define AT91_CHIPSELECT_3 0x40000000
  56 +#define AT91_CHIPSELECT_4 0x50000000
  57 +#define AT91_CHIPSELECT_5 0x60000000
  58 +#define AT91_CHIPSELECT_6 0x70000000
  59 +#define AT91_CHIPSELECT_7 0x80000000
  60 +
  61 +/* SDRAM */
  62 +#ifdef CONFIG_DRAM_BASE
  63 +#define AT91_SDRAM_BASE CONFIG_DRAM_BASE
  64 +#else
  65 +#define AT91_SDRAM_BASE AT91_CHIPSELECT_1
  66 +#endif
  67 +
51 68 /* Clocks */
52 69 #define AT91_SLOW_CLOCK 32768 /* slow clock */
53 70  
include/configs/pm9263.h
Diff comments   View file @ f0a2c7b
  1 +/*
  2 + * (C) Copyright 2007-2008
  3 + * Stelian Pop <stelian.pop@leadtechdesign.com>
  4 + * Lead Tech Design <www.leadtechdesign.com>
  5 + * Ilko Iliev <www.ronetix.at>
  6 + *
  7 + * Configuation settings for the RONETIX PM9263 board.
  8 + *
  9 + * See file CREDITS for list of people who contributed to this
  10 + * project.
  11 + *
  12 + * This program is free software; you can redistribute it and/or
  13 + * modify it under the terms of the GNU General Public License as
  14 + * published by the Free Software Foundation; either version 2 of
  15 + * the License, or (at your option) any later version.
  16 + *
  17 + * This program is distributed in the hope that it will be useful,
  18 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20 + * GNU General Public License for more details.
  21 + *
  22 + * You should have received a copy of the GNU General Public License
  23 + * along with this program; if not, write to the Free Software
  24 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25 + * MA 02111-1307 USA
  26 + */
  27 +
  28 +#ifndef __CONFIG_H
  29 +#define __CONFIG_H
  30 +
  31 +/* ARM asynchronous clock */
  32 +#define AT91_CPU_NAME "AT91SAM9263"
  33 +
  34 +#define CONFIG_DISPLAY_BOARDINFO
  35 +
  36 +#define MASTER_PLL_DIV 15
  37 +#define MASTER_PLL_MUL 162
  38 +#define MAIN_PLL_DIV 2 /* 2 or 4 */
  39 +#define AT91_MAIN_CLOCK 18432000
  40 +
  41 +#define CONFIG_SYS_HZ 1000000
  42 +
  43 +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
  44 +#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/
  45 +#define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */
  46 +#define CONFIG_ARCH_CPU_INIT
  47 +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
  48 +
  49 +/* clocks */
  50 +#define CONFIG_SYS_MOR_VAL 0x00002001 /* CKGR_MOR - enable main osc. */
  51 +#define CONFIG_SYS_PLLAR_VAL \
  52 + (0x2000BF00 | ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
  53 +
  54 +#if (MAIN_PLL_DIV == 2)
  55 +/* PCK/2 = MCK Master Clock from PLLA */
  56 +#define CONFIG_SYS_MCKR1_VAL 0x00000100
  57 +/* PCK/2 = MCK Master Clock from PLLA */
  58 +#define CONFIG_SYS_MCKR2_VAL 0x00000102
  59 +#else
  60 +/* PCK/4 = MCK Master Clock from PLLA */
  61 +#define CONFIG_SYS_MCKR1_VAL 0x00000200
  62 +/* PCK/4 = MCK Master Clock from PLLA */
  63 +#define CONFIG_SYS_MCKR2_VAL 0x00000202
  64 +#endif
  65 +/* define PDC[31:16] as DATA[31:16] */
  66 +#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
  67 +/* no pull-up for D[31:16] */
  68 +#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
  69 +/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
  70 +#define CONFIG_SYS_MATRIX_EBI0CSA_VAL 0x0001010A
  71 +/* EBI1_CSA, 3.3v, no pull-ups */
  72 +#define CONFIG_SYS_MATRIX_EBI1CSA_VAL 0x00010100
  73 +
  74 +/* SDRAM */
  75 +/* SDRAMC_MR Mode register */
  76 +#define CONFIG_SYS_SDRC_MR_VAL1 0
  77 +/* SDRAMC_TR - Refresh Timer register */
  78 +#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
  79 +#define CONFIG_SYS_SDRC_CR_VAL 0x85227279 /*CL3*/
  80 +/* Memory Device Register -> SDRAM */
  81 +#define CONFIG_SYS_SDRC_MDR_VAL 0
  82 +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000002 /* SDRAMC_MR */
  83 +#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
  84 +#define CONFIG_SYS_SDRC_MR_VAL3 4 /* SDRC_MR */
  85 +#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
  86 +#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
  87 +#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
  88 +#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
  89 +#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
  90 +#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
  91 +#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
  92 +#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
  93 +#define CONFIG_SYS_SDRC_MR_VAL4 3 /* SDRC_MR */
  94 +#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
  95 +#define CONFIG_SYS_SDRC_MR_VAL5 0 /* SDRC_MR */
  96 +#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
  97 +#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
  98 +#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
  99 +
  100 +/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
  101 +#define CONFIG_SYS_SMC0_SETUP0_VAL 0x0A0A0A0A /* SMC_SETUP */
  102 +#define CONFIG_SYS_SMC0_PULSE0_VAL 0x0B0B0B0B /* SMC_PULSE */
  103 +#define CONFIG_SYS_SMC0_CYCLE0_VAL 0x00160016 /* SMC_CYCLE */
  104 +#define CONFIG_SYS_SMC0_CTRL0_VAL 0x00161003 /* SMC_MODE */
  105 +
  106 +/* setup SMC1, CS0 (PSRAM) - 16-bit */
  107 +#define CONFIG_SYS_SMC1_SETUP0_VAL 0x00000000 /* SMC_SETUP */
  108 +#define CONFIG_SYS_SMC1_PULSE0_VAL 0x07020707 /* SMC_PULSE */
  109 +#define CONFIG_SYS_SMC1_CYCLE0_VAL 0x00080008 /* SMC_CYCLE */
  110 +#define CONFIG_SYS_SMC1_CTRL0_VAL 0x31001000 /* SMC_MODE */
  111 +
  112 +#define CONFIG_SYS_RSTC_RMR_VAL 0xA5000301 /* user reset enable */
  113 +
  114 +/* Watchdog */
  115 +#define CONFIG_SYS_WDTC_WDMR_VAL 0x3fff8fff /* disable watchdog */
  116 +
  117 +/* */
  118 +
  119 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
  120 +#define CONFIG_SETUP_MEMORY_TAGS 1
  121 +#define CONFIG_INITRD_TAG 1
  122 +
  123 +#undef CONFIG_SKIP_LOWLEVEL_INIT
  124 +#undef CONFIG_SKIP_RELOCATE_UBOOT
  125 +#define CONFIG_USER_LOWLEVEL_INIT 1
  126 +
  127 +/*
  128 + * Hardware drivers
  129 + */
  130 +#define CONFIG_ATMEL_USART 1
  131 +#undef CONFIG_USART0
  132 +#undef CONFIG_USART1
  133 +#undef CONFIG_USART2
  134 +#define CONFIG_USART3 1 /* USART 3 is DBGU */
  135 +
  136 +/* LCD */
  137 +#define CONFIG_LCD 1
  138 +#define LCD_BPP LCD_COLOR8
  139 +#define CONFIG_LCD_LOGO 1
  140 +#undef LCD_TEST_PATTERN
  141 +#define CONFIG_LCD_INFO 1
  142 +#define CONFIG_LCD_INFO_BELOW_LOGO 1
  143 +#define CONFIG_SYS_WHITE_ON_BLACK 1
  144 +#define CONFIG_ATMEL_LCD 1
  145 +#define CONFIG_ATMEL_LCD_BGR555 1
  146 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
  147 +
  148 +#define CONFIG_LCD_IN_PSRAM 1
  149 +
  150 +/* LED */
  151 +#define CONFIG_AT91_LED
  152 +#define CONFIG_RED_LED AT91_PIN_PB7 /* this is the power led */
  153 +#define CONFIG_GREEN_LED AT91_PIN_PB8 /* this is the user1 led */
  154 +
  155 +#define CONFIG_BOOTDELAY 3
  156 +
  157 +/*
  158 + * BOOTP options
  159 + */
  160 +#define CONFIG_BOOTP_BOOTFILESIZE 1
  161 +#define CONFIG_BOOTP_BOOTPATH 1
  162 +#define CONFIG_BOOTP_GATEWAY 1
  163 +#define CONFIG_BOOTP_HOSTNAME 1
  164 +
  165 +/*
  166 + * Command line configuration.
  167 + */
  168 +#include <config_cmd_default.h>
  169 +#undef CONFIG_CMD_BDI
  170 +#undef CONFIG_CMD_IMI
  171 +#undef CONFIG_CMD_AUTOSCRIPT
  172 +#undef CONFIG_CMD_FPGA
  173 +#undef CONFIG_CMD_LOADS
  174 +#undef CONFIG_CMD_IMLS
  175 +
  176 +#define CONFIG_CMD_PING 1
  177 +#define CONFIG_CMD_DHCP 1
  178 +#define CONFIG_CMD_NAND 1
  179 +#define CONFIG_CMD_USB 1
  180 +
  181 +/* SDRAM */
  182 +#define CONFIG_NR_DRAM_BANKS 1
  183 +#define PHYS_SDRAM 0x20000000
  184 +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
  185 +
  186 +/* DataFlash */
  187 +#define CONFIG_ATMEL_DATAFLASH_SPI
  188 +#define CONFIG_HAS_DATAFLASH 1
  189 +#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
  190 +#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
  191 +#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
  192 +#define AT91_SPI_CLK 15000000
  193 +#define DATAFLASH_TCSS (0x1a << 16)
  194 +#define DATAFLASH_TCHS (0x1 << 24)
  195 +
  196 +/* NOR flash, if populated */
  197 +#define CONFIG_SYS_FLASH_CFI 1
  198 +#define CONFIG_FLASH_CFI_DRIVER 1
  199 +#define PHYS_FLASH_1 0x10000000
  200 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
  201 +#define CONFIG_SYS_MAX_FLASH_SECT 256
  202 +#define CONFIG_SYS_MAX_FLASH_BANKS 1
  203 +
  204 +/* NAND flash */
  205 +#ifdef CONFIG_CMD_NAND
  206 +#define CONFIG_NAND_ATMEL
  207 +#define CONFIG_SYS_NAND_MAX_CHIPS 1
  208 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
  209 +#define CONFIG_SYS_NAND_BASE 0x40000000
  210 +#define CONFIG_SYS_NAND_DBW_8 1
  211 +/* our ALE is AD21 */
  212 +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
  213 +/* our CLE is AD22 */
  214 +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
  215 +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
  216 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PB30
  217 +#endif
  218 +
  219 +#define CONFIG_CMD_JFFS2 1
  220 +#define CONFIG_JFFS2_CMDLINE 1
  221 +#define CONFIG_JFFS2_NAND 1
  222 +#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
  223 +#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
  224 +#define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/
  225 +
  226 +/* PSRAM */
  227 +#define PHYS_PSRAM 0x70000000
  228 +#define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */
  229 +
  230 +/* Ethernet */
  231 +#define CONFIG_MACB 1
  232 +#define CONFIG_RMII 1
  233 +#define CONFIG_NET_MULTI 1
  234 +#define CONFIG_NET_RETRY_COUNT 20
  235 +#define CONFIG_RESET_PHY_R 1
  236 +
  237 +/* USB */
  238 +#define CONFIG_USB_ATMEL
  239 +#define CONFIG_USB_OHCI_NEW 1
  240 +#define CONFIG_DOS_PARTITION 1
  241 +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
  242 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
  243 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
  244 +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
  245 +#define CONFIG_USB_STORAGE 1
  246 +
  247 +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
  248 +
  249 +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
  250 +#define CONFIG_SYS_MEMTEST_END 0x23e00000
  251 +
  252 +#define CONFIG_SYS_USE_FLASH 1
  253 +#undef CONFIG_SYS_USE_DATAFLASH
  254 +#undef CONFIG_SYS_USE_NANDFLASH
  255 +
  256 +#ifdef CONFIG_SYS_USE_DATAFLASH
  257 +
  258 +/* bootstrap + u-boot + env + linux in dataflash on CS0 */
  259 +#define CONFIG_ENV_IS_IN_DATAFLASH
  260 +#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
  261 +#define CONFIG_ENV_OFFSET 0x4200
  262 +#define CONFIG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
  263 +#define CONFIG_ENV_SIZE 0x4200
  264 +#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
  265 +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
  266 + "root=/dev/mtdblock0 " \
  267 + "mtdparts=at91_nand:-(root) "\
  268 + "rw rootfstype=jffs2"
  269 +
  270 +#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */
  271 +
  272 +/* bootstrap + u-boot + env + linux in nandflash */
  273 +#define CONFIG_ENV_IS_IN_NAND
  274 +#define CONFIG_ENV_OFFSET 0x60000
  275 +#define CONFIG_ENV_OFFSET_REDUND 0x80000
  276 +#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
  277 +#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
  278 +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
  279 + "root=/dev/mtdblock5 " \
  280 + "mtdparts=at91_nand:" \
  281 + "128k(bootstrap)ro," \
  282 + "256k(uboot)ro," \
  283 + "128k(env1)ro," \
  284 + "128k(env2)ro," \
  285 + "2M(linux)," \
  286 + "-(root) " \
  287 + "rw rootfstype=jffs2"
  288 +
  289 +#elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */
  290 +
  291 +#define CONFIG_ENV_IS_IN_FLASH 1
  292 +#define CONFIG_ENV_OFFSET 0x40000
  293 +#define CONFIG_ENV_SECT_SIZE 0x10000
  294 +#define CONFIG_ENV_SIZE 0x10000
  295 +#define CONFIG_ENV_OVERWRITE 1
  296 +
  297 +/* JFFS Partition offset set */
  298 +#define CONFIG_SYS_JFFS2_FIRST_BANK 0
  299 +#define CONFIG_SYS_JFFS2_NUM_BANKS 1
  300 +
  301 +/* 512k reserved for u-boot */
  302 +#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
  303 +
  304 +#define CONFIG_BOOTCOMMAND "run flashboot"
  305 +#define CONFIG_ROOTPATH /ronetix/rootfs
  306 +#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
  307 +
  308 +#define CONFIG_CON_ROT "fbcon=rotate:3 "
  309 +#define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 "\
  310 + CONFIG_CON_ROT
  311 +
  312 +#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand"
  313 +#define MTDPARTS_DEFAULT \
  314 + "mtdparts=physmap-flash.0:" \
  315 + "256k(u-boot)ro," \
  316 + "64k(u-boot-env)ro," \
  317 + "1408k(kernel)," \
  318 + "-(rootfs);" \
  319 + "nand:-(nand)"
  320 +
  321 +#define CONFIG_EXTRA_ENV_SETTINGS \
  322 + "mtdids=" MTDIDS_DEFAULT "\0" \
  323 + "mtdparts=" MTDPARTS_DEFAULT "\0" \
  324 + "partition=nand0,0\0" \
  325 + "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
  326 + "nfsargs=setenv bootargs root=/dev/nfs rw " \
  327 + CONFIG_CON_ROT \
  328 + "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
  329 + "addip=setenv bootargs $(bootargs) " \
  330 + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
  331 + ":$(hostname):eth0:off\0" \
  332 + "ramboot=tftpboot 0x22000000 vmImage;" \
  333 + "run ramargs;run addip;bootm 22000000\0" \
  334 + "nfsboot=tftpboot 0x22000000 vmImage;" \
  335 + "run nfsargs;run addip;bootm 22000000\0" \
  336 + "flashboot=run ramargs;run addip;bootm 0x10050000\0" \
  337 + ""
  338 +
  339 +#else
  340 +#error "Undefined memory device"
  341 +#endif
  342 +
  343 +#define CONFIG_BAUDRATE 115200
  344 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
  345 +
  346 +#define CONFIG_SYS_PROMPT "u-boot-pm9263> "
  347 +#define CONFIG_SYS_CBSIZE 256
  348 +#define CONFIG_SYS_MAXARGS 16
  349 +#define CONFIG_SYS_PBSIZE \
  350 + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  351 +#define CONFIG_SYS_LONGHELP 1
  352 +#define CONFIG_CMDLINE_EDITING 1
  353 +
  354 +#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
  355 +/*
  356 + * Size of malloc() pool
  357 + */
  358 +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
  359 +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
  360 +
  361 +#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
  362 +
  363 +#ifdef CONFIG_USE_IRQ
  364 +#error CONFIG_USE_IRQ not supported
  365 +#endif
  366 +
  367 +#endif
... ... @@ -122,6 +122,9 @@
122 122 ifeq ($(VENDOR),atmel)
123 123 LOGO_BMP= logos/atmel.bmp
124 124 endif
  125 +ifeq ($(VENDOR),ronetix)
  126 +LOGO_BMP= logos/ronetix.bmp
  127 +endif
125 128  
126 129 # now $(obj) is defined
127 130 SRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c))
tools/logos/ronetix.bmp
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