Eric Lee / smarc-uboot

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Commit f12e568ca45f6c56b5a6d52a43524987e141abe7

Authored by wdenk
1 parent 0d4983930a
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

* Add support for NSCU board 

* Add support for TQM823M, TQM850M, TQM855M and TQM860M modules

* Add support for Am29LV160ML, Am29LV320ML, and Am29LV640ML
  mirror bit flash on TQM8xxM modules

Showing 18 changed files with 2456 additions and 41 deletions Side-by-side Diff

... ... @@ -2,6 +2,13 @@
2 2 Changes for U-Boot 0.4.2:
3 3 ======================================================================
4 4  
  5 +* Add support for NSCU board
  6 +
  7 +* Add support for TQM823M, TQM850M, TQM855M and TQM860M modules
  8 +
  9 +* Add support for Am29LV160ML, Am29LV320ML, and Am29LV640ML
  10 + mirror bit flash on TQM8xxM modules
  11 +
5 12 * Patch by Kenneth Johansson, 30 Jun 2003:
6 13 get rid of MK_CMD_ENTRY macro; update doc/README.command
7 14  
... ... @@ -372,6 +372,7 @@
372 372  
373 373 FPS850L_config \
374 374 FPS860L_config \
  375 +NSCU_config \
375 376 TQM823L_config \
376 377 TQM823L_66MHz_config \
377 378 TQM823L_80MHz_config \
... ... @@ -390,6 +391,15 @@
390 391 TQM862L_config \
391 392 TQM862L_66MHz_config \
392 393 TQM862L_80MHz_config \
  394 +TQM855M_config \
  395 +TQM855M_66MHz_config \
  396 +TQM855M_80MHz_config \
  397 +TQM860M_config \
  398 +TQM860M_66MHz_config \
  399 +TQM860M_80MHz_config \
  400 +TQM862M_config \
  401 +TQM862M_66MHz_config \
  402 +TQM862M_80MHz_config \
393 403 TQM862M_100MHz_config: unconfig
394 404 @ >include/config.h
395 405 @[ -z "$(findstring _66MHz,$@)" ] || \
board/tqm8xx/flash.c
Diff comments   View file @ f12e568
... ... @@ -209,6 +209,10 @@
209 209 #ifdef CONFIG_TQM8xxM /* mirror bit flash */
210 210 case FLASH_AMLV128U: printf ("AM29LV128ML (128Mbit, uniform sector size)\n");
211 211 break;
  212 + case FLASH_AMLV320U: printf ("AM29LV320ML (32Mbit, uniform sector size)\n");
  213 + break;
  214 + case FLASH_AMLV640U: printf ("AM29LV640ML (64Mbit, uniform sector size)\n");
  215 + break;
212 216 # else /* ! TQM8xxM */
213 217 case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
214 218 break;
215 219  
... ... @@ -218,15 +222,15 @@
218 222 break;
219 223 case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
220 224 break;
221   - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
222   - break;
223   - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
224   - break;
225 225 case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
226 226 break;
227 227 case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
228 228 break;
229 229 #endif /* TQM8xxM */
  230 + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
  231 + break;
  232 + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
  233 + break;
230 234 default: printf ("Unknown Chip Type\n");
231 235 break;
232 236 }
... ... @@ -294,6 +298,14 @@
294 298 switch (value) {
295 299 #ifdef CONFIG_TQM8xxM /* mirror bit flash */
296 300 case AMD_ID_MIRROR:
  301 + /* Special case for AMLV320MH/L */
  302 + if ((addr[14] & 0x00ff00ff) == 0x001d001d &&
  303 + (addr[15] & 0x00ff00ff) == 0x00000000) {
  304 + info->flash_id += FLASH_AMLV320U;
  305 + info->sector_count = 64;
  306 + info->size = 0x00800000; /* => 8 MB */
  307 + break;
  308 + }
297 309 switch(addr[14]) {
298 310 case AMD_ID_LV128U_2:
299 311 if (addr[15] != AMD_ID_LV128U_3) {
... ... @@ -305,6 +317,16 @@
305 317 info->size = 0x02000000;
306 318 }
307 319 break; /* => 32 MB */
  320 + case AMD_ID_LV640U_2:
  321 + if (addr[15] != AMD_ID_LV640U_3) {
  322 + info->flash_id = FLASH_UNKNOWN;
  323 + }
  324 + else {
  325 + info->flash_id += FLASH_AMLV640U;
  326 + info->sector_count = 128;
  327 + info->size = 0x01000000;
  328 + }
  329 + break; /* => 16 MB */
308 330 default:
309 331 info->flash_id = FLASH_UNKNOWN;
310 332 break;
... ... @@ -335,18 +357,6 @@
335 357 info->size = 0x00200000;
336 358 break; /* => 2 MB */
337 359  
338   - case AMD_ID_LV160T:
339   - info->flash_id += FLASH_AM160T;
340   - info->sector_count = 35;
341   - info->size = 0x00400000;
342   - break; /* => 4 MB */
343   -
344   - case AMD_ID_LV160B:
345   - info->flash_id += FLASH_AM160B;
346   - info->sector_count = 35;
347   - info->size = 0x00400000;
348   - break; /* => 4 MB */
349   -
350 360 case AMD_ID_LV320T:
351 361 info->flash_id += FLASH_AM320T;
352 362 info->sector_count = 71;
... ... @@ -359,6 +369,19 @@
359 369 info->size = 0x00800000;
360 370 break; /* => 8 MB */
361 371 #endif /* TQM8xxM */
  372 +
  373 + case AMD_ID_LV160T:
  374 + info->flash_id += FLASH_AM160T;
  375 + info->sector_count = 35;
  376 + info->size = 0x00400000;
  377 + break; /* => 4 MB */
  378 +
  379 + case AMD_ID_LV160B:
  380 + info->flash_id += FLASH_AM160B;
  381 + info->sector_count = 35;
  382 + info->size = 0x00400000;
  383 + break; /* => 4 MB */
  384 +
362 385 default:
363 386 info->flash_id = FLASH_UNKNOWN;
364 387 return (0); /* => no or unknown flash */
... ... @@ -371,6 +394,8 @@
371 394 switch (info->flash_id & FLASH_TYPEMASK) {
372 395 /* only known types here - no default */
373 396 case FLASH_AMLV128U:
  397 + case FLASH_AMLV640U:
  398 + case FLASH_AMLV320U:
374 399 for (i = 0; i < info->sector_count; i++) {
375 400 info->start[i] = base;
376 401 base += 0x20000;
... ... @@ -381,7 +406,6 @@
381 406 # else /* ! TQM8xxM */
382 407 case AMD_ID_LV400B:
383 408 case AMD_ID_LV800B:
384   - case AMD_ID_LV160B:
385 409 /* set sector offsets for bottom boot block type */
386 410 info->start[0] = base + 0x00000000;
387 411 info->start[1] = base + 0x00008000;
... ... @@ -393,7 +417,6 @@
393 417 break;
394 418 case AMD_ID_LV400T:
395 419 case AMD_ID_LV800T:
396   - case AMD_ID_LV160T:
397 420 /* set sector offsets for top boot block type */
398 421 i = info->sector_count - 1;
399 422 info->start[i--] = base + info->size - 0x00008000;
... ... @@ -428,6 +451,26 @@
428 451 }
429 452 break;
430 453 #endif /* TQM8xxM */
  454 + case AMD_ID_LV160B:
  455 + /* set sector offsets for bottom boot block type */
  456 + info->start[0] = base + 0x00000000;
  457 + info->start[1] = base + 0x00008000;
  458 + info->start[2] = base + 0x0000C000;
  459 + info->start[3] = base + 0x00010000;
  460 + for (i = 4; i < info->sector_count; i++) {
  461 + info->start[i] = base + (i * 0x00020000) - 0x00060000;
  462 + }
  463 + break;
  464 + case AMD_ID_LV160T:
  465 + /* set sector offsets for top boot block type */
  466 + i = info->sector_count - 1;
  467 + info->start[i--] = base + info->size - 0x00008000;
  468 + info->start[i--] = base + info->size - 0x0000C000;
  469 + info->start[i--] = base + info->size - 0x00010000;
  470 + for (; i >= 0; i--) {
  471 + info->start[i] = base + i * 0x00020000;
  472 + }
  473 + break;
431 474 default:
432 475 return (0);
433 476 break;
... ... @@ -1048,9 +1048,9 @@
1048 1048 /* -------------------------------------------------------------------- */
1049 1049  
1050 1050 U_BOOT_CMD(
1051   - hwflow [on|off], 2, 0, do_hwflow,
  1051 + hwflow, 2, 0, do_hwflow,
1052 1052 "hwflow - turn the harwdare flow control on/off\n",
1053   - "\n - change RTS/CTS hardware flow control over serial line\n"
  1053 + "[on|off]\n - change RTS/CTS hardware flow control over serial line\n"
1054 1054 );
1055 1055  
1056 1056 #endif /* CFG_CMD_HWFLOW */
include/configs/NSCU.h
Diff comments   View file @ f12e568
  1 +/*
  2 + * (C) Copyright 2000-2003
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +/*
  25 + * board/config.h - configuration options, board specific
  26 + */
  27 +
  28 +#ifndef __CONFIG_H
  29 +#define __CONFIG_H
  30 +
  31 +/*
  32 + * High Level Configuration Options
  33 + * (easy to change)
  34 + */
  35 +
  36 +#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
  37 +#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */
  38 +
  39 +#define CONFIG_8xx_CONS_SCC1 1 /* Console is on SMC1 */
  40 +
  41 +#define CONFIG_66MHz 1 /* running at 66 MHz, 1:1 clock */
  42 +
  43 +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
  44 +
  45 +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  46 +
  47 +#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in Hz */
  48 +
  49 +#define CONFIG_BOARD_TYPES 1 /* support board types */
  50 +
  51 +#define CONFIG_PREBOOT "echo;" \
  52 + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
  53 + "echo"
  54 +
  55 +#undef CONFIG_BOOTARGS
  56 +
  57 +#define CONFIG_EXTRA_ENV_SETTINGS \
  58 + "netdev=eth0\0" \
  59 + "nfsargs=setenv bootargs root=/dev/nfs rw " \
  60 + "nfsroot=$(serverip):$(rootpath)\0" \
  61 + "ramargs=setenv bootargs root=/dev/ram rw\0" \
  62 + "addip=setenv bootargs $(bootargs) " \
  63 + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
  64 + ":$(hostname):$(netdev):off panic=1\0" \
  65 + "flash_nfs=run nfsargs addip;" \
  66 + "bootm $(kernel_addr)\0" \
  67 + "flash_self=run ramargs addip;" \
  68 + "bootm $(kernel_addr) $(ramdisk_addr)\0" \
  69 + "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
  70 + "rootpath=/opt/eldk/ppc_8xx\0" \
  71 + "bootfile=/tftpboot/NSCU/uImage\0" \
  72 + "kernel_addr=40080000\0" \
  73 + "ramdisk_addr=40180000\0" \
  74 + ""
  75 +#define CONFIG_BOOTCOMMAND "run flash_self"
  76 +
  77 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  78 +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
  79 +
  80 +#undef CONFIG_WATCHDOG /* watchdog disabled */
  81 +
  82 +#define CONFIG_STATUS_LED 1 /* Status LED enabled */
  83 +
  84 +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
  85 +
  86 +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
  87 +
  88 +#define CONFIG_MAC_PARTITION
  89 +#define CONFIG_DOS_PARTITION
  90 +
  91 +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
  92 +
  93 +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
  94 + CFG_CMD_ASKENV | \
  95 + CFG_CMD_DHCP | \
  96 + CFG_CMD_IDE | \
  97 + CFG_CMD_DATE )
  98 +
  99 +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  100 +#include <cmd_confdefs.h>
  101 +
  102 +/*
  103 + * Miscellaneous configurable options
  104 + */
  105 +#define CFG_LONGHELP /* undef to save memory */
  106 +#define CFG_PROMPT "=> " /* Monitor Command Prompt */
  107 +
  108 +#if 0
  109 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
  110 +#endif
  111 +#ifdef CFG_HUSH_PARSER
  112 +#define CFG_PROMPT_HUSH_PS2 "> "
  113 +#endif
  114 +
  115 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  116 +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  117 +#else
  118 +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  119 +#endif
  120 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  121 +#define CFG_MAXARGS 16 /* max number of command args */
  122 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  123 +
  124 +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
  125 +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  126 +
  127 +#define CFG_LOAD_ADDR 0x100000 /* default load address */
  128 +
  129 +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  130 +
  131 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  132 +
  133 +/*
  134 + * Low Level Configuration Settings
  135 + * (address mappings, register initial values, etc.)
  136 + * You should know what you are doing if you make changes here.
  137 + */
  138 +/*-----------------------------------------------------------------------
  139 + * Internal Memory Mapped Register
  140 + */
  141 +#define CFG_IMMR 0xFFF00000
  142 +
  143 +/*-----------------------------------------------------------------------
  144 + * Definitions for initial stack pointer and data area (in DPRAM)
  145 + */
  146 +#define CFG_INIT_RAM_ADDR CFG_IMMR
  147 +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
  148 +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
  149 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  150 +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  151 +
  152 +/*-----------------------------------------------------------------------
  153 + * Start addresses for the final memory configuration
  154 + * (Set up by the startup code)
  155 + * Please note that CFG_SDRAM_BASE _must_ start at 0
  156 + */
  157 +#define CFG_SDRAM_BASE 0x00000000
  158 +#define CFG_FLASH_BASE 0x40000000
  159 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  160 +#define CFG_MONITOR_BASE CFG_FLASH_BASE
  161 +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  162 +
  163 +/*
  164 + * For booting Linux, the board info and command line data
  165 + * have to be in the first 8 MB of memory, since this is
  166 + * the maximum mapped by the Linux kernel during initialization.
  167 + */
  168 +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  169 +
  170 +/*-----------------------------------------------------------------------
  171 + * FLASH organization
  172 + */
  173 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
  174 +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  175 +
  176 +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  177 +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  178 +
  179 +#define CFG_ENV_IS_IN_FLASH 1
  180 +#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
  181 +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
  182 +#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
  183 +
  184 +/* Address and size of Redundant Environment Sector */
  185 +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
  186 +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
  187 +
  188 +/*-----------------------------------------------------------------------
  189 + * Hardware Information Block
  190 + */
  191 +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
  192 +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
  193 +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
  194 +
  195 +/*-----------------------------------------------------------------------
  196 + * Cache Configuration
  197 + */
  198 +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
  199 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  200 +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
  201 +#endif
  202 +
  203 +/*-----------------------------------------------------------------------
  204 + * SYPCR - System Protection Control 11-9
  205 + * SYPCR can only be written once after reset!
  206 + *-----------------------------------------------------------------------
  207 + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  208 + */
  209 +#if defined(CONFIG_WATCHDOG)
  210 +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
  211 + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
  212 +#else
  213 +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
  214 +#endif
  215 +
  216 +/*-----------------------------------------------------------------------
  217 + * SIUMCR - SIU Module Configuration 11-6
  218 + *-----------------------------------------------------------------------
  219 + * PCMCIA config., multi-function pin tri-state
  220 + */
  221 +#ifndef CONFIG_CAN_DRIVER
  222 +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
  223 +#else /* we must activate GPL5 in the SIUMCR for CAN */
  224 +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
  225 +#endif /* CONFIG_CAN_DRIVER */
  226 +
  227 +/*-----------------------------------------------------------------------
  228 + * TBSCR - Time Base Status and Control 11-26
  229 + *-----------------------------------------------------------------------
  230 + * Clear Reference Interrupt Status, Timebase freezing enabled
  231 + */
  232 +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
  233 +
  234 +/*-----------------------------------------------------------------------
  235 + * RTCSC - Real-Time Clock Status and Control Register 11-27
  236 + *-----------------------------------------------------------------------
  237 + */
  238 +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
  239 +
  240 +/*-----------------------------------------------------------------------
  241 + * PISCR - Periodic Interrupt Status and Control 11-31
  242 + *-----------------------------------------------------------------------
  243 + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  244 + */
  245 +#define CFG_PISCR (PISCR_PS | PISCR_PITF)
  246 +
  247 +/*-----------------------------------------------------------------------
  248 + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
  249 + *-----------------------------------------------------------------------
  250 + * Reset PLL lock status sticky bit, timer expired status bit and timer
  251 + * interrupt status bit
  252 + *
  253 + * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
  254 + */
  255 +#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
  256 +#define CFG_PLPRCR \
  257 + ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
  258 +#else /* up to 66 MHz we use a 1:1 clock */
  259 +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
  260 +#endif /* CONFIG_80MHz */
  261 +
  262 +/*-----------------------------------------------------------------------
  263 + * SCCR - System Clock and reset Control Register 15-27
  264 + *-----------------------------------------------------------------------
  265 + * Set clock output, timebase and RTC source and divider,
  266 + * power management and some other internal clocks
  267 + */
  268 +#define SCCR_MASK SCCR_EBDF11
  269 +#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
  270 +#define CFG_SCCR (/* SCCR_TBS | */ \
  271 + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
  272 + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
  273 + SCCR_DFALCD00)
  274 +#else /* up to 66 MHz we use a 1:1 clock */
  275 +#define CFG_SCCR (SCCR_TBS | \
  276 + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
  277 + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
  278 + SCCR_DFALCD00)
  279 +#endif /* CONFIG_80MHz */
  280 +
  281 +/*-----------------------------------------------------------------------
  282 + * PCMCIA stuff
  283 + *-----------------------------------------------------------------------
  284 + *
  285 + */
  286 +#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
  287 +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
  288 +#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
  289 +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
  290 +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
  291 +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
  292 +#define CFG_PCMCIA_IO_ADDR (0xEC000000)
  293 +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
  294 +
  295 +/*-----------------------------------------------------------------------
  296 + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
  297 + *-----------------------------------------------------------------------
  298 + */
  299 +
  300 +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
  301 +
  302 +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
  303 +#undef CONFIG_IDE_LED /* LED for ide not supported */
  304 +#undef CONFIG_IDE_RESET /* reset for ide not supported */
  305 +
  306 +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
  307 +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
  308 +
  309 +#define CFG_ATA_IDE0_OFFSET 0x0000
  310 +
  311 +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
  312 +
  313 +/* Offset for data I/O */
  314 +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
  315 +
  316 +/* Offset for normal register accesses */
  317 +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
  318 +
  319 +/* Offset for alternate registers */
  320 +#define CFG_ATA_ALT_OFFSET 0x0100
  321 +
  322 +/*-----------------------------------------------------------------------
  323 + *
  324 + *-----------------------------------------------------------------------
  325 + *
  326 + */
  327 +#define CFG_DER 0
  328 +
  329 +/*
  330 + * Init Memory Controller:
  331 + *
  332 + * BR0/1 and OR0/1 (FLASH)
  333 + */
  334 +
  335 +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
  336 +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
  337 +
  338 +/* used to re-map FLASH both when starting from SRAM or FLASH:
  339 + * restrict access enough to keep SRAM working (if any)
  340 + * but not too much to meddle with FLASH accesses
  341 + */
  342 +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
  343 +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
  344 +
  345 +/*
  346 + * FLASH timing:
  347 + */
  348 +#if defined(CONFIG_80MHz)
  349 +/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
  350 +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
  351 + OR_SCY_3_CLK | OR_EHTR | OR_BI)
  352 +#elif defined(CONFIG_66MHz)
  353 +/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
  354 +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
  355 + OR_SCY_3_CLK | OR_EHTR | OR_BI)
  356 +#else /* 50 MHz */
  357 +/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
  358 +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
  359 + OR_SCY_2_CLK | OR_EHTR | OR_BI)
  360 +#endif /*CONFIG_??MHz */
  361 +
  362 +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
  363 +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
  364 +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
  365 +
  366 +#define CFG_OR1_REMAP CFG_OR0_REMAP
  367 +#define CFG_OR1_PRELIM CFG_OR0_PRELIM
  368 +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
  369 +
  370 +/*
  371 + * BR2/3 and OR2/3 (SDRAM)
  372 + *
  373 + */
  374 +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
  375 +#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
  376 +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
  377 +
  378 +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
  379 +#define CFG_OR_TIMING_SDRAM 0x00000A00
  380 +
  381 +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
  382 +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
  383 +
  384 +#ifndef CONFIG_CAN_DRIVER
  385 +#define CFG_OR3_PRELIM CFG_OR2_PRELIM
  386 +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
  387 +#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
  388 +#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
  389 +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
  390 +#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
  391 +#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
  392 + BR_PS_8 | BR_MS_UPMB | BR_V )
  393 +#endif /* CONFIG_CAN_DRIVER */
  394 +
  395 +/*
  396 + * Memory Periodic Timer Prescaler
  397 + *
  398 + * The Divider for PTA (refresh timer) configuration is based on an
  399 + * example SDRAM configuration (64 MBit, one bank). The adjustment to
  400 + * the number of chip selects (NCS) and the actually needed refresh
  401 + * rate is done by setting MPTPR.
  402 + *
  403 + * PTA is calculated from
  404 + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
  405 + *
  406 + * gclk CPU clock (not bus clock!)
  407 + * Trefresh Refresh cycle * 4 (four word bursts used)
  408 + *
  409 + * 4096 Rows from SDRAM example configuration
  410 + * 1000 factor s -> ms
  411 + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
  412 + * 4 Number of refresh cycles per period
  413 + * 64 Refresh cycle in ms per number of rows
  414 + * --------------------------------------------
  415 + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
  416 + *
  417 + * 50 MHz => 50.000.000 / Divider = 98
  418 + * 66 Mhz => 66.000.000 / Divider = 129
  419 + * 80 Mhz => 80.000.000 / Divider = 156
  420 + */
  421 +#if defined(CONFIG_80MHz)
  422 +#define CFG_MAMR_PTA 156
  423 +#elif defined(CONFIG_66MHz)
  424 +#define CFG_MAMR_PTA 129
  425 +#else /* 50 MHz */
  426 +#define CFG_MAMR_PTA 98
  427 +#endif /*CONFIG_??MHz */
  428 +
  429 +/*
  430 + * For 16 MBit, refresh rates could be 31.3 us
  431 + * (= 64 ms / 2K = 125 / quad bursts).
  432 + * For a simpler initialization, 15.6 us is used instead.
  433 + *
  434 + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
  435 + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
  436 + */
  437 +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
  438 +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
  439 +
  440 +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
  441 +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
  442 +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
  443 +
  444 +/*
  445 + * MAMR settings for SDRAM
  446 + */
  447 +
  448 +/* 8 column SDRAM */
  449 +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
  450 + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
  451 + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
  452 +/* 9 column SDRAM */
  453 +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
  454 + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
  455 + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
  456 +
  457 +
  458 +/*
  459 + * Internal Definitions
  460 + *
  461 + * Boot Flags
  462 + */
  463 +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  464 +#define BOOTFLAG_WARM 0x02 /* Software reboot */
  465 +
  466 +#undef CONFIG_SCC1_ENET
  467 +#define CONFIG_FEC_ENET
  468 +/* #define CONFIG_ETHPRIME "FEC ETHERNET" */
  469 +
  470 +#endif /* __CONFIG_H */
include/configs/TQM823L.h
Diff comments   View file @ f12e568
1 1 /*
2   - * (C) Copyright 2000, 2001, 2002
  2 + * (C) Copyright 2000-2003
3 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 4 *
5 5 * See file CREDITS for list of people who contributed to this
... ... @@ -261,7 +261,7 @@
261 261 #ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
262 262 #define CFG_PLPRCR \
263 263 ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
264   -#else /* up to 50 MHz we use a 1:1 clock */
  264 +#else /* up to 66 MHz we use a 1:1 clock */
265 265 #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
266 266 #endif /* CONFIG_80MHz */
267 267  
... ... @@ -277,7 +277,7 @@
277 277 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
278 278 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
279 279 SCCR_DFALCD00)
280   -#else /* up to 50 MHz we use a 1:1 clock */
  280 +#else /* up to 66 MHz we use a 1:1 clock */
281 281 #define CFG_SCCR (SCCR_TBS | \
282 282 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
283 283 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
include/configs/TQM823M.h
Diff comments   View file @ f12e568
  1 +/*
  2 + * (C) Copyright 2000-2003
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +/*
  25 + * board/config.h - configuration options, board specific
  26 + */
  27 +
  28 +#ifndef __CONFIG_H
  29 +#define __CONFIG_H
  30 +
  31 +/*
  32 + * High Level Configuration Options
  33 + * (easy to change)
  34 + */
  35 +
  36 +#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
  37 +#define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */
  38 +
  39 +#ifdef CONFIG_LCD /* with LCD controller ? */
  40 +/* #define CONFIG_NEC_NL6648BC20 1 / * use NEC NL6648BC20 display */
  41 +#endif
  42 +
  43 +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
  44 +#undef CONFIG_8xx_CONS_SMC2
  45 +#undef CONFIG_8xx_CONS_NONE
  46 +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
  47 +#if 0
  48 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
  49 +#else
  50 +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  51 +#endif
  52 +
  53 +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
  54 +
  55 +#define CONFIG_BOARD_TYPES 1 /* support board types */
  56 +
  57 +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
  58 +
  59 +#undef CONFIG_BOOTARGS
  60 +
  61 +#define CONFIG_EXTRA_ENV_SETTINGS \
  62 + "netdev=eth0\0" \
  63 + "nfsargs=setenv bootargs root=/dev/nfs rw " \
  64 + "nfsroot=$(serverip):$(rootpath)\0" \
  65 + "ramargs=setenv bootargs root=/dev/ram rw\0" \
  66 + "addip=setenv bootargs $(bootargs) " \
  67 + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
  68 + ":$(hostname):$(netdev):off panic=1\0" \
  69 + "flash_nfs=run nfsargs addip;" \
  70 + "bootm $(kernel_addr)\0" \
  71 + "flash_self=run ramargs addip;" \
  72 + "bootm $(kernel_addr) $(ramdisk_addr)\0" \
  73 + "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
  74 + "rootpath=/opt/eldk/ppc_8xx\0" \
  75 + "bootfile=/tftpboot/TQM823M/uImage\0" \
  76 + "kernel_addr=40080000\0" \
  77 + "ramdisk_addr=40180000\0" \
  78 + ""
  79 +#define CONFIG_BOOTCOMMAND "run flash_self"
  80 +
  81 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  82 +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
  83 +
  84 +#undef CONFIG_WATCHDOG /* watchdog disabled */
  85 +
  86 +#ifdef CONFIG_LCD
  87 +# undef CONFIG_STATUS_LED /* disturbs display */
  88 +#else
  89 +# define CONFIG_STATUS_LED 1 /* Status LED enabled */
  90 +#endif /* CONFIG_LCD */
  91 +
  92 +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
  93 +
  94 +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
  95 +
  96 +#define CONFIG_MAC_PARTITION
  97 +#define CONFIG_DOS_PARTITION
  98 +
  99 +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
  100 +
  101 +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
  102 + CFG_CMD_ASKENV | \
  103 + CFG_CMD_DHCP | \
  104 + CFG_CMD_IDE | \
  105 + CFG_CMD_DATE )
  106 +
  107 +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  108 +#include <cmd_confdefs.h>
  109 +
  110 +/*
  111 + * Miscellaneous configurable options
  112 + */
  113 +#define CFG_LONGHELP /* undef to save memory */
  114 +#define CFG_PROMPT "=> " /* Monitor Command Prompt */
  115 +
  116 +#if 0
  117 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
  118 +#endif
  119 +#ifdef CFG_HUSH_PARSER
  120 +#define CFG_PROMPT_HUSH_PS2 "> "
  121 +#endif
  122 +
  123 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  124 +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  125 +#else
  126 +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  127 +#endif
  128 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  129 +#define CFG_MAXARGS 16 /* max number of command args */
  130 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  131 +
  132 +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
  133 +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  134 +
  135 +#define CFG_LOAD_ADDR 0x100000 /* default load address */
  136 +
  137 +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  138 +
  139 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  140 +
  141 +/*
  142 + * Low Level Configuration Settings
  143 + * (address mappings, register initial values, etc.)
  144 + * You should know what you are doing if you make changes here.
  145 + */
  146 +/*-----------------------------------------------------------------------
  147 + * Internal Memory Mapped Register
  148 + */
  149 +#define CFG_IMMR 0xFFF00000
  150 +
  151 +/*-----------------------------------------------------------------------
  152 + * Definitions for initial stack pointer and data area (in DPRAM)
  153 + */
  154 +#define CFG_INIT_RAM_ADDR CFG_IMMR
  155 +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
  156 +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
  157 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  158 +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  159 +
  160 +/*-----------------------------------------------------------------------
  161 + * Start addresses for the final memory configuration
  162 + * (Set up by the startup code)
  163 + * Please note that CFG_SDRAM_BASE _must_ start at 0
  164 + */
  165 +#define CFG_SDRAM_BASE 0x00000000
  166 +#define CFG_FLASH_BASE 0x40000000
  167 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  168 +#define CFG_MONITOR_BASE CFG_FLASH_BASE
  169 +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  170 +
  171 +/*
  172 + * For booting Linux, the board info and command line data
  173 + * have to be in the first 8 MB of memory, since this is
  174 + * the maximum mapped by the Linux kernel during initialization.
  175 + */
  176 +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  177 +
  178 +/*-----------------------------------------------------------------------
  179 + * FLASH organization
  180 + */
  181 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
  182 +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  183 +
  184 +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  185 +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  186 +
  187 +#define CFG_ENV_IS_IN_FLASH 1
  188 +#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
  189 +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
  190 +#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
  191 +
  192 +/* Address and size of Redundant Environment Sector */
  193 +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
  194 +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
  195 +
  196 +/*-----------------------------------------------------------------------
  197 + * Hardware Information Block
  198 + */
  199 +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
  200 +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
  201 +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
  202 +
  203 +/*-----------------------------------------------------------------------
  204 + * Cache Configuration
  205 + */
  206 +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
  207 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  208 +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
  209 +#endif
  210 +
  211 +/*-----------------------------------------------------------------------
  212 + * SYPCR - System Protection Control 11-9
  213 + * SYPCR can only be written once after reset!
  214 + *-----------------------------------------------------------------------
  215 + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  216 + */
  217 +#if defined(CONFIG_WATCHDOG)
  218 +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
  219 + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
  220 +#else
  221 +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
  222 +#endif
  223 +
  224 +/*-----------------------------------------------------------------------
  225 + * SIUMCR - SIU Module Configuration 11-6
  226 + *-----------------------------------------------------------------------
  227 + * PCMCIA config., multi-function pin tri-state
  228 + */
  229 +#ifndef CONFIG_CAN_DRIVER
  230 +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
  231 +#else /* we must activate GPL5 in the SIUMCR for CAN */
  232 +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
  233 +#endif /* CONFIG_CAN_DRIVER */
  234 +
  235 +/*-----------------------------------------------------------------------
  236 + * TBSCR - Time Base Status and Control 11-26
  237 + *-----------------------------------------------------------------------
  238 + * Clear Reference Interrupt Status, Timebase freezing enabled
  239 + */
  240 +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
  241 +
  242 +/*-----------------------------------------------------------------------
  243 + * RTCSC - Real-Time Clock Status and Control Register 11-27
  244 + *-----------------------------------------------------------------------
  245 + */
  246 +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
  247 +
  248 +/*-----------------------------------------------------------------------
  249 + * PISCR - Periodic Interrupt Status and Control 11-31
  250 + *-----------------------------------------------------------------------
  251 + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  252 + */
  253 +#define CFG_PISCR (PISCR_PS | PISCR_PITF)
  254 +
  255 +/*-----------------------------------------------------------------------
  256 + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
  257 + *-----------------------------------------------------------------------
  258 + * Reset PLL lock status sticky bit, timer expired status bit and timer
  259 + * interrupt status bit
  260 + *
  261 + * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
  262 + */
  263 +#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
  264 +#define CFG_PLPRCR \
  265 + ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
  266 +#else /* up to 66 MHz we use a 1:1 clock */
  267 +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
  268 +#endif /* CONFIG_80MHz */
  269 +
  270 +/*-----------------------------------------------------------------------
  271 + * SCCR - System Clock and reset Control Register 15-27
  272 + *-----------------------------------------------------------------------
  273 + * Set clock output, timebase and RTC source and divider,
  274 + * power management and some other internal clocks
  275 + */
  276 +#define SCCR_MASK SCCR_EBDF11
  277 +#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
  278 +#define CFG_SCCR (/* SCCR_TBS | */ \
  279 + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
  280 + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
  281 + SCCR_DFALCD00)
  282 +#else /* up to 66 MHz we use a 1:1 clock */
  283 +#define CFG_SCCR (SCCR_TBS | \
  284 + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
  285 + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
  286 + SCCR_DFALCD00)
  287 +#endif /* CONFIG_80MHz */
  288 +
  289 +/*-----------------------------------------------------------------------
  290 + * PCMCIA stuff
  291 + *-----------------------------------------------------------------------
  292 + *
  293 + */
  294 +#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
  295 +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
  296 +#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
  297 +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
  298 +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
  299 +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
  300 +#define CFG_PCMCIA_IO_ADDR (0xEC000000)
  301 +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
  302 +
  303 +/*-----------------------------------------------------------------------
  304 + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
  305 + *-----------------------------------------------------------------------
  306 + */
  307 +
  308 +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
  309 +
  310 +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
  311 +#undef CONFIG_IDE_LED /* LED for ide not supported */
  312 +#undef CONFIG_IDE_RESET /* reset for ide not supported */
  313 +
  314 +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
  315 +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
  316 +
  317 +#define CFG_ATA_IDE0_OFFSET 0x0000
  318 +
  319 +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
  320 +
  321 +/* Offset for data I/O */
  322 +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
  323 +
  324 +/* Offset for normal register accesses */
  325 +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
  326 +
  327 +/* Offset for alternate registers */
  328 +#define CFG_ATA_ALT_OFFSET 0x0100
  329 +
  330 +/*-----------------------------------------------------------------------
  331 + *
  332 + *-----------------------------------------------------------------------
  333 + *
  334 + */
  335 +#define CFG_DER 0
  336 +
  337 +/*
  338 + * Init Memory Controller:
  339 + *
  340 + * BR0/1 and OR0/1 (FLASH)
  341 + */
  342 +
  343 +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
  344 +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
  345 +
  346 +/* used to re-map FLASH both when starting from SRAM or FLASH:
  347 + * restrict access enough to keep SRAM working (if any)
  348 + * but not too much to meddle with FLASH accesses
  349 + */
  350 +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
  351 +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
  352 +
  353 +/*
  354 + * FLASH timing:
  355 + */
  356 +#if defined(CONFIG_80MHz)
  357 +/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
  358 +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
  359 + OR_SCY_3_CLK | OR_EHTR | OR_BI)
  360 +#elif defined(CONFIG_66MHz)
  361 +/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
  362 +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
  363 + OR_SCY_3_CLK | OR_EHTR | OR_BI)
  364 +#else /* 50 MHz */
  365 +/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
  366 +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
  367 + OR_SCY_2_CLK | OR_EHTR | OR_BI)
  368 +#endif /*CONFIG_??MHz */
  369 +
  370 +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
  371 +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
  372 +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
  373 +
  374 +#define CFG_OR1_REMAP CFG_OR0_REMAP
  375 +#define CFG_OR1_PRELIM CFG_OR0_PRELIM
  376 +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
  377 +
  378 +/*
  379 + * BR2/3 and OR2/3 (SDRAM)
  380 + *
  381 + */
  382 +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
  383 +#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
  384 +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
  385 +
  386 +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
  387 +#define CFG_OR_TIMING_SDRAM 0x00000A00
  388 +
  389 +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
  390 +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
  391 +
  392 +#ifndef CONFIG_CAN_DRIVER
  393 +#define CFG_OR3_PRELIM CFG_OR2_PRELIM
  394 +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
  395 +#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
  396 +#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
  397 +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
  398 +#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
  399 +#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
  400 + BR_PS_8 | BR_MS_UPMB | BR_V )
  401 +#endif /* CONFIG_CAN_DRIVER */
  402 +
  403 +/*
  404 + * Memory Periodic Timer Prescaler
  405 + *
  406 + * The Divider for PTA (refresh timer) configuration is based on an
  407 + * example SDRAM configuration (64 MBit, one bank). The adjustment to
  408 + * the number of chip selects (NCS) and the actually needed refresh
  409 + * rate is done by setting MPTPR.
  410 + *
  411 + * PTA is calculated from
  412 + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
  413 + *
  414 + * gclk CPU clock (not bus clock!)
  415 + * Trefresh Refresh cycle * 4 (four word bursts used)
  416 + *
  417 + * 4096 Rows from SDRAM example configuration
  418 + * 1000 factor s -> ms
  419 + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
  420 + * 4 Number of refresh cycles per period
  421 + * 64 Refresh cycle in ms per number of rows
  422 + * --------------------------------------------
  423 + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
  424 + *
  425 + * 50 MHz => 50.000.000 / Divider = 98
  426 + * 66 Mhz => 66.000.000 / Divider = 129
  427 + * 80 Mhz => 80.000.000 / Divider = 156
  428 + */
  429 +#if defined(CONFIG_80MHz)
  430 +#define CFG_MAMR_PTA 156
  431 +#elif defined(CONFIG_66MHz)
  432 +#define CFG_MAMR_PTA 129
  433 +#else /* 50 MHz */
  434 +#define CFG_MAMR_PTA 98
  435 +#endif /*CONFIG_??MHz */
  436 +
  437 +/*
  438 + * For 16 MBit, refresh rates could be 31.3 us
  439 + * (= 64 ms / 2K = 125 / quad bursts).
  440 + * For a simpler initialization, 15.6 us is used instead.
  441 + *
  442 + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
  443 + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
  444 + */
  445 +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
  446 +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
  447 +
  448 +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
  449 +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
  450 +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
  451 +
  452 +/*
  453 + * MAMR settings for SDRAM
  454 + */
  455 +
  456 +/* 8 column SDRAM */
  457 +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
  458 + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
  459 + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
  460 +/* 9 column SDRAM */
  461 +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
  462 + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
  463 + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
  464 +
  465 +
  466 +/*
  467 + * Internal Definitions
  468 + *
  469 + * Boot Flags
  470 + */
  471 +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  472 +#define BOOTFLAG_WARM 0x02 /* Software reboot */
  473 +
  474 +#endif /* __CONFIG_H */
include/configs/TQM8260.h
Diff comments   View file @ f12e568
1 1 /*
2   - * (C) Copyright 2001
  2 + * (C) Copyright 2001-2003
3 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 4 *
5 5 * See file CREDITS for list of people who contributed to this
include/configs/TQM850L.h
Diff comments   View file @ f12e568
1 1 /*
2   - * (C) Copyright 2000, 2001, 2002
  2 + * (C) Copyright 2000-2003
3 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 4 *
5 5 * See file CREDITS for list of people who contributed to this
... ... @@ -253,7 +253,7 @@
253 253 #ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
254 254 #define CFG_PLPRCR \
255 255 ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
256   -#else /* up to 50 MHz we use a 1:1 clock */
  256 +#else /* up to 66 MHz we use a 1:1 clock */
257 257 #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
258 258 #endif /* CONFIG_80MHz */
259 259  
... ... @@ -269,7 +269,7 @@
269 269 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
270 270 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
271 271 SCCR_DFALCD00)
272   -#else /* up to 50 MHz we use a 1:1 clock */
  272 +#else /* up to 66 MHz we use a 1:1 clock */
273 273 #define CFG_SCCR (SCCR_TBS | \
274 274 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
275 275 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
include/configs/TQM850M.h
Diff comments   View file @ f12e568
  1 +/*
  2 + * (C) Copyright 2000-2003
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +/*
  25 + * board/config.h - configuration options, board specific
  26 + */
  27 +
  28 +#ifndef __CONFIG_H
  29 +#define __CONFIG_H
  30 +
  31 +/*
  32 + * High Level Configuration Options
  33 + * (easy to change)
  34 + */
  35 +
  36 +#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
  37 +#define CONFIG_TQM850M 1 /* ...on a TQM8xxM module */
  38 +
  39 +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
  40 +#undef CONFIG_8xx_CONS_SMC2
  41 +#undef CONFIG_8xx_CONS_NONE
  42 +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
  43 +#if 0
  44 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
  45 +#else
  46 +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  47 +#endif
  48 +
  49 +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
  50 +
  51 +#define CONFIG_BOARD_TYPES 1 /* support board types */
  52 +
  53 +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
  54 +
  55 +#undef CONFIG_BOOTARGS
  56 +
  57 +#define CONFIG_EXTRA_ENV_SETTINGS \
  58 + "netdev=eth0\0" \
  59 + "nfsargs=setenv bootargs root=/dev/nfs rw " \
  60 + "nfsroot=$(serverip):$(rootpath)\0" \
  61 + "ramargs=setenv bootargs root=/dev/ram rw\0" \
  62 + "addip=setenv bootargs $(bootargs) " \
  63 + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
  64 + ":$(hostname):$(netdev):off panic=1\0" \
  65 + "flash_nfs=run nfsargs addip;" \
  66 + "bootm $(kernel_addr)\0" \
  67 + "flash_self=run ramargs addip;" \
  68 + "bootm $(kernel_addr) $(ramdisk_addr)\0" \
  69 + "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
  70 + "rootpath=/opt/eldk/ppc_8xx\0" \
  71 + "bootfile=/tftpboot/TQM850M/uImage\0" \
  72 + "kernel_addr=40080000\0" \
  73 + "ramdisk_addr=40180000\0" \
  74 + ""
  75 +#define CONFIG_BOOTCOMMAND "run flash_self"
  76 +
  77 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  78 +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
  79 +
  80 +#undef CONFIG_WATCHDOG /* watchdog disabled */
  81 +
  82 +#define CONFIG_STATUS_LED 1 /* Status LED enabled */
  83 +
  84 +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
  85 +
  86 +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
  87 +
  88 +#define CONFIG_MAC_PARTITION
  89 +#define CONFIG_DOS_PARTITION
  90 +
  91 +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
  92 +
  93 +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
  94 + CFG_CMD_ASKENV | \
  95 + CFG_CMD_DHCP | \
  96 + CFG_CMD_IDE | \
  97 + CFG_CMD_DATE )
  98 +
  99 +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  100 +#include <cmd_confdefs.h>
  101 +
  102 +/*
  103 + * Miscellaneous configurable options
  104 + */
  105 +#define CFG_LONGHELP /* undef to save memory */
  106 +#define CFG_PROMPT "=> " /* Monitor Command Prompt */
  107 +
  108 +#if 0
  109 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
  110 +#endif
  111 +#ifdef CFG_HUSH_PARSER
  112 +#define CFG_PROMPT_HUSH_PS2 "> "
  113 +#endif
  114 +
  115 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  116 +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  117 +#else
  118 +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  119 +#endif
  120 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  121 +#define CFG_MAXARGS 16 /* max number of command args */
  122 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  123 +
  124 +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
  125 +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  126 +
  127 +#define CFG_LOAD_ADDR 0x100000 /* default load address */
  128 +
  129 +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  130 +
  131 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  132 +
  133 +/*
  134 + * Low Level Configuration Settings
  135 + * (address mappings, register initial values, etc.)
  136 + * You should know what you are doing if you make changes here.
  137 + */
  138 +/*-----------------------------------------------------------------------
  139 + * Internal Memory Mapped Register
  140 + */
  141 +#define CFG_IMMR 0xFFF00000
  142 +
  143 +/*-----------------------------------------------------------------------
  144 + * Definitions for initial stack pointer and data area (in DPRAM)
  145 + */
  146 +#define CFG_INIT_RAM_ADDR CFG_IMMR
  147 +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
  148 +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
  149 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  150 +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  151 +
  152 +/*-----------------------------------------------------------------------
  153 + * Start addresses for the final memory configuration
  154 + * (Set up by the startup code)
  155 + * Please note that CFG_SDRAM_BASE _must_ start at 0
  156 + */
  157 +#define CFG_SDRAM_BASE 0x00000000
  158 +#define CFG_FLASH_BASE 0x40000000
  159 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  160 +#define CFG_MONITOR_BASE CFG_FLASH_BASE
  161 +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  162 +
  163 +/*
  164 + * For booting Linux, the board info and command line data
  165 + * have to be in the first 8 MB of memory, since this is
  166 + * the maximum mapped by the Linux kernel during initialization.
  167 + */
  168 +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  169 +
  170 +/*-----------------------------------------------------------------------
  171 + * FLASH organization
  172 + */
  173 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
  174 +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  175 +
  176 +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  177 +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  178 +
  179 +#define CFG_ENV_IS_IN_FLASH 1
  180 +#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
  181 +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
  182 +#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
  183 +
  184 +/* Address and size of Redundant Environment Sector */
  185 +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
  186 +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
  187 +
  188 +/*-----------------------------------------------------------------------
  189 + * Hardware Information Block
  190 + */
  191 +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
  192 +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
  193 +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
  194 +
  195 +/*-----------------------------------------------------------------------
  196 + * Cache Configuration
  197 + */
  198 +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
  199 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  200 +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
  201 +#endif
  202 +
  203 +/*-----------------------------------------------------------------------
  204 + * SYPCR - System Protection Control 11-9
  205 + * SYPCR can only be written once after reset!
  206 + *-----------------------------------------------------------------------
  207 + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  208 + */
  209 +#if defined(CONFIG_WATCHDOG)
  210 +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
  211 + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
  212 +#else
  213 +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
  214 +#endif
  215 +
  216 +/*-----------------------------------------------------------------------
  217 + * SIUMCR - SIU Module Configuration 11-6
  218 + *-----------------------------------------------------------------------
  219 + * PCMCIA config., multi-function pin tri-state
  220 + */
  221 +#ifndef CONFIG_CAN_DRIVER
  222 +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
  223 +#else /* we must activate GPL5 in the SIUMCR for CAN */
  224 +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
  225 +#endif /* CONFIG_CAN_DRIVER */
  226 +
  227 +/*-----------------------------------------------------------------------
  228 + * TBSCR - Time Base Status and Control 11-26
  229 + *-----------------------------------------------------------------------
  230 + * Clear Reference Interrupt Status, Timebase freezing enabled
  231 + */
  232 +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
  233 +
  234 +/*-----------------------------------------------------------------------
  235 + * RTCSC - Real-Time Clock Status and Control Register 11-27
  236 + *-----------------------------------------------------------------------
  237 + */
  238 +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
  239 +
  240 +/*-----------------------------------------------------------------------
  241 + * PISCR - Periodic Interrupt Status and Control 11-31
  242 + *-----------------------------------------------------------------------
  243 + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  244 + */
  245 +#define CFG_PISCR (PISCR_PS | PISCR_PITF)
  246 +
  247 +/*-----------------------------------------------------------------------
  248 + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
  249 + *-----------------------------------------------------------------------
  250 + * Reset PLL lock status sticky bit, timer expired status bit and timer
  251 + * interrupt status bit
  252 + *
  253 + * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
  254 + */
  255 +#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
  256 +#define CFG_PLPRCR \
  257 + ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
  258 +#else /* up to 66 MHz we use a 1:1 clock */
  259 +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
  260 +#endif /* CONFIG_80MHz */
  261 +
  262 +/*-----------------------------------------------------------------------
  263 + * SCCR - System Clock and reset Control Register 15-27
  264 + *-----------------------------------------------------------------------
  265 + * Set clock output, timebase and RTC source and divider,
  266 + * power management and some other internal clocks
  267 + */
  268 +#define SCCR_MASK SCCR_EBDF11
  269 +#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
  270 +#define CFG_SCCR (/* SCCR_TBS | */ \
  271 + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
  272 + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
  273 + SCCR_DFALCD00)
  274 +#else /* up to 66 MHz we use a 1:1 clock */
  275 +#define CFG_SCCR (SCCR_TBS | \
  276 + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
  277 + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
  278 + SCCR_DFALCD00)
  279 +#endif /* CONFIG_80MHz */
  280 +
  281 +/*-----------------------------------------------------------------------
  282 + * PCMCIA stuff
  283 + *-----------------------------------------------------------------------
  284 + *
  285 + */
  286 +#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
  287 +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
  288 +#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
  289 +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
  290 +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
  291 +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
  292 +#define CFG_PCMCIA_IO_ADDR (0xEC000000)
  293 +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
  294 +
  295 +/*-----------------------------------------------------------------------
  296 + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
  297 + *-----------------------------------------------------------------------
  298 + */
  299 +
  300 +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
  301 +
  302 +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
  303 +#undef CONFIG_IDE_LED /* LED for ide not supported */
  304 +#undef CONFIG_IDE_RESET /* reset for ide not supported */
  305 +
  306 +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
  307 +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
  308 +
  309 +#define CFG_ATA_IDE0_OFFSET 0x0000
  310 +
  311 +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
  312 +
  313 +/* Offset for data I/O */
  314 +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
  315 +
  316 +/* Offset for normal register accesses */
  317 +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
  318 +
  319 +/* Offset for alternate registers */
  320 +#define CFG_ATA_ALT_OFFSET 0x0100
  321 +
  322 +/*-----------------------------------------------------------------------
  323 + *
  324 + *-----------------------------------------------------------------------
  325 + *
  326 + */
  327 +#define CFG_DER 0
  328 +
  329 +/*
  330 + * Init Memory Controller:
  331 + *
  332 + * BR0/1 and OR0/1 (FLASH)
  333 + */
  334 +
  335 +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
  336 +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
  337 +
  338 +/* used to re-map FLASH both when starting from SRAM or FLASH:
  339 + * restrict access enough to keep SRAM working (if any)
  340 + * but not too much to meddle with FLASH accesses
  341 + */
  342 +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
  343 +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
  344 +
  345 +/*
  346 + * FLASH timing:
  347 + */
  348 +#if defined(CONFIG_80MHz)
  349 +/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
  350 +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
  351 + OR_SCY_3_CLK | OR_EHTR | OR_BI)
  352 +#elif defined(CONFIG_66MHz)
  353 +/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
  354 +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
  355 + OR_SCY_3_CLK | OR_EHTR | OR_BI)
  356 +#else /* 50 MHz */
  357 +/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
  358 +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
  359 + OR_SCY_2_CLK | OR_EHTR | OR_BI)
  360 +#endif /*CONFIG_??MHz */
  361 +
  362 +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
  363 +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
  364 +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
  365 +
  366 +#define CFG_OR1_REMAP CFG_OR0_REMAP
  367 +#define CFG_OR1_PRELIM CFG_OR0_PRELIM
  368 +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
  369 +
  370 +/*
  371 + * BR2/3 and OR2/3 (SDRAM)
  372 + *
  373 + */
  374 +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
  375 +#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
  376 +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
  377 +
  378 +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
  379 +#define CFG_OR_TIMING_SDRAM 0x00000A00
  380 +
  381 +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
  382 +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
  383 +
  384 +#ifndef CONFIG_CAN_DRIVER
  385 +#define CFG_OR3_PRELIM CFG_OR2_PRELIM
  386 +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
  387 +#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
  388 +#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
  389 +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
  390 +#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
  391 +#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
  392 + BR_PS_8 | BR_MS_UPMB | BR_V )
  393 +#endif /* CONFIG_CAN_DRIVER */
  394 +
  395 +/*
  396 + * Memory Periodic Timer Prescaler
  397 + *
  398 + * The Divider for PTA (refresh timer) configuration is based on an
  399 + * example SDRAM configuration (64 MBit, one bank). The adjustment to
  400 + * the number of chip selects (NCS) and the actually needed refresh
  401 + * rate is done by setting MPTPR.
  402 + *
  403 + * PTA is calculated from
  404 + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
  405 + *
  406 + * gclk CPU clock (not bus clock!)
  407 + * Trefresh Refresh cycle * 4 (four word bursts used)
  408 + *
  409 + * 4096 Rows from SDRAM example configuration
  410 + * 1000 factor s -> ms
  411 + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
  412 + * 4 Number of refresh cycles per period
  413 + * 64 Refresh cycle in ms per number of rows
  414 + * --------------------------------------------
  415 + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
  416 + *
  417 + * 50 MHz => 50.000.000 / Divider = 98
  418 + * 66 Mhz => 66.000.000 / Divider = 129
  419 + * 80 Mhz => 80.000.000 / Divider = 156
  420 + */
  421 +#if defined(CONFIG_80MHz)
  422 +#define CFG_MAMR_PTA 156
  423 +#elif defined(CONFIG_66MHz)
  424 +#define CFG_MAMR_PTA 129
  425 +#else /* 50 MHz */
  426 +#define CFG_MAMR_PTA 98
  427 +#endif /*CONFIG_??MHz */
  428 +
  429 +/*
  430 + * For 16 MBit, refresh rates could be 31.3 us
  431 + * (= 64 ms / 2K = 125 / quad bursts).
  432 + * For a simpler initialization, 15.6 us is used instead.
  433 + *
  434 + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
  435 + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
  436 + */
  437 +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
  438 +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
  439 +
  440 +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
  441 +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
  442 +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
  443 +
  444 +/*
  445 + * MAMR settings for SDRAM
  446 + */
  447 +
  448 +/* 8 column SDRAM */
  449 +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
  450 + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
  451 + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
  452 +/* 9 column SDRAM */
  453 +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
  454 + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
  455 + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
  456 +
  457 +
  458 +/*
  459 + * Internal Definitions
  460 + *
  461 + * Boot Flags
  462 + */
  463 +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  464 +#define BOOTFLAG_WARM 0x02 /* Software reboot */
  465 +
  466 +#endif /* __CONFIG_H */
include/configs/TQM855L.h
Diff comments   View file @ f12e568
1 1 /*
2   - * (C) Copyright 2000, 2001, 2002
  2 + * (C) Copyright 2000-2003
3 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 4 *
5 5 * See file CREDITS for list of people who contributed to this
... ... @@ -253,7 +253,7 @@
253 253 #ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
254 254 #define CFG_PLPRCR \
255 255 ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
256   -#else /* up to 50 MHz we use a 1:1 clock */
  256 +#else /* up to 66 MHz we use a 1:1 clock */
257 257 #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
258 258 #endif /* CONFIG_80MHz */
259 259  
... ... @@ -269,7 +269,7 @@
269 269 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
270 270 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
271 271 SCCR_DFALCD00)
272   -#else /* up to 50 MHz we use a 1:1 clock */
  272 +#else /* up to 66 MHz we use a 1:1 clock */
273 273 #define CFG_SCCR (SCCR_TBS | \
274 274 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
275 275 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
include/configs/TQM855M.h
Diff comments   View file @ f12e568
  1 +/*
  2 + * (C) Copyright 2000-2003
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +/*
  25 + * board/config.h - configuration options, board specific
  26 + */
  27 +
  28 +#ifndef __CONFIG_H
  29 +#define __CONFIG_H
  30 +
  31 +/*
  32 + * High Level Configuration Options
  33 + * (easy to change)
  34 + */
  35 +
  36 +#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
  37 +#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */
  38 +
  39 +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
  40 +#undef CONFIG_8xx_CONS_SMC2
  41 +#undef CONFIG_8xx_CONS_NONE
  42 +
  43 +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
  44 +
  45 +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  46 +
  47 +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
  48 +
  49 +#define CONFIG_BOARD_TYPES 1 /* support board types */
  50 +
  51 +#define CONFIG_PREBOOT "echo;" \
  52 + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
  53 + "echo"
  54 +
  55 +#undef CONFIG_BOOTARGS
  56 +
  57 +#define CONFIG_EXTRA_ENV_SETTINGS \
  58 + "netdev=eth0\0" \
  59 + "nfsargs=setenv bootargs root=/dev/nfs rw " \
  60 + "nfsroot=$(serverip):$(rootpath)\0" \
  61 + "ramargs=setenv bootargs root=/dev/ram rw\0" \
  62 + "addip=setenv bootargs $(bootargs) " \
  63 + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
  64 + ":$(hostname):$(netdev):off panic=1\0" \
  65 + "flash_nfs=run nfsargs addip;" \
  66 + "bootm $(kernel_addr)\0" \
  67 + "flash_self=run ramargs addip;" \
  68 + "bootm $(kernel_addr) $(ramdisk_addr)\0" \
  69 + "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
  70 + "rootpath=/opt/eldk/ppc_8xx\0" \
  71 + "bootfile=/tftpboot/TQM855M/uImage\0" \
  72 + "kernel_addr=40080000\0" \
  73 + "ramdisk_addr=40180000\0" \
  74 + ""
  75 +#define CONFIG_BOOTCOMMAND "run flash_self"
  76 +
  77 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  78 +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
  79 +
  80 +#undef CONFIG_WATCHDOG /* watchdog disabled */
  81 +
  82 +#define CONFIG_STATUS_LED 1 /* Status LED enabled */
  83 +
  84 +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
  85 +
  86 +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
  87 +
  88 +#define CONFIG_MAC_PARTITION
  89 +#define CONFIG_DOS_PARTITION
  90 +
  91 +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
  92 +
  93 +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
  94 + CFG_CMD_ASKENV | \
  95 + CFG_CMD_DHCP | \
  96 + CFG_CMD_IDE | \
  97 + CFG_CMD_DATE )
  98 +
  99 +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  100 +#include <cmd_confdefs.h>
  101 +
  102 +/*
  103 + * Miscellaneous configurable options
  104 + */
  105 +#define CFG_LONGHELP /* undef to save memory */
  106 +#define CFG_PROMPT "=> " /* Monitor Command Prompt */
  107 +
  108 +#if 0
  109 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
  110 +#endif
  111 +#ifdef CFG_HUSH_PARSER
  112 +#define CFG_PROMPT_HUSH_PS2 "> "
  113 +#endif
  114 +
  115 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  116 +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  117 +#else
  118 +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  119 +#endif
  120 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  121 +#define CFG_MAXARGS 16 /* max number of command args */
  122 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  123 +
  124 +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
  125 +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  126 +
  127 +#define CFG_LOAD_ADDR 0x100000 /* default load address */
  128 +
  129 +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  130 +
  131 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  132 +
  133 +/*
  134 + * Low Level Configuration Settings
  135 + * (address mappings, register initial values, etc.)
  136 + * You should know what you are doing if you make changes here.
  137 + */
  138 +/*-----------------------------------------------------------------------
  139 + * Internal Memory Mapped Register
  140 + */
  141 +#define CFG_IMMR 0xFFF00000
  142 +
  143 +/*-----------------------------------------------------------------------
  144 + * Definitions for initial stack pointer and data area (in DPRAM)
  145 + */
  146 +#define CFG_INIT_RAM_ADDR CFG_IMMR
  147 +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
  148 +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
  149 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  150 +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  151 +
  152 +/*-----------------------------------------------------------------------
  153 + * Start addresses for the final memory configuration
  154 + * (Set up by the startup code)
  155 + * Please note that CFG_SDRAM_BASE _must_ start at 0
  156 + */
  157 +#define CFG_SDRAM_BASE 0x00000000
  158 +#define CFG_FLASH_BASE 0x40000000
  159 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  160 +#define CFG_MONITOR_BASE CFG_FLASH_BASE
  161 +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  162 +
  163 +/*
  164 + * For booting Linux, the board info and command line data
  165 + * have to be in the first 8 MB of memory, since this is
  166 + * the maximum mapped by the Linux kernel during initialization.
  167 + */
  168 +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  169 +
  170 +/*-----------------------------------------------------------------------
  171 + * FLASH organization
  172 + */
  173 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
  174 +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  175 +
  176 +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  177 +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  178 +
  179 +#define CFG_ENV_IS_IN_FLASH 1
  180 +#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
  181 +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
  182 +#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
  183 +
  184 +/* Address and size of Redundant Environment Sector */
  185 +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
  186 +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
  187 +
  188 +/*-----------------------------------------------------------------------
  189 + * Hardware Information Block
  190 + */
  191 +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
  192 +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
  193 +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
  194 +
  195 +/*-----------------------------------------------------------------------
  196 + * Cache Configuration
  197 + */
  198 +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
  199 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  200 +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
  201 +#endif
  202 +
  203 +/*-----------------------------------------------------------------------
  204 + * SYPCR - System Protection Control 11-9
  205 + * SYPCR can only be written once after reset!
  206 + *-----------------------------------------------------------------------
  207 + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  208 + */
  209 +#if defined(CONFIG_WATCHDOG)
  210 +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
  211 + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
  212 +#else
  213 +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
  214 +#endif
  215 +
  216 +/*-----------------------------------------------------------------------
  217 + * SIUMCR - SIU Module Configuration 11-6
  218 + *-----------------------------------------------------------------------
  219 + * PCMCIA config., multi-function pin tri-state
  220 + */
  221 +#ifndef CONFIG_CAN_DRIVER
  222 +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
  223 +#else /* we must activate GPL5 in the SIUMCR for CAN */
  224 +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
  225 +#endif /* CONFIG_CAN_DRIVER */
  226 +
  227 +/*-----------------------------------------------------------------------
  228 + * TBSCR - Time Base Status and Control 11-26
  229 + *-----------------------------------------------------------------------
  230 + * Clear Reference Interrupt Status, Timebase freezing enabled
  231 + */
  232 +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
  233 +
  234 +/*-----------------------------------------------------------------------
  235 + * RTCSC - Real-Time Clock Status and Control Register 11-27
  236 + *-----------------------------------------------------------------------
  237 + */
  238 +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
  239 +
  240 +/*-----------------------------------------------------------------------
  241 + * PISCR - Periodic Interrupt Status and Control 11-31
  242 + *-----------------------------------------------------------------------
  243 + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  244 + */
  245 +#define CFG_PISCR (PISCR_PS | PISCR_PITF)
  246 +
  247 +/*-----------------------------------------------------------------------
  248 + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
  249 + *-----------------------------------------------------------------------
  250 + * Reset PLL lock status sticky bit, timer expired status bit and timer
  251 + * interrupt status bit
  252 + *
  253 + * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
  254 + */
  255 +#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
  256 +#define CFG_PLPRCR \
  257 + ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
  258 +#else /* up to 66 MHz we use a 1:1 clock */
  259 +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
  260 +#endif /* CONFIG_80MHz */
  261 +
  262 +/*-----------------------------------------------------------------------
  263 + * SCCR - System Clock and reset Control Register 15-27
  264 + *-----------------------------------------------------------------------
  265 + * Set clock output, timebase and RTC source and divider,
  266 + * power management and some other internal clocks
  267 + */
  268 +#define SCCR_MASK SCCR_EBDF11
  269 +#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
  270 +#define CFG_SCCR (/* SCCR_TBS | */ \
  271 + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
  272 + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
  273 + SCCR_DFALCD00)
  274 +#else /* up to 66 MHz we use a 1:1 clock */
  275 +#define CFG_SCCR (SCCR_TBS | \
  276 + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
  277 + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
  278 + SCCR_DFALCD00)
  279 +#endif /* CONFIG_80MHz */
  280 +
  281 +/*-----------------------------------------------------------------------
  282 + * PCMCIA stuff
  283 + *-----------------------------------------------------------------------
  284 + *
  285 + */
  286 +#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
  287 +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
  288 +#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
  289 +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
  290 +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
  291 +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
  292 +#define CFG_PCMCIA_IO_ADDR (0xEC000000)
  293 +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
  294 +
  295 +/*-----------------------------------------------------------------------
  296 + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
  297 + *-----------------------------------------------------------------------
  298 + */
  299 +
  300 +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
  301 +
  302 +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
  303 +#undef CONFIG_IDE_LED /* LED for ide not supported */
  304 +#undef CONFIG_IDE_RESET /* reset for ide not supported */
  305 +
  306 +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
  307 +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
  308 +
  309 +#define CFG_ATA_IDE0_OFFSET 0x0000
  310 +
  311 +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
  312 +
  313 +/* Offset for data I/O */
  314 +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
  315 +
  316 +/* Offset for normal register accesses */
  317 +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
  318 +
  319 +/* Offset for alternate registers */
  320 +#define CFG_ATA_ALT_OFFSET 0x0100
  321 +
  322 +/*-----------------------------------------------------------------------
  323 + *
  324 + *-----------------------------------------------------------------------
  325 + *
  326 + */
  327 +#define CFG_DER 0
  328 +
  329 +/*
  330 + * Init Memory Controller:
  331 + *
  332 + * BR0/1 and OR0/1 (FLASH)
  333 + */
  334 +
  335 +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
  336 +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
  337 +
  338 +/* used to re-map FLASH both when starting from SRAM or FLASH:
  339 + * restrict access enough to keep SRAM working (if any)
  340 + * but not too much to meddle with FLASH accesses
  341 + */
  342 +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
  343 +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
  344 +
  345 +/*
  346 + * FLASH timing:
  347 + */
  348 +#if defined(CONFIG_80MHz)
  349 +/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
  350 +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
  351 + OR_SCY_3_CLK | OR_EHTR | OR_BI)
  352 +#elif defined(CONFIG_66MHz)
  353 +/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
  354 +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
  355 + OR_SCY_3_CLK | OR_EHTR | OR_BI)
  356 +#else /* 50 MHz */
  357 +/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
  358 +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
  359 + OR_SCY_2_CLK | OR_EHTR | OR_BI)
  360 +#endif /*CONFIG_??MHz */
  361 +
  362 +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
  363 +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
  364 +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
  365 +
  366 +#define CFG_OR1_REMAP CFG_OR0_REMAP
  367 +#define CFG_OR1_PRELIM CFG_OR0_PRELIM
  368 +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
  369 +
  370 +/*
  371 + * BR2/3 and OR2/3 (SDRAM)
  372 + *
  373 + */
  374 +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
  375 +#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
  376 +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
  377 +
  378 +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
  379 +#define CFG_OR_TIMING_SDRAM 0x00000A00
  380 +
  381 +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
  382 +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
  383 +
  384 +#ifndef CONFIG_CAN_DRIVER
  385 +#define CFG_OR3_PRELIM CFG_OR2_PRELIM
  386 +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
  387 +#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
  388 +#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
  389 +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
  390 +#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
  391 +#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
  392 + BR_PS_8 | BR_MS_UPMB | BR_V )
  393 +#endif /* CONFIG_CAN_DRIVER */
  394 +
  395 +/*
  396 + * Memory Periodic Timer Prescaler
  397 + *
  398 + * The Divider for PTA (refresh timer) configuration is based on an
  399 + * example SDRAM configuration (64 MBit, one bank). The adjustment to
  400 + * the number of chip selects (NCS) and the actually needed refresh
  401 + * rate is done by setting MPTPR.
  402 + *
  403 + * PTA is calculated from
  404 + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
  405 + *
  406 + * gclk CPU clock (not bus clock!)
  407 + * Trefresh Refresh cycle * 4 (four word bursts used)
  408 + *
  409 + * 4096 Rows from SDRAM example configuration
  410 + * 1000 factor s -> ms
  411 + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
  412 + * 4 Number of refresh cycles per period
  413 + * 64 Refresh cycle in ms per number of rows
  414 + * --------------------------------------------
  415 + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
  416 + *
  417 + * 50 MHz => 50.000.000 / Divider = 98
  418 + * 66 Mhz => 66.000.000 / Divider = 129
  419 + * 80 Mhz => 80.000.000 / Divider = 156
  420 + */
  421 +#if defined(CONFIG_80MHz)
  422 +#define CFG_MAMR_PTA 156
  423 +#elif defined(CONFIG_66MHz)
  424 +#define CFG_MAMR_PTA 129
  425 +#else /* 50 MHz */
  426 +#define CFG_MAMR_PTA 98
  427 +#endif /*CONFIG_??MHz */
  428 +
  429 +/*
  430 + * For 16 MBit, refresh rates could be 31.3 us
  431 + * (= 64 ms / 2K = 125 / quad bursts).
  432 + * For a simpler initialization, 15.6 us is used instead.
  433 + *
  434 + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
  435 + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
  436 + */
  437 +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
  438 +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
  439 +
  440 +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
  441 +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
  442 +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
  443 +
  444 +/*
  445 + * MAMR settings for SDRAM
  446 + */
  447 +
  448 +/* 8 column SDRAM */
  449 +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
  450 + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
  451 + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
  452 +/* 9 column SDRAM */
  453 +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
  454 + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
  455 + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
  456 +
  457 +
  458 +/*
  459 + * Internal Definitions
  460 + *
  461 + * Boot Flags
  462 + */
  463 +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  464 +#define BOOTFLAG_WARM 0x02 /* Software reboot */
  465 +
  466 +#define CONFIG_SCC1_ENET
  467 +#define CONFIG_FEC_ENET
  468 +#define CONFIG_ETHPRIME "SCC ETHERNET"
  469 +
  470 +#endif /* __CONFIG_H */
include/configs/TQM860L.h
Diff comments   View file @ f12e568
1 1 /*
2   - * (C) Copyright 2000, 2001, 2002
  2 + * (C) Copyright 2000-2003
3 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 4 *
5 5 * See file CREDITS for list of people who contributed to this
... ... @@ -254,7 +254,7 @@
254 254 #ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
255 255 #define CFG_PLPRCR \
256 256 ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
257   -#else /* up to 50 MHz we use a 1:1 clock */
  257 +#else /* up to 66 MHz we use a 1:1 clock */
258 258 #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
259 259 #endif /* CONFIG_80MHz */
260 260  
... ... @@ -270,7 +270,7 @@
270 270 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
271 271 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
272 272 SCCR_DFALCD00)
273   -#else /* up to 50 MHz we use a 1:1 clock */
  273 +#else /* up to 66 MHz we use a 1:1 clock */
274 274 #define CFG_SCCR (SCCR_TBS | \
275 275 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
276 276 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
include/configs/TQM860M.h
Diff comments   View file @ f12e568
  1 +/*
  2 + * (C) Copyright 2000-2003
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +/*
  25 + * board/config.h - configuration options, board specific
  26 + */
  27 +
  28 +#ifndef __CONFIG_H
  29 +#define __CONFIG_H
  30 +
  31 +/*
  32 + * High Level Configuration Options
  33 + * (easy to change)
  34 + */
  35 +
  36 +#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
  37 +#define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */
  38 +
  39 +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
  40 +#undef CONFIG_8xx_CONS_SMC2
  41 +#undef CONFIG_8xx_CONS_NONE
  42 +
  43 +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
  44 +
  45 +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  46 +
  47 +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
  48 +
  49 +#define CONFIG_BOARD_TYPES 1 /* support board types */
  50 +
  51 +#define CONFIG_PREBOOT "echo;" \
  52 + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
  53 + "echo"
  54 +
  55 +#undef CONFIG_BOOTARGS
  56 +
  57 +#define CONFIG_EXTRA_ENV_SETTINGS \
  58 + "netdev=eth0\0" \
  59 + "nfsargs=setenv bootargs root=/dev/nfs rw " \
  60 + "nfsroot=$(serverip):$(rootpath)\0" \
  61 + "ramargs=setenv bootargs root=/dev/ram rw\0" \
  62 + "addip=setenv bootargs $(bootargs) " \
  63 + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
  64 + ":$(hostname):$(netdev):off panic=1\0" \
  65 + "flash_nfs=run nfsargs addip;" \
  66 + "bootm $(kernel_addr)\0" \
  67 + "flash_self=run ramargs addip;" \
  68 + "bootm $(kernel_addr) $(ramdisk_addr)\0" \
  69 + "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
  70 + "rootpath=/opt/eldk/ppc_8xx\0" \
  71 + "bootfile=/tftpboot/TQM860M/uImage\0" \
  72 + "kernel_addr=40080000\0" \
  73 + "ramdisk_addr=40180000\0" \
  74 + ""
  75 +#define CONFIG_BOOTCOMMAND "run flash_self"
  76 +
  77 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  78 +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
  79 +
  80 +#undef CONFIG_WATCHDOG /* watchdog disabled */
  81 +
  82 +#define CONFIG_STATUS_LED 1 /* Status LED enabled */
  83 +
  84 +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
  85 +
  86 +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
  87 +
  88 +#define CONFIG_MAC_PARTITION
  89 +#define CONFIG_DOS_PARTITION
  90 +
  91 +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
  92 +
  93 +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
  94 + CFG_CMD_ASKENV | \
  95 + CFG_CMD_DHCP | \
  96 + CFG_CMD_ELF | \
  97 + CFG_CMD_IDE | \
  98 + CFG_CMD_DATE )
  99 +
  100 +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  101 +#include <cmd_confdefs.h>
  102 +
  103 +/*
  104 + * Miscellaneous configurable options
  105 + */
  106 +#define CFG_LONGHELP /* undef to save memory */
  107 +#define CFG_PROMPT "=> " /* Monitor Command Prompt */
  108 +
  109 +#if 0
  110 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
  111 +#endif
  112 +#ifdef CFG_HUSH_PARSER
  113 +#define CFG_PROMPT_HUSH_PS2 "> "
  114 +#endif
  115 +
  116 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  117 +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  118 +#else
  119 +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  120 +#endif
  121 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  122 +#define CFG_MAXARGS 16 /* max number of command args */
  123 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  124 +
  125 +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
  126 +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  127 +
  128 +#define CFG_LOAD_ADDR 0x100000 /* default load address */
  129 +
  130 +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  131 +
  132 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  133 +
  134 +/*
  135 + * Low Level Configuration Settings
  136 + * (address mappings, register initial values, etc.)
  137 + * You should know what you are doing if you make changes here.
  138 + */
  139 +/*-----------------------------------------------------------------------
  140 + * Internal Memory Mapped Register
  141 + */
  142 +#define CFG_IMMR 0xFFF00000
  143 +
  144 +/*-----------------------------------------------------------------------
  145 + * Definitions for initial stack pointer and data area (in DPRAM)
  146 + */
  147 +#define CFG_INIT_RAM_ADDR CFG_IMMR
  148 +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
  149 +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
  150 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  151 +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  152 +
  153 +/*-----------------------------------------------------------------------
  154 + * Start addresses for the final memory configuration
  155 + * (Set up by the startup code)
  156 + * Please note that CFG_SDRAM_BASE _must_ start at 0
  157 + */
  158 +#define CFG_SDRAM_BASE 0x00000000
  159 +#define CFG_FLASH_BASE 0x40000000
  160 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  161 +#define CFG_MONITOR_BASE CFG_FLASH_BASE
  162 +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  163 +
  164 +/*
  165 + * For booting Linux, the board info and command line data
  166 + * have to be in the first 8 MB of memory, since this is
  167 + * the maximum mapped by the Linux kernel during initialization.
  168 + */
  169 +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  170 +
  171 +/*-----------------------------------------------------------------------
  172 + * FLASH organization
  173 + */
  174 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
  175 +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  176 +
  177 +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  178 +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  179 +
  180 +#define CFG_ENV_IS_IN_FLASH 1
  181 +#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
  182 +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
  183 +#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
  184 +
  185 +/* Address and size of Redundant Environment Sector */
  186 +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
  187 +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
  188 +
  189 +/*-----------------------------------------------------------------------
  190 + * Hardware Information Block
  191 + */
  192 +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
  193 +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
  194 +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
  195 +
  196 +/*-----------------------------------------------------------------------
  197 + * Cache Configuration
  198 + */
  199 +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
  200 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  201 +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
  202 +#endif
  203 +
  204 +/*-----------------------------------------------------------------------
  205 + * SYPCR - System Protection Control 11-9
  206 + * SYPCR can only be written once after reset!
  207 + *-----------------------------------------------------------------------
  208 + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  209 + */
  210 +#if defined(CONFIG_WATCHDOG)
  211 +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
  212 + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
  213 +#else
  214 +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
  215 +#endif
  216 +
  217 +/*-----------------------------------------------------------------------
  218 + * SIUMCR - SIU Module Configuration 11-6
  219 + *-----------------------------------------------------------------------
  220 + * PCMCIA config., multi-function pin tri-state
  221 + */
  222 +#ifndef CONFIG_CAN_DRIVER
  223 +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
  224 +#else /* we must activate GPL5 in the SIUMCR for CAN */
  225 +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
  226 +#endif /* CONFIG_CAN_DRIVER */
  227 +
  228 +/*-----------------------------------------------------------------------
  229 + * TBSCR - Time Base Status and Control 11-26
  230 + *-----------------------------------------------------------------------
  231 + * Clear Reference Interrupt Status, Timebase freezing enabled
  232 + */
  233 +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
  234 +
  235 +/*-----------------------------------------------------------------------
  236 + * RTCSC - Real-Time Clock Status and Control Register 11-27
  237 + *-----------------------------------------------------------------------
  238 + */
  239 +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
  240 +
  241 +/*-----------------------------------------------------------------------
  242 + * PISCR - Periodic Interrupt Status and Control 11-31
  243 + *-----------------------------------------------------------------------
  244 + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  245 + */
  246 +#define CFG_PISCR (PISCR_PS | PISCR_PITF)
  247 +
  248 +/*-----------------------------------------------------------------------
  249 + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
  250 + *-----------------------------------------------------------------------
  251 + * Reset PLL lock status sticky bit, timer expired status bit and timer
  252 + * interrupt status bit
  253 + *
  254 + * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
  255 + */
  256 +#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
  257 +#define CFG_PLPRCR \
  258 + ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
  259 +#else /* up to 66 MHz we use a 1:1 clock */
  260 +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
  261 +#endif /* CONFIG_80MHz */
  262 +
  263 +/*-----------------------------------------------------------------------
  264 + * SCCR - System Clock and reset Control Register 15-27
  265 + *-----------------------------------------------------------------------
  266 + * Set clock output, timebase and RTC source and divider,
  267 + * power management and some other internal clocks
  268 + */
  269 +#define SCCR_MASK SCCR_EBDF11
  270 +#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
  271 +#define CFG_SCCR (/* SCCR_TBS | */ \
  272 + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
  273 + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
  274 + SCCR_DFALCD00)
  275 +#else /* up to 66 MHz we use a 1:1 clock */
  276 +#define CFG_SCCR (SCCR_TBS | \
  277 + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
  278 + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
  279 + SCCR_DFALCD00)
  280 +#endif /* CONFIG_80MHz */
  281 +
  282 +/*-----------------------------------------------------------------------
  283 + * PCMCIA stuff
  284 + *-----------------------------------------------------------------------
  285 + *
  286 + */
  287 +#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
  288 +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
  289 +#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
  290 +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
  291 +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
  292 +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
  293 +#define CFG_PCMCIA_IO_ADDR (0xEC000000)
  294 +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
  295 +
  296 +/*-----------------------------------------------------------------------
  297 + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
  298 + *-----------------------------------------------------------------------
  299 + */
  300 +
  301 +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
  302 +
  303 +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
  304 +#undef CONFIG_IDE_LED /* LED for ide not supported */
  305 +#undef CONFIG_IDE_RESET /* reset for ide not supported */
  306 +
  307 +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
  308 +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
  309 +
  310 +#define CFG_ATA_IDE0_OFFSET 0x0000
  311 +
  312 +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
  313 +
  314 +/* Offset for data I/O */
  315 +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
  316 +
  317 +/* Offset for normal register accesses */
  318 +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
  319 +
  320 +/* Offset for alternate registers */
  321 +#define CFG_ATA_ALT_OFFSET 0x0100
  322 +
  323 +/*-----------------------------------------------------------------------
  324 + *
  325 + *-----------------------------------------------------------------------
  326 + *
  327 + */
  328 +#define CFG_DER 0
  329 +
  330 +/*
  331 + * Init Memory Controller:
  332 + *
  333 + * BR0/1 and OR0/1 (FLASH)
  334 + */
  335 +
  336 +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
  337 +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
  338 +
  339 +/* used to re-map FLASH both when starting from SRAM or FLASH:
  340 + * restrict access enough to keep SRAM working (if any)
  341 + * but not too much to meddle with FLASH accesses
  342 + */
  343 +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
  344 +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
  345 +
  346 +/*
  347 + * FLASH timing:
  348 + */
  349 +#if defined(CONFIG_80MHz)
  350 +/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
  351 +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
  352 + OR_SCY_3_CLK | OR_EHTR | OR_BI)
  353 +#elif defined(CONFIG_66MHz)
  354 +/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
  355 +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
  356 + OR_SCY_3_CLK | OR_EHTR | OR_BI)
  357 +#else /* 50 MHz */
  358 +/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
  359 +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
  360 + OR_SCY_2_CLK | OR_EHTR | OR_BI)
  361 +#endif /*CONFIG_??MHz */
  362 +
  363 +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
  364 +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
  365 +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
  366 +
  367 +#define CFG_OR1_REMAP CFG_OR0_REMAP
  368 +#define CFG_OR1_PRELIM CFG_OR0_PRELIM
  369 +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
  370 +
  371 +/*
  372 + * BR2/3 and OR2/3 (SDRAM)
  373 + *
  374 + */
  375 +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
  376 +#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
  377 +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
  378 +
  379 +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
  380 +#define CFG_OR_TIMING_SDRAM 0x00000A00
  381 +
  382 +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
  383 +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
  384 +
  385 +#ifndef CONFIG_CAN_DRIVER
  386 +#define CFG_OR3_PRELIM CFG_OR2_PRELIM
  387 +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
  388 +#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
  389 +#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
  390 +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
  391 +#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
  392 +#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
  393 + BR_PS_8 | BR_MS_UPMB | BR_V )
  394 +#endif /* CONFIG_CAN_DRIVER */
  395 +
  396 +/*
  397 + * Memory Periodic Timer Prescaler
  398 + *
  399 + * The Divider for PTA (refresh timer) configuration is based on an
  400 + * example SDRAM configuration (64 MBit, one bank). The adjustment to
  401 + * the number of chip selects (NCS) and the actually needed refresh
  402 + * rate is done by setting MPTPR.
  403 + *
  404 + * PTA is calculated from
  405 + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
  406 + *
  407 + * gclk CPU clock (not bus clock!)
  408 + * Trefresh Refresh cycle * 4 (four word bursts used)
  409 + *
  410 + * 4096 Rows from SDRAM example configuration
  411 + * 1000 factor s -> ms
  412 + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
  413 + * 4 Number of refresh cycles per period
  414 + * 64 Refresh cycle in ms per number of rows
  415 + * --------------------------------------------
  416 + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
  417 + *
  418 + * 50 MHz => 50.000.000 / Divider = 98
  419 + * 66 Mhz => 66.000.000 / Divider = 129
  420 + * 80 Mhz => 80.000.000 / Divider = 156
  421 + */
  422 +#if defined(CONFIG_80MHz)
  423 +#define CFG_MAMR_PTA 156
  424 +#elif defined(CONFIG_66MHz)
  425 +#define CFG_MAMR_PTA 129
  426 +#else /* 50 MHz */
  427 +#define CFG_MAMR_PTA 98
  428 +#endif /*CONFIG_??MHz */
  429 +
  430 +/*
  431 + * For 16 MBit, refresh rates could be 31.3 us
  432 + * (= 64 ms / 2K = 125 / quad bursts).
  433 + * For a simpler initialization, 15.6 us is used instead.
  434 + *
  435 + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
  436 + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
  437 + */
  438 +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
  439 +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
  440 +
  441 +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
  442 +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
  443 +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
  444 +
  445 +/*
  446 + * MAMR settings for SDRAM
  447 + */
  448 +
  449 +/* 8 column SDRAM */
  450 +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
  451 + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
  452 + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
  453 +/* 9 column SDRAM */
  454 +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
  455 + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
  456 + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
  457 +
  458 +
  459 +/*
  460 + * Internal Definitions
  461 + *
  462 + * Boot Flags
  463 + */
  464 +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  465 +#define BOOTFLAG_WARM 0x02 /* Software reboot */
  466 +
  467 +#define CONFIG_SCC1_ENET
  468 +#define CONFIG_FEC_ENET
  469 +#define CONFIG_ETHPRIME "SCC ETHERNET"
  470 +
  471 +#endif /* __CONFIG_H */
include/configs/TQM862L.h
Diff comments   View file @ f12e568
1 1 /*
2   - * (C) Copyright 2000, 2001, 2002
  2 + * (C) Copyright 2000-2003
3 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 4 *
5 5 * See file CREDITS for list of people who contributed to this
... ... @@ -258,7 +258,7 @@
258 258 #if defined(CONFIG_80MHz) || defined(CONFIG_100MHz)
259 259 #define CFG_PLPRCR \
260 260 ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
261   -#else /* up to 50 MHz we use a 1:1 clock */
  261 +#else /* up to 66 MHz we use a 1:1 clock */
262 262 #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
263 263 #endif /* CONFIG_80MHz | CONFIG_100MHz */
264 264  
... ... @@ -274,7 +274,7 @@
274 274 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
275 275 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
276 276 SCCR_DFALCD00)
277   -#else /* up to 50 MHz we use a 1:1 clock */
  277 +#else /* up to 66 MHz we use a 1:1 clock */
278 278 #define CFG_SCCR (SCCR_TBS | \
279 279 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
280 280 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
include/configs/TQM862M.h
Diff comments   View file @ f12e568
1 1 /*
2   - * (C) Copyright 2000, 2001, 2002
  2 + * (C) Copyright 2000-2003
3 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 4 *
5 5 * See file CREDITS for list of people who contributed to this
... ... @@ -260,7 +260,7 @@
260 260 #if defined(CONFIG_80MHz) || defined(CONFIG_100MHz)
261 261 #define CFG_PLPRCR \
262 262 ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
263   -#else /* up to 50 MHz we use a 1:1 clock */
  263 +#else /* up to 66 MHz we use a 1:1 clock */
264 264 #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
265 265 #endif /* CONFIG_80MHz | CONFIG_100MHz */
266 266  
... ... @@ -276,7 +276,7 @@
276 276 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
277 277 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
278 278 SCCR_DFALCD00)
279   -#else /* up to 50 MHz we use a 1:1 clock */
  279 +#else /* up to 66 MHz we use a 1:1 clock */
280 280 #define CFG_SCCR (SCCR_TBS | \
281 281 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
282 282 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
include/configs/lwmon.h
Diff comments   View file @ f12e568
... ... @@ -189,9 +189,9 @@
189 189 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
190 190  
191 191 #define CFG_HUSH_PARSER 1 /* use "hush" command parser */
192   -#endif
193 192 #ifdef CFG_HUSH_PARSER
194 193 #define CFG_PROMPT_HUSH_PS2 "> "
  194 +#endif
195 195  
196 196 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
197 197 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
... ... @@ -160,6 +160,8 @@
160 160  
161 161 #define AMD_ID_DL640 0x227E227E /* 29DL640D ID (64 M, dual boot sectors)*/
162 162 #define AMD_ID_MIRROR 0x227E227E /* 1st ID word for MirrorBit family */
  163 +#define AMD_ID_LV640U_2 0x220C220C /* 2d ID word for AM29LV640M at 0x38 */
  164 +#define AMD_ID_LV640U_3 0x22012201 /* 3d ID word for AM29LV640M at 0x3c */
163 165 #define AMD_ID_LV128U_2 0x22122212 /* 2d ID word for AM29LV128M at 0x38 */
164 166 #define AMD_ID_LV128U_3 0x22002200 /* 3d ID word for AM29LV128M at 0x3c */
165 167  
... ... @@ -314,7 +316,9 @@
314 316 #define FLASH_28F320C3B 0x009F /* Intel 28F320C3B ( 32M = 2M x 16 ) */
315 317 #define FLASH_28F640C3T 0x00A0 /* Intel 28F640C3T ( 64M = 4M x 16 ) */
316 318 #define FLASH_28F640C3B 0x00A1 /* Intel 28F640C3B ( 64M = 4M x 16 ) */
317   -#define FLASH_AMLV128U 0x00A2 /* AMD 29LV128M ( 128M = 8M x 16 ) */
  319 +#define FLASH_AMLV320U 0x00A2 /* AMD 29LV128M ( 128M = 8M x 16 ) */
  320 +#define FLASH_AMLV640U 0x00A4 /* AMD 29LV640M ( 64M = 4M x 16 ) */
  321 +#define FLASH_AMLV128U 0x00A6 /* AMD 29LV128M ( 128M = 8M x 16 ) */
318 322  
319 323 #define FLASH_UNKNOWN 0xFFFF /* unknown flash type */
320 324