arc: introduce U-Boot port for ARCv2 ISA

ARC HS and ARC EM are new cores based on ARCv2 ISA which is binary incompatible with ISAv1 (AKA ARCompact). Significant difference between ISAv2 and v1 is implementation of interrupt vector table. In v1 it is implemented in the same way as on many other architectures - as a special location where user may put whether code executed in place (if machine word of space is enough) or jump to a full-scale interrupt handler. In v2 interrupt table is just an array of adresses of real interrupt handlers. That requires a separate section for IVT that is not encoded as code by assembler. This change adds support for following cores: * ARC EM6 (simple 32-bit microcontroller without MMU) * ARC HS36 (advanced 32-bit microcontroller without MMU) * ARC HS38 (advanced 32-bit microcontroller with MMU) As a part of ARC HS38 new version of MMU (v4) was introduced. Also this change adds AXS131 board which is the same DW ARC SDP base board but with ARC HS38 CPU tile. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

arc: introduce U-Boot port for ARCv2 ISA
ARC HS and ARC EM are new cores based on ARCv2 ISA which is binary incompatible with ISAv1 (AKA ARCompact). Significant difference between ISAv2 and v1 is implementation of interrupt vector table. In v1 it is implemented in the same way as on many other architectures - as a special location where user may put whether code executed in place (if machine word of space is enough) or jump to a full-scale interrupt handler. In v2 interrupt table is just an array of adresses of real interrupt handlers. That requires a separate section for IVT that is not encoded as code by assembler. This change adds support for following cores: * ARC EM6 (simple 32-bit microcontroller without MMU) * ARC HS36 (advanced 32-bit microcontroller without MMU) * ARC HS38 (advanced 32-bit microcontroller with MMU) As a part of ARC HS38 new version of MMU (v4) was introduced. Also this change adds AXS131 board which is the same DW ARC SDP base board but with ARC HS38 CPU tile. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Alexey Brodkin
1 parent bd2a4888b1
Showing 6 changed files with 340 additions and 3 deletions Side-by-side Diff
arch/arc/Kconfig
arch/arc/config.mk
arch/arc/cpu/arcv2/Makefile
arch/arc/cpu/arcv2/start.S
arch/arc/include/asm/cache.h
configs/axs103_defconfig
@@ -8,31 +8,80 @@
 	default y
  
 config SYS_CPU
-	default "arcv1"
+	default "arcv1" if ISA_ARCOMPACT
+	default "arcv2" if ISA_ARCV2
  
 choice
+	prompt "ARC Instruction Set"
+	default ISA_ARCOMPACT
+
+config ISA_ARCOMPACT
+	bool "ARCompact ISA"
+	help
+	  The original ARC ISA of ARC600/700 cores
+
+config ISA_ARCV2
+	bool "ARC ISA v2"
+	help
+	  ISA for the Next Generation ARC-HS cores
+
+endchoice
+
+choice
 	prompt "CPU selection"
-	default CPU_ARC770D
+	default CPU_ARC770D if ISA_ARCOMPACT
+	default CPU_ARCHS38 if ISA_ARCV2
  
 config CPU_ARC750D
 	bool "ARC 750D"
 	select ARC_MMU_V2
+	depends on ISA_ARCOMPACT
 	help
 	  Choose this option to build an U-Boot for ARC750D CPU.
  
 config CPU_ARC770D
 	bool "ARC 770D"
 	select ARC_MMU_V3
+	depends on ISA_ARCOMPACT
 	help
 	  Choose this option to build an U-Boot for ARC770D CPU.
  
+config CPU_ARCEM6
+	bool "ARC EM6"
+	select ARC_MMU_ABSENT
+	depends on ISA_ARCV2
+	help
+	  Next Generation ARC Core based on ISA-v2 ISA without MMU.
+
+config CPU_ARCHS36
+	bool "ARC HS36"
+	select ARC_MMU_ABSENT
+	depends on ISA_ARCV2
+	help
+	  Next Generation ARC Core based on ISA-v2 ISA without MMU.
+
+config CPU_ARCHS38
+	bool "ARC HS38"
+	select ARC_MMU_V4
+	depends on ISA_ARCV2
+	help
+	  Next Generation ARC Core based on ISA-v2 ISA with MMU.
+
 endchoice
  
 choice
 	prompt "MMU Version"
 	default ARC_MMU_V3 if CPU_ARC770D
 	default ARC_MMU_V2 if CPU_ARC750D
+	default ARC_MMU_ABSENT if CPU_ARCEM6
+	default ARC_MMU_ABSENT if CPU_ARCHS36
+	default ARC_MMU_V4 if CPU_ARCHS38
  
+config ARC_MMU_ABSENT
+	bool "No MMU"
+	help
+	  No MMU
+
 config ARC_MMU_V2
 	bool "MMU v2"
 	depends on CPU_ARC750D
@@ -47,6 +96,12 @@
 	  Introduced with ARC700 4.10: New Features
 	  Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
 	  Shared Address Spaces (SASID)
+
+config ARC_MMU_V4
+	bool "MMU v4"
+	depends on CPU_ARCHS38
+	help
+	  Introduced as a part of ARC HS38 release.
  
 endchoice
  
@@ -38,6 +38,18 @@
 PLATFORM_CPPFLAGS += -marc700 -mlock -mswape
 endif
  
+ifdef CONFIG_CPU_ARCEM6
+PLATFORM_CPPFLAGS += -marcem
+endif
+
+ifdef CONFIG_CPU_ARCHS34
+PLATFORM_CPPFLAGS += -marchs
+endif
+
+ifdef CONFIG_CPU_ARCHS38
+PLATFORM_CPPFLAGS += -marchs
+endif
+
 PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2
  
 # Needed for relocation
+#
+# Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += start.o
+/*
+ * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/arcregs.h>
+
+/*
+ * Note on the LD/ST addressing modes with address register write-back
+ *
+ * LD.a same as LD.aw
+ *
+ * LD.a    reg1, [reg2, x]  => Pre Incr
+ *      Eff Addr for load = [reg2 + x]
+ *
+ * LD.ab   reg1, [reg2, x]  => Post Incr
+ *      Eff Addr for load = [reg2]
+ */
+
+.macro PUSH reg
+	st.a	\reg, [%sp, -4]
+.endm
+
+.macro PUSHAX aux
+	lr	%r9, [\aux]
+	PUSH	%r9
+.endm
+
+.macro  SAVE_R1_TO_R24
+	PUSH	%r1
+	PUSH	%r2
+	PUSH	%r3
+	PUSH	%r4
+	PUSH	%r5
+	PUSH	%r6
+	PUSH	%r7
+	PUSH	%r8
+	PUSH	%r9
+	PUSH	%r10
+	PUSH	%r11
+	PUSH	%r12
+	PUSH	%r13
+	PUSH	%r14
+	PUSH	%r15
+	PUSH	%r16
+	PUSH	%r17
+	PUSH	%r18
+	PUSH	%r19
+	PUSH	%r20
+	PUSH	%r21
+	PUSH	%r22
+	PUSH	%r23
+	PUSH	%r24
+.endm
+
+.macro SAVE_ALL_SYS
+	/* saving %r0 to reg->r0 in advance since weread %ecr into it */
+	st	%r0, [%sp, -8]
+	lr	%r0, [%ecr]	/* all stack addressing is manual so far */
+	st	%r0, [%sp]
+	st	%sp, [%sp, -4]
+	/* now move %sp to reg->r0 position so we can do "push" automatically */
+	sub	%sp, %sp, 8
+
+	SAVE_R1_TO_R24
+	PUSH	%r25
+	PUSH	%gp
+	PUSH	%fp
+	PUSH	%blink
+	PUSHAX	%eret
+	PUSHAX	%erstatus
+	PUSH	%lp_count
+	PUSHAX	%lp_end
+	PUSHAX	%lp_start
+	PUSHAX	%erbta
+.endm
+
+.macro SAVE_EXCEPTION_SOURCE
+#ifdef CONFIG_MMU
+	/* If MMU exists exception faulting address is loaded in EFA reg */
+	lr	%r0, [%efa]
+#else
+	/* Otherwise in ERET (exception return) reg */
+	lr	%r0, [%eret]
+#endif
+.endm
+
+.section .ivt, "a",@progbits
+.align 4
+	/* Critical system events */
+.word	_start			/* 0 - 0x000 */
+.word	memory_error		/* 1 - 0x008 */
+.word	instruction_error	/* 2 - 0x010 */
+
+	/* Exceptions */
+.word	EV_MachineCheck		/* 0x100, Fatal Machine check  (0x20) */
+.word	EV_TLBMissI		/* 0x108, Intruction TLB miss  (0x21) */
+.word	EV_TLBMissD		/* 0x110, Data TLB miss        (0x22) */
+.word	EV_TLBProtV		/* 0x118, Protection Violation (0x23)
+							or Misaligned Access  */
+.word	EV_PrivilegeV		/* 0x120, Privilege Violation  (0x24) */
+.word	EV_Trap			/* 0x128, Trap exception       (0x25) */
+.word	EV_Extension		/* 0x130, Extn Intruction Excp (0x26) */
+
+	/* Device interrupts */
+.rept	29
+	j	interrupt_handler	/* 3:31 - 0x018:0xF8 */
+.endr
+
+.text
+.globl _start
+_start:
+	/* Setup interrupt vector base that matches "__text_start" */
+	sr	__ivt_start, [ARC_AUX_INTR_VEC_BASE]
+
+	/* Setup stack pointer */
+	mov	%sp, CONFIG_SYS_INIT_SP_ADDR
+	mov	%fp, %sp
+
+	/* Clear bss */
+	mov	%r0, __bss_start
+	mov	%r1, __bss_end
+
+clear_bss:
+	st.ab	0, [%r0, 4]
+	brlt	%r0, %r1, clear_bss
+
+	/* Zero the one and only argument of "board_init_f" */
+	mov_s	%r0, 0
+	j	board_init_f
+
+memory_error:
+	SAVE_ALL_SYS
+	SAVE_EXCEPTION_SOURCE
+	mov	%r1, %sp
+	j	do_memory_error
+
+instruction_error:
+	SAVE_ALL_SYS
+	SAVE_EXCEPTION_SOURCE
+	mov	%r1, %sp
+	j	do_instruction_error
+
+interrupt_handler:
+	/* Todo - save and restore CPU context when interrupts will be in use */
+	bl	do_interrupt_handler
+	rtie
+
+EV_MachineCheck:
+	SAVE_ALL_SYS
+	SAVE_EXCEPTION_SOURCE
+	mov	%r1, %sp
+	j	do_machine_check_fault
+
+EV_TLBMissI:
+	SAVE_ALL_SYS
+	mov	%r0, %sp
+	j	do_itlb_miss
+
+EV_TLBMissD:
+	SAVE_ALL_SYS
+	mov	%r0, %sp
+	j	do_dtlb_miss
+
+EV_TLBProtV:
+	SAVE_ALL_SYS
+	SAVE_EXCEPTION_SOURCE
+	mov	%r1, %sp
+	j	do_tlb_prot_violation
+
+EV_PrivilegeV:
+	SAVE_ALL_SYS
+	mov	%r0, %sp
+	j	do_privilege_violation
+
+EV_Trap:
+	SAVE_ALL_SYS
+	mov	%r0, %sp
+	j	do_trap
+
+EV_Extension:
+	SAVE_ALL_SYS
+	mov	%r0, %sp
+	j	do_extension
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r0 = start_addr_sp
+ * r1 = new__gd
+ * r2 = relocaddr
+ */
+.align 4
+.globl	relocate_code
+relocate_code:
+	/*
+	 * r0-r12 might be clobbered by C functions
+	 * so we use r13-r16 for storage here
+	 */
+	mov	%r13, %r0		/* save addr_sp */
+	mov	%r14, %r1		/* save addr of gd */
+	mov	%r15, %r2		/* save addr of destination */
+
+	mov	%r16, %r2		/* %r9 - relocation offset */
+	sub	%r16, %r16, __image_copy_start
+
+/* Set up the stack */
+stack_setup:
+	mov	%sp, %r13
+	mov	%fp, %sp
+
+/* Check if monitor is loaded right in place for relocation */
+	mov	%r0, __image_copy_start
+	cmp	%r0, %r15		/* skip relocation if code loaded */
+	bz	do_board_init_r		/* in target location already */
+
+/* Copy data (__image_copy_start - __image_copy_end) to new location */
+	mov	%r1, %r15
+	mov	%r2, __image_copy_end
+	sub	%r2, %r2, %r0		/* r3 <- amount of bytes to copy */
+	asr	%r2, %r2, 2		/* r3 <- amount of words to copy */
+	mov	%lp_count, %r2
+	lp	copy_end
+	ld.ab	%r2,[%r0,4]
+	st.ab	%r2,[%r1,4]
+copy_end:
+
+/* Fix relocations related issues */
+	bl	do_elf_reloc_fixups
+#ifndef CONFIG_SYS_ICACHE_OFF
+	bl	invalidate_icache_all
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+	bl	flush_dcache_all
+#endif
+
+/* Update position of intterupt vector table */
+	lr	%r0, [ARC_AUX_INTR_VEC_BASE]	/* Read current position */
+	add	%r0, %r0, %r16			/* Update address */
+	sr	%r0, [ARC_AUX_INTR_VEC_BASE]	/* Write new position */
+
+do_board_init_r:
+/* Prepare for exection of "board_init_r" in relocated monitor */
+	mov	%r2, board_init_r	/* old address of "board_init_r()" */
+	add	%r2, %r2, %r16		/* new address of "board_init_r()" */
+	mov	%r0, %r14		/* 1-st parameter: gd_t */
+	mov	%r1, %r15		/* 2-nd parameter: dest_addr */
+	j	[%r2]
@@ -17,10 +17,14 @@
 #define ARCH_DMA_MINALIGN		128
 #endif
  
-#if defined(CONFIG_ARC_MMU_V2)
+#if defined(ARC_MMU_ABSENT)
+#define CONFIG_ARC_MMU_VER 0
+#elif defined(CONFIG_ARC_MMU_V2)
 #define CONFIG_ARC_MMU_VER 2
 #elif defined(CONFIG_ARC_MMU_V3)
 #define CONFIG_ARC_MMU_VER 3
+#elif defined(CONFIG_ARC_MMU_V4)
+#define CONFIG_ARC_MMU_VER 4
 #endif
  
 #endif /* __ASM_ARC_CACHE_H */
+CONFIG_SYS_TEXT_BASE=0x81000000
+CONFIG_SYS_CLK_FREQ=50000000
+CONFIG_ARC=y
+CONFIG_ISA_ARCV2=y
+CONFIG_TARGET_AXS101=y
...	...	@@ -8,31 +8,80 @@
8	8	default y
9	9
10	10	config SYS_CPU
11		- default "arcv1"
	11	+ default "arcv1" if ISA_ARCOMPACT
	12	+ default "arcv2" if ISA_ARCV2
12	13
13	14	choice
	15	+ prompt "ARC Instruction Set"
	16	+ default ISA_ARCOMPACT
	17	+
	18	+config ISA_ARCOMPACT
	19	+ bool "ARCompact ISA"
	20	+ help
	21	+ The original ARC ISA of ARC600/700 cores
	22	+
	23	+config ISA_ARCV2
	24	+ bool "ARC ISA v2"
	25	+ help
	26	+ ISA for the Next Generation ARC-HS cores
	27	+
	28	+endchoice
	29	+
	30	+choice
14	31	prompt "CPU selection"
15		- default CPU_ARC770D
	32	+ default CPU_ARC770D if ISA_ARCOMPACT
	33	+ default CPU_ARCHS38 if ISA_ARCV2
16	34
17	35	config CPU_ARC750D
18	36	bool "ARC 750D"
19	37	select ARC_MMU_V2
	38	+ depends on ISA_ARCOMPACT
20	39	help
21	40	Choose this option to build an U-Boot for ARC750D CPU.
22	41
23	42	config CPU_ARC770D
24	43	bool "ARC 770D"
25	44	select ARC_MMU_V3
	45	+ depends on ISA_ARCOMPACT
26	46	help
27	47	Choose this option to build an U-Boot for ARC770D CPU.
28	48
	49	+config CPU_ARCEM6
	50	+ bool "ARC EM6"
	51	+ select ARC_MMU_ABSENT
	52	+ depends on ISA_ARCV2
	53	+ help
	54	+ Next Generation ARC Core based on ISA-v2 ISA without MMU.
	55	+
	56	+config CPU_ARCHS36
	57	+ bool "ARC HS36"
	58	+ select ARC_MMU_ABSENT
	59	+ depends on ISA_ARCV2
	60	+ help
	61	+ Next Generation ARC Core based on ISA-v2 ISA without MMU.
	62	+
	63	+config CPU_ARCHS38
	64	+ bool "ARC HS38"
	65	+ select ARC_MMU_V4
	66	+ depends on ISA_ARCV2
	67	+ help
	68	+ Next Generation ARC Core based on ISA-v2 ISA with MMU.
	69	+
29	70	endchoice
30	71
31	72	choice
32	73	prompt "MMU Version"
33	74	default ARC_MMU_V3 if CPU_ARC770D
34	75	default ARC_MMU_V2 if CPU_ARC750D
	76	+ default ARC_MMU_ABSENT if CPU_ARCEM6
	77	+ default ARC_MMU_ABSENT if CPU_ARCHS36
	78	+ default ARC_MMU_V4 if CPU_ARCHS38
35	79
	80	+config ARC_MMU_ABSENT
	81	+ bool "No MMU"
	82	+ help
	83	+ No MMU
	84	+
36	85	config ARC_MMU_V2
37	86	bool "MMU v2"
38	87	depends on CPU_ARC750D
...	...	@@ -47,6 +96,12 @@
47	96	Introduced with ARC700 4.10: New Features
48	97	Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
49	98	Shared Address Spaces (SASID)
	99	+
	100	+config ARC_MMU_V4
	101	+ bool "MMU v4"
	102	+ depends on CPU_ARCHS38
	103	+ help
	104	+ Introduced as a part of ARC HS38 release.
50	105
51	106	endchoice
52	107
...	...	@@ -38,6 +38,18 @@
38	38	PLATFORM_CPPFLAGS += -marc700 -mlock -mswape
39	39	endif
40	40
	41	+ifdef CONFIG_CPU_ARCEM6
	42	+PLATFORM_CPPFLAGS += -marcem
	43	+endif
	44	+
	45	+ifdef CONFIG_CPU_ARCHS34
	46	+PLATFORM_CPPFLAGS += -marchs
	47	+endif
	48	+
	49	+ifdef CONFIG_CPU_ARCHS38
	50	+PLATFORM_CPPFLAGS += -marchs
	51	+endif
	52	+
41	53	PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2
42	54
43	55	# Needed for relocation
	1	+#
	2	+# Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
	3	+#
	4	+# SPDX-License-Identifier: GPL-2.0+
	5	+#
	6	+
	7	+obj-y += start.o
	1	+/*
	2	+ * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ */
	6	+
	7	+#include <asm-offsets.h>
	8	+#include <config.h>
	9	+#include <asm/arcregs.h>
	10	+
	11	+/*
	12	+ * Note on the LD/ST addressing modes with address register write-back
	13	+ *
	14	+ * LD.a same as LD.aw
	15	+ *
	16	+ * LD.a reg1, [reg2, x] => Pre Incr
	17	+ * Eff Addr for load = [reg2 + x]
	18	+ *
	19	+ * LD.ab reg1, [reg2, x] => Post Incr
	20	+ * Eff Addr for load = [reg2]
	21	+ */
	22	+
	23	+.macro PUSH reg
	24	+ st.a \reg, [%sp, -4]
	25	+.endm
	26	+
	27	+.macro PUSHAX aux
	28	+ lr %r9, [\aux]
	29	+ PUSH %r9
	30	+.endm
	31	+
	32	+.macro SAVE_R1_TO_R24
	33	+ PUSH %r1
	34	+ PUSH %r2
	35	+ PUSH %r3
	36	+ PUSH %r4
	37	+ PUSH %r5
	38	+ PUSH %r6
	39	+ PUSH %r7
	40	+ PUSH %r8
	41	+ PUSH %r9
	42	+ PUSH %r10
	43	+ PUSH %r11
	44	+ PUSH %r12
	45	+ PUSH %r13
	46	+ PUSH %r14
	47	+ PUSH %r15
	48	+ PUSH %r16
	49	+ PUSH %r17
	50	+ PUSH %r18
	51	+ PUSH %r19
	52	+ PUSH %r20
	53	+ PUSH %r21
	54	+ PUSH %r22
	55	+ PUSH %r23
	56	+ PUSH %r24
	57	+.endm
	58	+
	59	+.macro SAVE_ALL_SYS
	60	+ /* saving %r0 to reg->r0 in advance since weread %ecr into it */
	61	+ st %r0, [%sp, -8]
	62	+ lr %r0, [%ecr] /* all stack addressing is manual so far */
	63	+ st %r0, [%sp]
	64	+ st %sp, [%sp, -4]
	65	+ /* now move %sp to reg->r0 position so we can do "push" automatically */
	66	+ sub %sp, %sp, 8
	67	+
	68	+ SAVE_R1_TO_R24
	69	+ PUSH %r25
	70	+ PUSH %gp
	71	+ PUSH %fp
	72	+ PUSH %blink
	73	+ PUSHAX %eret
	74	+ PUSHAX %erstatus
	75	+ PUSH %lp_count
	76	+ PUSHAX %lp_end
	77	+ PUSHAX %lp_start
	78	+ PUSHAX %erbta
	79	+.endm
	80	+
	81	+.macro SAVE_EXCEPTION_SOURCE
	82	+#ifdef CONFIG_MMU
	83	+ /* If MMU exists exception faulting address is loaded in EFA reg */
	84	+ lr %r0, [%efa]
	85	+#else
	86	+ /* Otherwise in ERET (exception return) reg */
	87	+ lr %r0, [%eret]
	88	+#endif
	89	+.endm
	90	+
	91	+.section .ivt, "a",@progbits
	92	+.align 4
	93	+ /* Critical system events */
	94	+.word _start /* 0 - 0x000 */
	95	+.word memory_error /* 1 - 0x008 */
	96	+.word instruction_error /* 2 - 0x010 */
	97	+
	98	+ /* Exceptions */
	99	+.word EV_MachineCheck /* 0x100, Fatal Machine check (0x20) */
	100	+.word EV_TLBMissI /* 0x108, Intruction TLB miss (0x21) */
	101	+.word EV_TLBMissD /* 0x110, Data TLB miss (0x22) */
	102	+.word EV_TLBProtV /* 0x118, Protection Violation (0x23)
	103	+ or Misaligned Access */
	104	+.word EV_PrivilegeV /* 0x120, Privilege Violation (0x24) */
	105	+.word EV_Trap /* 0x128, Trap exception (0x25) */
	106	+.word EV_Extension /* 0x130, Extn Intruction Excp (0x26) */
	107	+
	108	+ /* Device interrupts */
	109	+.rept 29
	110	+ j interrupt_handler /* 3:31 - 0x018:0xF8 */
	111	+.endr
	112	+
	113	+.text
	114	+.globl _start
	115	+_start:
	116	+ /* Setup interrupt vector base that matches "__text_start" */
	117	+ sr __ivt_start, [ARC_AUX_INTR_VEC_BASE]
	118	+
	119	+ /* Setup stack pointer */
	120	+ mov %sp, CONFIG_SYS_INIT_SP_ADDR
	121	+ mov %fp, %sp
	122	+
	123	+ /* Clear bss */
	124	+ mov %r0, __bss_start
	125	+ mov %r1, __bss_end
	126	+
	127	+clear_bss:
	128	+ st.ab 0, [%r0, 4]
	129	+ brlt %r0, %r1, clear_bss
	130	+
	131	+ /* Zero the one and only argument of "board_init_f" */
	132	+ mov_s %r0, 0
	133	+ j board_init_f
	134	+
	135	+memory_error:
	136	+ SAVE_ALL_SYS
	137	+ SAVE_EXCEPTION_SOURCE
	138	+ mov %r1, %sp
	139	+ j do_memory_error
	140	+
	141	+instruction_error:
	142	+ SAVE_ALL_SYS
	143	+ SAVE_EXCEPTION_SOURCE
	144	+ mov %r1, %sp
	145	+ j do_instruction_error
	146	+
	147	+interrupt_handler:
	148	+ /* Todo - save and restore CPU context when interrupts will be in use */
	149	+ bl do_interrupt_handler
	150	+ rtie
	151	+
	152	+EV_MachineCheck:
	153	+ SAVE_ALL_SYS
	154	+ SAVE_EXCEPTION_SOURCE
	155	+ mov %r1, %sp
	156	+ j do_machine_check_fault
	157	+
	158	+EV_TLBMissI:
	159	+ SAVE_ALL_SYS
	160	+ mov %r0, %sp
	161	+ j do_itlb_miss
	162	+
	163	+EV_TLBMissD:
	164	+ SAVE_ALL_SYS
	165	+ mov %r0, %sp
	166	+ j do_dtlb_miss
	167	+
	168	+EV_TLBProtV:
	169	+ SAVE_ALL_SYS
	170	+ SAVE_EXCEPTION_SOURCE
	171	+ mov %r1, %sp
	172	+ j do_tlb_prot_violation
	173	+
	174	+EV_PrivilegeV:
	175	+ SAVE_ALL_SYS
	176	+ mov %r0, %sp
	177	+ j do_privilege_violation
	178	+
	179	+EV_Trap:
	180	+ SAVE_ALL_SYS
	181	+ mov %r0, %sp
	182	+ j do_trap
	183	+
	184	+EV_Extension:
	185	+ SAVE_ALL_SYS
	186	+ mov %r0, %sp
	187	+ j do_extension
	188	+
	189	+/*
	190	+ * void relocate_code (addr_sp, gd, addr_moni)
	191	+ *
	192	+ * This "function" does not return, instead it continues in RAM
	193	+ * after relocating the monitor code.
	194	+ *
	195	+ * r0 = start_addr_sp
	196	+ * r1 = new__gd
	197	+ * r2 = relocaddr
	198	+ */
	199	+.align 4
	200	+.globl relocate_code
	201	+relocate_code:
	202	+ /*
	203	+ * r0-r12 might be clobbered by C functions
	204	+ * so we use r13-r16 for storage here
	205	+ */
	206	+ mov %r13, %r0 /* save addr_sp */
	207	+ mov %r14, %r1 /* save addr of gd */
	208	+ mov %r15, %r2 /* save addr of destination */
	209	+
	210	+ mov %r16, %r2 /* %r9 - relocation offset */
	211	+ sub %r16, %r16, __image_copy_start
	212	+
	213	+/* Set up the stack */
	214	+stack_setup:
	215	+ mov %sp, %r13
	216	+ mov %fp, %sp
	217	+
	218	+/* Check if monitor is loaded right in place for relocation */
	219	+ mov %r0, __image_copy_start
	220	+ cmp %r0, %r15 /* skip relocation if code loaded */
	221	+ bz do_board_init_r /* in target location already */
	222	+
	223	+/* Copy data (__image_copy_start - __image_copy_end) to new location */
	224	+ mov %r1, %r15
	225	+ mov %r2, __image_copy_end
	226	+ sub %r2, %r2, %r0 /* r3 <- amount of bytes to copy */
	227	+ asr %r2, %r2, 2 /* r3 <- amount of words to copy */
	228	+ mov %lp_count, %r2
	229	+ lp copy_end
	230	+ ld.ab %r2,[%r0,4]
	231	+ st.ab %r2,[%r1,4]
	232	+copy_end:
	233	+
	234	+/* Fix relocations related issues */
	235	+ bl do_elf_reloc_fixups
	236	+#ifndef CONFIG_SYS_ICACHE_OFF
	237	+ bl invalidate_icache_all
	238	+#endif
	239	+#ifndef CONFIG_SYS_DCACHE_OFF
	240	+ bl flush_dcache_all
	241	+#endif
	242	+
	243	+/* Update position of intterupt vector table */
	244	+ lr %r0, [ARC_AUX_INTR_VEC_BASE] /* Read current position */
	245	+ add %r0, %r0, %r16 /* Update address */
	246	+ sr %r0, [ARC_AUX_INTR_VEC_BASE] /* Write new position */
	247	+
	248	+do_board_init_r:
	249	+/* Prepare for exection of "board_init_r" in relocated monitor */
	250	+ mov %r2, board_init_r /* old address of "board_init_r()" */
	251	+ add %r2, %r2, %r16 /* new address of "board_init_r()" */
	252	+ mov %r0, %r14 /* 1-st parameter: gd_t */
	253	+ mov %r1, %r15 /* 2-nd parameter: dest_addr */
	254	+ j [%r2]
...	...	@@ -17,10 +17,14 @@
17	17	#define ARCH_DMA_MINALIGN 128
18	18	#endif
19	19
20		-#if defined(CONFIG_ARC_MMU_V2)
	20	+#if defined(ARC_MMU_ABSENT)
	21	+#define CONFIG_ARC_MMU_VER 0
	22	+#elif defined(CONFIG_ARC_MMU_V2)
21	23	#define CONFIG_ARC_MMU_VER 2
22	24	#elif defined(CONFIG_ARC_MMU_V3)
23	25	#define CONFIG_ARC_MMU_VER 3
	26	+#elif defined(CONFIG_ARC_MMU_V4)
	27	+#define CONFIG_ARC_MMU_VER 4
24	28	#endif
25	29
26	30	#endif /* __ASM_ARC_CACHE_H */
	1	+CONFIG_SYS_TEXT_BASE=0x81000000
	2	+CONFIG_SYS_CLK_FREQ=50000000
	3	+CONFIG_ARC=y
	4	+CONFIG_ISA_ARCV2=y
	5	+CONFIG_TARGET_AXS101=y