Eric Lee / smarc-uboot

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Commit f14ae4180a37cf05c6bcfa5d55cc2955e920e1e2

Authored by Sascha Laue
Committed by Stefan Roese
1 parent d0e6665a24
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ppc4xx: Big lwmon5 board support rework/update 

This patch brings the lwmon5 board support up-to-date. Here a
summary of the changes:

lwmon5 board port related:
- GPIO's changed to control the LSB transmitter
- Reset USB PHY's upon power-up
- Enable CAN upon power-up
- USB init error workaround (errata CHIP_6)
- EBC: Enable burstmode and modify the timings for the GDC memory
- EBC: Speed up NOR flash timings

lwmon5 board POST related:
- Add FPGA memory test
- Add GDC memory test
- DSP POST reworked
- SYSMON POST: Fix handling of negative temperatures
- Add output for sysmon1 POST
- HW-watchdog min. time test reworked

Additionally some coding-style changes were done.

Signed-off-by: Sascha Laue <sascha.laue@liebherr.com>
Signed-off-by: Stefan Roese <sr@denx.de>

Showing 9 changed files with 1090 additions and 359 deletions Side-by-side Diff

... ... @@ -45,6 +45,10 @@
45 45 /*--------------------- Local macros and constants --------------------*/
46 46 #define _NOT_USED_ 0xFFFFFFFF
47 47  
  48 +/*------------------------- dspic io expander -----------------------*/
  49 +#define DSPIC_PON_STATUS_REG 0x80A
  50 +#define DSPIC_PON_INV_STATUS_REG 0x80C
  51 +#define DSPIC_PON_KEY_REG 0x810
48 52 /*------------------------- Keyboard controller -----------------------*/
49 53 /* command codes */
50 54 #define KEYBD_CMD_READ_KEYS 0x01
... ... @@ -75,6 +79,7 @@
75 79 /* maximum number of "magic" key codes that can be assigned */
76 80  
77 81 static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR;
  82 +static uchar dspic_addr = CONFIG_SYS_I2C_DSPIC_IO_ADDR;
78 83  
79 84 static uchar *key_match (uchar *);
80 85  
... ... @@ -167,6 +172,23 @@
167 172 }
168 173 }
169 174  
  175 +
  176 +/* Read a register from the dsPIC. */
  177 +int _dspic_read(ushort reg, ushort *data)
  178 +{
  179 + uchar buf[sizeof(*data)];
  180 + int rval;
  181 +
  182 + if (i2c_read(dspic_addr, reg, 2, buf, 2))
  183 + return -1;
  184 +
  185 + rval = i2c_read(dspic_addr, reg, sizeof(reg), buf, sizeof(*data));
  186 + *data = (buf[0] << 8) | buf[1];
  187 +
  188 + return rval;
  189 +}
  190 +
  191 +
170 192 /***********************************************************************
171 193 F* Function: int misc_init_r (void) P*A*Z*
172 194 *
... ... @@ -197,6 +219,7 @@
197 219 uchar kbd_init_status = gd->kbd_status >> 8;
198 220 uchar kbd_status = gd->kbd_status;
199 221 uchar val;
  222 + ushort data, inv_data;
200 223 char *str;
201 224 int i;
202 225  
203 226  
... ... @@ -231,9 +254,31 @@
231 254 i2c_write (kbd_addr, 0, 0, &val, 1);
232 255 i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
233 256  
  257 + /* read out start key from bse01 received via can */
  258 + _dspic_read(DSPIC_PON_STATUS_REG, &data);
  259 + /* check highbyte from status register */
  260 + if (data > 0xFF) {
  261 + _dspic_read(DSPIC_PON_INV_STATUS_REG, &inv_data);
  262 +
  263 + /* check inverse data */
  264 + if ((data+inv_data) == 0xFFFF) {
  265 + /* don't overwrite local key */
  266 + if (kbd_data[1] == 0) {
  267 + /* read key value */
  268 + _dspic_read(DSPIC_PON_KEY_REG, &data);
  269 + str = (char *)&data;
  270 + /* swap bytes */
  271 + kbd_data[1] = str[1];
  272 + kbd_data[2] = str[0];
  273 + printf("CAN received startkey: 0x%X\n", data);
  274 + }
  275 + }
  276 + }
  277 +
234 278 for (i = 0; i < KEYBD_DATALEN; ++i) {
235 279 sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
236 280 }
  281 +
237 282 setenv ("keybd", keybd_env);
238 283  
239 284 str = strdup ((char *)key_match (kbd_data)); /* decode keys */
board/lwmon5/lwmon5.c
Diff comments   View file @ f14ae41
1 1 /*
2   - * (C) Copyright 2007
  2 + * (C) Copyright 2007-2010
3 3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 4 *
5 5 * This program is free software; you can redistribute it and/or
6 6  
... ... @@ -24,10 +24,13 @@
24 24 #include <asm/processor.h>
25 25 #include <asm/ppc4xx-gpio.h>
26 26 #include <asm/io.h>
  27 +#include <post.h>
  28 +#include <flash.h>
  29 +#include <mtd/cfi_flash.h>
27 30  
28 31 DECLARE_GLOBAL_DATA_PTR;
29 32  
30   -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
  33 +static phys_addr_t lwmon5_cfi_flash_bank_addr[2] = CONFIG_SYS_FLASH_BANKS_LIST;
31 34  
32 35 ulong flash_get_size(ulong base, int banknum);
33 36 int misc_init_r_kbd(void);
34 37  
35 38  
... ... @@ -97,16 +100,18 @@
97 100 gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1);
98 101  
99 102 #if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
100   - gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 1);
  103 + /* enable the LSB transmitter */
  104 + gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
  105 + /* enable the CAN transmitter */
  106 + gpio_write_bit(CONFIG_SYS_GPIO_CAN_ENABLE, 1);
101 107  
102 108 reg = 0; /* reuse as counter */
103 109 out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
104 110 in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR)
105 111 & ~CONFIG_SYS_DSPIC_TEST_MASK);
106   - while (!gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) {
  112 + while (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) {
107 113 udelay(1000);
108 114 }
109   - gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 0);
110 115 if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) {
111 116 /* set "boot error" flag */
112 117 out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
... ... @@ -135,9 +140,61 @@
135 140 return 0;
136 141 }
137 142  
138   -/*---------------------------------------------------------------------------+
139   - | misc_init_r.
140   - +---------------------------------------------------------------------------*/
  143 +/*
  144 + * Override weak default with board specific version
  145 + */
  146 +phys_addr_t cfi_flash_bank_addr(int bank)
  147 +{
  148 + return lwmon5_cfi_flash_bank_addr[bank];
  149 +}
  150 +
  151 +/*
  152 + * Override the weak default mapping function with a board specific one
  153 + */
  154 +u32 flash_get_bank_size(int cs, int idx)
  155 +{
  156 + return flash_info[idx].size;
  157 +}
  158 +
  159 +int board_early_init_r(void)
  160 +{
  161 + u32 val0, val1;
  162 +
  163 + /*
  164 + * lwmon5 is manufactured in 2 different board versions:
  165 + * The lwmon5a board has 64MiB NOR flash instead of the
  166 + * 128MiB of the original lwmon5. Unfortunately the CFI driver
  167 + * will report 2 banks of 64MiB even for the smaller flash
  168 + * chip, since the bank is mirrored. To fix this, we bring
  169 + * one bank into CFI query mode and read its response. This
  170 + * enables us to detect the real number of flash devices/
  171 + * banks which will be used later on by the common CFI driver.
  172 + */
  173 +
  174 + /* Put bank 0 into CFI command mode and read */
  175 + out_be32((void *)CONFIG_SYS_FLASH0, 0x00980098);
  176 + val0 = in_be32((void *)CONFIG_SYS_FLASH0 + FLASH_OFFSET_CFI_RESP);
  177 + val1 = in_be32((void *)CONFIG_SYS_FLASH1 + FLASH_OFFSET_CFI_RESP);
  178 +
  179 + /* Reset flash again out of query mode */
  180 + out_be32((void *)CONFIG_SYS_FLASH0, 0x00f000f0);
  181 +
  182 + /* When not identical, we have 2 different flash devices/banks */
  183 + if (val0 != val1)
  184 + return 0;
  185 +
  186 + /*
  187 + * Now we're sure that we're running on a LWMON5a board with
  188 + * only 64MiB NOR flash in one bank:
  189 + *
  190 + * Set flash base address and bank count for CFI driver probing.
  191 + */
  192 + cfi_flash_num_flash_banks = 1;
  193 + lwmon5_cfi_flash_bank_addr[0] = CONFIG_SYS_FLASH0;
  194 +
  195 + return 0;
  196 +}
  197 +
141 198 int misc_init_r(void)
142 199 {
143 200 u32 pbcr;
... ... @@ -145,7 +202,7 @@
145 202 u32 reg;
146 203 unsigned long usb2d0cr = 0;
147 204 unsigned long usb2phy0cr, usb2h0cr = 0;
148   - unsigned long sdr0_pfc1;
  205 + unsigned long sdr0_pfc1, sdr0_srst;
149 206  
150 207 /*
151 208 * FLASH stuff...
... ... @@ -158,32 +215,7 @@
158 215 gd->bd->bi_flashoffset = 0;
159 216  
160 217 mfebc(PB0CR, pbcr);
161   - switch (gd->bd->bi_flashsize) {
162   - case 1 << 20:
163   - size_val = 0;
164   - break;
165   - case 2 << 20:
166   - size_val = 1;
167   - break;
168   - case 4 << 20:
169   - size_val = 2;
170   - break;
171   - case 8 << 20:
172   - size_val = 3;
173   - break;
174   - case 16 << 20:
175   - size_val = 4;
176   - break;
177   - case 32 << 20:
178   - size_val = 5;
179   - break;
180   - case 64 << 20:
181   - size_val = 6;
182   - break;
183   - case 128 << 20:
184   - size_val = 7;
185   - break;
186   - }
  218 + size_val = ffs(gd->bd->bi_flashsize) - 21;
187 219 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
188 220 mtebc(PB0CR, pbcr);
189 221  
190 222  
191 223  
192 224  
193 225  
194 226  
195 227  
196 228  
... ... @@ -193,53 +225,92 @@
193 225 flash_get_size(gd->bd->bi_flashstart, 0);
194 226  
195 227 /* Monitor protection ON by default */
196   - (void)flash_protect(FLAG_PROTECT_SET,
197   - -CONFIG_SYS_MONITOR_LEN,
198   - 0xffffffff,
199   - &flash_info[1]);
  228 + flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff,
  229 + &flash_info[cfi_flash_num_flash_banks - 1]);
200 230  
201 231 /* Env protection ON by default */
202   - (void)flash_protect(FLAG_PROTECT_SET,
203   - CONFIG_ENV_ADDR_REDUND,
204   - CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
205   - &flash_info[1]);
  232 + flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
  233 + CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1,
  234 + &flash_info[cfi_flash_num_flash_banks - 1]);
206 235  
207 236 /*
208 237 * USB suff...
209 238 */
  239 +
  240 + /* Reset USB */
  241 + /* Reset of USB2PHY0 must be active at least 10 us */
  242 + mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D);
  243 + udelay(2000);
  244 +
  245 + mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI |
  246 + SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 |
  247 + SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40);
  248 + udelay(2000);
  249 +
  250 + /* Errata CHIP_6 */
  251 +
  252 + /* 1. Set internal PHY configuration */
210 253 /* SDR Setting */
211 254 mfsdr(SDR0_PFC1, sdr0_pfc1);
212 255 mfsdr(SDR0_USB0, usb2d0cr);
213 256 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
214 257 mfsdr(SDR0_USB2H0CR, usb2h0cr);
215 258  
216   - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
217   - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
218   - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
219   - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
220   - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
221   - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
222   - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
223   - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
224   - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
225   - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
  259 + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
  260 + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
  261 + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
  262 + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
  263 + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
  264 + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
  265 + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
  266 + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
  267 + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
  268 + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
226 269  
227   - /* An 8-bit/60MHz interface is the only possible alternative
228   - when connecting the Device to the PHY */
229   - usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
230   - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
  270 + /*
  271 + * An 8-bit/60MHz interface is the only possible alternative
  272 + * when connecting the Device to the PHY
  273 + */
  274 + usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
  275 + usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
231 276  
232 277 mtsdr(SDR0_PFC1, sdr0_pfc1);
233 278 mtsdr(SDR0_USB0, usb2d0cr);
234 279 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
235 280 mtsdr(SDR0_USB2H0CR, usb2h0cr);
236 281  
  282 + /* 2. De-assert internal PHY reset */
  283 + mfsdr(SDR0_SRST1, sdr0_srst);
  284 + sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY;
  285 + mtsdr(SDR0_SRST1, sdr0_srst);
  286 +
  287 + /* 3. Wait for more than 1 ms */
  288 + udelay(2000);
  289 +
  290 + /* 4. De-assert USB 2.0 Host main reset */
  291 + mfsdr(SDR0_SRST0, sdr0_srst);
  292 + sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H;
  293 + mtsdr(SDR0_SRST0, sdr0_srst);
  294 + udelay(1000);
  295 +
  296 + /* 5. De-assert reset of OPB2 cores */
  297 + mfsdr(SDR0_SRST1, sdr0_srst);
  298 + sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1;
  299 + sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40;
  300 + sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2;
  301 + mtsdr(SDR0_SRST1, sdr0_srst);
  302 + udelay(1000);
  303 +
  304 + /* 6. Set EHCI Configure FLAG */
  305 +
  306 + /* 7. Reassert internal PHY reset: */
  307 + mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY);
  308 + udelay(1000);
  309 +
237 310 /*
238 311 * Clear resets
239 312 */
240   - udelay (1000);
241 313 mtsdr(SDR0_SRST1, 0x00000000);
242   - udelay (1000);
243 314 mtsdr(SDR0_SRST0, 0x00000000);
244 315  
245 316 printf("USB: Host(int phy) Device(ext phy)\n");
... ... @@ -264,7 +335,7 @@
264 335 {
265 336 char *s = getenv("serial#");
266 337  
267   - printf("Board: lwmon5");
  338 + puts("Board: lwmon5");
268 339  
269 340 if (s != NULL) {
270 341 puts(", serial# ");
271 342  
272 343  
... ... @@ -331,34 +402,33 @@
331 402  
332 403 extern GraphicDevice mb862xx;
333 404  
334   -static const gdc_regs init_regs [] =
335   -{
336   - {0x0100, 0x00000f00},
337   - {0x0020, 0x801401df},
338   - {0x0024, 0x00000000},
339   - {0x0028, 0x00000000},
340   - {0x002c, 0x00000000},
341   - {0x0110, 0x00000000},
342   - {0x0114, 0x00000000},
343   - {0x0118, 0x01df0280},
344   - {0x0004, 0x031f0000},
345   - {0x0008, 0x027f027f},
346   - {0x000c, 0x015f028f},
347   - {0x0010, 0x020c0000},
348   - {0x0014, 0x01df01ea},
349   - {0x0018, 0x00000000},
350   - {0x001c, 0x01e00280},
351   - {0x0100, 0x80010f00},
352   - {0x0, 0x0}
  405 +static const gdc_regs init_regs [] = {
  406 + { 0x0100, 0x00000f00 },
  407 + { 0x0020, 0x801401df },
  408 + { 0x0024, 0x00000000 },
  409 + { 0x0028, 0x00000000 },
  410 + { 0x002c, 0x00000000 },
  411 + { 0x0110, 0x00000000 },
  412 + { 0x0114, 0x00000000 },
  413 + { 0x0118, 0x01df0280 },
  414 + { 0x0004, 0x031f0000 },
  415 + { 0x0008, 0x027f027f },
  416 + { 0x000c, 0x015f028f },
  417 + { 0x0010, 0x020c0000 },
  418 + { 0x0014, 0x01df01ea },
  419 + { 0x0018, 0x00000000 },
  420 + { 0x001c, 0x01e00280 },
  421 + { 0x0100, 0x80010f00 },
  422 + { 0x0, 0x0 }
353 423 };
354 424  
355   -const gdc_regs *board_get_regs (void)
  425 +const gdc_regs *board_get_regs(void)
356 426 {
357 427 return init_regs;
358 428 }
359 429  
360 430 /* Returns Lime base address */
361   -unsigned int board_video_init (void)
  431 +unsigned int board_video_init(void)
362 432 {
363 433 /*
364 434 * Reset Lime controller
... ... @@ -375,7 +445,7 @@
375 445 return CONFIG_SYS_LIME_BASE_0;
376 446 }
377 447  
378   -#define DEFAULT_BRIGHTNESS 0x64
  448 +#define DEFAULT_BRIGHTNESS 0x64
379 449  
380 450 static void board_backlight_brightness(int brightness)
381 451 {
... ... @@ -390,7 +460,7 @@
390 460 }
391 461 }
392 462  
393   -void board_backlight_switch (int flag)
  463 +void board_backlight_switch(int flag)
394 464 {
395 465 char * param;
396 466 int rc;
397 467  
398 468  
399 469  
... ... @@ -410,15 +480,14 @@
410 480 /*
411 481 * Return text to be printed besides the logo.
412 482 */
413   -void video_get_info_str (int line_number, char *info)
  483 +void video_get_info_str(int line_number, char *info)
414 484 {
415   - if (line_number == 1) {
416   - strcpy (info, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
417   - } else {
  485 + if (line_number == 1)
  486 + strcpy(info, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
  487 + else
418 488 info [0] = '\0';
419   - }
420 489 }
421   -#endif
  490 +#endif /* CONFIG_CONSOLE_EXTRA_INFO */
422 491 #endif /* CONFIG_VIDEO */
423 492  
424 493 void board_reset(void)
include/configs/lwmon5.h
Diff comments   View file @ f14ae41
1 1 /*
2   - * (C) Copyright 2007-2008
  2 + * (C) Copyright 2007-2010
3 3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 4 *
5 5 * This program is free software; you can redistribute it and/or
6 6  
7 7  
8 8  
9 9  
10 10  
11 11  
12 12  
13 13  
14 14  
15 15  
... ... @@ -18,58 +18,63 @@
18 18 * MA 02111-1307 USA
19 19 */
20 20  
21   -/************************************************************************
  21 +/*
22 22 * lwmon5.h - configuration for lwmon5 board
23   - ***********************************************************************/
  23 + */
24 24 #ifndef __CONFIG_H
25 25 #define __CONFIG_H
26 26  
27   -/*-----------------------------------------------------------------------
  27 +/*
  28 + * Liebherr extra version info
  29 + */
  30 +#define CONFIG_IDENT_STRING " - v2.0"
  31 +
  32 +/*
28 33 * High Level Configuration Options
29   - *----------------------------------------------------------------------*/
  34 + */
30 35 #define CONFIG_LWMON5 1 /* Board is lwmon5 */
31 36 #define CONFIG_440EPX 1 /* Specific PPC440EPx */
32 37 #define CONFIG_440 1 /* ... PPC440 family */
33 38 #define CONFIG_4xx 1 /* ... PPC4xx family */
34 39 #define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
35 40  
36   -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
37   -#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */
38   -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
39   -#define CONFIG_BOARD_RESET 1 /* Call board_reset */
  41 +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */
  42 +#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
  43 +#define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */
  44 +#define CONFIG_MISC_INIT_R /* Call misc_init_r */
  45 +#define CONFIG_BOARD_RESET /* Call board_reset */
40 46  
41   -/*-----------------------------------------------------------------------
  47 +/*
42 48 * Base addresses -- Note these are effective addresses where the
43 49 * actual resources get mapped (not physical addresses)
44   - *----------------------------------------------------------------------*/
45   -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
46   -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */
  50 + */
  51 +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of U-Boot */
  52 +#define CONFIG_SYS_MONITOR_LEN (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1)
  53 +#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */
47 54  
48 55 #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
49 56 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
50 57 #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
51   -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
52   -#define CONFIG_SYS_LIME_BASE_0 0xc0000000
53   -#define CONFIG_SYS_LIME_BASE_1 0xc1000000
54   -#define CONFIG_SYS_LIME_BASE_2 0xc2000000
55   -#define CONFIG_SYS_LIME_BASE_3 0xc3000000
56   -#define CONFIG_SYS_FPGA_BASE_0 0xc4000000
57   -#define CONFIG_SYS_FPGA_BASE_1 0xc4200000
  58 +#define CONFIG_SYS_LIME_BASE_0 0xc0000000
  59 +#define CONFIG_SYS_LIME_BASE_1 0xc1000000
  60 +#define CONFIG_SYS_LIME_BASE_2 0xc2000000
  61 +#define CONFIG_SYS_LIME_BASE_3 0xc3000000
  62 +#define CONFIG_SYS_FPGA_BASE_0 0xc4000000
  63 +#define CONFIG_SYS_FPGA_BASE_1 0xc4200000
58 64 #define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
59 65 #define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
60 66 #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
61   -#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
62   -#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
63   -#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
  67 +#define CONFIG_SYS_PCI_MEMBASE1 (CONFIG_SYS_PCI_MEMBASE + 0x10000000)
  68 +#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
  69 +#define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
64 70  
65 71 #define CONFIG_SYS_USB2D0_BASE 0xe0000100
66 72 #define CONFIG_SYS_USB_DEVICE 0xe0000000
67 73 #define CONFIG_SYS_USB_HOST 0xe0000400
68 74  
69   -/*-----------------------------------------------------------------------
70   - * Initial RAM & stack pointer
71   - *----------------------------------------------------------------------*/
72 75 /*
  76 + * Initial RAM & stack pointer
  77 + *
73 78 * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
74 79 * the POST_WORD from OCM to a 440EPx register that preserves it's
75 80 * content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
76 81  
77 82  
78 83  
79 84  
80 85  
... ... @@ -77,18 +82,18 @@
77 82 */
78 83 #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
79 84 #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
80   -#define CONFIG_SYS_INIT_RAM_END (4 << 10)
  85 +#define CONFIG_SYS_INIT_RAM_END (4 << 10)
81 86 #define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data*/
82   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  87 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
  88 + CONFIG_SYS_GBL_DATA_SIZE)
83 89 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  90 +/* unused GPT0 COMP reg */
84 91 #define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
85   - /* unused GPT0 COMP reg */
86   -#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
87   - /* 440EPx errata CHIP 11 */
88 92 #define CONFIG_SYS_OCM_SIZE (16 << 10)
  93 +/* 440EPx errata CHIP 11: don't use last 4kbytes */
  94 +#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10)
89 95  
90 96 /* Additional registers for watchdog timer post test */
91   -
92 97 #define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
93 98 #define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
94 99 #define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
95 100  
... ... @@ -100,9 +105,9 @@
100 105 #define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300
101 106 #define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00
102 107  
103   -/*-----------------------------------------------------------------------
  108 +/*
104 109 * Serial Port
105   - *----------------------------------------------------------------------*/
  110 + */
106 111 #define CONFIG_CONS_INDEX 2 /* Use UART1 */
107 112 #define CONFIG_SYS_NS16550
108 113 #define CONFIG_SYS_NS16550_SERIAL
109 114  
110 115  
111 116  
112 117  
113 118  
114 119  
115 120  
116 121  
117 122  
118 123  
119 124  
120 125  
121 126  
122 127  
... ... @@ -110,77 +115,79 @@
110 115 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
111 116 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */
112 117 #define CONFIG_BAUDRATE 115200
113   -#define CONFIG_SERIAL_MULTI 1
  118 +#define CONFIG_SERIAL_MULTI
114 119  
115 120 #define CONFIG_SYS_BAUDRATE_TABLE \
116 121 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
117 122  
118   -/*-----------------------------------------------------------------------
  123 +/*
119 124 * Environment
120   - *----------------------------------------------------------------------*/
121   -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
  125 + */
  126 +#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
122 127  
123   -/*-----------------------------------------------------------------------
  128 +/*
124 129 * FLASH related
125   - *----------------------------------------------------------------------*/
126   -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
  130 + */
  131 +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
127 132 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
128 133  
129 134 #define CONFIG_SYS_FLASH0 0xFC000000
130 135 #define CONFIG_SYS_FLASH1 0xF8000000
131 136 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
132 137  
133   -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
  138 +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 /* max number of memory banks */
134 139 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
135 140  
136 141 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
137 142 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
138 143  
139   -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
140   -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
  144 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
  145 +#define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */
141 146  
142 147 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
143   -#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
  148 +#define CONFIG_SYS_FLASH_QUIET_TEST /* don't warn upon unknown flash */
144 149  
145 150 #define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
146   -#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
  151 +#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE)
147 152 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
148 153  
149 154 /* Address and size of Redundant Environment Sector */
150   -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
  155 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
151 156 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
152 157  
153   -/*-----------------------------------------------------------------------
  158 +/*
154 159 * DDR SDRAM
155   - *----------------------------------------------------------------------*/
156   -#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
  160 + */
  161 +#define CONFIG_SYS_MBYTES_SDRAM 256
157 162 #define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
158   -#define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */
159   -#define CONFIG_DDR_ECC 1 /* enable ECC */
160   -#define CONFIG_SYS_POST_ECC_ON CONFIG_SYS_POST_ECC
  163 +#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
  164 +#define CONFIG_DDR_ECC /* enable ECC */
161 165  
162 166 /* POST support */
163   -#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
164   - CONFIG_SYS_POST_CPU | \
165   - CONFIG_SYS_POST_ECC_ON | \
166   - CONFIG_SYS_POST_ETHER | \
167   - CONFIG_SYS_POST_FPU | \
168   - CONFIG_SYS_POST_I2C | \
169   - CONFIG_SYS_POST_MEMORY | \
170   - CONFIG_SYS_POST_OCM | \
171   - CONFIG_SYS_POST_RTC | \
172   - CONFIG_SYS_POST_SPR | \
173   - CONFIG_SYS_POST_UART | \
174   - CONFIG_SYS_POST_SYSMON | \
175   - CONFIG_SYS_POST_WATCHDOG | \
176   - CONFIG_SYS_POST_DSP | \
177   - CONFIG_SYS_POST_BSPEC1 | \
178   - CONFIG_SYS_POST_BSPEC2 | \
179   - CONFIG_SYS_POST_BSPEC3 | \
180   - CONFIG_SYS_POST_BSPEC4 | \
  167 +#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
  168 + CONFIG_SYS_POST_CPU | \
  169 + CONFIG_SYS_POST_ECC | \
  170 + CONFIG_SYS_POST_ETHER | \
  171 + CONFIG_SYS_POST_FPU | \
  172 + CONFIG_SYS_POST_I2C | \
  173 + CONFIG_SYS_POST_MEMORY | \
  174 + CONFIG_SYS_POST_OCM | \
  175 + CONFIG_SYS_POST_RTC | \
  176 + CONFIG_SYS_POST_SPR | \
  177 + CONFIG_SYS_POST_UART | \
  178 + CONFIG_SYS_POST_SYSMON | \
  179 + CONFIG_SYS_POST_WATCHDOG | \
  180 + CONFIG_SYS_POST_DSP | \
  181 + CONFIG_SYS_POST_BSPEC1 | \
  182 + CONFIG_SYS_POST_BSPEC2 | \
  183 + CONFIG_SYS_POST_BSPEC3 | \
  184 + CONFIG_SYS_POST_BSPEC4 | \
181 185 CONFIG_SYS_POST_BSPEC5)
182 186  
183   -#define CONFIG_POST_WATCHDOG {\
  187 +/* Define here the base-addresses of the UARTs to test in POST */
  188 +#define CONFIG_SYS_POST_UART_TABLE { UART0_BASE, UART1_BASE }
  189 +
  190 +#define CONFIG_POST_WATCHDOG { \
184 191 "Watchdog timer test", \
185 192 "watchdog", \
186 193 "This test checks the watchdog timer.", \
187 194  
... ... @@ -188,10 +195,10 @@
188 195 &lwmon5_watchdog_post_test, \
189 196 NULL, \
190 197 NULL, \
191   - CONFIG_SYS_POST_WATCHDOG \
  198 + CONFIG_SYS_POST_WATCHDOG \
192 199 }
193 200  
194   -#define CONFIG_POST_BSPEC1 {\
  201 +#define CONFIG_POST_BSPEC1 { \
195 202 "dsPIC init test", \
196 203 "dspic_init", \
197 204 "This test returns result of dsPIC READY test run earlier.", \
198 205  
... ... @@ -199,10 +206,10 @@
199 206 &dspic_init_post_test, \
200 207 NULL, \
201 208 NULL, \
202   - CONFIG_SYS_POST_BSPEC1 \
  209 + CONFIG_SYS_POST_BSPEC1 \
203 210 }
204 211  
205   -#define CONFIG_POST_BSPEC2 {\
  212 +#define CONFIG_POST_BSPEC2 { \
206 213 "dsPIC test", \
207 214 "dspic", \
208 215 "This test gets result of dsPIC POST and dsPIC version.", \
209 216  
210 217  
211 218  
212 219  
213 220  
214 221  
215 222  
... ... @@ -210,32 +217,32 @@
210 217 &dspic_post_test, \
211 218 NULL, \
212 219 NULL, \
213   - CONFIG_SYS_POST_BSPEC2 \
  220 + CONFIG_SYS_POST_BSPEC2 \
214 221 }
215 222  
216   -#define CONFIG_POST_BSPEC3 {\
  223 +#define CONFIG_POST_BSPEC3 { \
217 224 "FPGA test", \
218 225 "fpga", \
219 226 "This test checks FPGA registers and memory.", \
220   - POST_RAM | POST_ALWAYS, \
  227 + POST_RAM | POST_ALWAYS | POST_MANUAL, \
221 228 &fpga_post_test, \
222 229 NULL, \
223 230 NULL, \
224   - CONFIG_SYS_POST_BSPEC3 \
  231 + CONFIG_SYS_POST_BSPEC3 \
225 232 }
226 233  
227   -#define CONFIG_POST_BSPEC4 {\
  234 +#define CONFIG_POST_BSPEC4 { \
228 235 "GDC test", \
229 236 "gdc", \
230 237 "This test checks GDC registers and memory.", \
231   - POST_RAM | POST_ALWAYS, \
  238 + POST_RAM | POST_ALWAYS | POST_MANUAL,\
232 239 &gdc_post_test, \
233 240 NULL, \
234 241 NULL, \
235   - CONFIG_SYS_POST_BSPEC4 \
  242 + CONFIG_SYS_POST_BSPEC4 \
236 243 }
237 244  
238   -#define CONFIG_POST_BSPEC5 {\
  245 +#define CONFIG_POST_BSPEC5 { \
239 246 "SYSMON1 test", \
240 247 "sysmon1", \
241 248 "This test checks GPIO_62_EPX pin indicating power failure.", \
... ... @@ -243,7 +250,7 @@
243 250 &sysmon1_post_test, \
244 251 NULL, \
245 252 NULL, \
246   - CONFIG_SYS_POST_BSPEC5 \
  253 + CONFIG_SYS_POST_BSPEC5 \
247 254 }
248 255  
249 256 #define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
250 257  
251 258  
252 259  
253 260  
254 261  
255 262  
... ... @@ -253,34 +260,53 @@
253 260 #define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE)
254 261 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
255 262  
256   -/*-----------------------------------------------------------------------
  263 +/*
257 264 * I2C
258   - *----------------------------------------------------------------------*/
259   -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
  265 + */
  266 +#define CONFIG_HARD_I2C /* I2C with hardware support */
260 267 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
261 268 #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
262 269 #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
263 270 #define CONFIG_SYS_I2C_SLAVE 0x7F
264 271  
265   -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM AT24C128 */
  272 +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* RTC */
  273 +#define CONFIG_SYS_I2C_EEPROM_CPU_ADDR 0x52 /* EEPROM (CPU Modul) */
  274 +#define CONFIG_SYS_I2C_EEPROM_MB_ADDR 0x53 /* EEPROM AT24C128 (MainBoard) */
  275 +#define CONFIG_SYS_I2C_DSPIC_ADDR 0x54 /* dsPIC */
  276 +#define CONFIG_SYS_I2C_DSPIC_2_ADDR 0x55 /* dsPIC */
  277 +#define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR 0x56 /* dsPIC */
  278 +#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* dsPIC */
  279 +
266 280 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
267 281 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */
268 282 /* 64 byte page write mode using*/
269 283 /* last 6 bits of the address */
270 284 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
  285 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
271 286  
272   -#define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */
273   -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
274   -#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
275   -#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
  287 +#define CONFIG_RTC_PCF8563 /* enable Philips PCF8563 RTC */
  288 +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
  289 +#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
  290 +#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
276 291  
  292 +#define I2C_ADDR_LIST { \
  293 + CONFIG_SYS_I2C_RTC_ADDR, \
  294 + CONFIG_SYS_I2C_EEPROM_CPU_ADDR, \
  295 + CONFIG_SYS_I2C_EEPROM_MB_ADDR, \
  296 + CONFIG_SYS_I2C_DSPIC_ADDR, \
  297 + CONFIG_SYS_I2C_DSPIC_2_ADDR, \
  298 + CONFIG_SYS_I2C_DSPIC_KEYB_ADDR, \
  299 + CONFIG_SYS_I2C_DSPIC_IO_ADDR }
  300 +
  301 +/*
  302 + * Pass open firmware flat tree
  303 + */
  304 +#define CONFIG_OF_LIBFDT
  305 +#define CONFIG_OF_BOARD_SETUP
  306 +/* Update size in "reg" property of NOR FLASH device tree nodes */
  307 +#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
  308 +
277 309 #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
278   -#if 0
279   -#define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */
280   -#define CONFIG_AUTOBOOT_PROMPT \
281   - "\nEnter password - autoboot in %d sec...\n", bootdelay
282   -#define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */
283   -#endif
284 310  
285 311 #define CONFIG_PREBOOT "setenv bootdelay 15"
286 312  
287 313  
288 314  
... ... @@ -314,15 +340,11 @@
314 340 "cp.b 200000 FFF80000 80000\0" \
315 341 "upd=run load update\0" \
316 342 "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
317   - "source 200000 200000\0" \" \
  343 + "autoscr 200000 200000\0" \" \
318 344 ""
319 345 #define CONFIG_BOOTCOMMAND "run flash_self"
320 346  
321   -#if 0
322   -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
323   -#else
324 347 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
325   -#endif
326 348  
327 349 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
328 350 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
329 351  
... ... @@ -410,9 +432,9 @@
410 432 #define CONFIG_CMD_USB
411 433 #endif
412 434  
413   -/*-----------------------------------------------------------------------
  435 +/*
414 436 * Miscellaneous configurable options
415   - *----------------------------------------------------------------------*/
  437 + */
416 438 #define CONFIG_SUPPORT_VFAT
417 439  
418 440 #define CONFIG_SYS_LONGHELP /* undef to save memory */
419 441  
... ... @@ -445,9 +467,9 @@
445 467 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
446 468 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
447 469  
448   -/*-----------------------------------------------------------------------
  470 +/*
449 471 * PCI stuff
450   - *----------------------------------------------------------------------*/
  472 + */
451 473 /* General PCI */
452 474 #define CONFIG_PCI /* include pci support */
453 475 #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
454 476  
455 477  
456 478  
457 479  
458 480  
459 481  
460 482  
... ... @@ -461,29 +483,32 @@
461 483 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
462 484 #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
463 485  
  486 +#ifndef DEBUG
464 487 #define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
  488 +#endif
465 489 #define CONFIG_WD_PERIOD 40000 /* in usec */
466 490 #define CONFIG_WD_MAX_RATE 66600 /* in ticks */
467 491  
468 492 /*
469 493 * For booting Linux, the board info and command line data
470   - * have to be in the first 8 MB of memory, since this is
471   - * the maximum mapped by the Linux kernel during initialization.
  494 + * have to be in the first 16 MB of memory, since this is
  495 + * the maximum mapped by the 40x Linux kernel during initialization.
472 496 */
473   -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  497 +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */
  498 +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
474 499  
475   -/*-----------------------------------------------------------------------
  500 +/*
476 501 * External Bus Controller (EBC) Setup
477   - *----------------------------------------------------------------------*/
  502 + */
478 503 #define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
479 504  
480 505 /* Memory Bank 0 (NOR-FLASH) initialization */
481   -#define CONFIG_SYS_EBC_PB0AP 0x03050200
  506 +#define CONFIG_SYS_EBC_PB0AP 0x03000280
482 507 #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000)
483 508  
484 509 /* Memory Bank 1 (Lime) initialization */
485 510 #define CONFIG_SYS_EBC_PB1AP 0x01004380
486   -#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xdc000)
  511 +#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xbc000)
487 512  
488 513 /* Memory Bank 2 (FPGA) initialization */
489 514 #define CONFIG_SYS_EBC_PB2AP 0x01004400
490 515  
491 516  
492 517  
... ... @@ -495,19 +520,27 @@
495 520  
496 521 #define CONFIG_SYS_EBC_CFG 0xb8400000
497 522  
498   -/*-----------------------------------------------------------------------
  523 +/*
499 524 * Graphics (Fujitsu Lime)
500   - *----------------------------------------------------------------------*/
  525 + */
  526 +/* SDRAM Clock frequency adjustment register */
  527 +#define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038
  528 +#if 1 /* 133MHz is not tested enough, use 100MHz for now */
501 529 /* Lime Clock frequency is to set 100MHz */
502 530 #define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000
503   -#if 0
  531 +#else
504 532 /* Lime Clock frequency for 133MHz */
505 533 #define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000
506 534 #endif
507 535  
508   -/* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
509   - and pixel flare on display when 133MHz was configured. According to
510   - SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */
  536 +/* SDRAM Parameter register */
  537 +#define CONFIG_SYS_LIME_MMR 0xC1FCFFFC
  538 +/*
  539 + * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
  540 + * and pixel flare on display when 133MHz was configured. According to
  541 + * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed
  542 + * Grade
  543 + */
511 544 #ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
512 545 #define CONFIG_SYS_MB862xx_MMR 0x414FB7F3
513 546 #define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ
514 547  
515 548  
... ... @@ -516,13 +549,15 @@
516 549 #define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ
517 550 #endif
518 551  
519   -/*-----------------------------------------------------------------------
  552 +/*
520 553 * GPIO Setup
521   - *----------------------------------------------------------------------*/
  554 + */
522 555 #define CONFIG_SYS_GPIO_PHY1_RST 12
523 556 #define CONFIG_SYS_GPIO_FLASH_WP 14
524 557 #define CONFIG_SYS_GPIO_PHY0_RST 22
525 558 #define CONFIG_SYS_GPIO_DSPIC_READY 51
  559 +#define CONFIG_SYS_GPIO_CAN_ENABLE 53
  560 +#define CONFIG_SYS_GPIO_LSB_ENABLE 54
526 561 #define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55
527 562 #define CONFIG_SYS_GPIO_HIGHSIDE 56
528 563 #define CONFIG_SYS_GPIO_EEPROM_INT_WP 57
... ... @@ -532,7 +567,7 @@
532 567 #define CONFIG_SYS_GPIO_SYSMON_STATUS 62
533 568 #define CONFIG_SYS_GPIO_WATCHDOG 63
534 569  
535   -/*-----------------------------------------------------------------------
  570 +/*
536 571 * PPC440 GPIO Configuration
537 572 */
538 573 #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
post/board/lwmon5/dsp.c
Diff comments   View file @ f14ae41
... ... @@ -33,19 +33,36 @@
33 33  
34 34 DECLARE_GLOBAL_DATA_PTR;
35 35  
36   -#define DSP_STATUS_REG 0xC4000008
  36 +#define DSP_STATUS_REG 0xC4000008
  37 +#define FPGA_STATUS_REG 0xC400000C
37 38  
38 39 int dsp_post_test(int flags)
39 40 {
  41 + uint old_value;
40 42 uint read_value;
41 43 int ret;
42 44  
  45 + /* momorize fpga status */
  46 + old_value = in_be32((void *)FPGA_STATUS_REG);
  47 + /* enable outputs */
  48 + out_be32((void *)FPGA_STATUS_REG, 0x30);
  49 +
  50 + /* generate sync signal */
  51 + out_be32((void *)DSP_STATUS_REG, 0x300);
  52 + udelay(5);
  53 + out_be32((void *)DSP_STATUS_REG, 0);
  54 + udelay(500);
  55 +
  56 + /* read status */
43 57 ret = 0;
44 58 read_value = in_be32((void *)DSP_STATUS_REG) & 0x3;
45   - if (read_value != 0x3) {
  59 + if (read_value != 0x03) {
46 60 post_log("\nDSP status read %08X\n", read_value);
47 61 ret = 1;
48 62 }
  63 +
  64 + /* restore fpga status */
  65 + out_be32((void *)FPGA_STATUS_REG, old_value);
49 66  
50 67 return ret;
51 68 }
post/board/lwmon5/dspic.c
Diff comments   View file @ f14ae41
... ... @@ -38,14 +38,16 @@
38 38  
39 39 #define DSPIC_POST_ERROR_REG 0x800
40 40 #define DSPIC_SYS_ERROR_REG 0x802
41   -#define DSPIC_VERSION_REG 0x804
  41 +#define DSPIC_SYS_VERSION_REG 0x804
  42 +#define DSPIC_FW_VERSION_REG 0x808
42 43  
43 44 #if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
44 45  
45 46 /* Verify that dsPIC ready test done early at hw init passed ok */
46 47 int dspic_init_post_test(int flags)
47 48 {
48   - if (in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) & CONFIG_SYS_DSPIC_TEST_MASK) {
  49 + if (in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) &
  50 + CONFIG_SYS_DSPIC_TEST_MASK) {
49 51 post_log("dsPIC init test failed\n");
50 52 return 1;
51 53 }
52 54  
53 55  
54 56  
55 57  
56 58  
57 59  
58 60  
59 61  
60 62  
61 63  
... ... @@ -57,46 +59,60 @@
57 59  
58 60 #if CONFIG_POST & CONFIG_SYS_POST_BSPEC2
59 61 /* Read a register from the dsPIC. */
60   -int dspic_read(ushort reg)
  62 +int dspic_read(ushort reg, ushort *data)
61 63 {
62   - uchar buf[2];
  64 + uchar buf[sizeof(*data)];
  65 + int rval;
63 66  
64 67 if (i2c_read(CONFIG_SYS_I2C_DSPIC_IO_ADDR, reg, 2, buf, 2))
65 68 return -1;
  69 + rval = i2c_read(CONFIG_SYS_I2C_DSPIC_IO_ADDR, reg, sizeof(reg),
  70 + buf, sizeof(*data));
  71 + *data = (buf[0] << 8) | buf[1];
66 72  
67   - return (uint)((buf[0] << 8) | buf[1]);
  73 + return rval;
68 74 }
69 75  
70 76 /* Verify error codes regs, display version */
71 77 int dspic_post_test(int flags)
72 78 {
73   - int data;
  79 + ushort data;
74 80 int ret = 0;
75 81  
76 82 post_log("\n");
77   - data = dspic_read(DSPIC_VERSION_REG);
78   - if (data == -1) {
79   - post_log("dsPIC : failed read version\n");
  83 +
  84 + /* read dspic FW-Version */
  85 + if (dspic_read(DSPIC_FW_VERSION_REG, &data)) {
  86 + post_log("dsPIC: failed read FW-Version\n");
80 87 ret = 1;
81 88 } else {
82   - post_log("dsPIC version: %u.%u\n",
83   - (data >> 8) & 0xFF, data & 0xFF);
  89 + post_log("dsPIC FW-Version: %u.%u\n",
  90 + (data >> 8) & 0xFF, data & 0xFF);
84 91 }
85 92  
86   - data = dspic_read(DSPIC_POST_ERROR_REG);
87   - if (data != 0) ret = 1;
88   - if (data == -1) {
89   - post_log("dsPIC : failed read POST code\n");
  93 + /* read dspic SYS-Version */
  94 + if (dspic_read(DSPIC_SYS_VERSION_REG, &data)) {
  95 + post_log("dsPIC: failed read version\n");
  96 + ret = 1;
90 97 } else {
91   - post_log("dsPIC POST code 0x%04X\n", data);
  98 + post_log("dsPIC SYS-Version: %u.%u\n",
  99 + (data >> 8) & 0xFF, data & 0xFF);
92 100 }
93 101  
94   - data = dspic_read(DSPIC_SYS_ERROR_REG);
95   - if (data == -1) {
96   - post_log("dsPIC : failed read system error\n");
  102 + /* read dspic POST error code */
  103 + if (dspic_read(DSPIC_POST_ERROR_REG, &data)) {
  104 + post_log("dsPIC: failed read POST code\n");
97 105 ret = 1;
98 106 } else {
99   - post_log("dsPIC SYS-ERROR code: 0x%04X\n", data);
  107 + post_log("dsPIC POST-ERROR code: 0x%04X\n", data);
  108 + }
  109 +
  110 + /* read dspic SYS error code */
  111 + if ((data = dspic_read(DSPIC_SYS_ERROR_REG, &data))) {
  112 + post_log("dsPIC: failed read system error\n");
  113 + ret = 1;
  114 + } else {
  115 + post_log("dsPIC SYS-ERROR code: 0x%04X\n", data);
100 116 }
101 117  
102 118 return ret;
post/board/lwmon5/fpga.c
Diff comments   View file @ f14ae41
... ... @@ -28,7 +28,7 @@
28 28 */
29 29  
30 30 #include <post.h>
31   -
  31 +#include <watchdog.h>
32 32 #include <asm/io.h>
33 33  
34 34 DECLARE_GLOBAL_DATA_PTR;
35 35  
36 36  
37 37  
... ... @@ -38,18 +38,28 @@
38 38 #define FPGA_RAM_START 0xC4200000
39 39 #define FPGA_RAM_END 0xC4203FFF
40 40 #define FPGA_STAT 0xC400000C
  41 +#define FPGA_BUFFER 0x00800000
  42 +#define FPGA_RAM_SIZE (FPGA_RAM_END - FPGA_RAM_START + 1)
41 43  
42 44 #if CONFIG_POST & CONFIG_SYS_POST_BSPEC3
43 45  
44   -/* Testpattern for fpga memorytest */
45   -static uint pattern[] = {
  46 +const static unsigned long pattern[] = {
  47 + 0xffffffff,
  48 + 0xaaaaaaaa,
  49 + 0xcccccccc,
  50 + 0xf0f0f0f0,
  51 + 0xff00ff00,
  52 + 0xffff0000,
  53 + 0x0000ffff,
  54 + 0x00ff00ff,
  55 + 0x0f0f0f0f,
  56 + 0x33333333,
46 57 0x55555555,
47   - 0xAAAAAAAA,
48   - 0xAA5555AA,
49   - 0x55AAAA55,
50   - 0x0
  58 + 0x00000000,
51 59 };
52 60  
  61 +const static unsigned long otherpattern = 0x01234567;
  62 +
53 63 static int one_scratch_test(uint value)
54 64 {
55 65 uint read_value;
56 66  
57 67  
58 68  
59 69  
60 70  
61 71  
62 72  
63 73  
64 74  
65 75  
66 76  
... ... @@ -62,51 +72,226 @@
62 72 read_value = in_be32((void *)FPGA_SCRATCH_REG);
63 73 if (read_value != value) {
64 74 post_log("FPGA SCRATCH test failed write %08X, read %08X\n",
65   - value, read_value);
66   - ret = 1;
  75 + value, read_value);
  76 + ret = -1;
67 77 }
68 78  
69 79 return ret;
70 80 }
71 81  
  82 +static int fpga_post_test1(ulong *start, ulong size, ulong val)
  83 +{
  84 + int ret = 0;
  85 + ulong i = 0;
  86 + ulong *mem = start;
  87 + ulong readback;
  88 +
  89 + for (i = 0; i < size / sizeof(ulong); i++) {
  90 + mem[i] = val;
  91 + if (i % 1024 == 0)
  92 + WATCHDOG_RESET();
  93 + }
  94 +
  95 + for (i = 0; i < size / sizeof(ulong); i++) {
  96 + readback = mem[i];
  97 + if (readback != val) {
  98 + post_log("FPGA Memory error at %08x, "
  99 + "wrote %08x, read %08x !\n",
  100 + mem + i, val, readback);
  101 + ret = -1;
  102 + break;
  103 + }
  104 + if (i % 1024 == 0)
  105 + WATCHDOG_RESET();
  106 + }
  107 + return ret;
  108 +}
  109 +
  110 +static int fpga_post_test2(ulong *start, ulong size)
  111 +{
  112 + int ret = 0;
  113 + ulong i = 0;
  114 + ulong *mem = start;
  115 + ulong readback;
  116 +
  117 + for (i = 0; i < size / sizeof(ulong); i++) {
  118 + mem[i] = 1 << (i % 32);
  119 + if (i % 1024 == 0)
  120 + WATCHDOG_RESET();
  121 + }
  122 +
  123 + for (i = 0; i < size / sizeof(ulong); i++) {
  124 + readback = mem[i];
  125 + if (readback != 1 << (i % 32)) {
  126 + post_log("FPGA Memory error at %08x, "
  127 + "wrote %08x, read %08x !\n",
  128 + mem + i, 1 << (i % 32), readback);
  129 + ret = -1;
  130 + break;
  131 + }
  132 + if (i % 1024 == 0)
  133 + WATCHDOG_RESET();
  134 + }
  135 +
  136 + return ret;
  137 +}
  138 +
  139 +static int fpga_post_test3(ulong *start, ulong size)
  140 +{
  141 + int ret = 0;
  142 + ulong i = 0;
  143 + ulong *mem = start;
  144 + ulong readback;
  145 +
  146 + for (i = 0; i < size / sizeof(ulong); i++) {
  147 + mem[i] = i;
  148 + if (i % 1024 == 0)
  149 + WATCHDOG_RESET();
  150 + }
  151 +
  152 + for (i = 0; i < size / sizeof(ulong); i++) {
  153 + readback = mem[i];
  154 + if (readback != i) {
  155 + post_log("FPGA Memory error at %08x, "
  156 + "wrote %08x, read %08x !\n",
  157 + mem + i, i, readback);
  158 + ret = -1;
  159 + break;
  160 + }
  161 + if (i % 1024 == 0)
  162 + WATCHDOG_RESET();
  163 + }
  164 +
  165 + return ret;
  166 +}
  167 +
  168 +static int fpga_post_test4(ulong *start, ulong size)
  169 +{
  170 + int ret = 0;
  171 + ulong i = 0;
  172 + ulong *mem = start;
  173 + ulong readback;
  174 +
  175 + for (i = 0; i < size / sizeof(ulong); i++) {
  176 + mem[i] = ~i;
  177 + if (i % 1024 == 0)
  178 + WATCHDOG_RESET();
  179 + }
  180 +
  181 + for (i = 0; i < size / sizeof(ulong); i++) {
  182 + readback = mem[i];
  183 + if (readback != ~i) {
  184 + post_log("FPGA Memory error at %08x, "
  185 + "wrote %08x, read %08x !\n",
  186 + mem + i, ~i, readback);
  187 + ret = -1;
  188 + break;
  189 + }
  190 + if (i % 1024 == 0)
  191 + WATCHDOG_RESET();
  192 + }
  193 +
  194 + return ret;
  195 +}
  196 +
72 197 /* FPGA Memory-pattern-test */
73   -static int fpga_mem_test(void * address)
  198 +static int fpga_mem_test(void)
74 199 {
75   - int ret = 1;
76   - uint read_value;
77   - uint old_value;
78   - uint i = 0;
79   - /* save content */
80   - old_value = in_be32(address);
  200 + int ret = 0;
  201 + ulong* start = (ulong *)FPGA_RAM_START;
  202 + ulong size = FPGA_RAM_SIZE;
81 203  
82   - while (pattern[i] != 0) {
83   - out_be32(address, pattern[i]);
84   - /* read other location (protect against data lines capacity) */
85   - ret = in_be16((void *)FPGA_VERSION_REG);
86   - /* verify test pattern */
87   - read_value = in_be32(address);
  204 + if (ret == 0)
  205 + ret = fpga_post_test1(start, size, 0x00000000);
88 206  
89   - if (read_value != pattern[i]) {
90   - post_log("FPGA Memory test failed.");
91   - post_log(" write %08X, read %08X at address %08X\n",
92   - pattern[i], read_value, address);
  207 + if (ret == 0)
  208 + ret = fpga_post_test1(start, size, 0xffffffff);
  209 +
  210 + if (ret == 0)
  211 + ret = fpga_post_test1(start, size, 0x55555555);
  212 +
  213 + if (ret == 0)
  214 + ret = fpga_post_test1(start, size, 0xaaaaaaaa);
  215 +
  216 + WATCHDOG_RESET();
  217 +
  218 + if (ret == 0)
  219 + ret = fpga_post_test2(start, size);
  220 +
  221 + if (ret == 0)
  222 + ret = fpga_post_test3(start, size);
  223 +
  224 + if (ret == 0)
  225 + ret = fpga_post_test4(start, size);
  226 +
  227 + return ret;
  228 +}
  229 +
  230 +
  231 +
  232 +/* Verify FPGA addresslines */
  233 +static int fpga_post_addrline(ulong *address, ulong *base, ulong size)
  234 +{
  235 + unsigned long *target;
  236 + unsigned long *end;
  237 + unsigned long readback;
  238 + unsigned long xor;
  239 + int ret = 0;
  240 +
  241 + end = (ulong *)((ulong)base + size);
  242 + xor = 0;
  243 +
  244 + for (xor = sizeof(ulong); xor > 0; xor <<= 1) {
  245 + target = (ulong*)((ulong)address ^ xor);
  246 + if ((target >= base) && (target < end)) {
  247 + *address = ~*target;
  248 + readback = *target;
  249 +
  250 + if (readback == *address) {
  251 + post_log("Memory (address line) error at %08x"
  252 + "XOR value %08x !\n",
  253 + address, target, xor);
  254 + ret = -1;
  255 + break;
  256 + }
  257 + }
  258 + }
  259 +
  260 + return ret;
  261 +}
  262 +
  263 +/* Verify FPGA addresslines */
  264 +static int fpga_post_dataline(ulong *address)
  265 +{
  266 + unsigned long temp32 = 0;
  267 + int i = 0;
  268 + int ret = 0;
  269 +
  270 + for (i = 0; i < ARRAY_SIZE(pattern); i++) {
  271 + *address = pattern[i];
  272 + /*
  273 + * Put a different pattern on the data lines: otherwise they
  274 + * may float long enough to read back what we wrote.
  275 + */
  276 + *(address + 1) = otherpattern;
  277 + temp32 = *address;
  278 +
  279 + if (temp32 != pattern[i]){
  280 + post_log("Memory (date line) error at %08x, "
  281 + "wrote %08x, read %08x !\n",
  282 + address, pattern[i], temp32);
93 283 ret = 1;
94   - goto out;
95 284 }
96   - i++;
97 285 }
98 286  
99   - ret = 0;
100   -out:
101   - out_be32(address, old_value);
102 287 return ret;
103 288 }
  289 +
104 290 /* Verify FPGA, get version & memory size */
105 291 int fpga_post_test(int flags)
106 292 {
107   - uint address;
108 293 uint old_value;
109   - ushort version;
  294 + uint version;
110 295 uint read_value;
111 296 int ret = 0;
112 297  
113 298  
114 299  
115 300  
116 301  
117 302  
... ... @@ -120,24 +305,57 @@
120 305  
121 306 out_be32((void *)FPGA_SCRATCH_REG, old_value);
122 307  
123   - version = in_be16((void *)FPGA_VERSION_REG);
124   - post_log("FPGA : version %u.%u\n",
125   - (version >> 8) & 0xFF, version & 0xFF);
  308 + version = in_be32((void *)FPGA_VERSION_REG);
  309 + post_log("FPGA version %u.%u\n",
  310 + (version >> 8) & 0xFF, version & 0xFF);
126 311  
127 312 /* Enable write to FPGA RAM */
128 313 out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) | 0x1000);
129 314  
130   - read_value = get_ram_size((void *)CONFIG_SYS_FPGA_BASE_1, 0x4000);
131   - post_log("FPGA RAM size: %d bytes\n", read_value);
  315 + /* get RAM size */
  316 + read_value = get_ram_size((void *)CONFIG_SYS_FPGA_BASE_1, FPGA_RAM_SIZE);
  317 + post_log("FPGA RAM size %d bytes\n", read_value);
  318 + WATCHDOG_RESET();
132 319  
133   - for (address = 0; address < 0x1000; address++) {
134   - if (fpga_mem_test((void *)(FPGA_RAM_START + 4*address)) == 1) {
135   - ret = 1;
136   - goto out;
137   - }
  320 + /* copy fpga memory to DDR2 RAM*/
  321 + memcpy((void *)FPGA_BUFFER,(void *)FPGA_RAM_START, FPGA_RAM_SIZE);
  322 + WATCHDOG_RESET();
  323 +
  324 + /* Test datalines */
  325 + if (fpga_post_dataline((ulong *)FPGA_RAM_START)) {
  326 + ret = 1;
  327 + goto out;
138 328 }
  329 + WATCHDOG_RESET();
139 330  
  331 + /* Test addresslines */
  332 + if (fpga_post_addrline((ulong *)FPGA_RAM_START,
  333 + (ulong *)FPGA_RAM_START, FPGA_RAM_SIZE)) {
  334 + ret = 1;
  335 + goto out;
  336 + }
  337 + WATCHDOG_RESET();
  338 + if (fpga_post_addrline((ulong *)FPGA_RAM_END - sizeof(long),
  339 + (ulong *)FPGA_RAM_START, FPGA_RAM_SIZE)) {
  340 + ret = 1;
  341 + goto out;
  342 + }
  343 + WATCHDOG_RESET();
  344 +
  345 + /* Memory Pattern Test */
  346 + if (fpga_mem_test()) {
  347 + ret = 1;
  348 + goto out;
  349 + }
  350 + WATCHDOG_RESET();
  351 +
  352 + /* restore memory */
  353 + memcpy((void *)FPGA_RAM_START,(void *)FPGA_BUFFER, FPGA_RAM_SIZE);
  354 + WATCHDOG_RESET();
  355 +
140 356 out:
  357 + /* Disable write to RAM */
  358 + out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) & 0xEFFF);
141 359 return ret;
142 360 }
143 361  
post/board/lwmon5/gdc.c
Diff comments   View file @ f14ae41
... ... @@ -28,18 +28,39 @@
28 28 */
29 29  
30 30 #include <post.h>
31   -
  31 +#include <watchdog.h>
32 32 #include <asm/io.h>
  33 +#include <video.h>
33 34  
34 35 DECLARE_GLOBAL_DATA_PTR;
35 36  
36   -#define GDC_SCRATCH_REG 0xC1FF8044
37   -#define GDC_VERSION_REG 0xC1FF8084
38   -#define GDC_RAM_START 0xC0000000
39   -#define GDC_RAM_END 0xC2000000
  37 +#define GDC_SCRATCH_REG 0xC1FF8044
  38 +#define GDC_VERSION_REG 0xC1FF8084
  39 +#define GDC_HOST_BASE 0xC1FC0000
  40 +#define GDC_RAM_START 0xC0000000
  41 +#define GDC_RAM_END (GDC_HOST_BASE - 1)
  42 +#define GDC_RAM_SIZE (GDC_RAM_END - GDC_RAM_START)
40 43  
41 44 #if CONFIG_POST & CONFIG_SYS_POST_BSPEC4
42 45  
  46 +const static unsigned long pattern[] = {
  47 + 0xffffffff,
  48 + 0xaaaaaaaa,
  49 + 0xcccccccc,
  50 + 0xf0f0f0f0,
  51 + 0xff00ff00,
  52 + 0xffff0000,
  53 + 0x0000ffff,
  54 + 0x00ff00ff,
  55 + 0x0f0f0f0f,
  56 + 0x33333333,
  57 + 0x55555555,
  58 + 0x00000000
  59 +};
  60 +
  61 +const static unsigned long otherpattern = 0x01234567;
  62 +
  63 +/* test write/read og a given LIME Register */
43 64 static int gdc_test_reg_one(uint value)
44 65 {
45 66 int ret;
46 67  
47 68  
... ... @@ -53,17 +74,229 @@
53 74 read_value = in_be32((void *)GDC_SCRATCH_REG);
54 75 if (read_value != value) {
55 76 post_log("GDC SCRATCH test failed write %08X, read %08X\n",
56   - value, read_value);
  77 + value, read_value);
57 78 }
58 79  
59 80 return (read_value != value);
60 81 }
61 82  
62   -/* Verify GDC, get memory size */
  83 +/* test with a given static 32 bit pattern in a given memory addressrange */
  84 +static int gdc_post_test1(ulong *start, ulong size, ulong val)
  85 +{
  86 + int ret = 0;
  87 + ulong i = 0;
  88 + ulong *mem = start;
  89 + ulong readback;
  90 +
  91 + for (i = 0; i < size / sizeof(ulong); i++) {
  92 + mem[i] = val;
  93 + if (i % 1024 == 0)
  94 + WATCHDOG_RESET();
  95 + }
  96 +
  97 + for (i = 0; i < size / sizeof(ulong); i++) {
  98 + readback = mem[i];
  99 + if (readback != val) {
  100 + post_log("GDC Memory error at %08x, "
  101 + "wrote %08x, read %08x !\n",
  102 + mem + i, val, readback);
  103 + ret = -1;
  104 + break;
  105 + }
  106 + if (i % 1024 == 0)
  107 + WATCHDOG_RESET();
  108 + }
  109 +
  110 + return ret;
  111 +}
  112 +
  113 +/* test with dynamic 32 bit pattern in a given memory addressrange */
  114 +static int gdc_post_test2(ulong *start, ulong size)
  115 +{
  116 + int ret = 0;
  117 + ulong i = 0;
  118 + ulong *mem = start;
  119 + ulong readback;
  120 +
  121 + for (i = 0; i < size / sizeof(ulong); i++) {
  122 + mem[i] = 1 << (i % 32);
  123 + if (i % 1024 == 0)
  124 + WATCHDOG_RESET();
  125 + }
  126 +
  127 + for (i = 0; i < size / sizeof(ulong); i++) {
  128 + readback = mem[i];
  129 + if (readback != 1 << (i % 32)) {
  130 + post_log("GDC Memory error at %08x, "
  131 + "wrote %08x, read %08x !\n",
  132 + mem + i, 1 << (i % 32), readback);
  133 + ret = -1;
  134 + break;
  135 + }
  136 + if (i % 1024 == 0)
  137 + WATCHDOG_RESET();
  138 + }
  139 +
  140 + return ret;
  141 +}
  142 +
  143 +/* test with dynamic 32 bit pattern in a given memory addressrange */
  144 +static int gdc_post_test3(ulong *start, ulong size)
  145 +{
  146 + int ret = 0;
  147 + ulong i = 0;
  148 + ulong *mem = start;
  149 + ulong readback;
  150 +
  151 + for (i = 0; i < size / sizeof(ulong); i++) {
  152 + mem[i] = i;
  153 + if (i % 1024 == 0)
  154 + WATCHDOG_RESET();
  155 + }
  156 +
  157 + for (i = 0; i < size / sizeof(ulong); i++) {
  158 + readback = mem[i];
  159 + if (readback != i) {
  160 + post_log("GDC Memory error at %08x, "
  161 + "wrote %08x, read %08x !\n",
  162 + mem + i, i, readback);
  163 + ret = -1;
  164 + break;
  165 + }
  166 + if (i % 1024 == 0)
  167 + WATCHDOG_RESET();
  168 + }
  169 +
  170 + return ret;
  171 +}
  172 +
  173 +/* test with dynamic 32 bit pattern in a given memory addressrange */
  174 +static int gdc_post_test4(ulong *start, ulong size)
  175 +{
  176 + int ret = 0;
  177 + ulong i = 0;
  178 + ulong *mem = start;
  179 + ulong readback;
  180 +
  181 + for (i = 0; i < size / sizeof(ulong); i++) {
  182 + mem[i] = ~i;
  183 + if (i % 1024 == 0)
  184 + WATCHDOG_RESET();
  185 + }
  186 +
  187 + for (i = 0; i < size / sizeof(ulong); i++) {
  188 + readback = mem[i];
  189 + if (readback != ~i) {
  190 + post_log("GDC Memory error at %08x, "
  191 + "wrote %08x, read %08x !\n",
  192 + mem + i, ~i, readback);
  193 + ret = -1;
  194 + break;
  195 + }
  196 + if (i % 1024 == 0)
  197 + WATCHDOG_RESET();
  198 + }
  199 +
  200 + return ret;
  201 +}
  202 +
  203 +/* do some patterntests in a given addressrange */
  204 +int gdc_mem_test(ulong *start, ulong size)
  205 +{
  206 + int ret = 0;
  207 +
  208 + /*
  209 + * check addressrange and do different static and dynamic
  210 + * pattern tests with it.
  211 + */
  212 + if (((void *)start) + size <= (void *)GDC_RAM_END) {
  213 + if (ret == 0)
  214 + ret = gdc_post_test1(start, size, 0x00000000);
  215 +
  216 + if (ret == 0)
  217 + ret = gdc_post_test1(start, size, 0xffffffff);
  218 +
  219 + if (ret == 0)
  220 + ret = gdc_post_test1(start, size, 0x55555555);
  221 +
  222 + if (ret == 0)
  223 + ret = gdc_post_test1(start, size, 0xaaaaaaaa);
  224 +
  225 + if (ret == 0)
  226 + ret = gdc_post_test2(start, size);
  227 +
  228 + if (ret == 0)
  229 + ret = gdc_post_test3(start, size);
  230 +
  231 + if (ret == 0)
  232 + ret = gdc_post_test4(start, size);
  233 + }
  234 +
  235 + return ret;
  236 +}
  237 +
  238 +/* test function of gdc memory addresslines*/
  239 +static int gdc_post_addrline(ulong *address, ulong *base, ulong size)
  240 +{
  241 + ulong *target;
  242 + ulong *end;
  243 + ulong readback = 0;
  244 + ulong xor = 0;
  245 + int ret = 0;
  246 +
  247 + end = (ulong *)((ulong)base + size);
  248 +
  249 + for (xor = sizeof(long); xor > 0; xor <<= 1) {
  250 + target = (ulong *)((ulong)address ^ xor);
  251 + if ((target >= base) && (target < end)) {
  252 + *address = ~*target;
  253 + readback = *target;
  254 + }
  255 +
  256 + if (readback == *address) {
  257 + post_log("GDC Memory (address line) error at %08x"
  258 + "XOR value %08x !\n",
  259 + address, target , xor);
  260 + ret = -1;
  261 + break;
  262 + }
  263 + }
  264 +
  265 + return ret;
  266 +}
  267 +
  268 +static int gdc_post_dataline(ulong *address)
  269 +{
  270 + unsigned long temp32 = 0;
  271 + int i = 0;
  272 + int ret = 0;
  273 +
  274 + for (i = 0; i < ARRAY_SIZE(pattern); i++) {
  275 + *address = pattern[i];
  276 + /*
  277 + * Put a different pattern on the data lines: otherwise they
  278 + * may float long enough to read back what we wrote.
  279 + */
  280 + *(address + 1) = otherpattern;
  281 + temp32 = *address;
  282 +
  283 + if (temp32 != pattern[i]){
  284 + post_log("GDC Memory (date line) error at %08x, "
  285 + "wrote %08x, read %08x !\n",
  286 + address, pattern[i], temp32);
  287 + ret = 1;
  288 + }
  289 + }
  290 +
  291 + return ret;
  292 +}
  293 +
  294 +/* Verify GDC, get memory size, verify GDC memory */
63 295 int gdc_post_test(int flags)
64 296 {
65   - uint old_value;
66   - int ret = 0;
  297 + uint old_value;
  298 + int i = 0;
  299 + int ret = 0;
67 300  
68 301 post_log("\n");
69 302 old_value = in_be32((void *)GDC_SCRATCH_REG);
70 303  
71 304  
... ... @@ -84,13 +317,64 @@
84 317  
85 318 old_value = in_be32((void *)GDC_VERSION_REG);
86 319 post_log("GDC chip version %u.%u, year %04X\n",
87   - (old_value >> 8) & 0xFF, old_value & 0xFF,
88   - (old_value >> 16) & 0xFFFF);
  320 + (old_value >> 8) & 0xFF, old_value & 0xFF,
  321 + (old_value >> 16) & 0xFFFF);
89 322  
90 323 old_value = get_ram_size((void *)GDC_RAM_START,
91   - GDC_RAM_END - GDC_RAM_START);
  324 + 0x02000000);
  325 +
  326 + debug("GDC RAM size (ist): %d bytes\n", old_value);
  327 + debug("GDC RAM size (soll): %d bytes\n", GDC_RAM_SIZE);
92 328 post_log("GDC RAM size: %d bytes\n", old_value);
93 329  
  330 + /* Test SDRAM datalines */
  331 + if (gdc_post_dataline((ulong *)GDC_RAM_START)) {
  332 + ret = 1;
  333 + goto out;
  334 + }
  335 + WATCHDOG_RESET();
  336 +
  337 + /* Test SDRAM adresslines */
  338 + if (gdc_post_addrline((ulong *)GDC_RAM_START,
  339 + (ulong *)GDC_RAM_START, GDC_RAM_SIZE)) {
  340 + ret = 1;
  341 + goto out;
  342 + }
  343 + WATCHDOG_RESET();
  344 + if (gdc_post_addrline((ulong *)GDC_RAM_END - sizeof(long),
  345 + (ulong *)GDC_RAM_START, GDC_RAM_SIZE)) {
  346 + ret = 1;
  347 + goto out;
  348 + }
  349 + WATCHDOG_RESET();
  350 +
  351 + /* memory pattern test */
  352 + debug("GDC Memory test (flags %8x:%8x)\n", flags,
  353 + POST_SLOWTEST | POST_MANUAL);
  354 +
  355 + if (flags & POST_MANUAL) {
  356 + debug("Full memory test\n");
  357 + if (gdc_mem_test((ulong *)GDC_RAM_START, GDC_RAM_SIZE)) {
  358 + ret = 1;
  359 + goto out;
  360 + }
  361 + /* load splashscreen again */
  362 + } else {
  363 + debug("smart memory test\n");
  364 + for (i = 0; i < (GDC_RAM_SIZE >> 20) && ret == 0; i++) {
  365 + if (ret == 0)
  366 + ret = gdc_mem_test((ulong *)(GDC_RAM_START +
  367 + (i << 20)),
  368 + 0x800);
  369 + if (ret == 0)
  370 + ret = gdc_mem_test((ulong *)(GDC_RAM_START +
  371 + (i << 20) + 0xff800),
  372 + 0x800);
  373 + }
  374 + }
  375 + WATCHDOG_RESET();
  376 +
  377 +out:
94 378 return ret;
95 379 }
96 380 #endif /* CONFIG_POST & CONFIG_SYS_POST_BSPEC4 */
post/board/lwmon5/sysmon.c
Diff comments   View file @ f14ae41
... ... @@ -56,7 +56,7 @@
56 56 DECLARE_GLOBAL_DATA_PTR;
57 57  
58 58 /* from dspic.c */
59   -extern int dspic_read(ushort reg);
  59 +extern int dspic_read(ushort reg, ushort *data);
60 60  
61 61 #define REG_TEMPERATURE 0x12BC
62 62 #define REG_VOLTAGE_5V 0x12CA
63 63  
64 64  
65 65  
66 66  
67 67  
... ... @@ -76,31 +76,38 @@
76 76 typedef struct sysmon_s sysmon_t;
77 77 typedef struct sysmon_table_s sysmon_table_t;
78 78  
79   -static void sysmon_dspic_init (sysmon_t * this);
80   -static int sysmon_dspic_read (sysmon_t * this, uint addr);
81   -static void sysmon_backlight_disable (sysmon_table_t * this);
  79 +static void sysmon_dspic_init(sysmon_t *this);
  80 +static int sysmon_dspic_read(sysmon_t *this, uint addr, int *val);
  81 +static int sysmon_dspic_read_sgn(sysmon_t *this, uint addr, int *val);
  82 +static void sysmon_backlight_disable(sysmon_table_t *this);
82 83  
83   -struct sysmon_s
84   -{
  84 +struct sysmon_s {
85 85 uchar chip;
86 86 void (*init)(sysmon_t *);
87   - int (*read)(sysmon_t *, uint);
  87 + int (*read)(sysmon_t *, uint, int *);
88 88 };
89 89  
90   -static sysmon_t sysmon_dspic =
91   - {CONFIG_SYS_I2C_DSPIC_IO_ADDR, sysmon_dspic_init, sysmon_dspic_read};
  90 +static sysmon_t sysmon_dspic = {
  91 + CONFIG_SYS_I2C_DSPIC_IO_ADDR,
  92 + sysmon_dspic_init,
  93 + sysmon_dspic_read
  94 +};
92 95  
93   -static sysmon_t * sysmon_list[] =
94   -{
  96 +static sysmon_t sysmon_dspic_sgn = {
  97 + CONFIG_SYS_I2C_DSPIC_IO_ADDR,
  98 + sysmon_dspic_init,
  99 + sysmon_dspic_read_sgn
  100 +};
  101 +
  102 +static sysmon_t *sysmon_list[] = {
95 103 &sysmon_dspic,
96 104 NULL
97 105 };
98 106  
99   -struct sysmon_table_s
100   -{
101   - char * name;
102   - char * unit_name;
103   - sysmon_t * sysmon;
  107 +struct sysmon_table_s {
  108 + char *name;
  109 + char *unit_name;
  110 + sysmon_t *sysmon;
104 111 void (*exec_before)(sysmon_table_t *);
105 112 void (*exec_after)(sysmon_table_t *);
106 113  
107 114  
108 115  
109 116  
110 117  
111 118  
112 119  
113 120  
... ... @@ -118,37 +125,43 @@
118 125 uint addr;
119 126 };
120 127  
121   -static sysmon_table_t sysmon_table[] =
122   -{
  128 +static sysmon_table_t sysmon_table[] = {
123 129 {
124   - "Temperature", " C", &sysmon_dspic, NULL, sysmon_backlight_disable,
125   - 1, 1, -32768, 32767, 0xFFFF,
126   - 0x8000 + TEMPERATURE_MIN, 0x8000 + TEMPERATURE_MAX, 0,
127   - 0x8000 + TEMPERATURE_DISPLAY_MIN, 0x8000 + TEMPERATURE_DISPLAY_MAX, 0,
128   - REG_TEMPERATURE,
  130 + "Temperature", " C", &sysmon_dspic, NULL, sysmon_backlight_disable,
  131 + 1, 1, -32768, 32767, 0xFFFF,
  132 + 0x8000 + TEMPERATURE_MIN, 0x8000 + TEMPERATURE_MAX, 0,
  133 + 0x8000 + TEMPERATURE_DISPLAY_MIN, 0x8000 + TEMPERATURE_DISPLAY_MAX, 0,
  134 + REG_TEMPERATURE,
129 135 },
130 136  
131 137 {
132   - "+ 5 V", "V", &sysmon_dspic, NULL, NULL,
133   - 100, 1000, -0x8000, 0x7FFF, 0xFFFF,
134   - 0x8000 + VOLTAGE_5V_MIN, 0x8000 + VOLTAGE_5V_MAX, 0,
135   - 0x8000 + VOLTAGE_5V_MIN, 0x8000 + VOLTAGE_5V_MAX, 0,
136   - REG_VOLTAGE_5V,
  138 + "+ 5 V", "V", &sysmon_dspic, NULL, NULL,
  139 + 100, 1000, -0x8000, 0x7FFF, 0xFFFF,
  140 + 0x8000 + VOLTAGE_5V_MIN, 0x8000 + VOLTAGE_5V_MAX, 0,
  141 + 0x8000 + VOLTAGE_5V_MIN, 0x8000 + VOLTAGE_5V_MAX, 0,
  142 + REG_VOLTAGE_5V,
137 143 },
138 144  
139 145 {
140   - "+ 5 V standby", "V", &sysmon_dspic, NULL, NULL,
141   - 100, 1000, -0x8000, 0x7FFF, 0xFFFF,
142   - 0x8000 + VOLTAGE_5V_STANDBY_MIN, 0x8000 + VOLTAGE_5V_STANDBY_MAX, 0,
143   - 0x8000 + VOLTAGE_5V_STANDBY_MIN, 0x8000 + VOLTAGE_5V_STANDBY_MAX, 0,
144   - REG_VOLTAGE_5V_STANDBY,
  146 + "+ 5 V standby", "V", &sysmon_dspic, NULL, NULL,
  147 + 100, 1000, -0x8000, 0x7FFF, 0xFFFF,
  148 + 0x8000 + VOLTAGE_5V_STANDBY_MIN, 0x8000 + VOLTAGE_5V_STANDBY_MAX, 0,
  149 + 0x8000 + VOLTAGE_5V_STANDBY_MIN, 0x8000 + VOLTAGE_5V_STANDBY_MAX, 0,
  150 + REG_VOLTAGE_5V_STANDBY,
145 151 },
  152 +
  153 + {
  154 + "Temperature", "ยฐC", &sysmon_dspic_sgn, NULL, sysmon_backlight_disable,
  155 + 1, 1, -32768, 32767, 0xFFFF,
  156 + 0x8000 + TEMPERATURE_MIN, 0x8000 + TEMPERATURE_MAX, 0,
  157 + 0x8000 + TEMPERATURE_DISPLAY_MIN, 0x8000 + TEMPERATURE_DISPLAY_MAX, 0,
  158 + REG_TEMPERATURE,
  159 + },
146 160 };
147   -static int sysmon_table_size = sizeof(sysmon_table) / sizeof(sysmon_table[0]);
148 161  
149   -int sysmon_init_f (void)
  162 +int sysmon_init_f(void)
150 163 {
151   - sysmon_t ** l;
  164 + sysmon_t **l;
152 165  
153 166 for (l = sysmon_list; *l; l++)
154 167 (*l)->init(*l);
155 168  
... ... @@ -156,12 +169,12 @@
156 169 return 0;
157 170 }
158 171  
159   -void sysmon_reloc (void)
  172 +void sysmon_reloc(void)
160 173 {
161 174 /* Do nothing for now, sysmon_reloc() is required by the sysmon post */
162 175 }
163 176  
164   -static char *sysmon_unit_value (sysmon_table_t *s, uint val)
  177 +static char *sysmon_unit_value(sysmon_table_t *s, uint val)
165 178 {
166 179 static char buf[32];
167 180 char *p, sign;
168 181  
169 182  
170 183  
... ... @@ -176,14 +189,13 @@
176 189 if (unit_val < 0) {
177 190 sign = '-';
178 191 unit_val = -unit_val;
179   - } else
  192 + } else {
180 193 sign = '+';
  194 + }
181 195  
182 196 p = buf + sprintf(buf, "%c%2d", sign, unit_val / s->unit_div);
183 197  
184   -
185 198 frac = unit_val % s->unit_div;
186   -
187 199 frac /= (s->unit_div / s->unit_precision);
188 200  
189 201 decimal = s->unit_precision;
190 202  
191 203  
192 204  
193 205  
194 206  
195 207  
196 208  
197 209  
198 210  
199 211  
200 212  
201 213  
202 214  
203 215  
... ... @@ -197,58 +209,84 @@
197 209 return buf;
198 210 }
199 211  
200   -static void sysmon_dspic_init (sysmon_t * this)
  212 +static void sysmon_dspic_init(sysmon_t *this)
201 213 {
202 214 }
203 215  
204   -static int sysmon_dspic_read (sysmon_t * this, uint addr)
  216 +static int sysmon_dspic_read(sysmon_t *this, uint addr, int *val)
205 217 {
206   - int res = dspic_read(addr);
  218 + ushort data;
207 219  
208   - /* To fit into the table range we should add 0x8000 */
209   - return (res == -1) ? -1 : (res + 0x8000);
  220 + if (dspic_read(addr, &data) == 0){
  221 + /* To fit into the table range we should add 0x8000 */
  222 + *val = data + 0x8000;
  223 + return 0;
  224 + }
  225 +
  226 + return -1;
210 227 }
211 228  
212   -static void sysmon_backlight_disable (sysmon_table_t * this)
  229 +static int sysmon_dspic_read_sgn(sysmon_t *this, uint addr, int *val)
213 230 {
  231 + ushort data;
  232 +
  233 + if (dspic_read(addr, &data) == 0){
  234 + /* To fit into the table range we should add 0x8000 */
  235 + *val = (signed short)data + 0x8000;
  236 + return 0;
  237 + }
  238 +
  239 + return -1;
  240 +}
  241 +
  242 +static void sysmon_backlight_disable(sysmon_table_t *this)
  243 +{
214 244 #if defined(CONFIG_VIDEO)
215 245 board_backlight_switch(this->val_valid_alt);
216 246 #endif
217 247 }
218 248  
219   -int sysmon_post_test (int flags)
  249 +int sysmon_post_test(int flags)
220 250 {
221 251 int res = 0;
222 252 sysmon_table_t * t;
223 253 int val;
224 254  
225   - for (t = sysmon_table; t < sysmon_table + sysmon_table_size; t ++) {
  255 + for (t = sysmon_table; t < sysmon_table + ARRAY_SIZE(sysmon_table); t++) {
  256 + t->val_valid = 1;
226 257 if (t->exec_before)
227 258 t->exec_before(t);
228 259  
229   - val = t->sysmon->read(t->sysmon, t->addr);
230   - if (val != -1) {
231   - t->val_valid = val >= t->val_min && val <= t->val_max;
232   - t->val_valid_alt = val >= t->val_min_alt && val <= t->val_max_alt;
233   - } else {
  260 + if (t->sysmon->read(t->sysmon, t->addr, &val) != 0) {
234 261 t->val_valid = 0;
235 262 t->val_valid_alt = 0;
  263 + post_log(": read failed\n");
  264 + res = 1;
  265 + break;
236 266 }
237 267  
  268 + if (t->val_valid != 0) {
  269 + t->val_valid = val >= t->val_min && val <= t->val_max;
  270 + t->val_valid_alt = val >= t->val_min_alt && val <= t->val_max_alt;
  271 + }
  272 +
238 273 if (t->exec_after)
239 274 t->exec_after(t);
240 275  
241   - if ((!t->val_valid) || (flags & POST_MANUAL)) {
242   - printf("%-17s = %-10s ", t->name, sysmon_unit_value(t, val));
243   - printf("allowed range");
244   - printf(" %-8s ..", sysmon_unit_value(t, t->val_min));
245   - printf(" %-8s", sysmon_unit_value(t, t->val_max));
246   - printf(" %s\n", t->val_valid ? "OK" : "FAIL");
  276 + if ((!t->val_valid) || (flags)) {
  277 + post_log("\n\t%-17s = %-10s ", t->name, sysmon_unit_value(t, val));
  278 + post_log("allowed range");
  279 + post_log(" %-8s ..", sysmon_unit_value(t, t->val_min));
  280 + post_log(" %-8s", sysmon_unit_value(t, t->val_max));
  281 + post_log(" %s", t->val_valid ? "OK" : "FAIL");
247 282 }
248 283  
249   - if (!t->val_valid)
  284 + if (!t->val_valid) {
250 285 res = 1;
  286 + break;
  287 + }
251 288 }
  289 + post_log("\n");
252 290  
253 291 return res;
254 292 }
post/board/lwmon5/watchdog.c
Diff comments   View file @ f14ae41
... ... @@ -57,8 +57,11 @@
57 57 * 3.1. GPIO62 is low
58 58 * Assuming system voltage failure.
59 59 */
60   - post_log("Abnormal voltage detected (GPIO62)\n");
  60 + post_log("sysmon1 Abnormal voltage detected (GPIO62)\n");
  61 + post_log("POST sysmon1 FAILED\n");
61 62 return 1;
  63 + } else {
  64 + post_log("sysmon1 PASSED\n");
62 65 }
63 66  
64 67 return 0;
... ... @@ -117,10 +120,16 @@
117 120 ulong time;
118 121 /* 3.3.1. So, the test succeed, save measured time to syslog. */
119 122 time = in_be32((void *)CONFIG_SYS_WATCHDOG_TIME_ADDR);
120   - post_log("hw watchdog time : %u ms, passed ", time);
121   - /* 3.3.2. Set scratch register 1 to 0x0000xxxx */
122   - watchdog_magic_write(0);
123   - return 0;
  123 + if (time > 90 ) { /* ms*/
  124 + post_log("hw watchdog time : %u ms, passed ", time);
  125 + /* 3.3.2. Set scratch register 1 to 0x0000xxxx */
  126 + watchdog_magic_write(0);
  127 + return 0;
  128 + } else {
  129 + /*test minimum watchdogtime */
  130 + post_log("hw watchdog time : %u ms, failed ", time);
  131 + return 2;
  132 + }
124 133 }
125 134 return -1;
126 135 }