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Commit f15ece388f57a3b35704b5f2306ad462ccf6e2e8

Authored by Peng Fan
Committed by Stefano Babic
1 parent 2ee4065571
Exists in v2017.01-smarct4x and in 28 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2017.01-smarct3x, v2017.01-smarct3x-emmc

imx: imx6ul: disable POR_B internal pull up 

>From TO1.1, SNVS adds internal pull up control for POR_B,
the register filed is GPBIT[1:0], after system boot up,
it can be set to 2b'01 to disable internal pull up.
It can save about 30uA power in SNVS mode.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>

Showing 1 changed file with 21 additions and 8 deletions Inline Diff

arch/arm/cpu/armv7/mx6/soc.c
Diff comments   View file @ f15ece3
1 /* 1 /*
2 * (C) Copyright 2007 2 * (C) Copyright 2007
3 * Sascha Hauer, Pengutronix 3 * Sascha Hauer, Pengutronix
4 * 4 *
5 * (C) Copyright 2009 Freescale Semiconductor, Inc. 5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
6 * 6 *
7 * SPDX-License-Identifier: GPL-2.0+ 7 * SPDX-License-Identifier: GPL-2.0+
8 */ 8 */
9 9
10 #include <common.h> 10 #include <common.h>
11 #include <linux/errno.h> 11 #include <linux/errno.h>
12 #include <asm/io.h> 12 #include <asm/io.h>
13 #include <asm/arch/imx-regs.h> 13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h> 14 #include <asm/arch/clock.h>
15 #include <asm/arch/sys_proto.h> 15 #include <asm/arch/sys_proto.h>
16 #include <asm/imx-common/boot_mode.h> 16 #include <asm/imx-common/boot_mode.h>
17 #include <asm/imx-common/dma.h> 17 #include <asm/imx-common/dma.h>
18 #include <asm/imx-common/hab.h> 18 #include <asm/imx-common/hab.h>
19 #include <stdbool.h> 19 #include <stdbool.h>
20 #include <asm/arch/mxc_hdmi.h> 20 #include <asm/arch/mxc_hdmi.h>
21 #include <asm/arch/crm_regs.h> 21 #include <asm/arch/crm_regs.h>
22 #include <dm.h> 22 #include <dm.h>
23 #include <imx_thermal.h> 23 #include <imx_thermal.h>
24 #include <mmc.h> 24 #include <mmc.h>
25 25
26 enum ldo_reg { 26 enum ldo_reg {
27 LDO_ARM, 27 LDO_ARM,
28 LDO_SOC, 28 LDO_SOC,
29 LDO_PU, 29 LDO_PU,
30 }; 30 };
31 31
32 struct scu_regs { 32 struct scu_regs {
33 u32 ctrl; 33 u32 ctrl;
34 u32 config; 34 u32 config;
35 u32 status; 35 u32 status;
36 u32 invalidate; 36 u32 invalidate;
37 u32 fpga_rev; 37 u32 fpga_rev;
38 }; 38 };
39 39
40 #if defined(CONFIG_IMX_THERMAL) 40 #if defined(CONFIG_IMX_THERMAL)
41 static const struct imx_thermal_plat imx6_thermal_plat = { 41 static const struct imx_thermal_plat imx6_thermal_plat = {
42 .regs = (void *)ANATOP_BASE_ADDR, 42 .regs = (void *)ANATOP_BASE_ADDR,
43 .fuse_bank = 1, 43 .fuse_bank = 1,
44 .fuse_word = 6, 44 .fuse_word = 6,
45 }; 45 };
46 46
47 U_BOOT_DEVICE(imx6_thermal) = { 47 U_BOOT_DEVICE(imx6_thermal) = {
48 .name = "imx_thermal", 48 .name = "imx_thermal",
49 .platdata = &imx6_thermal_plat, 49 .platdata = &imx6_thermal_plat,
50 }; 50 };
51 #endif 51 #endif
52 52
53 #if defined(CONFIG_SECURE_BOOT) 53 #if defined(CONFIG_SECURE_BOOT)
54 struct imx_sec_config_fuse_t const imx_sec_config_fuse = { 54 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
55 .bank = 0, 55 .bank = 0,
56 .word = 6, 56 .word = 6,
57 }; 57 };
58 #endif 58 #endif
59 59
60 u32 get_nr_cpus(void) 60 u32 get_nr_cpus(void)
61 { 61 {
62 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; 62 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
63 return readl(&scu->config) & 3; 63 return readl(&scu->config) & 3;
64 } 64 }
65 65
66 u32 get_cpu_rev(void) 66 u32 get_cpu_rev(void)
67 { 67 {
68 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; 68 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
69 u32 reg = readl(&anatop->digprog_sololite); 69 u32 reg = readl(&anatop->digprog_sololite);
70 u32 type = ((reg >> 16) & 0xff); 70 u32 type = ((reg >> 16) & 0xff);
71 u32 major, cfg = 0; 71 u32 major, cfg = 0;
72 72
73 if (type != MXC_CPU_MX6SL) { 73 if (type != MXC_CPU_MX6SL) {
74 reg = readl(&anatop->digprog); 74 reg = readl(&anatop->digprog);
75 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; 75 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
76 cfg = readl(&scu->config) & 3; 76 cfg = readl(&scu->config) & 3;
77 type = ((reg >> 16) & 0xff); 77 type = ((reg >> 16) & 0xff);
78 if (type == MXC_CPU_MX6DL) { 78 if (type == MXC_CPU_MX6DL) {
79 if (!cfg) 79 if (!cfg)
80 type = MXC_CPU_MX6SOLO; 80 type = MXC_CPU_MX6SOLO;
81 } 81 }
82 82
83 if (type == MXC_CPU_MX6Q) { 83 if (type == MXC_CPU_MX6Q) {
84 if (cfg == 1) 84 if (cfg == 1)
85 type = MXC_CPU_MX6D; 85 type = MXC_CPU_MX6D;
86 } 86 }
87 87
88 } 88 }
89 major = ((reg >> 8) & 0xff); 89 major = ((reg >> 8) & 0xff);
90 if ((major >= 1) && 90 if ((major >= 1) &&
91 ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) { 91 ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
92 major--; 92 major--;
93 type = MXC_CPU_MX6QP; 93 type = MXC_CPU_MX6QP;
94 if (cfg == 1) 94 if (cfg == 1)
95 type = MXC_CPU_MX6DP; 95 type = MXC_CPU_MX6DP;
96 } 96 }
97 reg &= 0xff; /* mx6 silicon revision */ 97 reg &= 0xff; /* mx6 silicon revision */
98 return (type << 12) | (reg + (0x10 * (major + 1))); 98 return (type << 12) | (reg + (0x10 * (major + 1)));
99 } 99 }
100 100
101 /* 101 /*
102 * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440) 102 * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
103 * defines a 2-bit SPEED_GRADING 103 * defines a 2-bit SPEED_GRADING
104 */ 104 */
105 #define OCOTP_CFG3_SPEED_SHIFT 16 105 #define OCOTP_CFG3_SPEED_SHIFT 16
106 #define OCOTP_CFG3_SPEED_800MHZ 0 106 #define OCOTP_CFG3_SPEED_800MHZ 0
107 #define OCOTP_CFG3_SPEED_850MHZ 1 107 #define OCOTP_CFG3_SPEED_850MHZ 1
108 #define OCOTP_CFG3_SPEED_1GHZ 2 108 #define OCOTP_CFG3_SPEED_1GHZ 2
109 #define OCOTP_CFG3_SPEED_1P2GHZ 3 109 #define OCOTP_CFG3_SPEED_1P2GHZ 3
110 110
111 /* 111 /*
112 * For i.MX6UL 112 * For i.MX6UL
113 */ 113 */
114 #define OCOTP_CFG3_SPEED_528MHZ 1 114 #define OCOTP_CFG3_SPEED_528MHZ 1
115 #define OCOTP_CFG3_SPEED_696MHZ 2 115 #define OCOTP_CFG3_SPEED_696MHZ 2
116 116
117 u32 get_cpu_speed_grade_hz(void) 117 u32 get_cpu_speed_grade_hz(void)
118 { 118 {
119 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 119 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
120 struct fuse_bank *bank = &ocotp->bank[0]; 120 struct fuse_bank *bank = &ocotp->bank[0];
121 struct fuse_bank0_regs *fuse = 121 struct fuse_bank0_regs *fuse =
122 (struct fuse_bank0_regs *)bank->fuse_regs; 122 (struct fuse_bank0_regs *)bank->fuse_regs;
123 uint32_t val; 123 uint32_t val;
124 124
125 val = readl(&fuse->cfg3); 125 val = readl(&fuse->cfg3);
126 val >>= OCOTP_CFG3_SPEED_SHIFT; 126 val >>= OCOTP_CFG3_SPEED_SHIFT;
127 val &= 0x3; 127 val &= 0x3;
128 128
129 if (is_mx6ul() || is_mx6ull()) { 129 if (is_mx6ul() || is_mx6ull()) {
130 if (val == OCOTP_CFG3_SPEED_528MHZ) 130 if (val == OCOTP_CFG3_SPEED_528MHZ)
131 return 528000000; 131 return 528000000;
132 else if (val == OCOTP_CFG3_SPEED_696MHZ) 132 else if (val == OCOTP_CFG3_SPEED_696MHZ)
133 return 69600000; 133 return 69600000;
134 else 134 else
135 return 0; 135 return 0;
136 } 136 }
137 137
138 switch (val) { 138 switch (val) {
139 /* Valid for IMX6DQ */ 139 /* Valid for IMX6DQ */
140 case OCOTP_CFG3_SPEED_1P2GHZ: 140 case OCOTP_CFG3_SPEED_1P2GHZ:
141 if (is_mx6dq() || is_mx6dqp()) 141 if (is_mx6dq() || is_mx6dqp())
142 return 1200000000; 142 return 1200000000;
143 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */ 143 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
144 case OCOTP_CFG3_SPEED_1GHZ: 144 case OCOTP_CFG3_SPEED_1GHZ:
145 return 996000000; 145 return 996000000;
146 /* Valid for IMX6DQ */ 146 /* Valid for IMX6DQ */
147 case OCOTP_CFG3_SPEED_850MHZ: 147 case OCOTP_CFG3_SPEED_850MHZ:
148 if (is_mx6dq() || is_mx6dqp()) 148 if (is_mx6dq() || is_mx6dqp())
149 return 852000000; 149 return 852000000;
150 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */ 150 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
151 case OCOTP_CFG3_SPEED_800MHZ: 151 case OCOTP_CFG3_SPEED_800MHZ:
152 return 792000000; 152 return 792000000;
153 } 153 }
154 return 0; 154 return 0;
155 } 155 }
156 156
157 /* 157 /*
158 * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480) 158 * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
159 * defines a 2-bit Temperature Grade 159 * defines a 2-bit Temperature Grade
160 * 160 *
161 * return temperature grade and min/max temperature in celcius 161 * return temperature grade and min/max temperature in celcius
162 */ 162 */
163 #define OCOTP_MEM0_TEMP_SHIFT 6 163 #define OCOTP_MEM0_TEMP_SHIFT 6
164 164
165 u32 get_cpu_temp_grade(int *minc, int *maxc) 165 u32 get_cpu_temp_grade(int *minc, int *maxc)
166 { 166 {
167 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 167 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
168 struct fuse_bank *bank = &ocotp->bank[1]; 168 struct fuse_bank *bank = &ocotp->bank[1];
169 struct fuse_bank1_regs *fuse = 169 struct fuse_bank1_regs *fuse =
170 (struct fuse_bank1_regs *)bank->fuse_regs; 170 (struct fuse_bank1_regs *)bank->fuse_regs;
171 uint32_t val; 171 uint32_t val;
172 172
173 val = readl(&fuse->mem0); 173 val = readl(&fuse->mem0);
174 val >>= OCOTP_MEM0_TEMP_SHIFT; 174 val >>= OCOTP_MEM0_TEMP_SHIFT;
175 val &= 0x3; 175 val &= 0x3;
176 176
177 if (minc && maxc) { 177 if (minc && maxc) {
178 if (val == TEMP_AUTOMOTIVE) { 178 if (val == TEMP_AUTOMOTIVE) {
179 *minc = -40; 179 *minc = -40;
180 *maxc = 125; 180 *maxc = 125;
181 } else if (val == TEMP_INDUSTRIAL) { 181 } else if (val == TEMP_INDUSTRIAL) {
182 *minc = -40; 182 *minc = -40;
183 *maxc = 105; 183 *maxc = 105;
184 } else if (val == TEMP_EXTCOMMERCIAL) { 184 } else if (val == TEMP_EXTCOMMERCIAL) {
185 *minc = -20; 185 *minc = -20;
186 *maxc = 105; 186 *maxc = 105;
187 } else { 187 } else {
188 *minc = 0; 188 *minc = 0;
189 *maxc = 95; 189 *maxc = 95;
190 } 190 }
191 } 191 }
192 return val; 192 return val;
193 } 193 }
194 194
195 #ifdef CONFIG_REVISION_TAG 195 #ifdef CONFIG_REVISION_TAG
196 u32 __weak get_board_rev(void) 196 u32 __weak get_board_rev(void)
197 { 197 {
198 u32 cpurev = get_cpu_rev(); 198 u32 cpurev = get_cpu_rev();
199 u32 type = ((cpurev >> 12) & 0xff); 199 u32 type = ((cpurev >> 12) & 0xff);
200 if (type == MXC_CPU_MX6SOLO) 200 if (type == MXC_CPU_MX6SOLO)
201 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF); 201 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
202 202
203 if (type == MXC_CPU_MX6D) 203 if (type == MXC_CPU_MX6D)
204 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF); 204 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
205 205
206 return cpurev; 206 return cpurev;
207 } 207 }
208 #endif 208 #endif
209 209
210 static void clear_ldo_ramp(void) 210 static void clear_ldo_ramp(void)
211 { 211 {
212 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; 212 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
213 int reg; 213 int reg;
214 214
215 /* ROM may modify LDO ramp up time according to fuse setting, so in 215 /* ROM may modify LDO ramp up time according to fuse setting, so in
216 * order to be in the safe side we neeed to reset these settings to 216 * order to be in the safe side we neeed to reset these settings to
217 * match the reset value: 0'b00 217 * match the reset value: 0'b00
218 */ 218 */
219 reg = readl(&anatop->ana_misc2); 219 reg = readl(&anatop->ana_misc2);
220 reg &= ~(0x3f << 24); 220 reg &= ~(0x3f << 24);
221 writel(reg, &anatop->ana_misc2); 221 writel(reg, &anatop->ana_misc2);
222 } 222 }
223 223
224 /* 224 /*
225 * Set the PMU_REG_CORE register 225 * Set the PMU_REG_CORE register
226 * 226 *
227 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level. 227 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
228 * Possible values are from 0.725V to 1.450V in steps of 228 * Possible values are from 0.725V to 1.450V in steps of
229 * 0.025V (25mV). 229 * 0.025V (25mV).
230 */ 230 */
231 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv) 231 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
232 { 232 {
233 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; 233 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
234 u32 val, step, old, reg = readl(&anatop->reg_core); 234 u32 val, step, old, reg = readl(&anatop->reg_core);
235 u8 shift; 235 u8 shift;
236 236
237 if (mv < 725) 237 if (mv < 725)
238 val = 0x00; /* Power gated off */ 238 val = 0x00; /* Power gated off */
239 else if (mv > 1450) 239 else if (mv > 1450)
240 val = 0x1F; /* Power FET switched full on. No regulation */ 240 val = 0x1F; /* Power FET switched full on. No regulation */
241 else 241 else
242 val = (mv - 700) / 25; 242 val = (mv - 700) / 25;
243 243
244 clear_ldo_ramp(); 244 clear_ldo_ramp();
245 245
246 switch (ldo) { 246 switch (ldo) {
247 case LDO_SOC: 247 case LDO_SOC:
248 shift = 18; 248 shift = 18;
249 break; 249 break;
250 case LDO_PU: 250 case LDO_PU:
251 shift = 9; 251 shift = 9;
252 break; 252 break;
253 case LDO_ARM: 253 case LDO_ARM:
254 shift = 0; 254 shift = 0;
255 break; 255 break;
256 default: 256 default:
257 return -EINVAL; 257 return -EINVAL;
258 } 258 }
259 259
260 old = (reg & (0x1F << shift)) >> shift; 260 old = (reg & (0x1F << shift)) >> shift;
261 step = abs(val - old); 261 step = abs(val - old);
262 if (step == 0) 262 if (step == 0)
263 return 0; 263 return 0;
264 264
265 reg = (reg & ~(0x1F << shift)) | (val << shift); 265 reg = (reg & ~(0x1F << shift)) | (val << shift);
266 writel(reg, &anatop->reg_core); 266 writel(reg, &anatop->reg_core);
267 267
268 /* 268 /*
269 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per 269 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
270 * step 270 * step
271 */ 271 */
272 udelay(3 * step); 272 udelay(3 * step);
273 273
274 return 0; 274 return 0;
275 } 275 }
276 276
277 static void set_ahb_rate(u32 val) 277 static void set_ahb_rate(u32 val)
278 { 278 {
279 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 279 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
280 u32 reg, div; 280 u32 reg, div;
281 281
282 div = get_periph_clk() / val - 1; 282 div = get_periph_clk() / val - 1;
283 reg = readl(&mxc_ccm->cbcdr); 283 reg = readl(&mxc_ccm->cbcdr);
284 284
285 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) | 285 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
286 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr); 286 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
287 } 287 }
288 288
289 static void clear_mmdc_ch_mask(void) 289 static void clear_mmdc_ch_mask(void)
290 { 290 {
291 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 291 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
292 u32 reg; 292 u32 reg;
293 reg = readl(&mxc_ccm->ccdr); 293 reg = readl(&mxc_ccm->ccdr);
294 294
295 /* Clear MMDC channel mask */ 295 /* Clear MMDC channel mask */
296 if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl()) 296 if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl())
297 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK); 297 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
298 else 298 else
299 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); 299 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
300 writel(reg, &mxc_ccm->ccdr); 300 writel(reg, &mxc_ccm->ccdr);
301 } 301 }
302 302
303 static void init_bandgap(void) 303 static void init_bandgap(void)
304 { 304 {
305 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; 305 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
306 /* 306 /*
307 * Ensure the bandgap has stabilized. 307 * Ensure the bandgap has stabilized.
308 */ 308 */
309 while (!(readl(&anatop->ana_misc0) & 0x80)) 309 while (!(readl(&anatop->ana_misc0) & 0x80))
310 ; 310 ;
311 /* 311 /*
312 * For best noise performance of the analog blocks using the 312 * For best noise performance of the analog blocks using the
313 * outputs of the bandgap, the reftop_selfbiasoff bit should 313 * outputs of the bandgap, the reftop_selfbiasoff bit should
314 * be set. 314 * be set.
315 */ 315 */
316 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set); 316 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
317 /* 317 /*
318 * On i.MX6ULL, the LDO 1.2V bandgap voltage is 30mV higher. so set 318 * On i.MX6ULL, the LDO 1.2V bandgap voltage is 30mV higher. so set
319 * VBGADJ bits to 2b'110 to adjust it. 319 * VBGADJ bits to 2b'110 to adjust it.
320 */ 320 */
321 if (is_mx6ull()) 321 if (is_mx6ull())
322 writel(BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ, &anatop->ana_misc0_set); 322 writel(BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ, &anatop->ana_misc0_set);
323 } 323 }
324 324
325 325
326 #ifdef CONFIG_MX6SL 326 #ifdef CONFIG_MX6SL
327 static void set_preclk_from_osc(void) 327 static void set_preclk_from_osc(void)
328 { 328 {
329 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 329 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
330 u32 reg; 330 u32 reg;
331 331
332 reg = readl(&mxc_ccm->cscmr1); 332 reg = readl(&mxc_ccm->cscmr1);
333 reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK; 333 reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
334 writel(reg, &mxc_ccm->cscmr1); 334 writel(reg, &mxc_ccm->cscmr1);
335 } 335 }
336 #endif 336 #endif
337 337
338 int arch_cpu_init(void) 338 int arch_cpu_init(void)
339 { 339 {
340 init_aips(); 340 init_aips();
341 341
342 /* Need to clear MMDC_CHx_MASK to make warm reset work. */ 342 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
343 clear_mmdc_ch_mask(); 343 clear_mmdc_ch_mask();
344 344
345 /* 345 /*
346 * Disable self-bias circuit in the analog bandap. 346 * Disable self-bias circuit in the analog bandap.
347 * The self-bias circuit is used by the bandgap during startup. 347 * The self-bias circuit is used by the bandgap during startup.
348 * This bit should be set after the bandgap has initialized. 348 * This bit should be set after the bandgap has initialized.
349 */ 349 */
350 init_bandgap(); 350 init_bandgap();
351 351
352 if (!is_mx6ul() && !is_mx6ull()) { 352 if (!is_mx6ul() && !is_mx6ull()) {
353 /* 353 /*
354 * When low freq boot is enabled, ROM will not set AHB 354 * When low freq boot is enabled, ROM will not set AHB
355 * freq, so we need to ensure AHB freq is 132MHz in such 355 * freq, so we need to ensure AHB freq is 132MHz in such
356 * scenario. 356 * scenario.
357 * 357 *
358 * To i.MX6UL, when power up, default ARM core and 358 * To i.MX6UL, when power up, default ARM core and
359 * AHB rate is 396M and 132M. 359 * AHB rate is 396M and 132M.
360 */ 360 */
361 if (mxc_get_clock(MXC_ARM_CLK) == 396000000) 361 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
362 set_ahb_rate(132000000); 362 set_ahb_rate(132000000);
363 } 363 }
364 364
365 if (is_mx6ul() && is_soc_rev(CHIP_REV_1_0) == 0) { 365 if (is_mx6ul()) {
366 /* 366 if (is_soc_rev(CHIP_REV_1_0) == 0) {
367 * According to the design team's requirement on i.MX6UL, 367 /*
368 * the PMIC_STBY_REQ PAD should be configured as open 368 * According to the design team's requirement on
369 * drain 100K (0x0000b8a0). 369 * i.MX6UL,the PMIC_STBY_REQ PAD should be configured
370 * Only exists on TO1.0 370 * as open drain 100K (0x0000b8a0).
371 */ 371 * Only exists on TO1.0
372 writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c); 372 */
373 writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
374 } else {
375 /*
376 * From TO1.1, SNVS adds internal pull up control
377 * for POR_B, the register filed is GPBIT[1:0],
378 * after system boot up, it can be set to 2b'01
379 * to disable internal pull up.It can save about
380 * 30uA power in SNVS mode.
381 */
382 writel((readl(MX6UL_SNVS_LP_BASE_ADDR + 0x10) &
383 (~0x1400)) | 0x400,
384 MX6UL_SNVS_LP_BASE_ADDR + 0x10);
385 }
373 } 386 }
374 387
375 if (is_mx6ull()) { 388 if (is_mx6ull()) {
376 /* 389 /*
377 * GPBIT[1:0] is suggested to set to 2'b11: 390 * GPBIT[1:0] is suggested to set to 2'b11:
378 * 2'b00 : always PUP100K 391 * 2'b00 : always PUP100K
379 * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL 392 * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL
380 * 2'b10 : always disable PUP100K 393 * 2'b10 : always disable PUP100K
381 * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL 394 * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL
382 * register offset is different from i.MX6UL, since 395 * register offset is different from i.MX6UL, since
383 * i.MX6UL is fixed by ECO. 396 * i.MX6UL is fixed by ECO.
384 */ 397 */
385 writel(readl(MX6UL_SNVS_LP_BASE_ADDR) | 398 writel(readl(MX6UL_SNVS_LP_BASE_ADDR) |
386 0x3, MX6UL_SNVS_LP_BASE_ADDR); 399 0x3, MX6UL_SNVS_LP_BASE_ADDR);
387 } 400 }
388 401
389 /* Set perclk to source from OSC 24MHz */ 402 /* Set perclk to source from OSC 24MHz */
390 #if defined(CONFIG_MX6SL) 403 #if defined(CONFIG_MX6SL)
391 set_preclk_from_osc(); 404 set_preclk_from_osc();
392 #endif 405 #endif
393 406
394 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ 407 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
395 408
396 #ifdef CONFIG_APBH_DMA 409 #ifdef CONFIG_APBH_DMA
397 /* Start APBH DMA */ 410 /* Start APBH DMA */
398 mxs_dma_init(); 411 mxs_dma_init();
399 #endif 412 #endif
400 413
401 init_src(); 414 init_src();
402 415
403 return 0; 416 return 0;
404 } 417 }
405 418
406 #ifdef CONFIG_ENV_IS_IN_MMC 419 #ifdef CONFIG_ENV_IS_IN_MMC
407 __weak int board_mmc_get_env_dev(int devno) 420 __weak int board_mmc_get_env_dev(int devno)
408 { 421 {
409 return CONFIG_SYS_MMC_ENV_DEV; 422 return CONFIG_SYS_MMC_ENV_DEV;
410 } 423 }
411 424
412 static int mmc_get_boot_dev(void) 425 static int mmc_get_boot_dev(void)
413 { 426 {
414 struct src *src_regs = (struct src *)SRC_BASE_ADDR; 427 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
415 u32 soc_sbmr = readl(&src_regs->sbmr1); 428 u32 soc_sbmr = readl(&src_regs->sbmr1);
416 u32 bootsel; 429 u32 bootsel;
417 int devno; 430 int devno;
418 431
419 /* 432 /*
420 * Refer to 433 * Refer to
421 * "i.MX 6Dual/6Quad Applications Processor Reference Manual" 434 * "i.MX 6Dual/6Quad Applications Processor Reference Manual"
422 * Chapter "8.5.3.1 Expansion Device eFUSE Configuration" 435 * Chapter "8.5.3.1 Expansion Device eFUSE Configuration"
423 * i.MX6SL/SX/UL has same layout. 436 * i.MX6SL/SX/UL has same layout.
424 */ 437 */
425 bootsel = (soc_sbmr & 0x000000FF) >> 6; 438 bootsel = (soc_sbmr & 0x000000FF) >> 6;
426 439
427 /* No boot from sd/mmc */ 440 /* No boot from sd/mmc */
428 if (bootsel != 1) 441 if (bootsel != 1)
429 return -1; 442 return -1;
430 443
431 /* BOOT_CFG2[3] and BOOT_CFG2[4] */ 444 /* BOOT_CFG2[3] and BOOT_CFG2[4] */
432 devno = (soc_sbmr & 0x00001800) >> 11; 445 devno = (soc_sbmr & 0x00001800) >> 11;
433 446
434 return devno; 447 return devno;
435 } 448 }
436 449
437 int mmc_get_env_dev(void) 450 int mmc_get_env_dev(void)
438 { 451 {
439 int devno = mmc_get_boot_dev(); 452 int devno = mmc_get_boot_dev();
440 453
441 /* If not boot from sd/mmc, use default value */ 454 /* If not boot from sd/mmc, use default value */
442 if (devno < 0) 455 if (devno < 0)
443 return CONFIG_SYS_MMC_ENV_DEV; 456 return CONFIG_SYS_MMC_ENV_DEV;
444 457
445 return board_mmc_get_env_dev(devno); 458 return board_mmc_get_env_dev(devno);
446 } 459 }
447 460
448 #ifdef CONFIG_SYS_MMC_ENV_PART 461 #ifdef CONFIG_SYS_MMC_ENV_PART
449 __weak int board_mmc_get_env_part(int devno) 462 __weak int board_mmc_get_env_part(int devno)
450 { 463 {
451 return CONFIG_SYS_MMC_ENV_PART; 464 return CONFIG_SYS_MMC_ENV_PART;
452 } 465 }
453 466
454 uint mmc_get_env_part(struct mmc *mmc) 467 uint mmc_get_env_part(struct mmc *mmc)
455 { 468 {
456 int devno = mmc_get_boot_dev(); 469 int devno = mmc_get_boot_dev();
457 470
458 /* If not boot from sd/mmc, use default value */ 471 /* If not boot from sd/mmc, use default value */
459 if (devno < 0) 472 if (devno < 0)
460 return CONFIG_SYS_MMC_ENV_PART; 473 return CONFIG_SYS_MMC_ENV_PART;
461 474
462 return board_mmc_get_env_part(devno); 475 return board_mmc_get_env_part(devno);
463 } 476 }
464 #endif 477 #endif
465 #endif 478 #endif
466 479
467 int board_postclk_init(void) 480 int board_postclk_init(void)
468 { 481 {
469 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */ 482 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
470 483
471 return 0; 484 return 0;
472 } 485 }
473 486
474 #if defined(CONFIG_FEC_MXC) 487 #if defined(CONFIG_FEC_MXC)
475 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) 488 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
476 { 489 {
477 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 490 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
478 struct fuse_bank *bank = &ocotp->bank[4]; 491 struct fuse_bank *bank = &ocotp->bank[4];
479 struct fuse_bank4_regs *fuse = 492 struct fuse_bank4_regs *fuse =
480 (struct fuse_bank4_regs *)bank->fuse_regs; 493 (struct fuse_bank4_regs *)bank->fuse_regs;
481 494
482 if ((is_mx6sx() || is_mx6ul() || is_mx6ull()) && dev_id == 1) { 495 if ((is_mx6sx() || is_mx6ul() || is_mx6ull()) && dev_id == 1) {
483 u32 value = readl(&fuse->mac_addr2); 496 u32 value = readl(&fuse->mac_addr2);
484 mac[0] = value >> 24 ; 497 mac[0] = value >> 24 ;
485 mac[1] = value >> 16 ; 498 mac[1] = value >> 16 ;
486 mac[2] = value >> 8 ; 499 mac[2] = value >> 8 ;
487 mac[3] = value ; 500 mac[3] = value ;
488 501
489 value = readl(&fuse->mac_addr1); 502 value = readl(&fuse->mac_addr1);
490 mac[4] = value >> 24 ; 503 mac[4] = value >> 24 ;
491 mac[5] = value >> 16 ; 504 mac[5] = value >> 16 ;
492 505
493 } else { 506 } else {
494 u32 value = readl(&fuse->mac_addr1); 507 u32 value = readl(&fuse->mac_addr1);
495 mac[0] = (value >> 8); 508 mac[0] = (value >> 8);
496 mac[1] = value ; 509 mac[1] = value ;
497 510
498 value = readl(&fuse->mac_addr0); 511 value = readl(&fuse->mac_addr0);
499 mac[2] = value >> 24 ; 512 mac[2] = value >> 24 ;
500 mac[3] = value >> 16 ; 513 mac[3] = value >> 16 ;
501 mac[4] = value >> 8 ; 514 mac[4] = value >> 8 ;
502 mac[5] = value ; 515 mac[5] = value ;
503 } 516 }
504 517
505 } 518 }
506 #endif 519 #endif
507 520
508 /* 521 /*
509 * cfg_val will be used for 522 * cfg_val will be used for
510 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] 523 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
511 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0] 524 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
512 * instead of SBMR1 to determine the boot device. 525 * instead of SBMR1 to determine the boot device.
513 */ 526 */
514 const struct boot_mode soc_boot_modes[] = { 527 const struct boot_mode soc_boot_modes[] = {
515 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)}, 528 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
516 /* reserved value should start rom usb */ 529 /* reserved value should start rom usb */
517 {"usb", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, 530 {"usb", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
518 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)}, 531 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
519 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)}, 532 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
520 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)}, 533 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
521 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)}, 534 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
522 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)}, 535 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
523 /* 4 bit bus width */ 536 /* 4 bit bus width */
524 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, 537 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
525 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, 538 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
526 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 539 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
527 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, 540 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
528 {NULL, 0}, 541 {NULL, 0},
529 }; 542 };
530 543
531 void reset_misc(void) 544 void reset_misc(void)
532 { 545 {
533 #ifdef CONFIG_VIDEO_MXS 546 #ifdef CONFIG_VIDEO_MXS
534 lcdif_power_down(); 547 lcdif_power_down();
535 #endif 548 #endif
536 } 549 }
537 550
538 void s_init(void) 551 void s_init(void)
539 { 552 {
540 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; 553 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
541 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 554 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
542 u32 mask480; 555 u32 mask480;
543 u32 mask528; 556 u32 mask528;
544 u32 reg, periph1, periph2; 557 u32 reg, periph1, periph2;
545 558
546 if (is_mx6sx() || is_mx6ul() || is_mx6ull()) 559 if (is_mx6sx() || is_mx6ul() || is_mx6ull())
547 return; 560 return;
548 561
549 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs 562 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
550 * to make sure PFD is working right, otherwise, PFDs may 563 * to make sure PFD is working right, otherwise, PFDs may
551 * not output clock after reset, MX6DL and MX6SL have added 396M pfd 564 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
552 * workaround in ROM code, as bus clock need it 565 * workaround in ROM code, as bus clock need it
553 */ 566 */
554 567
555 mask480 = ANATOP_PFD_CLKGATE_MASK(0) | 568 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
556 ANATOP_PFD_CLKGATE_MASK(1) | 569 ANATOP_PFD_CLKGATE_MASK(1) |
557 ANATOP_PFD_CLKGATE_MASK(2) | 570 ANATOP_PFD_CLKGATE_MASK(2) |
558 ANATOP_PFD_CLKGATE_MASK(3); 571 ANATOP_PFD_CLKGATE_MASK(3);
559 mask528 = ANATOP_PFD_CLKGATE_MASK(1) | 572 mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
560 ANATOP_PFD_CLKGATE_MASK(3); 573 ANATOP_PFD_CLKGATE_MASK(3);
561 574
562 reg = readl(&ccm->cbcmr); 575 reg = readl(&ccm->cbcmr);
563 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) 576 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
564 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET); 577 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
565 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) 578 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
566 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET); 579 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
567 580
568 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */ 581 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
569 if ((periph2 != 0x2) && (periph1 != 0x2)) 582 if ((periph2 != 0x2) && (periph1 != 0x2))
570 mask528 |= ANATOP_PFD_CLKGATE_MASK(0); 583 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
571 584
572 if ((periph2 != 0x1) && (periph1 != 0x1) && 585 if ((periph2 != 0x1) && (periph1 != 0x1) &&
573 (periph2 != 0x3) && (periph1 != 0x3)) 586 (periph2 != 0x3) && (periph1 != 0x3))
574 mask528 |= ANATOP_PFD_CLKGATE_MASK(2); 587 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
575 588
576 writel(mask480, &anatop->pfd_480_set); 589 writel(mask480, &anatop->pfd_480_set);
577 writel(mask528, &anatop->pfd_528_set); 590 writel(mask528, &anatop->pfd_528_set);
578 writel(mask480, &anatop->pfd_480_clr); 591 writel(mask480, &anatop->pfd_480_clr);
579 writel(mask528, &anatop->pfd_528_clr); 592 writel(mask528, &anatop->pfd_528_clr);
580 } 593 }
581 594
582 #ifdef CONFIG_IMX_HDMI 595 #ifdef CONFIG_IMX_HDMI
583 void imx_enable_hdmi_phy(void) 596 void imx_enable_hdmi_phy(void)
584 { 597 {
585 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; 598 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
586 u8 reg; 599 u8 reg;
587 reg = readb(&hdmi->phy_conf0); 600 reg = readb(&hdmi->phy_conf0);
588 reg |= HDMI_PHY_CONF0_PDZ_MASK; 601 reg |= HDMI_PHY_CONF0_PDZ_MASK;
589 writeb(reg, &hdmi->phy_conf0); 602 writeb(reg, &hdmi->phy_conf0);
590 udelay(3000); 603 udelay(3000);
591 reg |= HDMI_PHY_CONF0_ENTMDS_MASK; 604 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
592 writeb(reg, &hdmi->phy_conf0); 605 writeb(reg, &hdmi->phy_conf0);
593 udelay(3000); 606 udelay(3000);
594 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; 607 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
595 writeb(reg, &hdmi->phy_conf0); 608 writeb(reg, &hdmi->phy_conf0);
596 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); 609 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
597 } 610 }
598 611
599 void imx_setup_hdmi(void) 612 void imx_setup_hdmi(void)
600 { 613 {
601 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 614 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
602 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; 615 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
603 int reg, count; 616 int reg, count;
604 u8 val; 617 u8 val;
605 618
606 /* Turn on HDMI PHY clock */ 619 /* Turn on HDMI PHY clock */
607 reg = readl(&mxc_ccm->CCGR2); 620 reg = readl(&mxc_ccm->CCGR2);
608 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK| 621 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
609 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; 622 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
610 writel(reg, &mxc_ccm->CCGR2); 623 writel(reg, &mxc_ccm->CCGR2);
611 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); 624 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
612 reg = readl(&mxc_ccm->chsccdr); 625 reg = readl(&mxc_ccm->chsccdr);
613 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK| 626 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
614 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK| 627 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
615 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); 628 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
616 reg |= (CHSCCDR_PODF_DIVIDE_BY_3 629 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
617 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) 630 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
618 |(CHSCCDR_IPU_PRE_CLK_540M_PFD 631 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
619 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); 632 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
620 writel(reg, &mxc_ccm->chsccdr); 633 writel(reg, &mxc_ccm->chsccdr);
621 634
622 /* Clear the overflow condition */ 635 /* Clear the overflow condition */
623 if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) { 636 if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
624 /* TMDS software reset */ 637 /* TMDS software reset */
625 writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz); 638 writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz);
626 val = readb(&hdmi->fc_invidconf); 639 val = readb(&hdmi->fc_invidconf);
627 /* Need minimum 3 times to write to clear the register */ 640 /* Need minimum 3 times to write to clear the register */
628 for (count = 0 ; count < 5 ; count++) 641 for (count = 0 ; count < 5 ; count++)
629 writeb(val, &hdmi->fc_invidconf); 642 writeb(val, &hdmi->fc_invidconf);
630 } 643 }
631 } 644 }
632 #endif 645 #endif
633 646
634 #ifdef CONFIG_IMX_BOOTAUX 647 #ifdef CONFIG_IMX_BOOTAUX
635 int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) 648 int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
636 { 649 {
637 struct src *src_reg; 650 struct src *src_reg;
638 u32 stack, pc; 651 u32 stack, pc;
639 652
640 if (!boot_private_data) 653 if (!boot_private_data)
641 return -EINVAL; 654 return -EINVAL;
642 655
643 stack = *(u32 *)boot_private_data; 656 stack = *(u32 *)boot_private_data;
644 pc = *(u32 *)(boot_private_data + 4); 657 pc = *(u32 *)(boot_private_data + 4);
645 658
646 /* Set the stack and pc to M4 bootROM */ 659 /* Set the stack and pc to M4 bootROM */
647 writel(stack, M4_BOOTROM_BASE_ADDR); 660 writel(stack, M4_BOOTROM_BASE_ADDR);
648 writel(pc, M4_BOOTROM_BASE_ADDR + 4); 661 writel(pc, M4_BOOTROM_BASE_ADDR + 4);
649 662
650 /* Enable M4 */ 663 /* Enable M4 */
651 src_reg = (struct src *)SRC_BASE_ADDR; 664 src_reg = (struct src *)SRC_BASE_ADDR;
652 clrsetbits_le32(&src_reg->scr, SRC_SCR_M4C_NON_SCLR_RST_MASK, 665 clrsetbits_le32(&src_reg->scr, SRC_SCR_M4C_NON_SCLR_RST_MASK,
653 SRC_SCR_M4_ENABLE_MASK); 666 SRC_SCR_M4_ENABLE_MASK);
654 667
655 return 0; 668 return 0;
656 } 669 }
657 670
658 int arch_auxiliary_core_check_up(u32 core_id) 671 int arch_auxiliary_core_check_up(u32 core_id)
659 { 672 {
660 struct src *src_reg = (struct src *)SRC_BASE_ADDR; 673 struct src *src_reg = (struct src *)SRC_BASE_ADDR;
661 unsigned val; 674 unsigned val;
662 675
663 val = readl(&src_reg->scr); 676 val = readl(&src_reg->scr);
664 677
665 if (val & SRC_SCR_M4C_NON_SCLR_RST_MASK) 678 if (val & SRC_SCR_M4C_NON_SCLR_RST_MASK)
666 return 0; /* assert in reset */ 679 return 0; /* assert in reset */
667 680
668 return 1; 681 return 1;
669 } 682 }
670 #endif 683 #endif
671 684