Eric Lee / smarc-uboot

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Commit f15ece388f57a3b35704b5f2306ad462ccf6e2e8

Authored by Peng Fan
Committed by Stefano Babic
1 parent 2ee4065571
Exists in v2017.01-smarct4x and in 28 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2017.01-smarct3x, v2017.01-smarct3x-emmc

imx: imx6ul: disable POR_B internal pull up 

>From TO1.1, SNVS adds internal pull up control for POR_B,
the register filed is GPBIT[1:0], after system boot up,
it can be set to 2b'01 to disable internal pull up.
It can save about 30uA power in SNVS mode.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>

Showing 1 changed file with 21 additions and 8 deletions Side-by-side Diff

arch/arm/cpu/armv7/mx6/soc.c
Diff comments   View file @ f15ece3
... ... @@ -362,14 +362,27 @@
362 362 set_ahb_rate(132000000);
363 363 }
364 364  
365   - if (is_mx6ul() && is_soc_rev(CHIP_REV_1_0) == 0) {
366   - /*
367   - * According to the design team's requirement on i.MX6UL,
368   - * the PMIC_STBY_REQ PAD should be configured as open
369   - * drain 100K (0x0000b8a0).
370   - * Only exists on TO1.0
371   - */
372   - writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
  365 + if (is_mx6ul()) {
  366 + if (is_soc_rev(CHIP_REV_1_0) == 0) {
  367 + /*
  368 + * According to the design team's requirement on
  369 + * i.MX6UL,the PMIC_STBY_REQ PAD should be configured
  370 + * as open drain 100K (0x0000b8a0).
  371 + * Only exists on TO1.0
  372 + */
  373 + writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
  374 + } else {
  375 + /*
  376 + * From TO1.1, SNVS adds internal pull up control
  377 + * for POR_B, the register filed is GPBIT[1:0],
  378 + * after system boot up, it can be set to 2b'01
  379 + * to disable internal pull up.It can save about
  380 + * 30uA power in SNVS mode.
  381 + */
  382 + writel((readl(MX6UL_SNVS_LP_BASE_ADDR + 0x10) &
  383 + (~0x1400)) | 0x400,
  384 + MX6UL_SNVS_LP_BASE_ADDR + 0x10);
  385 + }
373 386 }
374 387  
375 388 if (is_mx6ull()) {