sja1105: Add per port configuration

Add function that programmes RGMII ports on SJA1105 Issue: ALB-1755 Signed-off-by: Iustin Dumitrescu <iustin.dumitrescu@nxp.com>

sja1105: Add per port configuration
Add function that programmes RGMII ports on SJA1105 Issue: ALB-1755 Signed-off-by: Iustin Dumitrescu <iustin.dumitrescu@nxp.com>
Iustin Dumitrescu · Larisa Grigore
1 parent f0e1c30478
Showing 2 changed files with 74 additions and 2 deletions Side-by-side Diff
drivers/spi/sja1105.c
drivers/spi/sja1105_ll.h
@@ -294,6 +294,45 @@
 	return status;
 }
  
+void sja1105_port_cfg(struct sja_parms *sjap)
+{
+	u32 i;
+
+	for (i = 0; i < SJA1105_PORT_NB; i++) {
+		u32 port_status;
+
+		/* Get port type / speed */
+		port_status = sja1105_read_reg32(sjap,
+					SJA1105_PORT_STATUS_MII_PORT(i));
+
+		switch (port_status & SJA1105_PORT_STATUS_MII_MODE) {
+		case e_mii_mode_rgmii:
+			/* Set slew rate of TX Pins to high speed */
+			sja1105_write_reg32(sjap,
+					    SJA1105_CFG_PAD_MIIX_TX_PORT(i),
+					    SJA1105_CFG_PAD_MIIX_TX_SLEW_RGMII);
+
+			/* Set Clock delay */
+			sja1105_write_reg32(sjap,
+					    SJA1105_CFG_PAD_MIIX_ID_PORT(i),
+					    SJA1105_CFG_PAD_MIIX_ID_RGMII);
+
+			/* Disable IDIV */
+			sja1105_write_reg32(sjap, SJA1105_CGU_IDIV_PORT(i),
+					    SJA1105_CGU_IDIV_DISABLE);
+
+			/* Set Clock source to PLL0 */
+			sja1105_write_reg32(sjap,
+					    SJA1105_CGU_MII_TX_CLK_PORT(i),
+					    SJA1105_CGU_MII_CLK_SRC_PLL0);
+			break;
+
+		default:
+			break;
+		}
+	}
+}
+
 static int sja1105_configuration_load(struct sja_parms *sjap)
 {
 	int remaining_words;
  
@@ -371,10 +410,13 @@
 			sja1105_post_cfg_load_check(sjap);
 	}
  
-	if (!sja1105_post_cfg_load_check(sjap))  {
+	if (!sja1105_post_cfg_load_check(sjap)) {
 		printf("SJA1105 configuration failed\n");
 		return -ENXIO;
 	}
+
+	sja1105_port_cfg(sjap);
+
 	return 0;
 }
  
@@ -416,7 +458,7 @@
 	sjap.cs = cs;
 	sjap.bus = bus;
  
-	printf("Loading SJA1105 firmware over SPI\n");
+	printf("Loading SJA1105 firmware over SPI %d:%d\n", bus, cs);
  
 	sjap.devid = sja1105_check_device_id(&sjap);
  
@@ -187,6 +187,10 @@
 #define SJA1105_CGU_MII_TX_CLK_PORT(port)	(SJA1105_CGU_MII_TX_CLK_ADDR + \
 						 (port) * 6)
  
+#define SJA1105_CGU_IDIV_DISABLE		0x0A00001
+
+#define SJA1105_CGU_MII_CLK_SRC_PLL0		0XB000800
+
 /* Configuration registers */
  
 #define SJA1105_CFG_PAD_MIIX_TX_ADDR		0x100800
  
@@ -201,9 +205,35 @@
 #define SJA1105_PORT_STATUS_MII_PORT(port)	(SJA1105_PORT_STATUS_MII_ADDR \
 						 + (port))
  
+#define SJA1105_CFG_PAD_MIIX_TX_D32_OS_HS	0x18000000
+#define SJA1105_CFG_PAD_MIIX_TX_D32_IPUD_FS	0x02000000
+#define SJA1105_CFG_PAD_MIIX_TX_D10_OS_HS	0x00180000
+#define SJA1105_CFG_PAD_MIIX_TX_D10_IPUD_FS	0x00020000
+#define SJA1105_CFG_PAD_MIIX_TX_CTRL_OS_HS	0x00001800
+#define SJA1105_CFG_PAD_MIIX_TX_CTRL_IPUD_FS	0x00000200
+#define SJA1105_CFG_PAD_MIIX_TX_CLK_OS_HS	0x00000018
+#define SJA1105_CFG_PAD_MIIX_TX_CLK_IPUD_FS	0x00000002
+
+#define SJA1105_CFG_PAD_MIIX_TX_SLEW_RGMII	( \
+					SJA1105_CFG_PAD_MIIX_TX_D32_OS_HS      \
+					| SJA1105_CFG_PAD_MIIX_TX_D32_IPUD_FS  \
+					| SJA1105_CFG_PAD_MIIX_TX_D10_OS_HS    \
+					| SJA1105_CFG_PAD_MIIX_TX_D10_IPUD_FS  \
+					| SJA1105_CFG_PAD_MIIX_TX_CTRL_OS_HS   \
+					| SJA1105_CFG_PAD_MIIX_TX_CTRL_IPUD_FS \
+					| SJA1105_CFG_PAD_MIIX_TX_CLK_OS_HS    \
+					| SJA1105_CFG_PAD_MIIX_TX_CLK_IPUD_FS)
+
 #define SJA1105_CFG_PAD_MIIX_ID_RXC_DELAY(delay)	((delay) << 10)
 #define SJA1105_CFG_PAD_MIIX_ID_RXC_BYPASS		BIT(9)
 #define SJA1105_CFG_PAD_MIIX_ID_RXC_PD			BIT(8)
+#define SJA1105_CFG_PAD_MIIX_ID_TXC_DELAY(delay)	((delay) << 2)
+
+#define SJA1105_DELAY_81DEG			8
+
+#define SJA1105_CFG_PAD_MIIX_ID_RGMII	( \
+	SJA1105_CFG_PAD_MIIX_ID_RXC_DELAY(SJA1105_DELAY_81DEG) \
+	| SJA1105_CFG_PAD_MIIX_ID_TXC_DELAY(SJA1105_DELAY_81DEG))
  
 #define SJA1105_PORT_STATUS_MII_MODE		(0x00000003)
...	...	@@ -294,6 +294,45 @@
294	294	return status;
295	295	}
296	296
	297	+void sja1105_port_cfg(struct sja_parms *sjap)
	298	+{
	299	+ u32 i;
	300	+
	301	+ for (i = 0; i < SJA1105_PORT_NB; i++) {
	302	+ u32 port_status;
	303	+
	304	+ /* Get port type / speed */
	305	+ port_status = sja1105_read_reg32(sjap,
	306	+ SJA1105_PORT_STATUS_MII_PORT(i));
	307	+
	308	+ switch (port_status & SJA1105_PORT_STATUS_MII_MODE) {
	309	+ case e_mii_mode_rgmii:
	310	+ /* Set slew rate of TX Pins to high speed */
	311	+ sja1105_write_reg32(sjap,
	312	+ SJA1105_CFG_PAD_MIIX_TX_PORT(i),
	313	+ SJA1105_CFG_PAD_MIIX_TX_SLEW_RGMII);
	314	+
	315	+ /* Set Clock delay */
	316	+ sja1105_write_reg32(sjap,
	317	+ SJA1105_CFG_PAD_MIIX_ID_PORT(i),
	318	+ SJA1105_CFG_PAD_MIIX_ID_RGMII);
	319	+
	320	+ /* Disable IDIV */
	321	+ sja1105_write_reg32(sjap, SJA1105_CGU_IDIV_PORT(i),
	322	+ SJA1105_CGU_IDIV_DISABLE);
	323	+
	324	+ /* Set Clock source to PLL0 */
	325	+ sja1105_write_reg32(sjap,
	326	+ SJA1105_CGU_MII_TX_CLK_PORT(i),
	327	+ SJA1105_CGU_MII_CLK_SRC_PLL0);
	328	+ break;
	329	+
	330	+ default:
	331	+ break;
	332	+ }
	333	+ }
	334	+}
	335	+
297	336	static int sja1105_configuration_load(struct sja_parms *sjap)
298	337	{
299	338	int remaining_words;
300	339
...	...	@@ -371,10 +410,13 @@
371	410	sja1105_post_cfg_load_check(sjap);
372	411	}
373	412
374		- if (!sja1105_post_cfg_load_check(sjap)) {
	413	+ if (!sja1105_post_cfg_load_check(sjap)) {
375	414	printf("SJA1105 configuration failed\n");
376	415	return -ENXIO;
377	416	}
	417	+
	418	+ sja1105_port_cfg(sjap);
	419	+
378	420	return 0;
379	421	}
380	422
...	...	@@ -416,7 +458,7 @@
416	458	sjap.cs = cs;
417	459	sjap.bus = bus;
418	460
419		- printf("Loading SJA1105 firmware over SPI\n");
	461	+ printf("Loading SJA1105 firmware over SPI %d:%d\n", bus, cs);
420	462
421	463	sjap.devid = sja1105_check_device_id(&sjap);
422	464
...	...	@@ -187,6 +187,10 @@
187	187	#define SJA1105_CGU_MII_TX_CLK_PORT(port) (SJA1105_CGU_MII_TX_CLK_ADDR + \
188	188	(port) * 6)
189	189
	190	+#define SJA1105_CGU_IDIV_DISABLE 0x0A00001
	191	+
	192	+#define SJA1105_CGU_MII_CLK_SRC_PLL0 0XB000800
	193	+
190	194	/* Configuration registers */
191	195
192	196	#define SJA1105_CFG_PAD_MIIX_TX_ADDR 0x100800
193	197
...	...	@@ -201,9 +205,35 @@
201	205	#define SJA1105_PORT_STATUS_MII_PORT(port) (SJA1105_PORT_STATUS_MII_ADDR \
202	206	+ (port))
203	207
	208	+#define SJA1105_CFG_PAD_MIIX_TX_D32_OS_HS 0x18000000
	209	+#define SJA1105_CFG_PAD_MIIX_TX_D32_IPUD_FS 0x02000000
	210	+#define SJA1105_CFG_PAD_MIIX_TX_D10_OS_HS 0x00180000
	211	+#define SJA1105_CFG_PAD_MIIX_TX_D10_IPUD_FS 0x00020000
	212	+#define SJA1105_CFG_PAD_MIIX_TX_CTRL_OS_HS 0x00001800
	213	+#define SJA1105_CFG_PAD_MIIX_TX_CTRL_IPUD_FS 0x00000200
	214	+#define SJA1105_CFG_PAD_MIIX_TX_CLK_OS_HS 0x00000018
	215	+#define SJA1105_CFG_PAD_MIIX_TX_CLK_IPUD_FS 0x00000002
	216	+
	217	+#define SJA1105_CFG_PAD_MIIX_TX_SLEW_RGMII ( \
	218	+ SJA1105_CFG_PAD_MIIX_TX_D32_OS_HS \
	219	+ \| SJA1105_CFG_PAD_MIIX_TX_D32_IPUD_FS \
	220	+ \| SJA1105_CFG_PAD_MIIX_TX_D10_OS_HS \
	221	+ \| SJA1105_CFG_PAD_MIIX_TX_D10_IPUD_FS \
	222	+ \| SJA1105_CFG_PAD_MIIX_TX_CTRL_OS_HS \
	223	+ \| SJA1105_CFG_PAD_MIIX_TX_CTRL_IPUD_FS \
	224	+ \| SJA1105_CFG_PAD_MIIX_TX_CLK_OS_HS \
	225	+ \| SJA1105_CFG_PAD_MIIX_TX_CLK_IPUD_FS)
	226	+
204	227	#define SJA1105_CFG_PAD_MIIX_ID_RXC_DELAY(delay) ((delay) << 10)
205	228	#define SJA1105_CFG_PAD_MIIX_ID_RXC_BYPASS BIT(9)
206	229	#define SJA1105_CFG_PAD_MIIX_ID_RXC_PD BIT(8)
	230	+#define SJA1105_CFG_PAD_MIIX_ID_TXC_DELAY(delay) ((delay) << 2)
	231	+
	232	+#define SJA1105_DELAY_81DEG 8
	233	+
	234	+#define SJA1105_CFG_PAD_MIIX_ID_RGMII ( \
	235	+ SJA1105_CFG_PAD_MIIX_ID_RXC_DELAY(SJA1105_DELAY_81DEG) \
	236	+ \| SJA1105_CFG_PAD_MIIX_ID_TXC_DELAY(SJA1105_DELAY_81DEG))
207	237
208	238	#define SJA1105_PORT_STATUS_MII_MODE (0x00000003)
209	239