Commit f20393c5e787b3776c179d20f82a86bda124d651
1 parent
580ca3c2b1
Prepare v2009.11.1
Update CHANGELOG Signed-off-by: Wolfgang Denk <wd@denx.de>
Showing 2 changed files with 78 additions and 1 deletions Side-by-side Diff
CHANGELOG
| 1 | +commit 580ca3c2b1d032534195cd0bfd89aa11e8c03bb3 | |
| 2 | +Author: Stefan Roese <sr@denx.de> | |
| 3 | +Date: Thu Jan 21 11:37:31 2010 +0100 | |
| 4 | + | |
| 5 | + ppc4xx: Kilauea: Add CPLD version detection and EBC reconfiguration | |
| 6 | + | |
| 7 | + A newer CPLD version on the 405EX evaluation board requires a different | |
| 8 | + EBC controller setup for the CPLD register access. This patch adds a CPLD | |
| 9 | + version detection for Kilauea and code to reconfigure the EBC controller | |
| 10 | + (chip select 2) for the old CPLD if no new version is found. | |
| 11 | + | |
| 12 | + Additionally the CPLD version is printed upon bootup: | |
| 13 | + | |
| 14 | + Board: Kilauea - AMCC PPC405EX Evaluation Board (CPLD rev. 0) | |
| 15 | + | |
| 16 | + Signed-off-by: Stefan Roese <sr@denx.de> | |
| 17 | + Acked-by: Wolfgang Denk <wd@denx.de> | |
| 18 | + Cc: Zhang Bao Quan <bqzhang@udtech.com.cn> | |
| 19 | + | |
| 20 | +commit eb20392ca986074c78ee4f241a8f2369777a8df3 | |
| 21 | +Author: Felix Radensky <felix@embedded-sol.com> | |
| 22 | +Date: Sat Jan 23 01:35:24 2010 +0200 | |
| 23 | + | |
| 24 | + ppc4xx: Fix sending type 1 PCI transactions | |
| 25 | + | |
| 26 | + The list of 4xx SoCs that should send type 1 PCI transactions | |
| 27 | + is not defined correctly. As a result PCI-PCI bridges and devices | |
| 28 | + behind them are not identified. The following 4xx variants should | |
| 29 | + send type 1 transactions: 440GX, 440GP, 440SP, 440SPE, 460EX and 460GT. | |
| 30 | + | |
| 31 | + Signed-off-by: Felix Radensky <felix@embedded-sol.com> | |
| 32 | + Signed-off-by: Stefan Roese <sr@denx.de> | |
| 33 | + | |
| 34 | +commit 57ab8a129dd4121711540e2b976aff882998de51 | |
| 35 | +Author: Felix Radensky <felix@embedded-sol.com> | |
| 36 | +Date: Tue Jan 19 21:19:06 2010 +0200 | |
| 37 | + | |
| 38 | + ppc4xx: Allow setting a single SPD EEPROM address for DDR2 DIMMs | |
| 39 | + | |
| 40 | + On platforms where SPD EEPROM and another EEPROM have adjacent | |
| 41 | + I2C addresses SPD_EEPROM_ADDRESS should be defined as a single | |
| 42 | + element array, otherwise DDR2 setup code would fail with the | |
| 43 | + following error: | |
| 44 | + | |
| 45 | + ERROR: Unknown DIMM detected in slot 1 | |
| 46 | + | |
| 47 | + However, fixing SPD_EEPROM_ADDRESS would result in another | |
| 48 | + error: | |
| 49 | + | |
| 50 | + ERROR: DIMM's DDR1 and DDR2 type can not be mixed. | |
| 51 | + | |
| 52 | + This happens because initdram() routine does not explicitly | |
| 53 | + initialize dimm_populated array. This patch fixes the problem. | |
| 54 | + | |
| 55 | + Signed-off-by: Felix Radensky <felix@embedded-sol.com> | |
| 56 | + Signed-off-by: Stefan Roese <sr@denx.de> | |
| 57 | + | |
| 58 | +commit 17ab3057bde25208af71326c0ff213d05eadb318 | |
| 59 | +Author: Felix Radensky <felix@embedded-sol.com> | |
| 60 | +Date: Tue Jan 19 17:37:13 2010 +0200 | |
| 61 | + | |
| 62 | + ppc4xx: Fix reporting of bootstrap options G and F on 460EX/GT | |
| 63 | + | |
| 64 | + Bootstrap options G and F are reported incorrectly (G instead | |
| 65 | + of F and vice versa). This patch fixes this. | |
| 66 | + | |
| 67 | + Signed-off-by: Felix Radensky <felix@embedded-sol.com> | |
| 68 | + Signed-off-by: Stefan Roese <sr@denx.de> | |
| 69 | + | |
| 70 | +commit a200a7c04d89853d2a1395b96d8ca5e3dd754551 | |
| 71 | +Author: Wolfgang Denk <wd@denx.de> | |
| 72 | +Date: Tue Dec 15 23:20:54 2009 +0100 | |
| 73 | + | |
| 74 | + Update CHANGELOG; prepare Prepare v2009.11 | |
| 75 | + | |
| 76 | + Signed-off-by: Wolfgang Denk <wd@denx.de> | |
| 77 | + | |
| 1 | 78 | commit f9476902b789b0481b9df49af88d6ca94fb16fa0 |
| 2 | 79 | Author: Peter Tyser <ptyser@xes-inc.com> |
| 3 | 80 | Date: Tue Dec 15 12:10:47 2009 -0600 |