arm/errata: Update required bits for A57 cores erratas

This patch updates the setting of required bits for A57 cores erratas - 828024 and 826974 Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Dai Haruki <dai.haruki at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>

arm/errata: Update required bits for A57 cores erratas
This patch updates the setting of required bits for A57 cores erratas - 828024 and 826974 Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Dai Haruki <dai.haruki at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Bhupesh Sharma · York Sun
1 parent dbe94dd11c
Showing 1 changed file with 4 additions and 4 deletions Side-by-side Diff
arch/arm/cpu/armv8/start.S
@@ -115,18 +115,18 @@
 #ifdef CONFIG_ARM_ERRATA_828024
 	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
 	/* Disable non-allocate hint of w-b-n-a memory type */
-	mov	x0, #0x1 << 49
+	orr	x0, x0, #1 << 49
 	/* Disable write streaming no L1-allocate threshold */
-	mov	x0, #0x3 << 25
+	orr	x0, x0, #3 << 25
 	/* Disable write streaming no-allocate threshold */
-	mov	x0, #0x3 << 27
+	orr	x0, x0, #3 << 27
 	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
 #endif
  
 #ifdef CONFIG_ARM_ERRATA_826974
 	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
 	/* Disable speculative load execution ahead of a DMB */
-	mov	x0, #0x1 << 59
+	orr	x0, x0, #1 << 59
 	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
 #endif
...	...	@@ -115,18 +115,18 @@
115	115	#ifdef CONFIG_ARM_ERRATA_828024
116	116	mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
117	117	/* Disable non-allocate hint of w-b-n-a memory type */
118		- mov x0, #0x1 << 49
	118	+ orr x0, x0, #1 << 49
119	119	/* Disable write streaming no L1-allocate threshold */
120		- mov x0, #0x3 << 25
	120	+ orr x0, x0, #3 << 25
121	121	/* Disable write streaming no-allocate threshold */
122		- mov x0, #0x3 << 27
	122	+ orr x0, x0, #3 << 27
123	123	msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
124	124	#endif
125	125
126	126	#ifdef CONFIG_ARM_ERRATA_826974
127	127	mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
128	128	/* Disable speculative load execution ahead of a DMB */
129		- mov x0, #0x1 << 59
	129	+ orr x0, x0, #1 << 59
130	130	msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
131	131	#endif
132	132