Eric Lee / smarc-uboot

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Commit f2a73d6867ef973fbb8471cc87058205999b5e5c

Authored by Tom Rini
2 parents e6da32f243 8ee5e3c81f
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

Merge tag 'u-boot-stm32-20200214' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm 

- add DH Electronics DHCOM SoM and PDK2 board
- DT alignment with kernel v5.5-rc7 for stm32mp1 boards
- fix STM32 image format for big endian hosts in mkimage
- solve warnings in device tree and code for stm32mp1 boards
- remove fdt_high and initrd_high for stm32 and stih boards
- add support of STM32MP15x Rev.Z
- update stm32mp1 readme

Showing 42 changed files Side-by-side Diff

arch/arm/dts/Makefile
Diff comments   View file @ f2a73d6
... ... @@ -882,7 +882,8 @@
882 882 stm32mp157a-avenger96.dtb \
883 883 stm32mp157c-dk2.dtb \
884 884 stm32mp157c-ed1.dtb \
885   - stm32mp157c-ev1.dtb
  885 + stm32mp157c-ev1.dtb \
  886 + stm32mp15xx-dhcom-pdk2.dtb
886 887  
887 888 dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb
888 889 dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
arch/arm/dts/stm32mp15-ddr.dtsi
Diff comments   View file @ f2a73d6
... ... @@ -5,7 +5,7 @@
5 5  
6 6 / {
7 7 soc {
8   - ddr: ddr@5A003000 {
  8 + ddr: ddr@5a003000 {
9 9 u-boot,dm-pre-reloc;
10 10  
11 11 compatible = "st,stm32mp1-ddr";
arch/arm/dts/stm32mp157-pinctrl.dtsi
Diff comments   View file @ f2a73d6
... ... @@ -138,8 +138,17 @@
138 138 status = "disabled";
139 139 };
140 140  
141   - adc12_usb_pwr_pins_a: adc12-usb-pwr-pins-0 {
  141 + adc12_ain_pins_a: adc12-ain-0 {
142 142 pins {
  143 + pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */
  144 + <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
  145 + <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */
  146 + <STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */
  147 + };
  148 + };
  149 +
  150 + adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 {
  151 + pins {
143 152 pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */
144 153 <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */
145 154 };
... ... @@ -175,6 +184,18 @@
175 184 };
176 185 };
177 186  
  187 + dac_ch1_pins_a: dac-ch1 {
  188 + pins {
  189 + pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
  190 + };
  191 + };
  192 +
  193 + dac_ch2_pins_a: dac-ch2 {
  194 + pins {
  195 + pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
  196 + };
  197 + };
  198 +
178 199 dcmi_pins_a: dcmi-0 {
179 200 pins {
180 201 pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
181 202  
... ... @@ -622,13 +643,13 @@
622 643 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
623 644 bias-disable;
624 645 drive-push-pull;
625   - slew-rate = <3>;
  646 + slew-rate = <1>;
626 647 };
627 648 pins2 {
628 649 pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
629 650 bias-pull-up;
630 651 drive-push-pull;
631   - slew-rate = <3>;
  652 + slew-rate = <1>;
632 653 };
633 654 };
634 655  
635 656  
... ... @@ -650,13 +671,13 @@
650 671 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
651 672 bias-disable;
652 673 drive-push-pull;
653   - slew-rate = <3>;
  674 + slew-rate = <1>;
654 675 };
655 676 pins2 {
656 677 pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
657 678 bias-pull-up;
658 679 drive-push-pull;
659   - slew-rate = <3>;
  680 + slew-rate = <1>;
660 681 };
661 682 };
662 683  
arch/arm/dts/stm32mp157-u-boot.dtsi
Diff comments   View file @ f2a73d6
... ... @@ -128,12 +128,14 @@
128 128 u-boot,dm-pre-reloc;
129 129 };
130 130  
131   -&pwr {
  131 +&pwr_regulators {
132 132 u-boot,dm-pre-reloc;
133 133 };
134 134  
135 135 &rcc {
136 136 u-boot,dm-pre-reloc;
  137 + #address-cells = <1>;
  138 + #size-cells = <0>;
137 139 };
138 140  
139 141 &sdmmc1 {
arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi
Diff comments   View file @ f2a73d6
... ... @@ -91,7 +91,7 @@
91 91 CLK_UART6_HSI
92 92 CLK_UART78_HSI
93 93 CLK_SPDIF_PLL4P
94   - CLK_FDCAN_PLL4Q
  94 + CLK_FDCAN_PLL4R
95 95 CLK_SAI1_PLL3Q
96 96 CLK_SAI2_PLL3Q
97 97 CLK_SAI3_PLL3Q
... ... @@ -105,6 +105,8 @@
105 105  
106 106 /* VCO = 1300.0 MHz => P = 650 (CPU) */
107 107 pll1: st,pll@0 {
  108 + compatible = "st,stm32mp1-pll";
  109 + reg = <0>;
108 110 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
109 111 frac = < 0x800 >;
110 112 u-boot,dm-pre-reloc;
... ... @@ -112,6 +114,8 @@
112 114  
113 115 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
114 116 pll2: st,pll@1 {
  117 + compatible = "st,stm32mp1-pll";
  118 + reg = <1>;
115 119 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
116 120 frac = < 0x1400 >;
117 121 u-boot,dm-pre-reloc;
... ... @@ -119,6 +123,8 @@
119 123  
120 124 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
121 125 pll3: st,pll@2 {
  126 + compatible = "st,stm32mp1-pll";
  127 + reg = <2>;
122 128 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
123 129 frac = < 0x1a04 >;
124 130 u-boot,dm-pre-reloc;
... ... @@ -126,6 +132,8 @@
126 132  
127 133 /* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */
128 134 pll4: st,pll@3 {
  135 + compatible = "st,stm32mp1-pll";
  136 + reg = <3>;
129 137 cfg = < 1 39 3 11 4 PQR(1,1,1) >;
130 138 u-boot,dm-pre-reloc;
131 139 };
arch/arm/dts/stm32mp157a-avenger96.dts
Diff comments   View file @ f2a73d6
... ... @@ -252,14 +252,13 @@
252 252 regulator-name = "vbus_otg";
253 253 interrupts = <IT_OCP_OTG 0>;
254 254 interrupt-parent = <&pmic>;
255   - regulator-active-discharge;
256 255 };
257 256  
258 257 vbus_sw: pwr_sw2 {
259 258 regulator-name = "vbus_sw";
260 259 interrupts = <IT_OCP_SWOUT 0>;
261 260 interrupt-parent = <&pmic>;
262   - regulator-active-discharge;
  261 + regulator-active-discharge = <1>;
263 262 };
264 263 };
265 264  
... ... @@ -282,11 +281,9 @@
282 281 status = "okay";
283 282 };
284 283  
285   -&pwr {
286   - pwr-regulators {
287   - vdd-supply = <&vdd>;
288   - vdd_3v3_usbfs-supply = <&vdd_usb>;
289   - };
  284 +&pwr_regulators {
  285 + vdd-supply = <&vdd>;
  286 + vdd_3v3_usbfs-supply = <&vdd_usb>;
290 287 };
291 288  
292 289 &rng1 {
arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
Diff comments   View file @ f2a73d6
... ... @@ -35,24 +35,7 @@
35 35 };
36 36  
37 37 &adc {
38   - pinctrl-names = "default";
39   - pinctrl-0 = <&adc12_usb_pwr_pins_a>;
40   - vdd-supply = <&vdd>;
41   - vdda-supply = <&vdd>;
42   - vref-supply = <&vrefbuf>;
43 38 status = "okay";
44   - adc1: adc@0 {
45   - /*
46   - * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
47   - * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
48   - * 5 * (56 + 47kOhms) * 5pF => 2.5us.
49   - * Use arbitrary margin here (e.g. 5ยตs).
50   - */
51   - st,min-sample-time-nsecs = <5000>;
52   - /* ANA0, ANA1, USB Type-C CC1 & CC2 */
53   - st,adc-channels = <0 1 18 19>;
54   - status = "okay";
55   - };
56 39 };
57 40  
58 41 &clk_hse {
... ... @@ -127,7 +110,7 @@
127 110 CLK_UART6_HSI
128 111 CLK_UART78_HSI
129 112 CLK_SPDIF_PLL4P
130   - CLK_FDCAN_PLL4Q
  113 + CLK_FDCAN_PLL4R
131 114 CLK_SAI1_PLL3Q
132 115 CLK_SAI2_PLL3Q
133 116 CLK_SAI3_PLL3Q
... ... @@ -141,6 +124,8 @@
141 124  
142 125 /* VCO = 1300.0 MHz => P = 650 (CPU) */
143 126 pll1: st,pll@0 {
  127 + compatible = "st,stm32mp1-pll";
  128 + reg = <0>;
144 129 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
145 130 frac = < 0x800 >;
146 131 u-boot,dm-pre-reloc;
... ... @@ -148,6 +133,8 @@
148 133  
149 134 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
150 135 pll2: st,pll@1 {
  136 + compatible = "st,stm32mp1-pll";
  137 + reg = <1>;
151 138 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
152 139 frac = < 0x1400 >;
153 140 u-boot,dm-pre-reloc;
... ... @@ -155,6 +142,8 @@
155 142  
156 143 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
157 144 pll3: st,pll@2 {
  145 + compatible = "st,stm32mp1-pll";
  146 + reg = <2>;
158 147 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
159 148 frac = < 0x1a04 >;
160 149 u-boot,dm-pre-reloc;
... ... @@ -162,6 +151,8 @@
162 151  
163 152 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
164 153 pll4: st,pll@3 {
  154 + compatible = "st,stm32mp1-pll";
  155 + reg = <3>;
165 156 cfg = < 3 98 5 7 7 PQR(1,1,1) >;
166 157 u-boot,dm-pre-reloc;
167 158 };
arch/arm/dts/stm32mp157a-dk1.dts
Diff comments   View file @ f2a73d6
... ... @@ -25,6 +25,7 @@
25 25 };
26 26  
27 27 memory@c0000000 {
  28 + device_type = "memory";
28 29 reg = <0xc0000000 0x20000000>;
29 30 };
30 31  
31 32  
... ... @@ -92,11 +93,38 @@
92 93 "Playback" , "MCLK",
93 94 "Capture" , "MCLK",
94 95 "MICL" , "Mic Bias";
95   - dais = <&sai2a_port &sai2b_port>;
  96 + dais = <&sai2a_port &sai2b_port &i2s2_port>;
96 97 status = "okay";
97 98 };
98 99 };
99 100  
  101 +&adc {
  102 + pinctrl-names = "default";
  103 + pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>;
  104 + vdd-supply = <&vdd>;
  105 + vdda-supply = <&vdd>;
  106 + vref-supply = <&vrefbuf>;
  107 + status = "disabled";
  108 + adc1: adc@0 {
  109 + /*
  110 + * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
  111 + * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
  112 + * 5 * (56 + 47kOhms) * 5pF => 2.5us.
  113 + * Use arbitrary margin here (e.g. 5us).
  114 + */
  115 + st,min-sample-time-nsecs = <5000>;
  116 + /* AIN connector, USB Type-C CC1 & CC2 */
  117 + st,adc-channels = <0 1 6 13 18 19>;
  118 + status = "okay";
  119 + };
  120 + adc2: adc@100 {
  121 + /* AIN connector, USB Type-C CC1 & CC2 */
  122 + st,adc-channels = <0 1 2 6 18 19>;
  123 + st,min-sample-time-nsecs = <5000>;
  124 + status = "okay";
  125 + };
  126 +};
  127 +
100 128 &cec {
101 129 pinctrl-names = "default", "sleep";
102 130 pinctrl-0 = <&cec_pins_b>;
... ... @@ -146,9 +174,7 @@
146 174 reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>;
147 175 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
148 176 interrupt-parent = <&gpiog>;
149   - pinctrl-names = "default", "sleep";
150   - pinctrl-0 = <&ltdc_pins_a>;
151   - pinctrl-1 = <&ltdc_pins_sleep_a>;
  177 + #sound-dai-cells = <0>;
152 178 status = "okay";
153 179  
154 180 ports {
... ... @@ -161,6 +187,13 @@
161 187 remote-endpoint = <&ltdc_ep0_out>;
162 188 };
163 189 };
  190 +
  191 + port@3 {
  192 + reg = <3>;
  193 + sii9022_tx_endpoint: endpoint {
  194 + remote-endpoint = <&i2s2_endpoint>;
  195 + };
  196 + };
164 197 };
165 198 };
166 199  
... ... @@ -244,7 +277,7 @@
244 277  
245 278 vddcore: buck1 {
246 279 regulator-name = "vddcore";
247   - regulator-min-microvolt = <800000>;
  280 + regulator-min-microvolt = <1200000>;
248 281 regulator-max-microvolt = <1350000>;
249 282 regulator-always-on;
250 283 regulator-initial-mode = <0>;
... ... @@ -345,7 +378,7 @@
345 378 vbus_sw: pwr_sw2 {
346 379 regulator-name = "vbus_sw";
347 380 interrupts = <IT_OCP_SWOUT 0>;
348   - regulator-active-discharge;
  381 + regulator-active-discharge = <1>;
349 382 };
350 383 };
351 384  
... ... @@ -364,6 +397,23 @@
364 397 };
365 398 };
366 399  
  400 +&i2s2 {
  401 + clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
  402 + clock-names = "pclk", "i2sclk", "x8k", "x11k";
  403 + pinctrl-names = "default", "sleep";
  404 + pinctrl-0 = <&i2s2_pins_a>;
  405 + pinctrl-1 = <&i2s2_pins_sleep_a>;
  406 + status = "okay";
  407 +
  408 + i2s2_port: port {
  409 + i2s2_endpoint: endpoint {
  410 + remote-endpoint = <&sii9022_tx_endpoint>;
  411 + format = "i2s";
  412 + mclk-fs = <256>;
  413 + };
  414 + };
  415 +};
  416 +
367 417 &ipcc {
368 418 status = "okay";
369 419 };
... ... @@ -374,6 +424,9 @@
374 424 };
375 425  
376 426 &ltdc {
  427 + pinctrl-names = "default", "sleep";
  428 + pinctrl-0 = <&ltdc_pins_a>;
  429 + pinctrl-1 = <&ltdc_pins_sleep_a>;
377 430 status = "okay";
378 431  
379 432 port {
... ... @@ -397,11 +450,9 @@
397 450 status = "okay";
398 451 };
399 452  
400   -&pwr {
401   - pwr-regulators {
402   - vdd-supply = <&vdd>;
403   - vdd_3v3_usbfs-supply = <&vdd_usb>;
404   - };
  453 +&pwr_regulators {
  454 + vdd-supply = <&vdd>;
  455 + vdd_3v3_usbfs-supply = <&vdd_usb>;
405 456 };
406 457  
407 458 &rng1 {
arch/arm/dts/stm32mp157c-dk2.dts
Diff comments   View file @ f2a73d6
... ... @@ -53,6 +53,19 @@
53 53 };
54 54 };
55 55  
  56 +&i2c1 {
  57 + touchscreen@38 {
  58 + compatible = "focaltech,ft6236";
  59 + reg = <0x38>;
  60 + interrupts = <2 2>;
  61 + interrupt-parent = <&gpiof>;
  62 + interrupt-controller;
  63 + touchscreen-size-x = <480>;
  64 + touchscreen-size-y = <800>;
  65 + status = "okay";
  66 + };
  67 +};
  68 +
56 69 &ltdc {
57 70 status = "okay";
58 71  
arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
Diff comments   View file @ f2a73d6
... ... @@ -107,7 +107,7 @@
107 107 CLK_UART6_HSI
108 108 CLK_UART78_HSI
109 109 CLK_SPDIF_PLL4P
110   - CLK_FDCAN_PLL4Q
  110 + CLK_FDCAN_PLL4R
111 111 CLK_SAI1_PLL3Q
112 112 CLK_SAI2_PLL3Q
113 113 CLK_SAI3_PLL3Q
... ... @@ -121,6 +121,8 @@
121 121  
122 122 /* VCO = 1300.0 MHz => P = 650 (CPU) */
123 123 pll1: st,pll@0 {
  124 + compatible = "st,stm32mp1-pll";
  125 + reg = <0>;
124 126 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
125 127 frac = < 0x800 >;
126 128 u-boot,dm-pre-reloc;
... ... @@ -128,6 +130,8 @@
128 130  
129 131 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
130 132 pll2: st,pll@1 {
  133 + compatible = "st,stm32mp1-pll";
  134 + reg = <1>;
131 135 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
132 136 frac = < 0x1400 >;
133 137 u-boot,dm-pre-reloc;
... ... @@ -135,6 +139,8 @@
135 139  
136 140 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
137 141 pll3: st,pll@2 {
  142 + compatible = "st,stm32mp1-pll";
  143 + reg = <2>;
138 144 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
139 145 frac = < 0x1a04 >;
140 146 u-boot,dm-pre-reloc;
... ... @@ -142,6 +148,8 @@
142 148  
143 149 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
144 150 pll4: st,pll@3 {
  151 + compatible = "st,stm32mp1-pll";
  152 + reg = <3>;
145 153 cfg = < 3 98 5 7 7 PQR(1,1,1) >;
146 154 u-boot,dm-pre-reloc;
147 155 };
arch/arm/dts/stm32mp157c-ed1.dts
Diff comments   View file @ f2a73d6
... ... @@ -84,10 +84,24 @@
84 84  
85 85 gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>;
86 86 gpios-states = <0>;
87   - states = <1800000 0x1 2900000 0x0>;
  87 + states = <1800000 0x1>,
  88 + <2900000 0x0>;
88 89 };
89 90 };
90 91  
  92 +&dac {
  93 + pinctrl-names = "default";
  94 + pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
  95 + vref-supply = <&vdda>;
  96 + status = "disabled";
  97 + dac1: dac@1 {
  98 + status = "okay";
  99 + };
  100 + dac2: dac@2 {
  101 + status = "okay";
  102 + };
  103 +};
  104 +
91 105 &dts {
92 106 status = "okay";
93 107 };
... ... @@ -127,7 +141,7 @@
127 141  
128 142 vddcore: buck1 {
129 143 regulator-name = "vddcore";
130   - regulator-min-microvolt = <800000>;
  144 + regulator-min-microvolt = <1200000>;
131 145 regulator-max-microvolt = <1350000>;
132 146 regulator-always-on;
133 147 regulator-initial-mode = <0>;
... ... @@ -225,7 +239,7 @@
225 239 vbus_sw: pwr_sw2 {
226 240 regulator-name = "vbus_sw";
227 241 interrupts = <IT_OCP_SWOUT 0>;
228   - regulator-active-discharge;
  242 + regulator-active-discharge = <1>;
229 243 };
230 244 };
231 245  
... ... @@ -263,11 +277,9 @@
263 277 status = "okay";
264 278 };
265 279  
266   -&pwr {
267   - pwr-regulators {
268   - vdd-supply = <&vdd>;
269   - vdd_3v3_usbfs-supply = <&vdd_usb>;
270   - };
  280 +&pwr_regulators {
  281 + vdd-supply = <&vdd>;
  282 + vdd_3v3_usbfs-supply = <&vdd_usb>;
271 283 };
272 284  
273 285 &rng1 {
arch/arm/dts/stm32mp157c-ev1.dts
Diff comments   View file @ f2a73d6
... ... @@ -32,7 +32,6 @@
32 32  
33 33 joystick {
34 34 compatible = "gpio-keys";
35   - #size-cells = <0>;
36 35 pinctrl-0 = <&joystick_pins>;
37 36 pinctrl-names = "default";
38 37 button-0 {
... ... @@ -189,8 +188,8 @@
189 188 clocks = <&clk_ext_camera>;
190 189 clock-names = "xclk";
191 190 DOVDD-supply = <&v2v8>;
192   - powerdown-gpios = <&stmfx_pinctrl 18 GPIO_ACTIVE_HIGH>;
193   - reset-gpios = <&stmfx_pinctrl 19 GPIO_ACTIVE_LOW>;
  191 + powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>;
  192 + reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
194 193 rotation = <180>;
195 194 status = "okay";
196 195  
... ... @@ -223,7 +222,6 @@
223 222  
224 223 joystick_pins: joystick {
225 224 pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
226   - drive-push-pull;
227 225 bias-pull-down;
228 226 };
229 227  
230 228  
... ... @@ -344,14 +342,12 @@
344 342  
345 343 &usbh_ehci {
346 344 phys = <&usbphyc_port0>;
347   - phy-names = "usb";
348 345 status = "okay";
349 346 };
350 347  
351 348 &usbotg_hs {
352 349 dr_mode = "peripheral";
353 350 phys = <&usbphyc_port1 0>;
354   - phy-names = "usb2-phy";
355 351 status = "okay";
356 352 };
357 353  
arch/arm/dts/stm32mp157c.dtsi
Diff comments   View file @ f2a73d6
... ... @@ -939,7 +939,7 @@
939 939 interrupt-names = "int0", "int1";
940 940 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
941 941 clock-names = "hclk", "cclk";
942   - bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
  942 + bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
943 943 status = "disabled";
944 944 };
945 945  
... ... @@ -952,7 +952,7 @@
952 952 interrupt-names = "int0", "int1";
953 953 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
954 954 clock-names = "hclk", "cclk";
955   - bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
  955 + bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
956 956 status = "disabled";
957 957 };
958 958  
959 959  
960 960  
961 961  
... ... @@ -1110,36 +1110,26 @@
1110 1110 #reset-cells = <1>;
1111 1111 };
1112 1112  
1113   - pwr: pwr@50001000 {
1114   - compatible = "st,stm32mp1-pwr", "st,stm32-pwr", "syscon", "simple-mfd";
1115   - reg = <0x50001000 0x400>;
1116   - system-power-controller;
1117   - interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
1118   - st,sysrcc = <&rcc>;
1119   - clocks = <&rcc PLL2_R>;
1120   - clock-names = "phyclk";
  1113 + pwr_regulators: pwr@50001000 {
  1114 + compatible = "st,stm32mp1,pwr-reg";
  1115 + reg = <0x50001000 0x10>;
1121 1116  
1122   - pwr-regulators {
1123   - compatible = "st,stm32mp1,pwr-reg";
1124   - st,tzcr = <&rcc 0x0 0x1>;
  1117 + reg11: reg11 {
  1118 + regulator-name = "reg11";
  1119 + regulator-min-microvolt = <1100000>;
  1120 + regulator-max-microvolt = <1100000>;
  1121 + };
1125 1122  
1126   - reg11: reg11 {
1127   - regulator-name = "reg11";
1128   - regulator-min-microvolt = <1100000>;
1129   - regulator-max-microvolt = <1100000>;
1130   - };
  1123 + reg18: reg18 {
  1124 + regulator-name = "reg18";
  1125 + regulator-min-microvolt = <1800000>;
  1126 + regulator-max-microvolt = <1800000>;
  1127 + };
1131 1128  
1132   - reg18: reg18 {
1133   - regulator-name = "reg18";
1134   - regulator-min-microvolt = <1800000>;
1135   - regulator-max-microvolt = <1800000>;
1136   - };
1137   -
1138   - usb33: usb33 {
1139   - regulator-name = "usb33";
1140   - regulator-min-microvolt = <3300000>;
1141   - regulator-max-microvolt = <3300000>;
1142   - };
  1129 + usb33: usb33 {
  1130 + regulator-name = "usb33";
  1131 + regulator-min-microvolt = <3300000>;
  1132 + regulator-max-microvolt = <3300000>;
1143 1133 };
1144 1134 };
1145 1135  
arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi
Diff comments   View file @ f2a73d6
  1 +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2 +/*
  3 + * Copyright (C) 2019 Marek Vasut <marex@denx.de>
  4 + */
  5 +
  6 +#include "stm32mp15xx-dhcom-u-boot.dtsi"
arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
Diff comments   View file @ f2a73d6
  1 +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2 +/*
  3 + * Copyright (C) 2019 Marek Vasut <marex@denx.de>
  4 + */
  5 +
  6 +#include "stm32mp15xx-dhcom.dtsi"
  7 +
  8 +/ {
  9 + model = "STMicroelectronics STM32MP15xx DHCOM Premium Developer Kit (2)";
  10 + compatible = "dh,stm32mp15xx-dhcom-pdk2", "st,stm32mp15x";
  11 +
  12 + aliases {
  13 + serial0 = &uart4;
  14 + ethernet0 = &ethernet0;
  15 + };
  16 +
  17 + chosen {
  18 + stdout-path = "serial0:115200n8";
  19 + };
  20 +
  21 + ethernet_vio: vioregulator {
  22 + compatible = "regulator-fixed";
  23 + regulator-name = "vio";
  24 + regulator-min-microvolt = <3300000>;
  25 + regulator-max-microvolt = <3300000>;
  26 + gpio = <&gpiog 3 GPIO_ACTIVE_LOW>;
  27 + regulator-always-on;
  28 + regulator-boot-on;
  29 + };
  30 +};
  31 +
  32 +&ethernet0 {
  33 + status = "okay";
  34 + pinctrl-0 = <&ethernet0_rmii_pins_a>;
  35 + pinctrl-1 = <&ethernet0_rmii_pins_sleep_a>;
  36 + pinctrl-names = "default", "sleep";
  37 + phy-mode = "rmii";
  38 + max-speed = <100>;
  39 + phy-handle = <&phy0>;
  40 + st,eth_ref_clk_sel;
  41 + phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>;
  42 +
  43 + mdio0 {
  44 + #address-cells = <1>;
  45 + #size-cells = <0>;
  46 + compatible = "snps,dwmac-mdio";
  47 +
  48 + phy0: ethernet-phy@1 {
  49 + reg = <1>;
  50 + };
  51 + };
  52 +};
  53 +
  54 +&pinctrl {
  55 + ethernet0_rmii_pins_a: rmii-0 {
  56 + pins1 {
  57 + pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
  58 + <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
  59 + <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
  60 + <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */
  61 + <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
  62 + <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
  63 + bias-disable;
  64 + drive-push-pull;
  65 + slew-rate = <2>;
  66 + };
  67 + pins2 {
  68 + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
  69 + <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
  70 + <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
  71 + bias-disable;
  72 + };
  73 + };
  74 +
  75 + ethernet0_rmii_pins_sleep_a: rmii-sleep-0 {
  76 + pins1 {
  77 + pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
  78 + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
  79 + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
  80 + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
  81 + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
  82 + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
  83 + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
  84 + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
  85 + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
  86 + };
  87 + };
  88 +};
arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
Diff comments   View file @ f2a73d6
  1 +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2 +/*
  3 + * Copyright (C) 2019 Marek Vasut <marex@denx.de>
  4 + */
  5 +
  6 +#include <dt-bindings/clock/stm32mp1-clksrc.h>
  7 +#include "stm32mp157-u-boot.dtsi"
  8 +#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
  9 +
  10 +/ {
  11 + aliases {
  12 + i2c1 = &i2c2;
  13 + i2c3 = &i2c4;
  14 + i2c4 = &i2c5;
  15 + mmc0 = &sdmmc1;
  16 + mmc1 = &sdmmc2;
  17 + spi0 = &qspi;
  18 + usb0 = &usbotg_hs;
  19 + };
  20 +
  21 + config {
  22 + u-boot,boot-led = "heartbeat";
  23 + u-boot,error-led = "error";
  24 + st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  25 + st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
  26 + };
  27 +
  28 + led {
  29 + red {
  30 + label = "error";
  31 + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  32 + default-state = "off";
  33 + status = "okay";
  34 + };
  35 +
  36 + blue {
  37 + default-state = "on";
  38 + };
  39 + };
  40 +};
  41 +
  42 +&i2c4 {
  43 + u-boot,dm-pre-reloc;
  44 +};
  45 +
  46 +&i2c4_pins_a {
  47 + u-boot,dm-pre-reloc;
  48 + pins {
  49 + u-boot,dm-pre-reloc;
  50 + };
  51 +};
  52 +
  53 +&pmic {
  54 + u-boot,dm-pre-reloc;
  55 +};
  56 +
  57 +&flash0 {
  58 + u-boot,dm-spl;
  59 +};
  60 +
  61 +&qspi {
  62 + u-boot,dm-spl;
  63 +};
  64 +
  65 +&qspi_clk_pins_a {
  66 + u-boot,dm-spl;
  67 + pins {
  68 + u-boot,dm-spl;
  69 + };
  70 +};
  71 +
  72 +&qspi_bk1_pins_a {
  73 + u-boot,dm-spl;
  74 + pins1 {
  75 + u-boot,dm-spl;
  76 + };
  77 + pins2 {
  78 + u-boot,dm-spl;
  79 + };
  80 +};
  81 +
  82 +&qspi_bk2_pins_a {
  83 + u-boot,dm-spl;
  84 + pins1 {
  85 + u-boot,dm-spl;
  86 + };
  87 + pins2 {
  88 + u-boot,dm-spl;
  89 + };
  90 +};
  91 +
  92 +&rcc {
  93 + st,clksrc = <
  94 + CLK_MPU_PLL1P
  95 + CLK_AXI_PLL2P
  96 + CLK_MCU_PLL3P
  97 + CLK_PLL12_HSE
  98 + CLK_PLL3_HSE
  99 + CLK_PLL4_HSE
  100 + CLK_RTC_LSE
  101 + CLK_MCO1_DISABLED
  102 + CLK_MCO2_DISABLED
  103 + >;
  104 +
  105 + st,clkdiv = <
  106 + 1 /*MPU*/
  107 + 0 /*AXI*/
  108 + 0 /*MCU*/
  109 + 1 /*APB1*/
  110 + 1 /*APB2*/
  111 + 1 /*APB3*/
  112 + 1 /*APB4*/
  113 + 2 /*APB5*/
  114 + 23 /*RTC*/
  115 + 0 /*MCO1*/
  116 + 0 /*MCO2*/
  117 + >;
  118 +
  119 + st,pkcs = <
  120 + CLK_CKPER_HSE
  121 + CLK_FMC_ACLK
  122 + CLK_QSPI_ACLK
  123 + CLK_ETH_PLL4P
  124 + CLK_SDMMC12_PLL4P
  125 + CLK_DSI_DSIPLL
  126 + CLK_STGEN_HSE
  127 + CLK_USBPHY_HSE
  128 + CLK_SPI2S1_PLL3Q
  129 + CLK_SPI2S23_PLL3Q
  130 + CLK_SPI45_HSI
  131 + CLK_SPI6_HSI
  132 + CLK_I2C46_HSI
  133 + CLK_SDMMC3_PLL4P
  134 + CLK_USBO_USBPHY
  135 + CLK_ADC_CKPER
  136 + CLK_CEC_LSE
  137 + CLK_I2C12_HSI
  138 + CLK_I2C35_HSI
  139 + CLK_UART1_HSI
  140 + CLK_UART24_HSI
  141 + CLK_UART35_HSI
  142 + CLK_UART6_HSI
  143 + CLK_UART78_HSI
  144 + CLK_SPDIF_PLL4P
  145 + CLK_FDCAN_PLL4R
  146 + CLK_SAI1_PLL3Q
  147 + CLK_SAI2_PLL3Q
  148 + CLK_SAI3_PLL3Q
  149 + CLK_SAI4_PLL3Q
  150 + CLK_RNG1_LSI
  151 + CLK_RNG2_LSI
  152 + CLK_LPTIM1_PCLK1
  153 + CLK_LPTIM23_PCLK3
  154 + CLK_LPTIM45_LSE
  155 + >;
  156 +
  157 + /* VCO = 1300.0 MHz => P = 650 (CPU) */
  158 + pll1: st,pll@0 {
  159 + compatible = "st,stm32mp1-pll";
  160 + reg = <0>;
  161 + cfg = < 2 80 0 0 0 PQR(1,0,0) >;
  162 + frac = < 0x800 >;
  163 + u-boot,dm-pre-reloc;
  164 + };
  165 +
  166 + /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
  167 + pll2: st,pll@1 {
  168 + compatible = "st,stm32mp1-pll";
  169 + reg = <1>;
  170 + cfg = < 2 65 1 0 0 PQR(1,1,1) >;
  171 + frac = < 0x1400 >;
  172 + u-boot,dm-pre-reloc;
  173 + };
  174 +
  175 + /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
  176 + pll3: st,pll@2 {
  177 + compatible = "st,stm32mp1-pll";
  178 + reg = <2>;
  179 + cfg = < 1 33 1 16 36 PQR(1,1,1) >;
  180 + frac = < 0x1a04 >;
  181 + u-boot,dm-pre-reloc;
  182 + };
  183 +
  184 + /* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */
  185 + pll4: st,pll@3 {
  186 + compatible = "st,stm32mp1-pll";
  187 + reg = <3>;
  188 + cfg = < 1 49 11 11 11 PQR(1,1,1) >;
  189 + u-boot,dm-pre-reloc;
  190 + };
  191 +};
  192 +
  193 +&sdmmc1 {
  194 + u-boot,dm-spl;
  195 +};
  196 +
  197 +&sdmmc1_b4_pins_a {
  198 + u-boot,dm-spl;
  199 + pins {
  200 + u-boot,dm-spl;
  201 + };
  202 +};
  203 +
  204 +&sdmmc1_dir_pins_a {
  205 + u-boot,dm-spl;
  206 + pins1 {
  207 + u-boot,dm-spl;
  208 + };
  209 + pins2 {
  210 + u-boot,dm-spl;
  211 + };
  212 +};
  213 +
  214 +&sdmmc2 {
  215 + u-boot,dm-spl;
  216 +};
  217 +
  218 +&sdmmc2_b4_pins_a {
  219 + u-boot,dm-spl;
  220 + pins {
  221 + u-boot,dm-spl;
  222 + };
  223 +};
  224 +
  225 +&sdmmc2_d47_pins_a {
  226 + u-boot,dm-spl;
  227 + pins {
  228 + u-boot,dm-spl;
  229 + };
  230 +};
  231 +
  232 +&uart4 {
  233 + u-boot,dm-pre-reloc;
  234 +};
  235 +
  236 +&uart4_pins_a {
  237 + u-boot,dm-pre-reloc;
  238 + pins1 {
  239 + u-boot,dm-pre-reloc;
  240 + };
  241 + pins2 {
  242 + u-boot,dm-pre-reloc;
  243 + /* pull-up on rx to avoid floating level */
  244 + bias-pull-up;
  245 + };
  246 +};
arch/arm/dts/stm32mp15xx-dhcom.dtsi
Diff comments   View file @ f2a73d6
  1 +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
  2 +/*
  3 + * Copyright (C) 2019 Marek Vasut <marex@denx.de>
  4 + */
  5 +/dts-v1/;
  6 +
  7 +#include "stm32mp157c.dtsi"
  8 +#include "stm32mp157xaa-pinctrl.dtsi"
  9 +#include <dt-bindings/gpio/gpio.h>
  10 +#include <dt-bindings/mfd/st,stpmic1.h>
  11 +
  12 +/ {
  13 + memory@c0000000 {
  14 + device_type = "memory";
  15 + reg = <0xC0000000 0x40000000>;
  16 + };
  17 +};
  18 +
  19 +&cec {
  20 + pinctrl-names = "default";
  21 + pinctrl-0 = <&cec_pins_a>;
  22 + status = "okay";
  23 +};
  24 +
  25 +&dcmi {
  26 + status = "okay";
  27 + pinctrl-names = "default", "sleep";
  28 + pinctrl-0 = <&dcmi_pins_a>;
  29 + pinctrl-1 = <&dcmi_sleep_pins_a>;
  30 +};
  31 +
  32 +&dts {
  33 + status = "okay";
  34 +};
  35 +
  36 +&i2c2 {
  37 + pinctrl-names = "default";
  38 + pinctrl-0 = <&i2c2_pins_a>;
  39 + i2c-scl-rising-time-ns = <185>;
  40 + i2c-scl-falling-time-ns = <20>;
  41 + status = "okay";
  42 +};
  43 +
  44 +&i2c4 {
  45 + pinctrl-names = "default";
  46 + pinctrl-0 = <&i2c4_pins_a>;
  47 + i2c-scl-rising-time-ns = <185>;
  48 + i2c-scl-falling-time-ns = <20>;
  49 + status = "okay";
  50 + /* spare dmas for other usage */
  51 + /delete-property/dmas;
  52 + /delete-property/dma-names;
  53 +
  54 + pmic: stpmic@33 {
  55 + compatible = "st,stpmic1";
  56 + reg = <0x33>;
  57 + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
  58 + interrupt-controller;
  59 + #interrupt-cells = <2>;
  60 + status = "okay";
  61 +
  62 + regulators {
  63 + compatible = "st,stpmic1-regulators";
  64 + ldo1-supply = <&v3v3>;
  65 + ldo2-supply = <&v3v3>;
  66 + ldo3-supply = <&vdd_ddr>;
  67 + ldo5-supply = <&v3v3>;
  68 + ldo6-supply = <&v3v3>;
  69 + pwr_sw1-supply = <&bst_out>;
  70 + pwr_sw2-supply = <&bst_out>;
  71 +
  72 + vddcore: buck1 {
  73 + regulator-name = "vddcore";
  74 + regulator-min-microvolt = <800000>;
  75 + regulator-max-microvolt = <1350000>;
  76 + regulator-always-on;
  77 + regulator-initial-mode = <0>;
  78 + regulator-over-current-protection;
  79 + };
  80 +
  81 + vdd_ddr: buck2 {
  82 + regulator-name = "vdd_ddr";
  83 + regulator-min-microvolt = <1350000>;
  84 + regulator-max-microvolt = <1350000>;
  85 + regulator-always-on;
  86 + regulator-initial-mode = <0>;
  87 + regulator-over-current-protection;
  88 + };
  89 +
  90 + vdd: buck3 {
  91 + regulator-name = "vdd";
  92 + regulator-min-microvolt = <3300000>;
  93 + regulator-max-microvolt = <3300000>;
  94 + regulator-always-on;
  95 + st,mask-reset;
  96 + regulator-initial-mode = <0>;
  97 + regulator-over-current-protection;
  98 + };
  99 +
  100 + v3v3: buck4 {
  101 + regulator-name = "v3v3";
  102 + regulator-min-microvolt = <3300000>;
  103 + regulator-max-microvolt = <3300000>;
  104 + regulator-always-on;
  105 + regulator-over-current-protection;
  106 + regulator-initial-mode = <0>;
  107 + };
  108 +
  109 + vdda: ldo1 {
  110 + regulator-name = "vdda";
  111 + regulator-min-microvolt = <2900000>;
  112 + regulator-max-microvolt = <2900000>;
  113 + interrupts = <IT_CURLIM_LDO1 0>;
  114 + };
  115 +
  116 + v2v8: ldo2 {
  117 + regulator-name = "v2v8";
  118 + regulator-min-microvolt = <2800000>;
  119 + regulator-max-microvolt = <2800000>;
  120 + interrupts = <IT_CURLIM_LDO2 0>;
  121 + };
  122 +
  123 + vtt_ddr: ldo3 {
  124 + regulator-name = "vtt_ddr";
  125 + regulator-min-microvolt = <500000>;
  126 + regulator-max-microvolt = <750000>;
  127 + regulator-always-on;
  128 + regulator-over-current-protection;
  129 + };
  130 +
  131 + vdd_usb: ldo4 {
  132 + regulator-name = "vdd_usb";
  133 + regulator-min-microvolt = <3300000>;
  134 + regulator-max-microvolt = <3300000>;
  135 + interrupts = <IT_CURLIM_LDO4 0>;
  136 + };
  137 +
  138 + vdd_sd: ldo5 {
  139 + regulator-name = "vdd_sd";
  140 + regulator-min-microvolt = <2900000>;
  141 + regulator-max-microvolt = <2900000>;
  142 + interrupts = <IT_CURLIM_LDO5 0>;
  143 + regulator-boot-on;
  144 + };
  145 +
  146 + v1v8: ldo6 {
  147 + regulator-name = "v1v8";
  148 + regulator-min-microvolt = <1800000>;
  149 + regulator-max-microvolt = <1800000>;
  150 + interrupts = <IT_CURLIM_LDO6 0>;
  151 + };
  152 +
  153 + vref_ddr: vref_ddr {
  154 + regulator-name = "vref_ddr";
  155 + regulator-always-on;
  156 + regulator-over-current-protection;
  157 + };
  158 +
  159 + bst_out: boost {
  160 + regulator-name = "bst_out";
  161 + interrupts = <IT_OCP_BOOST 0>;
  162 + };
  163 +
  164 + vbus_otg: pwr_sw1 {
  165 + regulator-name = "vbus_otg";
  166 + interrupts = <IT_OCP_OTG 0>;
  167 + };
  168 +
  169 + vbus_sw: pwr_sw2 {
  170 + regulator-name = "vbus_sw";
  171 + interrupts = <IT_OCP_SWOUT 0>;
  172 + regulator-active-discharge;
  173 + };
  174 + };
  175 +
  176 + onkey {
  177 + compatible = "st,stpmic1-onkey";
  178 + interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
  179 + interrupt-names = "onkey-falling", "onkey-rising";
  180 + power-off-time-sec = <10>;
  181 + status = "okay";
  182 + };
  183 +
  184 + watchdog {
  185 + compatible = "st,stpmic1-wdt";
  186 + status = "disabled";
  187 + };
  188 + };
  189 +
  190 + eeprom@50 {
  191 + compatible = "atmel,24c02";
  192 + reg = <0x50>;
  193 + pagesize = <16>;
  194 + };
  195 +};
  196 +
  197 +&i2c5 {
  198 + pinctrl-names = "default";
  199 + pinctrl-0 = <&i2c5_pins_a>;
  200 + i2c-scl-rising-time-ns = <185>;
  201 + i2c-scl-falling-time-ns = <20>;
  202 + status = "okay";
  203 +};
  204 +
  205 +&ipcc {
  206 + status = "okay";
  207 +};
  208 +
  209 +&iwdg2 {
  210 + timeout-sec = <32>;
  211 + status = "okay";
  212 +};
  213 +
  214 +&m4_rproc {
  215 + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
  216 + mbox-names = "vq0", "vq1", "shutdown";
  217 + status = "okay";
  218 +};
  219 +
  220 +&pwr_regulators {
  221 + vdd-supply = <&vdd>;
  222 + vdd_3v3_usbfs-supply = <&vdd_usb>;
  223 +};
  224 +
  225 +&qspi {
  226 + pinctrl-names = "default", "sleep";
  227 + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
  228 + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
  229 + reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
  230 + #address-cells = <1>;
  231 + #size-cells = <0>;
  232 + status = "okay";
  233 +
  234 + flash0: mx66l51235l@0 {
  235 + compatible = "jedec,spi-nor";
  236 + reg = <0>;
  237 + spi-rx-bus-width = <4>;
  238 + spi-max-frequency = <108000000>;
  239 + #address-cells = <1>;
  240 + #size-cells = <1>;
  241 + };
  242 +
  243 + flash1: mx66l51235l@1 {
  244 + compatible = "jedec,spi-nor";
  245 + reg = <1>;
  246 + spi-rx-bus-width = <4>;
  247 + spi-max-frequency = <108000000>;
  248 + #address-cells = <1>;
  249 + #size-cells = <1>;
  250 + };
  251 +};
  252 +
  253 +&rng1 {
  254 + status = "okay";
  255 +};
  256 +
  257 +&rtc {
  258 + status = "okay";
  259 +};
  260 +
  261 +&sdmmc1 {
  262 + pinctrl-names = "default", "opendrain", "sleep";
  263 + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
  264 + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
  265 + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
  266 + broken-cd;
  267 + st,sig-dir;
  268 + st,neg-edge;
  269 + st,use-ckin;
  270 + bus-width = <4>;
  271 + vmmc-supply = <&vdd_sd>;
  272 + status = "okay";
  273 +};
  274 +
  275 +&sdmmc2 {
  276 + pinctrl-names = "default";
  277 + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
  278 + non-removable;
  279 + no-sd;
  280 + no-sdio;
  281 + st,sig-dir;
  282 + st,neg-edge;
  283 + bus-width = <8>;
  284 + vmmc-supply = <&v3v3>;
  285 + status = "okay";
  286 +};
  287 +
  288 +&spi1 {
  289 + pinctrl-names = "default";
  290 + pinctrl-0 = <&spi1_pins_a>;
  291 + status = "disabled";
  292 +};
  293 +
  294 +&timers2 {
  295 + /* spare dmas for other usage (un-delete to enable pwm capture) */
  296 + /delete-property/dmas;
  297 + /delete-property/dma-names;
  298 + status = "disabled";
  299 + pwm {
  300 + pinctrl-0 = <&pwm2_pins_a>;
  301 + pinctrl-names = "default";
  302 + status = "okay";
  303 + };
  304 + timer@1 {
  305 + status = "okay";
  306 + };
  307 +};
  308 +
  309 +&timers6 {
  310 + status = "okay";
  311 + /* spare dmas for other usage */
  312 + /delete-property/dmas;
  313 + /delete-property/dma-names;
  314 + timer@5 {
  315 + status = "okay";
  316 + };
  317 +};
  318 +
  319 +&timers8 {
  320 + /delete-property/dmas;
  321 + /delete-property/dma-names;
  322 + status = "disabled";
  323 + pwm {
  324 + pinctrl-0 = <&pwm8_pins_a>;
  325 + pinctrl-names = "default";
  326 + status = "okay";
  327 + };
  328 + timer@7 {
  329 + status = "okay";
  330 + };
  331 +};
  332 +
  333 +&timers12 {
  334 + /delete-property/dmas;
  335 + /delete-property/dma-names;
  336 + status = "disabled";
  337 + pwm {
  338 + pinctrl-0 = <&pwm12_pins_a>;
  339 + pinctrl-names = "default";
  340 + status = "okay";
  341 + };
  342 + timer@11 {
  343 + status = "okay";
  344 + };
  345 +};
  346 +
  347 +&uart4 {
  348 + pinctrl-names = "default";
  349 + pinctrl-0 = <&uart4_pins_a>;
  350 + status = "okay";
  351 +};
  352 +
  353 +&usbh_ehci {
  354 + phys = <&usbphyc_port0>;
  355 + phy-names = "usb";
  356 + status = "okay";
  357 +};
  358 +
  359 +&usbotg_hs {
  360 + dr_mode = "peripheral";
  361 + phys = <&usbphyc_port1 0>;
  362 + phy-names = "usb2-phy";
  363 + vbus-supply = <&vbus_otg>;
  364 + status = "okay";
  365 +};
  366 +
  367 +&usbphyc {
  368 + status = "okay";
  369 +};
  370 +
  371 +&usbphyc_port0 {
  372 + phy-supply = <&vdd_usb>;
  373 +};
  374 +
  375 +&usbphyc_port1 {
  376 + phy-supply = <&vdd_usb>;
  377 +};
arch/arm/mach-stm32mp/Kconfig
Diff comments   View file @ f2a73d6
... ... @@ -73,6 +73,14 @@
73 73 Evalulation board (EV1) or Discovery board (DK1 and DK2).
74 74 The difference between board are managed with devicetree
75 75  
  76 +config TARGET_DH_STM32MP1_PDK2
  77 + bool "DH STM32MP1 PDK2"
  78 + select STM32MP15x
  79 + imply BOOTCOUNT_LIMIT
  80 + imply CMD_BOOTCOUNT
  81 + help
  82 + Target the DH PDK2 development kit with STM32MP15x SoM.
  83 +
76 84 endchoice
77 85  
78 86 config STM32MP1_TRUSTED
... ... @@ -158,6 +166,7 @@
158 166 endif
159 167  
160 168 source "board/st/stm32mp1/Kconfig"
  169 +source "board/dhelectronics/dh_stm32mp1/Kconfig"
161 170  
162 171 endif
arch/arm/mach-stm32mp/cpu.c
Diff comments   View file @ f2a73d6
... ... @@ -342,6 +342,9 @@
342 342 case CPU_REVB:
343 343 cpu_r = "B";
344 344 break;
  345 + case CPU_REVZ:
  346 + cpu_r = "Z";
  347 + break;
345 348 default:
346 349 cpu_r = "?";
347 350 break;
arch/arm/mach-stm32mp/include/mach/stm32.h
Diff comments   View file @ f2a73d6
... ... @@ -37,7 +37,6 @@
37 37 /* enumerated used to identify the SYSCON driver instance */
38 38 enum {
39 39 STM32MP_SYSCON_UNKNOWN,
40   - STM32MP_SYSCON_PWR,
41 40 STM32MP_SYSCON_SYSCFG,
42 41 };
43 42  
arch/arm/mach-stm32mp/include/mach/sys_proto.h
Diff comments   View file @ f2a73d6
... ... @@ -16,6 +16,7 @@
16 16  
17 17 #define CPU_REVA 0x1000
18 18 #define CPU_REVB 0x2000
  19 +#define CPU_REVZ 0x2001
19 20  
20 21 /* return CPU_REV constants */
21 22 u32 get_cpu_rev(void);
arch/arm/mach-stm32mp/pwr_regulator.c
Diff comments   View file @ f2a73d6
... ... @@ -6,8 +6,8 @@
6 6 #include <common.h>
7 7 #include <dm.h>
8 8 #include <errno.h>
9   -#include <regmap.h>
10 9 #include <syscon.h>
  10 +#include <asm/io.h>
11 11 #include <dm/device_compat.h>
12 12 #include <linux/err.h>
13 13 #include <power/pmic.h>
... ... @@ -28,7 +28,7 @@
28 28 };
29 29  
30 30 struct stm32mp_pwr_priv {
31   - struct regmap *regmap;
  31 + fdt_addr_t base;
32 32 };
33 33  
34 34 static int stm32mp_pwr_write(struct udevice *dev, uint reg,
... ... @@ -40,7 +40,9 @@
40 40 if (len != 4)
41 41 return -EINVAL;
42 42  
43   - return regmap_write(priv->regmap, STM32MP_PWR_CR3, val);
  43 + writel(val, priv->base + STM32MP_PWR_CR3);
  44 +
  45 + return 0;
44 46 }
45 47  
46 48 static int stm32mp_pwr_read(struct udevice *dev, uint reg, uint8_t *buff,
47 49  
48 50  
... ... @@ -51,21 +53,18 @@
51 53 if (len != 4)
52 54 return -EINVAL;
53 55  
54   - return regmap_read(priv->regmap, STM32MP_PWR_CR3, (u32 *)buff);
  56 + *(u32 *)buff = readl(priv->base + STM32MP_PWR_CR3);
  57 +
  58 + return 0;
55 59 }
56 60  
57 61 static int stm32mp_pwr_ofdata_to_platdata(struct udevice *dev)
58 62 {
59 63 struct stm32mp_pwr_priv *priv = dev_get_priv(dev);
60   - struct regmap *regmap;
61 64  
62   - regmap = syscon_get_regmap_by_driver_data(STM32MP_SYSCON_PWR);
63   - if (IS_ERR(regmap)) {
64   - pr_err("%s: unable to find regmap (%ld)\n", __func__,
65   - PTR_ERR(regmap));
66   - return PTR_ERR(regmap);
67   - }
68   - priv->regmap = regmap;
  65 + priv->base = dev_read_addr(dev);
  66 + if (priv->base == FDT_ADDR_T_NONE)
  67 + return -EINVAL;
69 68  
70 69 return 0;
71 70 }
arch/arm/mach-stm32mp/syscon.c
Diff comments   View file @ f2a73d6
... ... @@ -9,7 +9,6 @@
9 9 #include <asm/arch/stm32.h>
10 10  
11 11 static const struct udevice_id stm32mp_syscon_ids[] = {
12   - { .compatible = "st,stm32mp1-pwr", .data = STM32MP_SYSCON_PWR },
13 12 { .compatible = "st,stm32mp157-syscfg",
14 13 .data = STM32MP_SYSCON_SYSCFG },
15 14 { }
board/dhelectronics/dh_stm32mp1/Kconfig
Diff comments   View file @ f2a73d6
  1 +if TARGET_DH_STM32MP1_PDK2
  2 +
  3 +config SYS_BOARD
  4 + default "dh_stm32mp1"
  5 +
  6 +config SYS_VENDOR
  7 + default "dhelectronics"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "stm32mp1"
  11 +
  12 +config ENV_SECT_SIZE
  13 + default 0x10000 if ENV_IS_IN_SPI_FLASH
  14 +
  15 +config ENV_OFFSET
  16 + default 0x1E0000 if ENV_IS_IN_SPI_FLASH
  17 +
  18 +config ENV_OFFSET_REDUND
  19 + default 0x1F0000 if ENV_IS_IN_SPI_FLASH
  20 +
  21 +endif
board/dhelectronics/dh_stm32mp1/MAINTAINERS
Diff comments   View file @ f2a73d6
  1 +DH_STM32MP1_PDK2 BOARD
  2 +M: Marek Vasut <marex@denx.de>
  3 +S: Maintained
  4 +F: arch/arm/dts/stm32mp15xx-dhcom*
  5 +F: board/dhelectronics/dh_stm32mp1/
  6 +F: configs/stm32mp15_dhcom_basic_defconfig
  7 +F: include/configs/stm32mp1.h
board/dhelectronics/dh_stm32mp1/Makefile
Diff comments   View file @ f2a73d6
  1 +# SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2 +#
  3 +# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4 +#
  5 +
  6 +ifdef CONFIG_SPL_BUILD
  7 +obj-y += ../../st/stm32mp1/spl.o
  8 +endif
  9 +
  10 +obj-y += ../../st/stm32mp1/board.o board.o
board/dhelectronics/dh_stm32mp1/board.c
Diff comments   View file @ f2a73d6
  1 +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2 +/*
  3 + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4 + */
  5 +
  6 +#include <common.h>
  7 +#include <adc.h>
  8 +#include <asm/arch/stm32.h>
  9 +#include <asm/arch/sys_proto.h>
  10 +#include <asm/gpio.h>
  11 +#include <asm/io.h>
  12 +#include <bootm.h>
  13 +#include <clk.h>
  14 +#include <config.h>
  15 +#include <dm.h>
  16 +#include <dm/device.h>
  17 +#include <dm/uclass.h>
  18 +#include <env.h>
  19 +#include <env_internal.h>
  20 +#include <g_dnl.h>
  21 +#include <generic-phy.h>
  22 +#include <hang.h>
  23 +#include <i2c.h>
  24 +#include <i2c_eeprom.h>
  25 +#include <init.h>
  26 +#include <led.h>
  27 +#include <memalign.h>
  28 +#include <misc.h>
  29 +#include <mtd.h>
  30 +#include <mtd_node.h>
  31 +#include <netdev.h>
  32 +#include <phy.h>
  33 +#include <power/regulator.h>
  34 +#include <remoteproc.h>
  35 +#include <reset.h>
  36 +#include <syscon.h>
  37 +#include <usb.h>
  38 +#include <usb/dwc2_udc.h>
  39 +#include <watchdog.h>
  40 +
  41 +/* SYSCFG registers */
  42 +#define SYSCFG_BOOTR 0x00
  43 +#define SYSCFG_PMCSETR 0x04
  44 +#define SYSCFG_IOCTRLSETR 0x18
  45 +#define SYSCFG_ICNR 0x1C
  46 +#define SYSCFG_CMPCR 0x20
  47 +#define SYSCFG_CMPENSETR 0x24
  48 +#define SYSCFG_PMCCLRR 0x44
  49 +
  50 +#define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
  51 +#define SYSCFG_BOOTR_BOOTPD_SHIFT 4
  52 +
  53 +#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0)
  54 +#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1)
  55 +#define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2)
  56 +#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3)
  57 +#define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4)
  58 +
  59 +#define SYSCFG_CMPCR_SW_CTRL BIT(1)
  60 +#define SYSCFG_CMPCR_READY BIT(8)
  61 +
  62 +#define SYSCFG_CMPENSETR_MPU_EN BIT(0)
  63 +
  64 +#define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16)
  65 +#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17)
  66 +
  67 +#define SYSCFG_PMCSETR_ETH_SELMII BIT(20)
  68 +
  69 +#define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21)
  70 +#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0
  71 +#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
  72 +#define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23)
  73 +
  74 +/*
  75 + * Get a global data pointer
  76 + */
  77 +DECLARE_GLOBAL_DATA_PTR;
  78 +
  79 +int setup_mac_address(void)
  80 +{
  81 + struct udevice *dev;
  82 + ofnode eeprom;
  83 + unsigned char enetaddr[6];
  84 + int ret;
  85 +
  86 + ret = eth_env_get_enetaddr("ethaddr", enetaddr);
  87 + if (ret) /* ethaddr is already set */
  88 + return 0;
  89 +
  90 + eeprom = ofnode_path("/soc/i2c@5c002000/eeprom@50");
  91 + if (!ofnode_valid(eeprom)) {
  92 + printf("Invalid hardware path to EEPROM!\n");
  93 + return -ENODEV;
  94 + }
  95 +
  96 + ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev);
  97 + if (ret) {
  98 + printf("Cannot find EEPROM!\n");
  99 + return ret;
  100 + }
  101 +
  102 + ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
  103 + if (ret) {
  104 + printf("Error reading configuration EEPROM!\n");
  105 + return ret;
  106 + }
  107 +
  108 + if (is_valid_ethaddr(enetaddr))
  109 + eth_env_set_enetaddr("ethaddr", enetaddr);
  110 +
  111 + return 0;
  112 +}
  113 +
  114 +int checkboard(void)
  115 +{
  116 + char *mode;
  117 + const char *fdt_compat;
  118 + int fdt_compat_len;
  119 +
  120 + if (IS_ENABLED(CONFIG_STM32MP1_OPTEE))
  121 + mode = "trusted with OP-TEE";
  122 + else if (IS_ENABLED(CONFIG_STM32MP1_TRUSTED))
  123 + mode = "trusted";
  124 + else
  125 + mode = "basic";
  126 +
  127 + printf("Board: stm32mp1 in %s mode", mode);
  128 + fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
  129 + &fdt_compat_len);
  130 + if (fdt_compat && fdt_compat_len)
  131 + printf(" (%s)", fdt_compat);
  132 + puts("\n");
  133 +
  134 + return 0;
  135 +}
  136 +
  137 +static void board_key_check(void)
  138 +{
  139 +#if defined(CONFIG_FASTBOOT) || defined(CONFIG_CMD_STM32PROG)
  140 + ofnode node;
  141 + struct gpio_desc gpio;
  142 + enum forced_boot_mode boot_mode = BOOT_NORMAL;
  143 +
  144 + node = ofnode_path("/config");
  145 + if (!ofnode_valid(node)) {
  146 + debug("%s: no /config node?\n", __func__);
  147 + return;
  148 + }
  149 +#ifdef CONFIG_FASTBOOT
  150 + if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0,
  151 + &gpio, GPIOD_IS_IN)) {
  152 + debug("%s: could not find a /config/st,fastboot-gpios\n",
  153 + __func__);
  154 + } else {
  155 + if (dm_gpio_get_value(&gpio)) {
  156 + puts("Fastboot key pressed, ");
  157 + boot_mode = BOOT_FASTBOOT;
  158 + }
  159 +
  160 + dm_gpio_free(NULL, &gpio);
  161 + }
  162 +#endif
  163 +#ifdef CONFIG_CMD_STM32PROG
  164 + if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0,
  165 + &gpio, GPIOD_IS_IN)) {
  166 + debug("%s: could not find a /config/st,stm32prog-gpios\n",
  167 + __func__);
  168 + } else {
  169 + if (dm_gpio_get_value(&gpio)) {
  170 + puts("STM32Programmer key pressed, ");
  171 + boot_mode = BOOT_STM32PROG;
  172 + }
  173 + dm_gpio_free(NULL, &gpio);
  174 + }
  175 +#endif
  176 +
  177 + if (boot_mode != BOOT_NORMAL) {
  178 + puts("entering download mode...\n");
  179 + clrsetbits_le32(TAMP_BOOT_CONTEXT,
  180 + TAMP_BOOT_FORCED_MASK,
  181 + boot_mode);
  182 + }
  183 +#endif
  184 +}
  185 +
  186 +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
  187 +
  188 +#include <usb/dwc2_udc.h>
  189 +int g_dnl_board_usb_cable_connected(void)
  190 +{
  191 + struct udevice *dwc2_udc_otg;
  192 + int ret;
  193 +
  194 + ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
  195 + DM_GET_DRIVER(dwc2_udc_otg),
  196 + &dwc2_udc_otg);
  197 + if (!ret)
  198 + debug("dwc2_udc_otg init failed\n");
  199 +
  200 + return dwc2_udc_B_session_valid(dwc2_udc_otg);
  201 +}
  202 +
  203 +#define STM32MP1_G_DNL_DFU_PRODUCT_NUM 0xdf11
  204 +#define STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM 0x0afb
  205 +
  206 +int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
  207 +{
  208 + if (!strcmp(name, "usb_dnl_dfu"))
  209 + put_unaligned(STM32MP1_G_DNL_DFU_PRODUCT_NUM, &dev->idProduct);
  210 + else if (!strcmp(name, "usb_dnl_fastboot"))
  211 + put_unaligned(STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM,
  212 + &dev->idProduct);
  213 + else
  214 + put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct);
  215 +
  216 + return 0;
  217 +}
  218 +
  219 +#endif /* CONFIG_USB_GADGET */
  220 +
  221 +#ifdef CONFIG_LED
  222 +static int get_led(struct udevice **dev, char *led_string)
  223 +{
  224 + char *led_name;
  225 + int ret;
  226 +
  227 + led_name = fdtdec_get_config_string(gd->fdt_blob, led_string);
  228 + if (!led_name) {
  229 + pr_debug("%s: could not find %s config string\n",
  230 + __func__, led_string);
  231 + return -ENOENT;
  232 + }
  233 + ret = led_get_by_label(led_name, dev);
  234 + if (ret) {
  235 + debug("%s: get=%d\n", __func__, ret);
  236 + return ret;
  237 + }
  238 +
  239 + return 0;
  240 +}
  241 +
  242 +static int setup_led(enum led_state_t cmd)
  243 +{
  244 + struct udevice *dev;
  245 + int ret;
  246 +
  247 + ret = get_led(&dev, "u-boot,boot-led");
  248 + if (ret)
  249 + return ret;
  250 +
  251 + ret = led_set_state(dev, cmd);
  252 + return ret;
  253 +}
  254 +#endif
  255 +
  256 +static void __maybe_unused led_error_blink(u32 nb_blink)
  257 +{
  258 +#ifdef CONFIG_LED
  259 + int ret;
  260 + struct udevice *led;
  261 + u32 i;
  262 +#endif
  263 +
  264 + if (!nb_blink)
  265 + return;
  266 +
  267 +#ifdef CONFIG_LED
  268 + ret = get_led(&led, "u-boot,error-led");
  269 + if (!ret) {
  270 + /* make u-boot,error-led blinking */
  271 + /* if U32_MAX and 125ms interval, for 17.02 years */
  272 + for (i = 0; i < 2 * nb_blink; i++) {
  273 + led_set_state(led, LEDST_TOGGLE);
  274 + mdelay(125);
  275 + WATCHDOG_RESET();
  276 + }
  277 + }
  278 +#endif
  279 +
  280 + /* infinite: the boot process must be stopped */
  281 + if (nb_blink == U32_MAX)
  282 + hang();
  283 +}
  284 +
  285 +static void sysconf_init(void)
  286 +{
  287 +#ifndef CONFIG_STM32MP1_TRUSTED
  288 + u8 *syscfg;
  289 +#ifdef CONFIG_DM_REGULATOR
  290 + struct udevice *pwr_dev;
  291 + struct udevice *pwr_reg;
  292 + struct udevice *dev;
  293 + int ret;
  294 + u32 otp = 0;
  295 +#endif
  296 + u32 bootr;
  297 +
  298 + syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
  299 +
  300 + /* interconnect update : select master using the port 1 */
  301 + /* LTDC = AXI_M9 */
  302 + /* GPU = AXI_M8 */
  303 + /* today information is hardcoded in U-Boot */
  304 + writel(BIT(9), syscfg + SYSCFG_ICNR);
  305 +
  306 + /* disable Pull-Down for boot pin connected to VDD */
  307 + bootr = readl(syscfg + SYSCFG_BOOTR);
  308 + bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT);
  309 + bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT;
  310 + writel(bootr, syscfg + SYSCFG_BOOTR);
  311 +
  312 +#ifdef CONFIG_DM_REGULATOR
  313 + /* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
  314 + * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
  315 + * The customer will have to disable this for low frequencies
  316 + * or if AFMUX is selected but the function not used, typically for
  317 + * TRACE. Otherwise, impact on power consumption.
  318 + *
  319 + * WARNING:
  320 + * enabling High Speed mode while VDD>2.7V
  321 + * with the OTP product_below_2v5 (OTP 18, BIT 13)
  322 + * erroneously set to 1 can damage the IC!
  323 + * => U-Boot set the register only if VDD < 2.7V (in DT)
  324 + * but this value need to be consistent with board design
  325 + */
  326 + ret = uclass_get_device_by_driver(UCLASS_PMIC,
  327 + DM_GET_DRIVER(stm32mp_pwr_pmic),
  328 + &pwr_dev);
  329 + if (!ret) {
  330 + ret = uclass_get_device_by_driver(UCLASS_MISC,
  331 + DM_GET_DRIVER(stm32mp_bsec),
  332 + &dev);
  333 + if (ret) {
  334 + pr_err("Can't find stm32mp_bsec driver\n");
  335 + return;
  336 + }
  337 +
  338 + ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4);
  339 + if (ret > 0)
  340 + otp = otp & BIT(13);
  341 +
  342 + /* get VDD = vdd-supply */
  343 + ret = device_get_supply_regulator(pwr_dev, "vdd-supply",
  344 + &pwr_reg);
  345 +
  346 + /* check if VDD is Low Voltage */
  347 + if (!ret) {
  348 + if (regulator_get_value(pwr_reg) < 2700000) {
  349 + writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
  350 + SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
  351 + SYSCFG_IOCTRLSETR_HSLVEN_ETH |
  352 + SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
  353 + SYSCFG_IOCTRLSETR_HSLVEN_SPI,
  354 + syscfg + SYSCFG_IOCTRLSETR);
  355 +
  356 + if (!otp)
  357 + pr_err("product_below_2v5=0: HSLVEN protected by HW\n");
  358 + } else {
  359 + if (otp)
  360 + pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
  361 + }
  362 + } else {
  363 + debug("VDD unknown");
  364 + }
  365 + }
  366 +#endif
  367 +
  368 + /* activate automatic I/O compensation
  369 + * warning: need to ensure CSI enabled and ready in clock driver
  370 + */
  371 + writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR);
  372 +
  373 + while (!(readl(syscfg + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY))
  374 + ;
  375 + clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
  376 +#endif
  377 +}
  378 +
  379 +/* board dependent setup after realloc */
  380 +int board_init(void)
  381 +{
  382 + struct udevice *dev;
  383 +
  384 + /* address of boot parameters */
  385 + gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
  386 +
  387 + /* probe all PINCTRL for hog */
  388 + for (uclass_first_device(UCLASS_PINCTRL, &dev);
  389 + dev;
  390 + uclass_next_device(&dev)) {
  391 + pr_debug("probe pincontrol = %s\n", dev->name);
  392 + }
  393 +
  394 + board_key_check();
  395 +
  396 +#ifdef CONFIG_DM_REGULATOR
  397 + regulators_enable_boot_on(_DEBUG);
  398 +#endif
  399 +
  400 + sysconf_init();
  401 +
  402 + if (CONFIG_IS_ENABLED(CONFIG_LED))
  403 + led_default_state();
  404 +
  405 + return 0;
  406 +}
  407 +
  408 +int board_late_init(void)
  409 +{
  410 + char *boot_device;
  411 +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  412 + const void *fdt_compat;
  413 + int fdt_compat_len;
  414 +
  415 + fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
  416 + &fdt_compat_len);
  417 + if (fdt_compat && fdt_compat_len) {
  418 + if (strncmp(fdt_compat, "st,", 3) != 0)
  419 + env_set("board_name", fdt_compat);
  420 + else
  421 + env_set("board_name", fdt_compat + 3);
  422 + }
  423 +#endif
  424 +
  425 + /* Check the boot-source to disable bootdelay */
  426 + boot_device = env_get("boot_device");
  427 + if (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb"))
  428 + env_set("bootdelay", "0");
  429 +
  430 + return 0;
  431 +}
  432 +
  433 +void board_quiesce_devices(void)
  434 +{
  435 +#ifdef CONFIG_LED
  436 + setup_led(LEDST_OFF);
  437 +#endif
  438 +}
  439 +
  440 +/* eth init function : weak called in eqos driver */
  441 +int board_interface_eth_init(struct udevice *dev,
  442 + phy_interface_t interface_type)
  443 +{
  444 + u8 *syscfg;
  445 + u32 value;
  446 + bool eth_clk_sel_reg = false;
  447 + bool eth_ref_clk_sel_reg = false;
  448 +
  449 + /* Gigabit Ethernet 125MHz clock selection. */
  450 + eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
  451 +
  452 + /* Ethernet 50Mhz RMII clock selection */
  453 + eth_ref_clk_sel_reg =
  454 + dev_read_bool(dev, "st,eth_ref_clk_sel");
  455 +
  456 + syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
  457 +
  458 + if (!syscfg)
  459 + return -ENODEV;
  460 +
  461 + switch (interface_type) {
  462 + case PHY_INTERFACE_MODE_MII:
  463 + value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
  464 + SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
  465 + debug("%s: PHY_INTERFACE_MODE_MII\n", __func__);
  466 + break;
  467 + case PHY_INTERFACE_MODE_GMII:
  468 + if (eth_clk_sel_reg)
  469 + value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
  470 + SYSCFG_PMCSETR_ETH_CLK_SEL;
  471 + else
  472 + value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
  473 + debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__);
  474 + break;
  475 + case PHY_INTERFACE_MODE_RMII:
  476 + if (eth_ref_clk_sel_reg)
  477 + value = SYSCFG_PMCSETR_ETH_SEL_RMII |
  478 + SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
  479 + else
  480 + value = SYSCFG_PMCSETR_ETH_SEL_RMII;
  481 + debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__);
  482 + break;
  483 + case PHY_INTERFACE_MODE_RGMII:
  484 + case PHY_INTERFACE_MODE_RGMII_ID:
  485 + case PHY_INTERFACE_MODE_RGMII_RXID:
  486 + case PHY_INTERFACE_MODE_RGMII_TXID:
  487 + if (eth_clk_sel_reg)
  488 + value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
  489 + SYSCFG_PMCSETR_ETH_CLK_SEL;
  490 + else
  491 + value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
  492 + debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__);
  493 + break;
  494 + default:
  495 + debug("%s: Do not manage %d interface\n",
  496 + __func__, interface_type);
  497 + /* Do not manage others interfaces */
  498 + return -EINVAL;
  499 + }
  500 +
  501 + /* clear and set ETH configuration bits */
  502 + writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
  503 + SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
  504 + syscfg + SYSCFG_PMCCLRR);
  505 + writel(value, syscfg + SYSCFG_PMCSETR);
  506 +
  507 + return 0;
  508 +}
  509 +
  510 +enum env_location env_get_location(enum env_operation op, int prio)
  511 +{
  512 + if (prio)
  513 + return ENVL_UNKNOWN;
  514 +
  515 +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
  516 + return ENVL_SPI_FLASH;
  517 +#else
  518 + return ENVL_NOWHERE;
  519 +#endif
  520 +}
  521 +
  522 +#ifdef CONFIG_SYS_MTDPARTS_RUNTIME
  523 +
  524 +#define MTDPARTS_LEN 256
  525 +#define MTDIDS_LEN 128
  526 +
  527 +/**
  528 + * The mtdparts_nand0 and mtdparts_nor0 variable tends to be long.
  529 + * If we need to access it before the env is relocated, then we need
  530 + * to use our own stack buffer. gd->env_buf will be too small.
  531 + *
  532 + * @param buf temporary buffer pointer MTDPARTS_LEN long
  533 + * @return mtdparts variable string, NULL if not found
  534 + */
  535 +static const char *env_get_mtdparts(const char *str, char *buf)
  536 +{
  537 + if (gd->flags & GD_FLG_ENV_READY)
  538 + return env_get(str);
  539 + if (env_get_f(str, buf, MTDPARTS_LEN) != -1)
  540 + return buf;
  541 +
  542 + return NULL;
  543 +}
  544 +
  545 +/**
  546 + * update the variables "mtdids" and "mtdparts" with content of mtdparts_<dev>
  547 + */
  548 +static void board_get_mtdparts(const char *dev,
  549 + char *mtdids,
  550 + char *mtdparts)
  551 +{
  552 + char env_name[32] = "mtdparts_";
  553 + char tmp_mtdparts[MTDPARTS_LEN];
  554 + const char *tmp;
  555 +
  556 + /* name of env variable to read = mtdparts_<dev> */
  557 + strcat(env_name, dev);
  558 + tmp = env_get_mtdparts(env_name, tmp_mtdparts);
  559 + if (tmp) {
  560 + /* mtdids: "<dev>=<dev>, ...." */
  561 + if (mtdids[0] != '\0')
  562 + strcat(mtdids, ",");
  563 + strcat(mtdids, dev);
  564 + strcat(mtdids, "=");
  565 + strcat(mtdids, dev);
  566 +
  567 + /* mtdparts: "mtdparts=<dev>:<mtdparts_<dev>>;..." */
  568 + if (mtdparts[0] != '\0')
  569 + strncat(mtdparts, ";", MTDPARTS_LEN);
  570 + else
  571 + strcat(mtdparts, "mtdparts=");
  572 + strncat(mtdparts, dev, MTDPARTS_LEN);
  573 + strncat(mtdparts, ":", MTDPARTS_LEN);
  574 + strncat(mtdparts, tmp, MTDPARTS_LEN);
  575 + }
  576 +}
  577 +
  578 +void board_mtdparts_default(const char **mtdids, const char **mtdparts)
  579 +{
  580 + struct udevice *dev;
  581 + static char parts[3 * MTDPARTS_LEN + 1];
  582 + static char ids[MTDIDS_LEN + 1];
  583 + static bool mtd_initialized;
  584 +
  585 + if (mtd_initialized) {
  586 + *mtdids = ids;
  587 + *mtdparts = parts;
  588 + return;
  589 + }
  590 +
  591 + memset(parts, 0, sizeof(parts));
  592 + memset(ids, 0, sizeof(ids));
  593 +
  594 + /* probe all MTD devices */
  595 + for (uclass_first_device(UCLASS_MTD, &dev);
  596 + dev;
  597 + uclass_next_device(&dev)) {
  598 + pr_debug("mtd device = %s\n", dev->name);
  599 + }
  600 +
  601 + if (!uclass_get_device(UCLASS_SPI_FLASH, 0, &dev))
  602 + board_get_mtdparts("nor0", ids, parts);
  603 +
  604 + mtd_initialized = true;
  605 + *mtdids = ids;
  606 + *mtdparts = parts;
  607 + debug("%s:mtdids=%s & mtdparts=%s\n", __func__, ids, parts);
  608 +}
  609 +#endif
  610 +
  611 +#if defined(CONFIG_OF_BOARD_SETUP)
  612 +int ft_board_setup(void *blob, bd_t *bd)
  613 +{
  614 + return 0;
  615 +}
  616 +#endif
  617 +
  618 +#ifdef CONFIG_SET_DFU_ALT_INFO
  619 +#define DFU_ALT_BUF_LEN SZ_1K
  620 +
  621 +static void board_get_alt_info(const char *dev, char *buff)
  622 +{
  623 + char var_name[32] = "dfu_alt_info_";
  624 + int ret;
  625 +
  626 + ALLOC_CACHE_ALIGN_BUFFER(char, tmp_alt, DFU_ALT_BUF_LEN);
  627 +
  628 + /* name of env variable to read = dfu_alt_info_<dev> */
  629 + strcat(var_name, dev);
  630 + ret = env_get_f(var_name, tmp_alt, DFU_ALT_BUF_LEN);
  631 + if (ret) {
  632 + if (buff[0] != '\0')
  633 + strcat(buff, "&");
  634 + strncat(buff, tmp_alt, DFU_ALT_BUF_LEN);
  635 + }
  636 +}
  637 +
  638 +void set_dfu_alt_info(char *interface, char *devstr)
  639 +{
  640 + struct udevice *dev;
  641 +
  642 + ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
  643 +
  644 + if (env_get("dfu_alt_info"))
  645 + return;
  646 +
  647 + memset(buf, 0, sizeof(buf));
  648 +
  649 + /* probe all MTD devices */
  650 + mtd_probe_devices();
  651 +
  652 + board_get_alt_info("ram", buf);
  653 +
  654 + if (!uclass_get_device(UCLASS_MMC, 0, &dev))
  655 + board_get_alt_info("mmc0", buf);
  656 +
  657 + if (!uclass_get_device(UCLASS_MMC, 1, &dev))
  658 + board_get_alt_info("mmc1", buf);
  659 +
  660 + if (!uclass_get_device(UCLASS_SPI_FLASH, 0, &dev))
  661 + board_get_alt_info("nor0", buf);
  662 +
  663 + env_set("dfu_alt_info", buf);
  664 + puts("DFU alt info setting: done\n");
  665 +}
  666 +#endif
  667 +
  668 +static void board_copro_image_process(ulong fw_image, size_t fw_size)
  669 +{
  670 + int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */
  671 +
  672 + if (!rproc_is_initialized())
  673 + if (rproc_init()) {
  674 + printf("Remote Processor %d initialization failed\n",
  675 + id);
  676 + return;
  677 + }
  678 +
  679 + ret = rproc_load(id, fw_image, fw_size);
  680 + printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
  681 + id, fw_image, fw_size, ret ? " Failed!" : " Success!");
  682 +
  683 + if (!ret) {
  684 + rproc_start(id);
  685 + env_set("copro_state", "booted");
  686 + }
  687 +}
  688 +
  689 +U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process);
board/st/stm32mp1/README
Diff comments   View file @ f2a73d6
... ... @@ -3,8 +3,8 @@
3 3 # Copyright (C) 2018 STMicroelectronics - All Rights Reserved
4 4 #
5 5  
6   -U-Boot on STMicroelectronics STM32MP1
7   -======================================
  6 +U-Boot on STMicroelectronics STM32MP15x
  7 +=======================================
8 8  
9 9 1. Summary
10 10 ==========
11 11  
12 12  
... ... @@ -12,12 +12,12 @@
12 12  
13 13 2. Supported devices
14 14 ====================
15   -U-Boot supports one STMP32MP1 SoCs: STM32MP157
  15 +U-Boot supports STMP32MP15x SoCs: STM32MP157, STM32MP153 and STM32MP151
16 16  
17   -The STM32MP157 is a Cortex-A MPU aimed at various applications.
  17 +The STM32MP15x is a Cortex-A MPU aimed at various applications.
18 18 It features:
19   -- Dual core Cortex-A7 application core
20   -- 2D/3D image composition with GPU
  19 +- Dual core Cortex-A7 application core (Single on STM32MP151)
  20 +- 2D/3D image composition with GPU (only on STM32MP157)
21 21 - Standard memories interface support
22 22 - Standard connectivity, widely inherited from the STM32 MCU family
23 23 - Comprehensive security support
... ... @@ -37,11 +37,11 @@
37 37 4. Fuse
38 38  
39 39 Currently the following boards are supported:
40   -+ stm32mp157c-ev1
41   -+ stm32mp157c-ed1
42   -+ stm32mp157a-dk1
43   -+ stm32mp157c-dk2
44   -+ stm32mp157a-avenger96
  40 ++ stm32mp157a-avenger96.dts
  41 ++ stm32mp157a-dk1.dts
  42 ++ stm32mp157c-dk2.dts
  43 ++ stm32mp157c-ed1.dts
  44 ++ stm32mp157c-ev1.dts
45 45  
46 46 3. Boot Sequences
47 47 =================
... ... @@ -74,7 +74,7 @@
74 74 U-Boot is running in secure mode and provide a secure monitor to the kernel
75 75 with only PSCI support (Power State Coordination Interface defined by ARM).
76 76  
77   -All the STM32MP1 boards supported by U-Boot use the same generic board
  77 +All the STM32MP15x boards supported by U-Boot use the same generic board
78 78 stm32mp1 which support all the bootable devices.
79 79  
80 80 Each board is configurated only with the associated device tree.
... ... @@ -108,7 +108,7 @@
108 108 + install package needed in U-Boot makefile
109 109 (libssl-dev, swig, libpython-dev...)
110 110 + install ARMv7 toolchain for 32bit Cortex-A (from Linaro,
111   - from SDK for STM32MP1, or any crosstoolchains from your distribution)
  111 + from SDK for STM32MP15x, or any crosstoolchains from your distribution)
112 112  
113 113 2. Set the cross compiler:
114 114  
... ... @@ -323,8 +323,7 @@
323 323 # ext4load mmc 0:4 0xC0000000 u-boot.img
324 324 # mmc dev 1
325 325 # part start mmc 1 1 partstart
326   - # part size mmc 1 1 partsize
327   - # mmc write ${fileaddr} ${partstart} ${partsize}
  326 + # mmc write ${fileaddr} ${partstart} ${filesize}
328 327  
329 328 To boot from eMMC, select BootPinMode = 0 1 0 and reset.
330 329  
331 330  
332 331  
... ... @@ -334,15 +333,28 @@
334 333 Please read doc/README.enetaddr for the implementation guidelines for mac id
335 334 usage. Basically, environment has precedence over board specific storage.
336 335  
337   -Mac id storage and retrieval in stm32mp otp :
  336 +For STMicroelectonics board, it is retrieved in STM32MP15x otp :
338 337 - OTP_57[31:0] = MAC_ADDR[31:0]
339 338 - OTP_58[15:0] = MAC_ADDR[47:32]
340 339  
341 340 To program a MAC address on virgin OTP words above, you can use the fuse command
342 341 on bank 0 to access to internal OTP:
343 342  
344   - example to set mac address "12:34:56:78:9a:bc"
  343 + Prerequisite: check if a MAC address isn't yet programmed in OTP
345 344  
  345 + 1- check OTP: their value must be equal to 0
  346 +
  347 + STM32MP> fuse sense 0 57 2
  348 + Sensing bank 0:
  349 + Word 0x00000039: 00000000 00000000
  350 +
  351 + 2- check environment variable
  352 +
  353 + STM32MP> env print ethaddr
  354 + ## Error: "ethaddr" not defined
  355 +
  356 + Example to set mac address "12:34:56:78:9a:bc"
  357 +
346 358 1- Write OTP
347 359 STM32MP> fuse prog -y 0 57 0x78563412 0x0000bc9a
348 360  
349 361  
... ... @@ -355,8 +367,12 @@
355 367 ### Setting environment from OTP MAC address = "12:34:56:78:9a:bc"
356 368  
357 369 4 check env update
358   - STM32MP> print ethaddr
  370 + STM32MP> env print ethaddr
359 371 ethaddr=12:34:56:78:9a:bc
  372 +
  373 +warning:: This MAC address provisioning can't be executed twice on the same
  374 + board as the OTP are protected. It is already done for the board
  375 + provided by STMicroelectronics.
360 376  
361 377 10. Coprocessor firmware
362 378 ========================
board/st/stm32mp1/stm32mp1.c
Diff comments   View file @ f2a73d6
... ... @@ -7,6 +7,7 @@
7 7 #include <bootm.h>
8 8 #include <clk.h>
9 9 #include <config.h>
  10 +#include <dfu.h>
10 11 #include <dm.h>
11 12 #include <env.h>
12 13 #include <env_internal.h>
... ... @@ -1011,7 +1012,7 @@
1011 1012 #include <dfu.h>
1012 1013 #include <power/stpmic1.h>
1013 1014  
1014   -int dfu_otp_read(u64 offset, u8 *buffer, long *size)
  1015 +static int dfu_otp_read(u64 offset, u8 *buffer, long *size)
1015 1016 {
1016 1017 struct udevice *dev;
1017 1018 int ret;
... ... @@ -1031,7 +1032,7 @@
1031 1032 return 0;
1032 1033 }
1033 1034  
1034   -int dfu_pmic_read(u64 offset, u8 *buffer, long *size)
  1035 +static int dfu_pmic_read(u64 offset, u8 *buffer, long *size)
1035 1036 {
1036 1037 int ret;
1037 1038 #ifdef CONFIG_PMIC_STPMIC1
configs/stm32mp15_dhcom_basic_defconfig
Diff comments   View file @ f2a73d6
  1 +CONFIG_ARM=y
  2 +CONFIG_ARCH_STM32MP=y
  3 +CONFIG_SYS_MALLOC_F_LEN=0x3000
  4 +CONFIG_ENV_SIZE=0x4000
  5 +CONFIG_SPL_MMC_SUPPORT=y
  6 +CONFIG_SPL=y
  7 +CONFIG_TARGET_DH_STM32MP1_PDK2=y
  8 +CONFIG_SPL_SPI_FLASH_SUPPORT=y
  9 +CONFIG_SPL_SPI_SUPPORT=y
  10 +# CONFIG_ARMV7_VIRT is not set
  11 +CONFIG_SPL_TEXT_BASE=0x2FFC2500
  12 +CONFIG_DISTRO_DEFAULTS=y
  13 +CONFIG_FIT=y
  14 +CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
  15 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
  16 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
  17 +CONFIG_SPL_I2C_SUPPORT=y
  18 +CONFIG_SPL_MTD_SUPPORT=y
  19 +CONFIG_SPL_POWER_SUPPORT=y
  20 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
  21 +CONFIG_SYS_PROMPT="STM32MP> "
  22 +# CONFIG_CMD_BOOTD is not set
  23 +# CONFIG_CMD_ELF is not set
  24 +# CONFIG_CMD_IMI is not set
  25 +# CONFIG_CMD_XIMG is not set
  26 +# CONFIG_CMD_EXPORTENV is not set
  27 +CONFIG_CMD_EEPROM=y
  28 +CONFIG_CMD_MEMINFO=y
  29 +CONFIG_CMD_MEMTEST=y
  30 +CONFIG_CMD_ADC=y
  31 +CONFIG_CMD_CLK=y
  32 +CONFIG_CMD_DFU=y
  33 +CONFIG_CMD_FUSE=y
  34 +CONFIG_CMD_GPIO=y
  35 +CONFIG_CMD_GPT=y
  36 +CONFIG_CMD_I2C=y
  37 +CONFIG_CMD_MMC=y
  38 +CONFIG_CMD_MTD=y
  39 +CONFIG_CMD_REMOTEPROC=y
  40 +CONFIG_CMD_SPI=y
  41 +CONFIG_CMD_USB=y
  42 +CONFIG_CMD_USB_MASS_STORAGE=y
  43 +CONFIG_CMD_BMP=y
  44 +CONFIG_CMD_CACHE=y
  45 +CONFIG_CMD_TIME=y
  46 +CONFIG_CMD_TIMER=y
  47 +CONFIG_CMD_PMIC=y
  48 +CONFIG_CMD_REGULATOR=y
  49 +CONFIG_CMD_EXT4_WRITE=y
  50 +CONFIG_CMD_MTDPARTS=y
  51 +# CONFIG_SPL_DOS_PARTITION is not set
  52 +CONFIG_DEFAULT_DEVICE_TREE="stm32mp15xx-dhcom-pdk2"
  53 +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
  54 +CONFIG_ENV_IS_IN_SPI_FLASH=y
  55 +CONFIG_USE_ENV_SPI_BUS=y
  56 +CONFIG_ENV_SPI_BUS=0
  57 +CONFIG_USE_ENV_SPI_CS=y
  58 +CONFIG_ENV_SPI_CS=0
  59 +CONFIG_USE_ENV_SPI_MAX_HZ=y
  60 +CONFIG_ENV_SPI_MAX_HZ=10000000
  61 +CONFIG_USE_ENV_SPI_MODE=y
  62 +CONFIG_ENV_SPI_MODE=0x0
  63 +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
  64 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
  65 +CONFIG_NET_RANDOM_ETHADDR=y
  66 +CONFIG_IP_DEFRAG=y
  67 +CONFIG_TFTP_BLOCKSIZE=1536
  68 +CONFIG_STM32_ADC=y
  69 +CONFIG_SPL_BLOCK_CACHE=y
  70 +CONFIG_DFU_MMC=y
  71 +CONFIG_DFU_RAM=y
  72 +CONFIG_DFU_VIRT=y
  73 +CONFIG_DM_HWSPINLOCK=y
  74 +CONFIG_HWSPINLOCK_STM32=y
  75 +CONFIG_DM_I2C=y
  76 +CONFIG_SYS_I2C_STM32F7=y
  77 +CONFIG_LED=y
  78 +CONFIG_LED_GPIO=y
  79 +CONFIG_DM_MAILBOX=y
  80 +CONFIG_STM32_IPCC=y
  81 +CONFIG_I2C_EEPROM=y
  82 +CONFIG_DM_MMC=y
  83 +CONFIG_SUPPORT_EMMC_BOOT=y
  84 +CONFIG_STM32_SDMMC2=y
  85 +CONFIG_MTD=y
  86 +CONFIG_DM_SPI_FLASH=y
  87 +CONFIG_SPI_FLASH_MACRONIX=y
  88 +CONFIG_SPI_FLASH_SPANSION=y
  89 +CONFIG_SPI_FLASH_STMICRO=y
  90 +CONFIG_SPI_FLASH_WINBOND=y
  91 +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  92 +CONFIG_SPI_FLASH_MTD=y
  93 +CONFIG_SPL_SPI_FLASH_MTD=y
  94 +CONFIG_DM_ETH=y
  95 +CONFIG_DWC_ETH_QOS=y
  96 +CONFIG_PHY=y
  97 +CONFIG_PHY_STM32_USBPHYC=y
  98 +CONFIG_PINCONF=y
  99 +# CONFIG_SPL_PINCTRL_FULL is not set
  100 +CONFIG_PINCTRL_STMFX=y
  101 +CONFIG_DM_PMIC=y
  102 +# CONFIG_SPL_PMIC_CHILDREN is not set
  103 +CONFIG_PMIC_STPMIC1=y
  104 +CONFIG_DM_REGULATOR_FIXED=y
  105 +CONFIG_DM_REGULATOR_GPIO=y
  106 +CONFIG_DM_REGULATOR_STM32_VREFBUF=y
  107 +CONFIG_DM_REGULATOR_STPMIC1=y
  108 +CONFIG_REMOTEPROC_STM32_COPRO=y
  109 +CONFIG_DM_RTC=y
  110 +CONFIG_RTC_STM32=y
  111 +CONFIG_SERIAL_RX_BUFFER=y
  112 +CONFIG_SPI=y
  113 +CONFIG_DM_SPI=y
  114 +CONFIG_STM32_QSPI=y
  115 +CONFIG_STM32_SPI=y
  116 +CONFIG_USB=y
  117 +CONFIG_DM_USB=y
  118 +CONFIG_DM_USB_GADGET=y
  119 +CONFIG_USB_EHCI_HCD=y
  120 +CONFIG_USB_EHCI_GENERIC=y
  121 +CONFIG_USB_GADGET=y
  122 +CONFIG_USB_GADGET_MANUFACTURER="dh"
  123 +CONFIG_USB_GADGET_VENDOR_NUM=0x0483
  124 +CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
  125 +CONFIG_USB_GADGET_DWC2_OTG=y
  126 +CONFIG_USB_GADGET_DOWNLOAD=y
  127 +CONFIG_USB_HOST_ETHER=y
  128 +CONFIG_USB_ETHER_ASIX=y
  129 +CONFIG_DM_VIDEO=y
  130 +CONFIG_BACKLIGHT_GPIO=y
  131 +CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
  132 +CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y
  133 +CONFIG_VIDEO_STM32=y
  134 +CONFIG_VIDEO_STM32_DSI=y
  135 +CONFIG_VIDEO_STM32_MAX_XRES=1280
  136 +CONFIG_VIDEO_STM32_MAX_YRES=800
  137 +CONFIG_LZO=y
  138 +CONFIG_FDT_FIXUP_PARTITIONS=y
doc/device-tree-bindings/clock/st,stm32mp1.txt
Diff comments   View file @ f2a73d6
... ... @@ -12,6 +12,9 @@
12 12 in Linux binding for compatible "st,stm32mp1-rcc" defined in st,stm32mp1-rcc.txt
13 13 file.
14 14  
  15 +This parent node may optionally have additional children nodes which define
  16 +specific init values for RCC elements.
  17 +
15 18 The added properties for clock tree initialization are:
16 19  
17 20 Required properties:
18 21  
19 22  
20 23  
... ... @@ -78,14 +81,17 @@
78 81 >;
79 82  
80 83 Optional Properties:
81   -- st,pll : A specific PLL configuration, including frequency.
  84 +- children for a PLL configuration with "st,stm32mp1-pll" compatible
82 85  
83   - PLL children nodes for PLL1 to PLL4 (see ref manual for details)
84   - are listed with associated index 0 to 3 (st,pll@0 to st,pll@3).
85   - PLLx is off when the associated node is absent.
  86 + each PLL children nodes for PLL1 to PLL4 (see ref manual for details)
  87 + are listed with associated reg 0 to 3.
  88 + PLLx is off when the associated node is absent or deactivated.
86 89  
87 90 Here are the available properties for each PLL node:
  91 + - compatible: should be "st,stm32mp1-pll"
88 92  
  93 + - reg: index of the pll instance
  94 +
89 95 - cfg: The parameters for PLL configuration in the following order:
90 96 DIVM DIVN DIVP DIVQ DIVR Output.
91 97  
92 98  
93 99  
94 100  
... ... @@ -118,18 +124,26 @@
118 124  
119 125 Example:
120 126 st,pll@0 {
  127 + compatible = "st,stm32mp1-pll";
  128 + reg = <0>;
121 129 cfg = < 1 53 0 0 0 1 >;
122 130 frac = < 0x810 >;
123 131 };
124 132 st,pll@1 {
  133 + compatible = "st,stm32mp1-pll";
  134 + reg = <1>;
125 135 cfg = < 1 43 1 0 0 PQR(0,1,1) >;
126 136 csg = < 10 20 1 >;
127 137 };
128 138 st,pll@2 {
  139 + compatible = "st,stm32mp1-pll";
  140 + reg = <2>;
129 141 cfg = < 2 85 3 13 3 0 >;
130 142 csg = < 10 20 SSCG_MODE_CENTER_SPREAD >;
131 143 };
132 144 st,pll@3 {
  145 + compatible = "st,stm32mp1-pll";
  146 + reg = <3>;
133 147 cfg = < 2 78 4 7 9 3 >;
134 148 };
135 149  
... ... @@ -277,6 +291,8 @@
277 291 u-boot,dm-pre-reloc;
278 292 compatible = "st,stm32mp1-rcc", "syscon";
279 293 reg = <0x50000000 0x1000>;
  294 + #address-cells = <1>;
  295 + #size-cells = <0>;
280 296 #clock-cells = <1>;
281 297 #reset-cells = <1>;
282 298 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
... ... @@ -347,6 +363,8 @@
347 363  
348 364 /* VCO = 1300.0 MHz => P = 650 (CPU) */
349 365 pll1: st,pll@0 {
  366 + compatible = "st,stm32mp1-pll";
  367 + reg = <0>;
350 368 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
351 369 frac = < 0x800 >;
352 370 u-boot,dm-pre-reloc;
... ... @@ -355,6 +373,8 @@
355 373 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU),
356 374 R = 533 (DDR) */
357 375 pll2: st,pll@1 {
  376 + compatible = "st,stm32mp1-pll";
  377 + reg = <1>;
358 378 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
359 379 frac = < 0x1400 >;
360 380 u-boot,dm-pre-reloc;
... ... @@ -362,6 +382,8 @@
362 382  
363 383 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
364 384 pll3: st,pll@2 {
  385 + compatible = "st,stm32mp1-pll";
  386 + reg = <2>;
365 387 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
366 388 frac = < 0x1a04 >;
367 389 u-boot,dm-pre-reloc;
... ... @@ -369,6 +391,8 @@
369 391  
370 392 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
371 393 pll4: st,pll@3 {
  394 + compatible = "st,stm32mp1-pll";
  395 + reg = <3>;
372 396 cfg = < 3 98 5 7 7 PQR(1,1,1) >;
373 397 u-boot,dm-pre-reloc;
374 398 };
doc/device-tree-bindings/mtd/stm32-fmc2-nand.txt
Diff comments   View file @ f2a73d6
... ... @@ -18,8 +18,10 @@
18 18 - dmas: DMA specifiers (see: dma/stm32-mdma.txt)
19 19 - dma-names: Must be "tx", "rx" and "ecc"
20 20  
21   -Optional children nodes:
22   -Children nodes represent the available NAND chips.
  21 +* NAND device bindings:
  22 +
  23 +Required properties:
  24 +- reg: describes the CS lines assigned to the NAND device.
23 25  
24 26 Optional properties:
25 27 - nand-on-flash-bbt: see nand.txt
drivers/clk/clk_stm32mp1.c
Diff comments   View file @ f2a73d6
... ... @@ -1218,7 +1218,7 @@
1218 1218 }
1219 1219  
1220 1220 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
1221   - int lsedrv)
  1221 + u32 lsedrv)
1222 1222 {
1223 1223 u32 value;
1224 1224  
... ... @@ -1651,8 +1651,8 @@
1651 1651 unsigned int clkdiv[CLKDIV_NB];
1652 1652 unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1653 1653 ofnode plloff[_PLL_NB];
1654   - int ret;
1655   - int i, len;
  1654 + int ret, len;
  1655 + uint i;
1656 1656 int lse_css = 0;
1657 1657 const u32 *pkcs_cell;
1658 1658  
... ... @@ -1698,7 +1698,8 @@
1698 1698 stm32mp1_lsi_set(rcc, 1);
1699 1699  
1700 1700 if (priv->osc[_LSE]) {
1701   - int bypass, digbyp, lsedrv;
  1701 + int bypass, digbyp;
  1702 + u32 lsedrv;
1702 1703 struct udevice *dev = priv->osc_dev[_LSE];
1703 1704  
1704 1705 bypass = dev_read_bool(dev, "st,bypass");
drivers/pinctrl/pinctrl-stmfx.c
Diff comments   View file @ f2a73d6
... ... @@ -352,11 +352,12 @@
352 352 int ret;
353 353 struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
354 354  
355   - id = dm_i2c_reg_read(dev, STMFX_REG_CHIP_ID);
356   - if (id < 0) {
357   - dev_err(dev, "error reading chip id: %d\n", id);
  355 + ret = dm_i2c_reg_read(dev, STMFX_REG_CHIP_ID);
  356 + if (ret < 0) {
  357 + dev_err(dev, "error reading chip id: %d\n", ret);
358 358 return ret;
359 359 }
  360 + id = (u8)ret;
360 361 /*
361 362 * Check that ID is the complement of the I2C address:
362 363 * STMFX I2C address follows the 7-bit format (MSB), that's why
include/configs/stih410-b2260.h
Diff comments   View file @ f2a73d6
... ... @@ -19,6 +19,12 @@
19 19  
20 20 /* Environment */
21 21  
  22 +/*
  23 + * For booting Linux, use the first 256 MB of memory, since this is
  24 + * the maximum mapped by the Linux kernel during initialization.
  25 + */
  26 +#define CONFIG_SYS_BOOTMAPSZ SZ_256M
  27 +
22 28 #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
23 29 #define CONFIG_SYS_BOOTM_LEN SZ_16M
24 30  
... ... @@ -34,8 +40,6 @@
34 40 "fdt_addr_r=0x47000000\0" \
35 41 "scriptaddr=0x50000000\0" \
36 42 "pxefile_addr_r=0x50100000\0" \
37   - "fdt_high=0xffffffffffffffff\0" \
38   - "initrd_high=0xffffffffffffffff\0" \
39 43 "ramdisk_addr_r=0x48000000\0" \
40 44 BOOTENV
41 45  
include/configs/stm32f429-evaluation.h
Diff comments   View file @ f2a73d6
... ... @@ -7,6 +7,11 @@
7 7 #ifndef __CONFIG_H
8 8 #define __CONFIG_H
9 9  
  10 +#include <linux/sizes.h>
  11 +
  12 +/* For booting Linux, use the first 16MB of memory */
  13 +#define CONFIG_SYS_BOOTMAPSZ SZ_16M
  14 +
10 15 #define CONFIG_SYS_FLASH_BASE 0x08000000
11 16  
12 17 #define CONFIG_SYS_INIT_SP_ADDR 0x10010000
... ... @@ -40,12 +45,10 @@
40 45 #define CONFIG_EXTRA_ENV_SETTINGS \
41 46 "kernel_addr_r=0x00008000\0" \
42 47 "fdtfile=stm32429i-eval.dtb\0" \
43   - "fdt_addr_r=0x00700000\0" \
44   - "scriptaddr=0x00800000\0" \
45   - "pxefile_addr_r=0x00800000\0" \
46   - "fdt_high=0xffffffffffffffff\0" \
47   - "initrd_high=0xffffffffffffffff\0" \
48   - "ramdisk_addr_r=0x00900000\0" \
  48 + "fdt_addr_r=0x00408000\0" \
  49 + "scriptaddr=0x00418000\0" \
  50 + "pxefile_addr_r=0x00428000\0" \
  51 + "ramdisk_addr_r=0x00438000\0" \
49 52 BOOTENV
50 53  
51 54 /*
include/configs/stm32f469-discovery.h
Diff comments   View file @ f2a73d6
... ... @@ -7,6 +7,11 @@
7 7 #ifndef __CONFIG_H
8 8 #define __CONFIG_H
9 9  
  10 +#include <linux/sizes.h>
  11 +
  12 +/* For booting Linux, use the first 12MB of memory */
  13 +#define CONFIG_SYS_BOOTMAPSZ SZ_8M + SZ_4M
  14 +
10 15 #define CONFIG_SYS_FLASH_BASE 0x08000000
11 16  
12 17 #define CONFIG_SYS_INIT_SP_ADDR 0x10010000
... ... @@ -40,12 +45,10 @@
40 45 #define CONFIG_EXTRA_ENV_SETTINGS \
41 46 "kernel_addr_r=0x00008000\0" \
42 47 "fdtfile=stm32f469-disco.dtb\0" \
43   - "fdt_addr_r=0x00700000\0" \
44   - "scriptaddr=0x00800000\0" \
45   - "pxefile_addr_r=0x00800000\0" \
46   - "fdt_high=0xffffffffffffffff\0" \
47   - "initrd_high=0xffffffffffffffff\0" \
48   - "ramdisk_addr_r=0x00900000\0" \
  48 + "fdt_addr_r=0x00408000\0" \
  49 + "scriptaddr=0x00418000\0" \
  50 + "pxefile_addr_r=0x00428000\0" \
  51 + "ramdisk_addr_r=0x00438000\0" \
49 52 BOOTENV
50 53  
51 54 /*
include/configs/stm32f746-disco.h
Diff comments   View file @ f2a73d6
... ... @@ -7,6 +7,11 @@
7 7 #ifndef __CONFIG_H
8 8 #define __CONFIG_H
9 9  
  10 +#include <linux/sizes.h>
  11 +
  12 +/* For booting Linux, use the first 6MB of memory */
  13 +#define CONFIG_SYS_BOOTMAPSZ SZ_4M + SZ_2M
  14 +
10 15 #define CONFIG_SYS_FLASH_BASE 0x08000000
11 16 #define CONFIG_SYS_INIT_SP_ADDR 0x20050000
12 17  
... ... @@ -48,12 +53,10 @@
48 53 #define CONFIG_EXTRA_ENV_SETTINGS \
49 54 "kernel_addr_r=0xC0008000\0" \
50 55 "fdtfile=stm32f746-disco.dtb\0" \
51   - "fdt_addr_r=0xC0500000\0" \
52   - "scriptaddr=0xC0008000\0" \
53   - "pxefile_addr_r=0xC0008000\0" \
54   - "fdt_high=0xffffffffffffffff\0" \
55   - "initrd_high=0xffffffffffffffff\0" \
56   - "ramdisk_addr_r=0xC0600000\0" \
  56 + "fdt_addr_r=0xC0408000\0" \
  57 + "scriptaddr=0xC0418000\0" \
  58 + "pxefile_addr_r=0xC0428000\0" \
  59 + "ramdisk_addr_r=0xC0438000\0" \
57 60 BOOTENV
58 61  
59 62 /*
include/configs/stm32h743-disco.h
Diff comments   View file @ f2a73d6
... ... @@ -8,7 +8,11 @@
8 8 #define __CONFIG_H
9 9  
10 10 #include <config.h>
  11 +#include <linux/sizes.h>
11 12  
  13 +/* For booting Linux, use the first 16MB of memory */
  14 +#define CONFIG_SYS_BOOTMAPSZ SZ_16M
  15 +
12 16 #define CONFIG_SYS_FLASH_BASE 0x08000000
13 17 #define CONFIG_SYS_INIT_SP_ADDR 0x24040000
14 18  
... ... @@ -35,12 +39,10 @@
35 39 #define CONFIG_EXTRA_ENV_SETTINGS \
36 40 "kernel_addr_r=0xD0008000\0" \
37 41 "fdtfile=stm32h743i-disco.dtb\0" \
38   - "fdt_addr_r=0xD0700000\0" \
39   - "scriptaddr=0xD0800000\0" \
40   - "pxefile_addr_r=0xD0800000\0" \
41   - "fdt_high=0xffffffffffffffff\0" \
42   - "initrd_high=0xffffffffffffffff\0" \
43   - "ramdisk_addr_r=0xD0900000\0" \
  42 + "fdt_addr_r=0xD0408000\0" \
  43 + "scriptaddr=0xD0418000\0" \
  44 + "pxefile_addr_r=0xD0428000\0" \
  45 + "ramdisk_addr_r=0xD0438000\0" \
44 46 BOOTENV
45 47  
46 48 /*
include/configs/stm32h743-eval.h
Diff comments   View file @ f2a73d6
... ... @@ -8,7 +8,11 @@
8 8 #define __CONFIG_H
9 9  
10 10 #include <config.h>
  11 +#include <linux/sizes.h>
11 12  
  13 +/* For booting Linux, use the first 16MB of memory */
  14 +#define CONFIG_SYS_BOOTMAPSZ SZ_16M
  15 +
12 16 #define CONFIG_SYS_FLASH_BASE 0x08000000
13 17 #define CONFIG_SYS_INIT_SP_ADDR 0x24040000
14 18  
... ... @@ -35,12 +39,10 @@
35 39 #define CONFIG_EXTRA_ENV_SETTINGS \
36 40 "kernel_addr_r=0xD0008000\0" \
37 41 "fdtfile=stm32h743i-eval.dtb\0" \
38   - "fdt_addr_r=0xD0700000\0" \
39   - "scriptaddr=0xD0800000\0" \
40   - "pxefile_addr_r=0xD0800000\0" \
41   - "fdt_high=0xffffffffffffffff\0" \
42   - "initrd_high=0xffffffffffffffff\0" \
43   - "ramdisk_addr_r=0xD0900000\0" \
  42 + "fdt_addr_r=0xD0408000\0" \
  43 + "scriptaddr=0xD0418000\0" \
  44 + "pxefile_addr_r=0xD0428000\0" \
  45 + "ramdisk_addr_r=0xD0438000\0" \
44 46 BOOTENV
45 47  
46 48 /*
include/configs/stm32mp1.h
Diff comments   View file @ f2a73d6
... ... @@ -43,8 +43,14 @@
43 43 #define CONFIG_SETUP_MEMORY_TAGS
44 44 #define CONFIG_INITRD_TAG
45 45  
  46 +/*
  47 + * For booting Linux, use the first 256 MB of memory, since this is
  48 + * the maximum mapped by the Linux kernel during initialization.
  49 + */
  50 +#define CONFIG_SYS_BOOTMAPSZ SZ_256M
  51 +
46 52 /* Extend size of kernel image for uncompression */
47   -#define CONFIG_SYS_BOOTM_LEN SZ_32M
  53 +#define CONFIG_SYS_BOOTM_LEN SZ_32M
48 54  
49 55 /* SPL support */
50 56 #ifdef CONFIG_SPL
... ... @@ -215,8 +221,6 @@
215 221 "pxefile_addr_r=0xc4200000\0" \
216 222 "splashimage=0xc4300000\0" \
217 223 "ramdisk_addr_r=0xc4400000\0" \
218   - "fdt_high=0xffffffff\0" \
219   - "initrd_high=0xffffffff\0" \
220 224 "altbootcmd=run bootcmd\0" \
221 225 "env_default=1\0" \
222 226 "env_check=if test $env_default -eq 1;"\
... ... @@ -45,7 +45,7 @@
45 45 ptr->magic_number = HEADER_MAGIC;
46 46 ptr->header_version[VER_MAJOR_IDX] = HEADER_VERSION_V1;
47 47 ptr->option_flags = HEADER_DEFAULT_OPTION;
48   - ptr->ecdsa_algorithm = 1;
  48 + ptr->ecdsa_algorithm = cpu_to_le32(1);
49 49 ptr->binary_type = HEADER_TYPE_UBOOT;
50 50 }
51 51  
... ... @@ -131,7 +131,8 @@
131 131 stm32hdr->image_entry_point = cpu_to_le32(params->ep);
132 132 stm32hdr->image_length = cpu_to_le32((uint32_t)sbuf->st_size -
133 133 sizeof(struct stm32_header));
134   - stm32hdr->image_checksum = stm32image_checksum(ptr, sbuf->st_size);
  134 + stm32hdr->image_checksum =
  135 + cpu_to_le32(stm32image_checksum(ptr, sbuf->st_size));
135 136 }
136 137  
137 138 /*