Eric Lee / smarc-uboot

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Commit f2cc8be7b561567cbb9e3096ffb9a5c433804b4c

Authored by Han Xu
Committed by Ye Li
1 parent 29c20316ab
Exists in smarc_8mq-imx_v2020.04_5.4.24_2.1.0 and in 3 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, smarc-8m-android-10.0.0_2.6.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0

MLK-23691-4: imx8dxl: add nand pad settings and init code in imx8dxl board file 

add nand pad settings and init code in imx8dxl board file.

Signed-off-by: Han Xu <han.xu@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit fdb39fffc55c2ff02fe00a94b3f0208fae75d6df)

Showing 1 changed file with 50 additions and 0 deletions Side-by-side Diff

board/freescale/imx8dxl_evk/imx8dxl_evk.c
Diff comments   View file @ f2cc8be
... ... @@ -29,6 +29,9 @@
29 29 #define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
30 30 | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
31 31  
  32 +#define GPMI_NAND_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) \
  33 + | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  34 +
32 35 #define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
33 36 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
34 37 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
... ... @@ -49,6 +52,48 @@
49 52 imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
50 53 }
51 54  
  55 +#ifdef CONFIG_SPL_BUILD
  56 +#ifdef CONFIG_NAND_MXS
  57 +static iomux_cfg_t gpmi_nand_pads[] = {
  58 + SC_P_EMMC0_DATA0 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  59 + SC_P_EMMC0_DATA1 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  60 + SC_P_EMMC0_DATA2 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  61 + SC_P_EMMC0_DATA3 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  62 + SC_P_EMMC0_DATA4 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  63 + SC_P_EMMC0_DATA5 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  64 + SC_P_EMMC0_DATA6 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  65 + SC_P_EMMC0_DATA7 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  66 + SC_P_EMMC0_STROBE | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  67 + SC_P_EMMC0_RESET_B | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  68 + SC_P_EMMC0_CLK | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  69 + SC_P_EMMC0_CMD | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  70 +
  71 + SC_P_USDHC1_RESET_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  72 + SC_P_USDHC1_WP | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  73 + SC_P_USDHC1_VSELECT | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  74 +
  75 +};
  76 +
  77 +static void setup_iomux_gpmi_nand(void)
  78 +{
  79 + imx8_iomux_setup_multiple_pads(gpmi_nand_pads, ARRAY_SIZE(gpmi_nand_pads));
  80 +}
  81 +
  82 +static void imx8dxl_gpmi_nand_initialize(void)
  83 +{
  84 + int ret;
  85 +
  86 + ret = sc_pm_set_resource_power_mode(-1, SC_R_NAND, SC_PM_PW_MODE_ON);
  87 + if (ret != SC_ERR_NONE)
  88 + return;
  89 +
  90 + init_clk_gpmi_nand();
  91 + setup_iomux_gpmi_nand();
  92 +}
  93 +#endif
  94 +#endif
  95 +
  96 +
52 97 int board_early_init_f(void)
53 98 {
54 99 sc_pm_clock_rate_t rate = SC_80MHZ;
... ... @@ -61,6 +106,11 @@
61 106  
62 107 setup_iomux_uart();
63 108  
  109 +#ifdef CONFIG_SPL_BUILD
  110 +#ifdef CONFIG_NAND_MXS
  111 + imx8dxl_gpmi_nand_initialize();
  112 +#endif
  113 +#endif
64 114 return 0;
65 115 }
66 116