Commit f2cff6b104f82b993bef6086ce0c97159bbe1add
Committed by
Andrew Fleming-AFLEMING
Andrew Fleming-AFLEMING
1 parent
837f1ba05c
Exists in
master
and in
55 other branches
8548cds PCIE support.
Make the early L1 cache stack region guarded to prevent speculative fetches outside the locked range. Use _PHYS defines, not _MEM for cpu-side PCI memory mapped regions. init.S whitespace cleanup. Allow TEXT_BASE value to be specified on command line. This allows it to be set to 0xfffc0000 which cuts the uboot binary in half. Clear and enable lbc and ecm errors. Update last_busno in device-tree for pci and pcie. Remove load of obsolete cpu/mpc85xx/pci.0 Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
Showing 5 changed files with 522 additions and 221 deletions Side-by-side Diff
board/cds/mpc8548cds/config.mk
| 1 | 1 | # |
| 2 | -# Copyright 2004 Freescale Semiconductor. | |
| 2 | +# Copyright 2004, 2007 Freescale Semiconductor. | |
| 3 | 3 | # |
| 4 | 4 | # See file CREDITS for list of people who contributed to this |
| 5 | 5 | # project. |
| 6 | 6 | |
| ... | ... | @@ -23,7 +23,9 @@ |
| 23 | 23 | # |
| 24 | 24 | # mpc8548cds board |
| 25 | 25 | # |
| 26 | +ifndef TEXT_BASE | |
| 26 | 27 | TEXT_BASE = 0xfff80000 |
| 28 | +endif | |
| 27 | 29 | |
| 28 | 30 | PLATFORM_CPPFLAGS += -DCONFIG_E500=1 |
| 29 | 31 | PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 |
board/cds/mpc8548cds/init.S
| 1 | 1 | /* |
| 2 | - * Copyright 2004 Freescale Semiconductor. | |
| 2 | + * Copyright 2004, 2007 Freescale Semiconductor. | |
| 3 | 3 | * Copyright 2002,2003, Motorola Inc. |
| 4 | 4 | * |
| 5 | 5 | * See file CREDITS for list of people who contributed to this |
| ... | ... | @@ -28,6 +28,12 @@ |
| 28 | 28 | #include <config.h> |
| 29 | 29 | #include <mpc85xx.h> |
| 30 | 30 | |
| 31 | +#define LAWAR_TRGT_PCI1 0x00000000 | |
| 32 | +#define LAWAR_TRGT_PCI2 0x00100000 | |
| 33 | +#define LAWAR_TRGT_PCIE 0x00200000 | |
| 34 | +#define LAWAR_TRGT_RIO 0x00c00000 | |
| 35 | +#define LAWAR_TRGT_LBC 0x00400000 | |
| 36 | +#define LAWAR_TRGT_DDR 0x00f00000 | |
| 31 | 37 | |
| 32 | 38 | /* |
| 33 | 39 | * TLB0 and TLB1 Entries |
| ... | ... | @@ -47,8 +53,8 @@ |
| 47 | 53 | */ |
| 48 | 54 | |
| 49 | 55 | #define entry_start \ |
| 50 | - mflr r1 ; \ | |
| 51 | - bl 0f ; | |
| 56 | + mflr r1 ; \ | |
| 57 | + bl 0f ; | |
| 52 | 58 | |
| 53 | 59 | #define entry_end \ |
| 54 | 60 | 0: mflr r0 ; \ |
| ... | ... | @@ -84,8 +90,8 @@ |
| 84 | 90 | #endif |
| 85 | 91 | |
| 86 | 92 | /* |
| 87 | - * TLB0 16K Cacheable, non-guarded | |
| 88 | - * 0xd001_0000 16K Temporary Global data for initialization | |
| 93 | + * TLB0 16K Cacheable, guarded | |
| 94 | + * Temporary Global data for initialization | |
| 89 | 95 | * |
| 90 | 96 | * Use four 4K TLB0 entries. These entries must be cacheable |
| 91 | 97 | * as they provide the bootstrap memory before the memory |
| 92 | 98 | |
| 93 | 99 | |
| 94 | 100 | |
| ... | ... | @@ -97,28 +103,28 @@ |
| 97 | 103 | .long TLB1_MAS0(0, 0, 0) |
| 98 | 104 | .long TLB1_MAS1(1, 0, 0, 0, 0) |
| 99 | 105 | .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), |
| 100 | - 0,0,0,0,0,0,0,0) | |
| 106 | + 0,0,0,0,0,0,1,0) | |
| 101 | 107 | .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), |
| 102 | 108 | 0,0,0,0,0,1,0,1,0,1) |
| 103 | 109 | |
| 104 | 110 | .long TLB1_MAS0(0, 0, 0) |
| 105 | 111 | .long TLB1_MAS1(1, 0, 0, 0, 0) |
| 106 | 112 | .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), |
| 107 | - 0,0,0,0,0,0,0,0) | |
| 113 | + 0,0,0,0,0,0,1,0) | |
| 108 | 114 | .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), |
| 109 | 115 | 0,0,0,0,0,1,0,1,0,1) |
| 110 | 116 | |
| 111 | 117 | .long TLB1_MAS0(0, 0, 0) |
| 112 | 118 | .long TLB1_MAS1(1, 0, 0, 0, 0) |
| 113 | 119 | .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), |
| 114 | - 0,0,0,0,0,0,0,0) | |
| 120 | + 0,0,0,0,0,0,1,0) | |
| 115 | 121 | .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), |
| 116 | 122 | 0,0,0,0,0,1,0,1,0,1) |
| 117 | 123 | |
| 118 | 124 | .long TLB1_MAS0(0, 0, 0) |
| 119 | 125 | .long TLB1_MAS1(1, 0, 0, 0, 0) |
| 120 | 126 | .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), |
| 121 | - 0,0,0,0,0,0,0,0) | |
| 127 | + 0,0,0,0,0,0,1,0) | |
| 122 | 128 | .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), |
| 123 | 129 | 0,0,0,0,0,1,0,1,0,1) |
| 124 | 130 | |
| 125 | 131 | |
| 126 | 132 | |
| 127 | 133 | |
| 128 | 134 | |
| 129 | 135 | |
| 130 | 136 | |
| 131 | 137 | |
| 132 | 138 | |
| 133 | 139 | |
| 134 | 140 | |
| ... | ... | @@ -130,51 +136,44 @@ |
| 130 | 136 | */ |
| 131 | 137 | .long TLB1_MAS0(1, 0, 0) |
| 132 | 138 | .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) |
| 133 | - .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) | |
| 134 | - .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) | |
| 139 | + .long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0) | |
| 140 | + .long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1) | |
| 135 | 141 | |
| 136 | 142 | /* |
| 137 | - * TLB 1: 256M Non-cacheable, guarded | |
| 138 | - * 0x80000000 256M PCI1 MEM | |
| 143 | + * TLB 1: 1G Non-cacheable, guarded | |
| 144 | + * 0x80000000 1G PCI1/PCIE 8,9,a,b | |
| 139 | 145 | */ |
| 140 | 146 | .long TLB1_MAS0(1, 1, 0) |
| 141 | - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) | |
| 142 | - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) | |
| 143 | - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) | |
| 147 | + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G) | |
| 148 | + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS), 0,0,0,0,1,0,1,0) | |
| 149 | + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS), 0,0,0,0,0,1,0,1,0,1) | |
| 144 | 150 | |
| 151 | +#ifdef CFG_RIO_MEM_PHYS | |
| 145 | 152 | /* |
| 146 | 153 | * TLB 2: 256M Non-cacheable, guarded |
| 147 | - * 0x90000000 256M PCI2 MEM | |
| 148 | 154 | */ |
| 149 | 155 | .long TLB1_MAS0(1, 2, 0) |
| 150 | 156 | .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
| 151 | - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), | |
| 157 | + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS), | |
| 152 | 158 | 0,0,0,0,1,0,1,0) |
| 153 | - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), | |
| 154 | - 0,0,0,0,0,1,0,1,0,1) | |
| 159 | + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS), 0,0,0,0,0,1,0,1,0,1) | |
| 155 | 160 | |
| 156 | 161 | /* |
| 157 | - * TLB 3: 1GB Non-cacheable, guarded | |
| 158 | - * 0xa0000000 256M PEX MEM First half | |
| 159 | - * 0xb0000000 256M PEX MEM Second half | |
| 160 | - * 0xc0000000 256M Rapid IO MEM First half | |
| 161 | - * 0xd0000000 256M Rapid IO MEM Second half | |
| 162 | + * TLB 3: 256M Non-cacheable, guarded | |
| 162 | 163 | */ |
| 163 | 164 | .long TLB1_MAS0(1, 3, 0) |
| 164 | - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G) | |
| 165 | - .long TLB1_MAS2(E500_TLB_EPN(CFG_PEX_MEM_BASE), 0,0,0,0,1,0,1,0) | |
| 166 | - .long TLB1_MAS3(E500_TLB_RPN(CFG_PEX_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) | |
| 167 | - | |
| 165 | + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) | |
| 166 | + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS + 0x10000000), | |
| 167 | + 0,0,0,0,1,0,1,0) | |
| 168 | + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS + 0x10000000), | |
| 169 | + 0,0,0,0,0,1,0,1,0,1) | |
| 170 | +#endif | |
| 168 | 171 | /* |
| 169 | - * TLB 4: Reserved for future usage | |
| 170 | - */ | |
| 171 | - | |
| 172 | - /* | |
| 173 | 172 | * TLB 5: 64M Non-cacheable, guarded |
| 174 | 173 | * 0xe000_0000 1M CCSRBAR |
| 175 | - * 0xe200_0000 8M PCI1 IO | |
| 176 | - * 0xe280_0000 8M PCI2 IO | |
| 177 | - * 0xe300_0000 16M PEX IO | |
| 174 | + * 0xe200_0000 1M PCI1 IO | |
| 175 | + * 0xe210_0000 1M PCI2 IO | |
| 176 | + * 0xe300_0000 1M PCIe IO | |
| 178 | 177 | */ |
| 179 | 178 | .long TLB1_MAS0(1, 5, 0) |
| 180 | 179 | .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
| 181 | 180 | |
| 182 | 181 | |
| ... | ... | @@ -187,17 +186,18 @@ |
| 187 | 186 | */ |
| 188 | 187 | .long TLB1_MAS0(1, 6, 0) |
| 189 | 188 | .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
| 190 | - .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) | |
| 191 | - .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) | |
| 189 | + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,0,0,0) | |
| 190 | + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,1,0,1,0,1) | |
| 192 | 191 | |
| 193 | 192 | /* |
| 194 | - * TLB 7: 1M Non-cacheable, guarded | |
| 195 | - * 0xf8000000 1M CADMUS registers | |
| 193 | + * TLB 7: 64M Non-cacheable, guarded | |
| 194 | + * 0xf8000000 64M CADMUS registers, relocated L2SRAM | |
| 196 | 195 | */ |
| 197 | 196 | .long TLB1_MAS0(1, 7, 0) |
| 198 | - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M) | |
| 199 | - .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0) | |
| 200 | - .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1) | |
| 197 | + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) | |
| 198 | + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,1,0,1,0) | |
| 199 | + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,0,1,0,1,0,1) | |
| 200 | + | |
| 201 | 201 | 2: |
| 202 | 202 | entry_end |
| 203 | 203 | |
| 204 | 204 | |
| ... | ... | @@ -205,14 +205,13 @@ |
| 205 | 205 | * LAW(Local Access Window) configuration: |
| 206 | 206 | * |
| 207 | 207 | * 0x0000_0000 0x7fff_ffff DDR 2G |
| 208 | - * 0x8000_0000 0x8fff_ffff PCI1 MEM 256M | |
| 209 | - * 0x9000_0000 0x9fff_ffff PCI2 MEM 256M | |
| 210 | - * 0xa000_0000 0xbfff_ffff PEX MEM 512M | |
| 208 | + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M | |
| 209 | + * 0xa000_0000 0xbfff_ffff PCIe MEM 512M | |
| 211 | 210 | * 0xc000_0000 0xdfff_ffff RapidIO 512M |
| 212 | 211 | * 0xe000_0000 0xe000_ffff CCSR 1M |
| 213 | - * 0xe200_0000 0xe27f_ffff PCI1 IO 8M | |
| 214 | - * 0xe280_0000 0xe2ff_ffff PCI2 IO 8M | |
| 215 | - * 0xe300_0000 0xe3ff_ffff PEX IO 16M | |
| 212 | + * 0xe200_0000 0xe10f_ffff PCI1 IO 1M | |
| 213 | + * 0xe280_0000 0xe20f_ffff PCI2 IO 1M | |
| 214 | + * 0xe300_0000 0xe30f_ffff PCIe IO 1M | |
| 216 | 215 | * 0xf000_0000 0xf3ff_ffff SDRAM 64M |
| 217 | 216 | * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M |
| 218 | 217 | * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M |
| 219 | 218 | |
| 220 | 219 | |
| 221 | 220 | |
| 222 | 221 | |
| 223 | 222 | |
| 224 | 223 | |
| 225 | 224 | |
| 226 | 225 | |
| 227 | 226 | |
| 228 | 227 | |
| ... | ... | @@ -222,48 +221,51 @@ |
| 222 | 221 | * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
| 223 | 222 | * If flash is 8M at default position (last 8M), no LAW needed. |
| 224 | 223 | * |
| 225 | - * The defines below are 1-off of the actual LAWAR0 usage. | |
| 226 | - * So LAWAR3 define uses the LAWAR4 register in the ECM. | |
| 224 | + * LAW 0 is reserved for boot mapping | |
| 227 | 225 | */ |
| 228 | 226 | |
| 229 | -#define LAWBAR0 0 | |
| 230 | -#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) | |
| 227 | + .section .bootpg, "ax" | |
| 228 | + .globl law_entry | |
| 229 | +law_entry: | |
| 230 | + entry_start | |
| 231 | 231 | |
| 232 | -#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) | |
| 233 | -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) | |
| 232 | + .long (4f-3f)/8 | |
| 233 | +3: | |
| 234 | + .long 0 | |
| 235 | + .long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN | |
| 234 | 236 | |
| 235 | -#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) | |
| 236 | -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_256M)) | |
| 237 | +#ifdef CFG_PCI1_MEM_PHYS | |
| 238 | + .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff | |
| 239 | + .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M) | |
| 237 | 240 | |
| 238 | -#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) | |
| 239 | -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M)) | |
| 241 | + .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff | |
| 242 | + .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M) | |
| 243 | +#endif | |
| 240 | 244 | |
| 241 | -#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff) | |
| 242 | -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_8M)) | |
| 245 | +#ifdef CFG_PCI2_MEM_PHYS | |
| 246 | + .long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff | |
| 247 | + .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M) | |
| 243 | 248 | |
| 244 | -/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ | |
| 245 | -#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) | |
| 246 | -#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) | |
| 249 | + .long (CFG_PCI2_IO_PHYS>>12) & 0xfffff | |
| 250 | + .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M) | |
| 251 | +#endif | |
| 247 | 252 | |
| 248 | -#define LAWBAR6 ((CFG_PEX_MEM_BASE>>12) & 0xfffff) | |
| 249 | -#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M)) | |
| 253 | +#ifdef CFG_PCIE1_MEM_PHYS | |
| 254 | + .long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff | |
| 255 | + .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M) | |
| 250 | 256 | |
| 251 | -#define LAWBAR7 ((CFG_PEX_IO_PHYS>>12) & 0xfffff) | |
| 252 | -#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_16M)) | |
| 257 | + .long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff | |
| 258 | + .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M) | |
| 259 | +#endif | |
| 253 | 260 | |
| 254 | -#define LAWBAR8 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) | |
| 255 | -#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) | |
| 261 | + /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ | |
| 262 | + .long (CFG_LBC_CACHE_BASE>>12) & 0xfffff | |
| 263 | + .long LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M) | |
| 256 | 264 | |
| 257 | - .section .bootpg, "ax" | |
| 258 | - .globl law_entry | |
| 259 | - | |
| 260 | -law_entry: | |
| 261 | - entry_start | |
| 262 | - .long (4f-3f)/8 | |
| 263 | -3: | |
| 264 | - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 | |
| 265 | - .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5,LAWBAR6,LAWAR6,LAWBAR7,LAWAR7 | |
| 266 | - .long LAWBAR8,LAWAR8 | |
| 265 | +#ifdef CFG_RIO_MEM_PHYS | |
| 266 | + .long (CFG_RIO_MEM_PHYS>>12) & 0xfffff | |
| 267 | + .long LAWAR_EN | LAWAR_TRGT_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M) | |
| 268 | +#endif | |
| 267 | 269 | 4: |
| 268 | 270 | entry_end |
board/cds/mpc8548cds/mpc8548cds.c
| 1 | 1 | /* |
| 2 | - * Copyright 2004 Freescale Semiconductor. | |
| 2 | + * Copyright 2004, 2007 Freescale Semiconductor. | |
| 3 | 3 | * |
| 4 | 4 | * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> |
| 5 | 5 | * |
| ... | ... | @@ -26,6 +26,7 @@ |
| 26 | 26 | #include <pci.h> |
| 27 | 27 | #include <asm/processor.h> |
| 28 | 28 | #include <asm/immap_85xx.h> |
| 29 | +#include <asm/immap_fsl_pci.h> | |
| 29 | 30 | #include <spd.h> |
| 30 | 31 | #include <miiphy.h> |
| 31 | 32 | |
| 32 | 33 | |
| ... | ... | @@ -33,10 +34,15 @@ |
| 33 | 34 | #include "../common/eeprom.h" |
| 34 | 35 | #include "../common/via.h" |
| 35 | 36 | |
| 37 | +#if defined(CONFIG_OF_FLAT_TREE) | |
| 38 | +#include <ft_build.h> | |
| 39 | +#endif | |
| 36 | 40 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
| 37 | 41 | extern void ddr_enable_ecc(unsigned int dram_size); |
| 38 | 42 | #endif |
| 39 | 43 | |
| 44 | +DECLARE_GLOBAL_DATA_PTR; | |
| 45 | + | |
| 40 | 46 | extern long int spd_sdram(void); |
| 41 | 47 | |
| 42 | 48 | void local_bus_init(void); |
| ... | ... | @@ -56,13 +62,6 @@ |
| 56 | 62 | /* PCI slot in USER bits CSR[6:7] by convention. */ |
| 57 | 63 | uint pci_slot = get_pci_slot (); |
| 58 | 64 | |
| 59 | - uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ | |
| 60 | - uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ | |
| 61 | - uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ | |
| 62 | - uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ | |
| 63 | - | |
| 64 | - uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ | |
| 65 | - | |
| 66 | 65 | uint cpu_board_rev = get_cpu_board_revision (); |
| 67 | 66 | |
| 68 | 67 | printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", |
| ... | ... | @@ -71,20 +70,6 @@ |
| 71 | 70 | printf ("CPU Board Revision %d.%d (0x%04x)\n", |
| 72 | 71 | MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), |
| 73 | 72 | MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); |
| 74 | - | |
| 75 | - printf (" PCI1: %d bit, %s MHz, %s\n", | |
| 76 | - (pci1_32) ? 32 : 64, | |
| 77 | - (pci1_speed == 33000000) ? "33" : | |
| 78 | - (pci1_speed == 66000000) ? "66" : "unknown", | |
| 79 | - pci1_clk_sel ? "sync" : "async"); | |
| 80 | - | |
| 81 | - if (pci_dual) { | |
| 82 | - printf (" PCI2: 32 bit, 66 MHz, %s\n", | |
| 83 | - pci2_clk_sel ? "sync" : "async"); | |
| 84 | - } else { | |
| 85 | - printf (" PCI2: disabled\n"); | |
| 86 | - } | |
| 87 | - | |
| 88 | 73 | /* |
| 89 | 74 | * Initialize local bus. |
| 90 | 75 | */ |
| ... | ... | @@ -102,6 +87,8 @@ |
| 102 | 87 | */ |
| 103 | 88 | gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ |
| 104 | 89 | |
| 90 | + ecm->eedr = 0xffffffff; /* clear ecm errors */ | |
| 91 | + ecm->eeer = 0xffffffff; /* enable ecm errors */ | |
| 105 | 92 | return 0; |
| 106 | 93 | } |
| 107 | 94 | |
| ... | ... | @@ -176,6 +163,9 @@ |
| 176 | 163 | lbc->lcrr |= 0x00030000; |
| 177 | 164 | |
| 178 | 165 | asm("sync;isync;msync"); |
| 166 | + | |
| 167 | + lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ | |
| 168 | + lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ | |
| 179 | 169 | } |
| 180 | 170 | |
| 181 | 171 | /* |
| ... | ... | @@ -301,7 +291,7 @@ |
| 301 | 291 | } |
| 302 | 292 | #endif |
| 303 | 293 | |
| 304 | -#if defined(CONFIG_PCI) | |
| 294 | +#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) | |
| 305 | 295 | /* For some reason the Tundra PCI bridge shows up on itself as a |
| 306 | 296 | * different device. Work around that by refusing to configure it. |
| 307 | 297 | */ |
| 308 | 298 | |
| 309 | 299 | |
| 310 | 300 | |
| 311 | 301 | |
| 312 | 302 | |
| ... | ... | @@ -320,23 +310,177 @@ |
| 320 | 310 | {}, |
| 321 | 311 | }; |
| 322 | 312 | |
| 323 | -static struct pci_controller hose[] = { | |
| 324 | - { config_table: pci_mpc85xxcds_config_table,}, | |
| 325 | -#ifdef CONFIG_MPC85XX_PCI2 | |
| 326 | - {}, | |
| 327 | -#endif | |
| 328 | -}; | |
| 329 | - | |
| 313 | +static struct pci_controller pci1_hose = { | |
| 314 | + config_table: pci_mpc85xxcds_config_table}; | |
| 330 | 315 | #endif /* CONFIG_PCI */ |
| 331 | 316 | |
| 317 | +#ifdef CONFIG_PCI2 | |
| 318 | +static struct pci_controller pci2_hose; | |
| 319 | +#endif /* CONFIG_PCI2 */ | |
| 320 | + | |
| 321 | +#ifdef CONFIG_PCIE1 | |
| 322 | +static struct pci_controller pcie1_hose; | |
| 323 | +#endif /* CONFIG_PCIE1 */ | |
| 324 | + | |
| 325 | +int first_free_busno=0; | |
| 326 | + | |
| 332 | 327 | void |
| 333 | 328 | pci_init_board(void) |
| 334 | 329 | { |
| 335 | -#ifdef CONFIG_PCI | |
| 336 | - pci_mpc85xx_init(&hose); | |
| 330 | + volatile immap_t *immap = (immap_t *)CFG_IMMR; | |
| 331 | + volatile ccsr_gur_t *gur = &immap->im_gur; | |
| 332 | + uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; | |
| 333 | + uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; | |
| 334 | + | |
| 335 | + | |
| 336 | +#ifdef CONFIG_PCI1 | |
| 337 | +{ | |
| 338 | + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; | |
| 339 | + extern void fsl_pci_init(struct pci_controller *hose); | |
| 340 | + struct pci_controller *hose = &pci1_hose; | |
| 341 | + struct pci_config_table *table; | |
| 342 | + | |
| 343 | + uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ | |
| 344 | + uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ | |
| 345 | + uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ | |
| 346 | + | |
| 347 | + uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); | |
| 348 | + | |
| 349 | + uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ | |
| 350 | + | |
| 351 | + if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { | |
| 352 | + printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", | |
| 353 | + (pci_32) ? 32 : 64, | |
| 354 | + (pci_speed == 33333000) ? "33" : | |
| 355 | + (pci_speed == 66666000) ? "66" : "unknown", | |
| 356 | + pci_clk_sel ? "sync" : "async", | |
| 357 | + pci_agent ? "agent" : "host", | |
| 358 | + pci_arb ? "arbiter" : "external-arbiter" | |
| 359 | + ); | |
| 360 | + | |
| 361 | + | |
| 362 | + /* outbound memory */ | |
| 363 | + pci_set_region(hose->regions + 0, | |
| 364 | + CFG_PCI1_MEM_BASE, | |
| 365 | + CFG_PCI1_MEM_PHYS, | |
| 366 | + CFG_PCI1_MEM_SIZE, | |
| 367 | + PCI_REGION_MEM); | |
| 368 | + | |
| 369 | + /* outbound io */ | |
| 370 | + pci_set_region(hose->regions + 1, | |
| 371 | + CFG_PCI1_IO_BASE, | |
| 372 | + CFG_PCI1_IO_PHYS, | |
| 373 | + CFG_PCI1_IO_SIZE, | |
| 374 | + PCI_REGION_IO); | |
| 375 | + hose->region_count = 2; | |
| 376 | + | |
| 377 | + /* relocate config table pointers */ | |
| 378 | + hose->config_table = \ | |
| 379 | + (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off); | |
| 380 | + for (table = hose->config_table; table && table->vendor; table++) | |
| 381 | + table->config_device += gd->reloc_off; | |
| 382 | + | |
| 383 | + hose->first_busno=first_free_busno; | |
| 384 | + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); | |
| 385 | + | |
| 386 | + fsl_pci_init(hose); | |
| 387 | + first_free_busno=hose->last_busno+1; | |
| 388 | + printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); | |
| 389 | +#ifdef CONFIG_PCIX_CHECK | |
| 390 | + if (!(gur->pordevsr & PORDEVSR_PCI)) { | |
| 391 | + /* PCI-X init */ | |
| 392 | + if (CONFIG_SYS_CLK_FREQ < 66000000) | |
| 393 | + printf("PCI-X will only work at 66 MHz\n"); | |
| 394 | + | |
| 395 | + reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ | |
| 396 | + | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; | |
| 397 | + pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); | |
| 398 | + } | |
| 337 | 399 | #endif |
| 400 | + } else { | |
| 401 | + printf (" PCI: disabled\n"); | |
| 402 | + } | |
| 338 | 403 | } |
| 404 | +#else | |
| 405 | + gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ | |
| 406 | +#endif | |
| 339 | 407 | |
| 408 | +#ifdef CONFIG_PCI2 | |
| 409 | +{ | |
| 410 | + uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ | |
| 411 | + uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ | |
| 412 | + if (pci_dual) { | |
| 413 | + printf (" PCI2: 32 bit, 66 MHz, %s\n", | |
| 414 | + pci2_clk_sel ? "sync" : "async"); | |
| 415 | + } else { | |
| 416 | + printf (" PCI2: disabled\n"); | |
| 417 | + } | |
| 418 | +} | |
| 419 | +#else | |
| 420 | + gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */ | |
| 421 | +#endif /* CONFIG_PCI2 */ | |
| 422 | + | |
| 423 | +#ifdef CONFIG_PCIE1 | |
| 424 | +{ | |
| 425 | + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; | |
| 426 | + extern void fsl_pci_init(struct pci_controller *hose); | |
| 427 | + struct pci_controller *hose = &pcie1_hose; | |
| 428 | + int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); | |
| 429 | + | |
| 430 | + int pcie_configured = io_sel >= 1; | |
| 431 | + | |
| 432 | + if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ | |
| 433 | + printf ("\n PCIE connected to slot as %s (base address %x)", | |
| 434 | + pcie_ep ? "End Point" : "Root Complex", | |
| 435 | + (uint)pci); | |
| 436 | + | |
| 437 | + if (pci->pme_msg_det) { | |
| 438 | + pci->pme_msg_det = 0xffffffff; | |
| 439 | + debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); | |
| 440 | + } | |
| 441 | + printf ("\n"); | |
| 442 | + | |
| 443 | + /* inbound */ | |
| 444 | + pci_set_region(hose->regions + 0, | |
| 445 | + CFG_PCI_MEMORY_BUS, | |
| 446 | + CFG_PCI_MEMORY_PHYS, | |
| 447 | + CFG_PCI_MEMORY_SIZE, | |
| 448 | + PCI_REGION_MEM | PCI_REGION_MEMORY); | |
| 449 | + | |
| 450 | + /* outbound memory */ | |
| 451 | + pci_set_region(hose->regions + 1, | |
| 452 | + CFG_PCIE1_MEM_BASE, | |
| 453 | + CFG_PCIE1_MEM_PHYS, | |
| 454 | + CFG_PCIE1_MEM_SIZE, | |
| 455 | + PCI_REGION_MEM); | |
| 456 | + | |
| 457 | + /* outbound io */ | |
| 458 | + pci_set_region(hose->regions + 2, | |
| 459 | + CFG_PCIE1_IO_BASE, | |
| 460 | + CFG_PCIE1_IO_PHYS, | |
| 461 | + CFG_PCIE1_IO_SIZE, | |
| 462 | + PCI_REGION_IO); | |
| 463 | + | |
| 464 | + hose->region_count = 3; | |
| 465 | + | |
| 466 | + hose->first_busno=first_free_busno; | |
| 467 | + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); | |
| 468 | + | |
| 469 | + fsl_pci_init(hose); | |
| 470 | + printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno); | |
| 471 | + | |
| 472 | + first_free_busno=hose->last_busno+1; | |
| 473 | + | |
| 474 | + } else { | |
| 475 | + printf (" PCIE: disabled\n"); | |
| 476 | + } | |
| 477 | + } | |
| 478 | +#else | |
| 479 | + gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ | |
| 480 | +#endif | |
| 481 | + | |
| 482 | +} | |
| 483 | + | |
| 340 | 484 | int last_stage_init(void) |
| 341 | 485 | { |
| 342 | 486 | unsigned short temp; |
| ... | ... | @@ -367,4 +511,33 @@ |
| 367 | 511 | |
| 368 | 512 | return 0; |
| 369 | 513 | } |
| 514 | + | |
| 515 | + | |
| 516 | +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) | |
| 517 | +void | |
| 518 | +ft_pci_setup(void *blob, bd_t *bd) | |
| 519 | +{ | |
| 520 | + u32 *p; | |
| 521 | + int len; | |
| 522 | + | |
| 523 | + | |
| 524 | +#ifdef CONFIG_PCI1 | |
| 525 | + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len); | |
| 526 | + if (p != NULL) { | |
| 527 | + p[0] = 0; | |
| 528 | + p[1] = pci1_hose.last_busno - pci1_hose.first_busno; | |
| 529 | + debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]); | |
| 530 | + } | |
| 531 | +#endif | |
| 532 | + | |
| 533 | +#ifdef CONFIG_PCIE1 | |
| 534 | + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len); | |
| 535 | + if (p != NULL) { | |
| 536 | + p[0] = 0; | |
| 537 | + p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; | |
| 538 | + debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]); | |
| 539 | + } | |
| 540 | +#endif | |
| 541 | +} | |
| 542 | +#endif |
board/cds/mpc8548cds/u-boot.lds
| 1 | 1 | /* |
| 2 | - * Copyright 2004 Freescale Semiconductor. | |
| 2 | + * Copyright 2004, 2007 Freescale Semiconductor. | |
| 3 | 3 | * |
| 4 | 4 | * See file CREDITS for list of people who contributed to this |
| 5 | 5 | * project. |
| ... | ... | @@ -71,7 +71,6 @@ |
| 71 | 71 | cpu/mpc85xx/cpu.o (.text) |
| 72 | 72 | drivers/tsec.o (.text) |
| 73 | 73 | cpu/mpc85xx/speed.o (.text) |
| 74 | - cpu/mpc85xx/pci.o (.text) | |
| 75 | 74 | common/dlmalloc.o (.text) |
| 76 | 75 | lib_generic/crc32.o (.text) |
| 77 | 76 | lib_ppc/extable.o (.text) |
include/configs/MPC8548CDS.h
| 1 | 1 | /* |
| 2 | - * Copyright 2004 Freescale Semiconductor. | |
| 2 | + * Copyright 2004, 2007 Freescale Semiconductor. | |
| 3 | 3 | * |
| 4 | 4 | * See file CREDITS for list of people who contributed to this |
| 5 | 5 | * project. |
| ... | ... | @@ -11,7 +11,7 @@ |
| 11 | 11 | * |
| 12 | 12 | * This program is distributed in the hope that it will be useful, |
| 13 | 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 14 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | 15 | * GNU General Public License for more details. |
| 16 | 16 | * |
| 17 | 17 | * You should have received a copy of the GNU General Public License |
| ... | ... | @@ -36,8 +36,14 @@ |
| 36 | 36 | #define CONFIG_MPC8548 1 /* MPC8548 specific */ |
| 37 | 37 | #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ |
| 38 | 38 | |
| 39 | -#define CONFIG_PCI | |
| 40 | -#define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
| 39 | +#define CONFIG_PCI /* enable any pci type devices */ | |
| 40 | +#define CONFIG_PCI1 /* PCI controller 1 */ | |
| 41 | +#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ | |
| 42 | +#undef CONFIG_RIO | |
| 43 | +#undef CONFIG_PCI2 | |
| 44 | +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
| 45 | + | |
| 46 | +#define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
| 41 | 47 | #define CONFIG_ENV_OVERWRITE |
| 42 | 48 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ |
| 43 | 49 | #define CONFIG_DDR_DLL /* possible DLL fix needed */ |
| ... | ... | @@ -46,6 +52,7 @@ |
| 46 | 52 | #define CONFIG_DDR_ECC /* only for ECC DDR module */ |
| 47 | 53 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
| 48 | 54 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| 55 | +#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ | |
| 49 | 56 | |
| 50 | 57 | |
| 51 | 58 | /* |
| 52 | 59 | |
| ... | ... | @@ -65,16 +72,16 @@ |
| 65 | 72 | /* |
| 66 | 73 | * These can be toggled for performance analysis, otherwise use default. |
| 67 | 74 | */ |
| 68 | -#define CONFIG_L2_CACHE /* toggle L2 cache */ | |
| 69 | -#define CONFIG_BTB /* toggle branch predition */ | |
| 70 | -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ | |
| 75 | +#define CONFIG_L2_CACHE /* toggle L2 cache */ | |
| 76 | +#define CONFIG_BTB /* toggle branch predition */ | |
| 77 | +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ | |
| 78 | +#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ | |
| 71 | 79 | |
| 72 | 80 | /* |
| 73 | 81 | * Only possible on E500 Version 2 or newer cores. |
| 74 | 82 | */ |
| 75 | 83 | #define CONFIG_ENABLE_36BIT_PHYS 1 |
| 76 | 84 | |
| 77 | - | |
| 78 | 85 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
| 79 | 86 | |
| 80 | 87 | #undef CFG_DRAM_TEST /* memory test, takes time */ |
| 81 | 88 | |
| ... | ... | @@ -85,10 +92,14 @@ |
| 85 | 92 | * Base addresses -- Note these are effective addresses where the |
| 86 | 93 | * actual resources get mapped (not physical addresses) |
| 87 | 94 | */ |
| 88 | -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ | |
| 95 | +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ | |
| 89 | 96 | #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ |
| 90 | 97 | #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ |
| 91 | 98 | |
| 99 | +#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) | |
| 100 | +#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000) | |
| 101 | +#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) | |
| 102 | + | |
| 92 | 103 | /* |
| 93 | 104 | * DDR Setup |
| 94 | 105 | */ |
| ... | ... | @@ -106,7 +117,6 @@ |
| 106 | 117 | |
| 107 | 118 | #undef CONFIG_CLOCKS_IN_MHZ |
| 108 | 119 | |
| 109 | - | |
| 110 | 120 | /* |
| 111 | 121 | * Local Bus Definitions |
| 112 | 122 | */ |
| ... | ... | @@ -124,9 +134,9 @@ |
| 124 | 134 | * Use GPCM = BRx[24:26] = 000 |
| 125 | 135 | * Valid = BRx[31] = 1 |
| 126 | 136 | * |
| 127 | - * 0 4 8 12 16 20 24 28 | |
| 128 | - * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 | |
| 129 | - * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 | |
| 137 | + * 0 4 8 12 16 20 24 28 | |
| 138 | + * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 | |
| 139 | + * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 | |
| 130 | 140 | * |
| 131 | 141 | * OR0, OR1: |
| 132 | 142 | * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 |
| 133 | 143 | |
| ... | ... | @@ -137,11 +147,12 @@ |
| 137 | 147 | * TRLX = use relaxed timing = ORx[29] = 1 |
| 138 | 148 | * EAD = use external address latch delay = OR[31] = 1 |
| 139 | 149 | * |
| 140 | - * 0 4 8 12 16 20 24 28 | |
| 141 | - * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx | |
| 150 | + * 0 4 8 12 16 20 24 28 | |
| 151 | + * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx | |
| 142 | 152 | */ |
| 143 | 153 | |
| 144 | -#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */ | |
| 154 | +#define CFG_BOOT_BLOCK 0xff000000 /* boot TLB block */ | |
| 155 | +#define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 16M */ | |
| 145 | 156 | |
| 146 | 157 | #define CFG_BR0_PRELIM 0xff801001 |
| 147 | 158 | #define CFG_BR1_PRELIM 0xff001001 |
| ... | ... | @@ -156,7 +167,7 @@ |
| 156 | 167 | #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 157 | 168 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
| 158 | 169 | |
| 159 | -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
| 170 | +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
| 160 | 171 | |
| 161 | 172 | #define CFG_FLASH_CFI_DRIVER |
| 162 | 173 | #define CFG_FLASH_CFI |
| ... | ... | @@ -166,7 +177,12 @@ |
| 166 | 177 | /* |
| 167 | 178 | * SDRAM on the Local Bus |
| 168 | 179 | */ |
| 169 | -#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ | |
| 180 | +#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ | |
| 181 | +#define CFG_LBC_CACHE_SIZE 64 | |
| 182 | +#define CFG_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */ | |
| 183 | +#define CFG_LBC_NONCACHE_SIZE 64 | |
| 184 | + | |
| 185 | +#define CFG_LBC_SDRAM_BASE CFG_LBC_CACHE_BASE /* Localbus SDRAM */ | |
| 170 | 186 | #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
| 171 | 187 | |
| 172 | 188 | /* |
| 173 | 189 | |
| ... | ... | @@ -180,14 +196,14 @@ |
| 180 | 196 | * SDRAM for MSEL = BR2[24:26] = 011 |
| 181 | 197 | * Valid = BR[31] = 1 |
| 182 | 198 | * |
| 183 | - * 0 4 8 12 16 20 24 28 | |
| 199 | + * 0 4 8 12 16 20 24 28 | |
| 184 | 200 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 |
| 185 | 201 | * |
| 186 | 202 | * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into |
| 187 | 203 | * FIXME: the top 17 bits of BR2. |
| 188 | 204 | */ |
| 189 | 205 | |
| 190 | -#define CFG_BR2_PRELIM 0xf0001861 | |
| 206 | +#define CFG_BR2_PRELIM 0xf0001861 | |
| 191 | 207 | |
| 192 | 208 | /* |
| 193 | 209 | * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. |
| 194 | 210 | |
| 195 | 211 | |
| ... | ... | @@ -196,19 +212,19 @@ |
| 196 | 212 | * 64MB mask for AM, OR2[0:7] = 1111 1100 |
| 197 | 213 | * XAM, OR2[17:18] = 11 |
| 198 | 214 | * 9 columns OR2[19-21] = 010 |
| 199 | - * 13 rows OR2[23-25] = 100 | |
| 215 | + * 13 rows OR2[23-25] = 100 | |
| 200 | 216 | * EAD set for extra time OR[31] = 1 |
| 201 | 217 | * |
| 202 | - * 0 4 8 12 16 20 24 28 | |
| 218 | + * 0 4 8 12 16 20 24 28 | |
| 203 | 219 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 |
| 204 | 220 | */ |
| 205 | 221 | |
| 206 | 222 | #define CFG_OR2_PRELIM 0xfc006901 |
| 207 | 223 | |
| 208 | -#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ | |
| 209 | -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ | |
| 210 | -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
| 211 | -#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ | |
| 224 | +#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ | |
| 225 | +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ | |
| 226 | +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
| 227 | +#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ | |
| 212 | 228 | |
| 213 | 229 | /* |
| 214 | 230 | * LSDMR masks |
| ... | ... | @@ -236,7 +252,7 @@ |
| 236 | 252 | /* |
| 237 | 253 | * Common settings for all Local Bus SDRAM commands. |
| 238 | 254 | * At run time, either BSMA1516 (for CPU 1.1) |
| 239 | - * or BSMA1617 (for CPU 1.0) (old) | |
| 255 | + * or BSMA1617 (for CPU 1.0) (old) | |
| 240 | 256 | * is OR'ed in too. |
| 241 | 257 | */ |
| 242 | 258 | #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ |
| 243 | 259 | |
| 244 | 260 | |
| 245 | 261 | |
| 246 | 262 | |
| 247 | 263 | |
| 248 | 264 | |
| 249 | 265 | |
| 250 | 266 | |
| 251 | 267 | |
| 252 | 268 | |
| 253 | 269 | |
| 254 | 270 | |
| 255 | 271 | |
| 256 | 272 | |
| 257 | 273 | |
| ... | ... | @@ -256,61 +272,63 @@ |
| 256 | 272 | * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 |
| 257 | 273 | * port-size = 8-bits = BR[19:20] = 01 |
| 258 | 274 | * no parity checking = BR[21:22] = 00 |
| 259 | - * GPMC for MSEL = BR[24:26] = 000 | |
| 260 | - * Valid = BR[31] = 1 | |
| 275 | + * GPMC for MSEL = BR[24:26] = 000 | |
| 276 | + * Valid = BR[31] = 1 | |
| 261 | 277 | * |
| 262 | - * 0 4 8 12 16 20 24 28 | |
| 278 | + * 0 4 8 12 16 20 24 28 | |
| 263 | 279 | * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 |
| 264 | 280 | * |
| 265 | 281 | * For OR3, need: |
| 266 | - * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 | |
| 282 | + * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 | |
| 267 | 283 | * disable buffer ctrl OR[19] = 0 |
| 268 | - * CSNT OR[20] = 1 | |
| 269 | - * ACS OR[21:22] = 11 | |
| 270 | - * XACS OR[23] = 1 | |
| 284 | + * CSNT OR[20] = 1 | |
| 285 | + * ACS OR[21:22] = 11 | |
| 286 | + * XACS OR[23] = 1 | |
| 271 | 287 | * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe |
| 272 | - * SETA OR[28] = 0 | |
| 273 | - * TRLX OR[29] = 1 | |
| 274 | - * EHTR OR[30] = 1 | |
| 275 | - * EAD extra time OR[31] = 1 | |
| 288 | + * SETA OR[28] = 0 | |
| 289 | + * TRLX OR[29] = 1 | |
| 290 | + * EHTR OR[30] = 1 | |
| 291 | + * EAD extra time OR[31] = 1 | |
| 276 | 292 | * |
| 277 | - * 0 4 8 12 16 20 24 28 | |
| 293 | + * 0 4 8 12 16 20 24 28 | |
| 278 | 294 | * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 |
| 279 | 295 | */ |
| 280 | 296 | |
| 281 | 297 | #define CADMUS_BASE_ADDR 0xf8000000 |
| 282 | -#define CFG_BR3_PRELIM 0xf8000801 | |
| 283 | -#define CFG_OR3_PRELIM 0xfff00ff7 | |
| 298 | +#define CFG_BR3_PRELIM 0xf8000801 | |
| 299 | +#define CFG_OR3_PRELIM 0xfff00ff7 | |
| 284 | 300 | |
| 285 | 301 | #define CONFIG_L1_INIT_RAM |
| 286 | -#define CFG_INIT_RAM_LOCK 1 | |
| 302 | +#define CFG_INIT_RAM_LOCK 1 | |
| 287 | 303 | #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ |
| 288 | -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ | |
| 304 | +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ | |
| 289 | 305 | |
| 290 | -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ | |
| 306 | +#define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ | |
| 307 | + | |
| 308 | +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ | |
| 291 | 309 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
| 292 | 310 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
| 293 | 311 | |
| 294 | -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
| 295 | -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
| 312 | +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
| 313 | +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
| 296 | 314 | |
| 297 | 315 | /* Serial Port */ |
| 298 | -#define CONFIG_CONS_INDEX 2 | |
| 316 | +#define CONFIG_CONS_INDEX 2 | |
| 299 | 317 | #undef CONFIG_SERIAL_SOFTWARE_FIFO |
| 300 | 318 | #define CFG_NS16550 |
| 301 | 319 | #define CFG_NS16550_SERIAL |
| 302 | -#define CFG_NS16550_REG_SIZE 1 | |
| 320 | +#define CFG_NS16550_REG_SIZE 1 | |
| 303 | 321 | #define CFG_NS16550_CLK get_bus_freq(0) |
| 304 | 322 | |
| 305 | -#define CFG_BAUDRATE_TABLE \ | |
| 323 | +#define CFG_BAUDRATE_TABLE \ | |
| 306 | 324 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 307 | 325 | |
| 308 | -#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) | |
| 309 | -#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) | |
| 326 | +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) | |
| 327 | +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) | |
| 310 | 328 | |
| 311 | 329 | /* Use the HUSH parser */ |
| 312 | 330 | #define CFG_HUSH_PARSER |
| 313 | -#ifdef CFG_HUSH_PARSER | |
| 331 | +#ifdef CFG_HUSH_PARSER | |
| 314 | 332 | #define CFG_PROMPT_HUSH_PS2 "> " |
| 315 | 333 | #endif |
| 316 | 334 | |
| 317 | 335 | |
| 318 | 336 | |
| 319 | 337 | |
| 320 | 338 | |
| 321 | 339 | |
| 322 | 340 | |
| 323 | 341 | |
| 324 | 342 | |
| 325 | 343 | |
| 326 | 344 | |
| 327 | 345 | |
| 328 | 346 | |
| 329 | 347 | |
| 330 | 348 | |
| ... | ... | @@ -331,63 +349,74 @@ |
| 331 | 349 | */ |
| 332 | 350 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
| 333 | 351 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ |
| 334 | -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| 352 | +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| 335 | 353 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 336 | 354 | #define CFG_I2C_EEPROM_ADDR 0x57 |
| 337 | 355 | #define CFG_I2C_SLAVE 0x7F |
| 338 | -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
| 356 | +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
| 339 | 357 | #define CFG_I2C_OFFSET 0x3000 |
| 340 | 358 | |
| 341 | 359 | /* |
| 342 | 360 | * General PCI |
| 343 | 361 | * Memory space is mapped 1-1, but I/O space must start from 0. |
| 344 | 362 | */ |
| 363 | +#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */ | |
| 364 | + | |
| 345 | 365 | #define CFG_PCI1_MEM_BASE 0x80000000 |
| 346 | 366 | #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE |
| 347 | -#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
| 367 | +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ | |
| 348 | 368 | #define CFG_PCI1_IO_BASE 0x00000000 |
| 349 | 369 | #define CFG_PCI1_IO_PHYS 0xe2000000 |
| 350 | -#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */ | |
| 370 | +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
| 351 | 371 | |
| 352 | -#define CFG_PCI2_MEM_BASE 0x90000000 | |
| 372 | +#ifdef CONFIG_PCI2 | |
| 373 | +#define CFG_PCI2_MEM_BASE 0xa0000000 | |
| 353 | 374 | #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE |
| 354 | -#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ | |
| 375 | +#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ | |
| 355 | 376 | #define CFG_PCI2_IO_BASE 0x00000000 |
| 356 | 377 | #define CFG_PCI2_IO_PHYS 0xe2800000 |
| 357 | -#define CFG_PCI2_IO_SIZE 0x00800000 /* 8M */ | |
| 378 | +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ | |
| 379 | +#endif | |
| 358 | 380 | |
| 359 | -#define CFG_PEX_MEM_BASE 0xa0000000 | |
| 360 | -#define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE | |
| 361 | -#define CFG_PEX_MEM_SIZE 0x20000000 /* 512M */ | |
| 362 | -#define CFG_PEX_IO_BASE 0x00000000 | |
| 363 | -#define CFG_PEX_IO_PHYS 0xe3000000 | |
| 364 | -#define CFG_PEX_IO_SIZE 0x01000000 /* 16M */ | |
| 381 | +#ifdef CONFIG_PCIE1 | |
| 382 | +#define CFG_PCIE1_MEM_BASE 0xa0000000 | |
| 383 | +#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE | |
| 384 | +#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
| 385 | +#define CFG_PCIE1_IO_BASE 0x00000000 | |
| 386 | +#define CFG_PCIE1_IO_PHYS 0xe3000000 | |
| 387 | +#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ | |
| 388 | +#endif | |
| 365 | 389 | |
| 390 | +#ifdef CONFIG_RIO | |
| 366 | 391 | /* |
| 367 | 392 | * RapidIO MMU |
| 368 | 393 | */ |
| 369 | 394 | #define CFG_RIO_MEM_BASE 0xC0000000 |
| 370 | 395 | #define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */ |
| 396 | +#endif | |
| 371 | 397 | |
| 372 | 398 | #if defined(CONFIG_PCI) |
| 373 | 399 | |
| 374 | 400 | #define CONFIG_NET_MULTI |
| 375 | -#define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 376 | -#define CONFIG_85XX_PCI2 | |
| 401 | +#define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 377 | 402 | |
| 378 | 403 | #undef CONFIG_EEPRO100 |
| 379 | 404 | #undef CONFIG_TULIP |
| 380 | 405 | |
| 381 | 406 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 382 | -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ | |
| 383 | 407 | |
| 408 | +/* PCI view of System Memory */ | |
| 409 | +#define CFG_PCI_MEMORY_BUS 0x00000000 | |
| 410 | +#define CFG_PCI_MEMORY_PHYS 0x00000000 | |
| 411 | +#define CFG_PCI_MEMORY_SIZE 0x80000000 | |
| 412 | + | |
| 384 | 413 | #endif /* CONFIG_PCI */ |
| 385 | 414 | |
| 386 | 415 | |
| 387 | 416 | #if defined(CONFIG_TSEC_ENET) |
| 388 | 417 | |
| 389 | 418 | #ifndef CONFIG_NET_MULTI |
| 390 | -#define CONFIG_NET_MULTI 1 | |
| 419 | +#define CONFIG_NET_MULTI 1 | |
| 391 | 420 | #endif |
| 392 | 421 | |
| 393 | 422 | #define CONFIG_MII 1 /* MII PHY management */ |
| ... | ... | @@ -397,7 +426,7 @@ |
| 397 | 426 | #define CONFIG_TSEC2_NAME "eTSEC1" |
| 398 | 427 | #define CONFIG_TSEC3 1 |
| 399 | 428 | #define CONFIG_TSEC3_NAME "eTSEC2" |
| 400 | -#undef CONFIG_TSEC4 | |
| 429 | +#define CONFIG_TSEC4 | |
| 401 | 430 | #define CONFIG_TSEC4_NAME "eTSEC3" |
| 402 | 431 | #undef CONFIG_MPC85XX_FEC |
| 403 | 432 | |
| ... | ... | @@ -413,7 +442,7 @@ |
| 413 | 442 | |
| 414 | 443 | /* Options are: eTSEC[0-3] */ |
| 415 | 444 | #define CONFIG_ETHPRIME "eTSEC0" |
| 416 | - | |
| 445 | +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
| 417 | 446 | #endif /* CONFIG_TSEC_ENET */ |
| 418 | 447 | |
| 419 | 448 | /* |
| ... | ... | @@ -473,7 +502,7 @@ |
| 473 | 502 | * have to be in the first 8 MB of memory, since this is |
| 474 | 503 | * the maximum mapped by the Linux kernel during initialization. |
| 475 | 504 | */ |
| 476 | -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ | |
| 505 | +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ | |
| 477 | 506 | |
| 478 | 507 | /* Cache Configuration */ |
| 479 | 508 | #define CFG_DCACHE_SIZE 32768 |
| 480 | 509 | |
| 481 | 510 | |
| 482 | 511 | |
| 483 | 512 | |
| 484 | 513 | |
| 485 | 514 | |
| 486 | 515 | |
| 487 | 516 | |
| 488 | 517 | |
| 489 | 518 | |
| 490 | 519 | |
| 491 | 520 | |
| 492 | 521 | |
| 493 | 522 | |
| 494 | 523 | |
| ... | ... | @@ -501,59 +530,155 @@ |
| 501 | 530 | |
| 502 | 531 | /* The mac addresses for all ethernet interface */ |
| 503 | 532 | #if defined(CONFIG_TSEC_ENET) |
| 504 | -#define CONFIG_ETHADDR 00:E0:0C:00:00:FD | |
| 533 | +#define CONFIG_ETHADDR 00:E0:0C:00:00:FD | |
| 505 | 534 | #define CONFIG_HAS_ETH1 |
| 506 | -#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD | |
| 535 | +#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD | |
| 507 | 536 | #define CONFIG_HAS_ETH2 |
| 508 | -#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD | |
| 537 | +#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD | |
| 509 | 538 | #define CONFIG_HAS_ETH3 |
| 510 | -#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD | |
| 539 | +#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD | |
| 511 | 540 | #endif |
| 512 | 541 | |
| 513 | -#define CONFIG_IPADDR 192.168.1.253 | |
| 542 | +#define CONFIG_IPADDR 192.168.1.253 | |
| 514 | 543 | |
| 515 | -#define CONFIG_HOSTNAME unknown | |
| 516 | -#define CONFIG_ROOTPATH /nfsroot | |
| 517 | -#define CONFIG_BOOTFILE your.uImage | |
| 544 | +#define CONFIG_HOSTNAME unknown | |
| 545 | +#define CONFIG_ROOTPATH /nfsroot | |
| 546 | +#define CONFIG_BOOTFILE 8548cds/uImage.uboot | |
| 547 | +#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ | |
| 518 | 548 | |
| 519 | -#define CONFIG_SERVERIP 192.168.1.1 | |
| 549 | +#define CONFIG_SERVERIP 192.168.1.1 | |
| 520 | 550 | #define CONFIG_GATEWAYIP 192.168.1.1 |
| 521 | -#define CONFIG_NETMASK 255.255.255.0 | |
| 551 | +#define CONFIG_NETMASK 255.255.255.0 | |
| 522 | 552 | |
| 523 | -#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ | |
| 553 | +#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ | |
| 524 | 554 | |
| 525 | -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
| 526 | -#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ | |
| 555 | +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
| 556 | +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ | |
| 527 | 557 | |
| 528 | 558 | #define CONFIG_BAUDRATE 115200 |
| 529 | 559 | |
| 530 | -#define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 531 | - "netdev=eth0\0" \ | |
| 532 | - "consoledev=ttyS1\0" \ | |
| 533 | - "ramdiskaddr=600000\0" \ | |
| 534 | - "ramdiskfile=your.ramdisk.u-boot\0" \ | |
| 535 | - "fdtaddr=400000\0" \ | |
| 536 | - "fdtfile=your.fdt.dtb\0" | |
| 560 | +#if defined(CONFIG_PCIE1) | |
| 561 | +#define PCIE_ENV \ | |
| 562 | + "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ | |
| 563 | + "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ | |
| 564 | + "pcieerr=md ${a}020 1; md ${a}e00 e; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ | |
| 565 | + "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ | |
| 566 | + "pci d $b.0 130 1\0" \ | |
| 567 | + "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;" \ | |
| 568 | + "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;"\ | |
| 569 | + "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ | |
| 570 | + "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ | |
| 571 | + "pcie1regs=setenv a e000a; run pciereg\0" \ | |
| 572 | + "pcie1cfg=setenv b 3; run pciecfg\0" \ | |
| 573 | + "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \ | |
| 574 | + "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0" | |
| 575 | +#else | |
| 576 | +#define PCIE_ENV "" | |
| 577 | +#endif | |
| 537 | 578 | |
| 579 | +#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2) | |
| 580 | +#define PCI_ENV \ | |
| 581 | + "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ | |
| 582 | + "echo e;md ${a}e00 9\0" \ | |
| 583 | + "pcierr=md ${a}e00 8; pci d.b $b.0 7 1;pci d.w $b.0 1e 1;" \ | |
| 584 | + "pci d.w $b.0 56 1\0" \ | |
| 585 | + "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \ | |
| 586 | + "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0" | |
| 587 | +#else | |
| 588 | +#define PCI_ENV "" | |
| 589 | +#endif | |
| 538 | 590 | |
| 539 | -#define CONFIG_NFSBOOTCOMMAND \ | |
| 540 | - "setenv bootargs root=/dev/nfs rw " \ | |
| 541 | - "nfsroot=$serverip:$rootpath " \ | |
| 591 | +#if defined(CONFIG_PCI1) | |
| 592 | +#define PCI_ENV1 \ | |
| 593 | + "pci1regs=setenv a e0008; run pcireg\0" \ | |
| 594 | + "pci1err=setenv a e0008; setenv b 0; run pcierr\0" \ | |
| 595 | + "pci1errc=setenv a e0008; setenv b 0; run pcierrc\0" | |
| 596 | +#else | |
| 597 | +#define PCI_ENV1 "" | |
| 598 | +#endif | |
| 599 | + | |
| 600 | +#if defined(CONFIG_PCI2) | |
| 601 | +#define PCI_ENV2 \ | |
| 602 | + "pci2regs=setenv a e0009; run pcireg\0" \ | |
| 603 | + "pci2err=setenv a e0009; setenv b 123; run pcierr\0" \ | |
| 604 | + "pci2errc=setenv a e0009; setenv b 123; run pcierrc\0" | |
| 605 | +#else | |
| 606 | +#define PCI_ENV2 "" | |
| 607 | +#endif | |
| 608 | + | |
| 609 | +#if defined(CONFIG_TSEC_ENET) | |
| 610 | +#define ENET_ENV \ | |
| 611 | + "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \ | |
| 612 | + "md ${a}098 2\0" \ | |
| 613 | + "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \ | |
| 614 | + "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \ | |
| 615 | + "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \ | |
| 616 | + "echo mib;md ${a}680 31\0" \ | |
| 617 | + "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \ | |
| 618 | + "enet1regs=setenv a e0024; run enetreg\0" \ | |
| 619 | + "enet2regs=setenv a e0025; run enetreg\0" \ | |
| 620 | + "enet3regs=setenv a e0026; run enetreg\0" \ | |
| 621 | + "enet4regs=setenv a e0027; run enetreg\0" | |
| 622 | +#else | |
| 623 | +#define ENET_ENV "" | |
| 624 | +#endif | |
| 625 | + | |
| 626 | +#define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 627 | + "netdev=eth0\0" \ | |
| 628 | + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
| 629 | + "tftpflash=tftpboot $loadaddr $uboot; " \ | |
| 630 | + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ | |
| 631 | + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ | |
| 632 | + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ | |
| 633 | + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ | |
| 634 | + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ | |
| 635 | + "consoledev=ttyS1\0" \ | |
| 636 | + "ramdiskaddr=2000000\0" \ | |
| 637 | + "ramdiskfile=mpc8548cds\ramdisk.uboot\0" \ | |
| 638 | + "dtbaddr=c00000\0" \ | |
| 639 | + "dtbfile=mpc8548cds\mpc8548cds.dtb\0" \ | |
| 640 | + "eoi=mw e00400b0 0\0" \ | |
| 641 | + "iack=md e00400a0 1\0" \ | |
| 642 | + "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \ | |
| 643 | + "md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \ | |
| 644 | + "ddrregs=setenv a e0002; run ddrreg\0" \ | |
| 645 | + "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \ | |
| 646 | + "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \ | |
| 647 | + "guregs=setenv a e00e0; run gureg\0" \ | |
| 648 | + "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \ | |
| 649 | + "ecmregs=setenv a e0001; run ecmreg\0" \ | |
| 650 | + "lawregs=md e0000c08 4b\0" \ | |
| 651 | + "lbcregs=md e0005000 36\0" \ | |
| 652 | + "dma0regs=md e0021100 12\0" \ | |
| 653 | + "dma1regs=md e0021180 12\0" \ | |
| 654 | + "dma2regs=md e0021200 12\0" \ | |
| 655 | + "dma3regs=md e0021280 12\0" \ | |
| 656 | + PCIE_ENV \ | |
| 657 | + PCI_ENV \ | |
| 658 | + PCI_ENV1 \ | |
| 659 | + PCI_ENV2 \ | |
| 660 | + ENET_ENV | |
| 661 | + | |
| 662 | + | |
| 663 | +#define CONFIG_NFSBOOTCOMMAND \ | |
| 664 | + "setenv bootargs root=/dev/nfs rw " \ | |
| 665 | + "nfsroot=$serverip:$rootpath " \ | |
| 542 | 666 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| 543 | - "console=$consoledev,$baudrate $othbootargs;" \ | |
| 544 | - "tftp $loadaddr $bootfile;" \ | |
| 545 | - "tftp $fdtaddr $fdtfile;" \ | |
| 546 | - "bootm $loadaddr - $fdtaddr" | |
| 667 | + "console=$consoledev,$baudrate $othbootargs;" \ | |
| 668 | + "tftp $loadaddr $bootfile;" \ | |
| 669 | + "tftp $dtbaddr $dtbfile;" \ | |
| 670 | + "bootm $loadaddr - $dtbaddr" | |
| 547 | 671 | |
| 548 | 672 | |
| 549 | 673 | #define CONFIG_RAMBOOTCOMMAND \ |
| 550 | - "setenv bootargs root=/dev/ram rw " \ | |
| 551 | - "console=$consoledev,$baudrate $othbootargs;" \ | |
| 552 | - "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 553 | - "tftp $loadaddr $bootfile;" \ | |
| 554 | - "bootm $loadaddr $ramdiskaddr" | |
| 674 | + "setenv bootargs root=/dev/ram rw " \ | |
| 675 | + "console=$consoledev,$baudrate $othbootargs;" \ | |
| 676 | + "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 677 | + "tftp $loadaddr $bootfile;" \ | |
| 678 | + "tftp $dtbaddr $dtbfile;" \ | |
| 679 | + "bootm $loadaddr $ramdiskaddr $dtbaddr" | |
| 555 | 680 | |
| 556 | -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
| 681 | +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
| 557 | 682 | |
| 558 | 683 | #endif /* __CONFIG_H */ |