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Commit f2e4d6a58cafb219b1850c3db1238887109cd94d

Authored by Marek Vasut
Committed by Stefano Babic
1 parent d59d7b915e
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: mx6: novena: Pull video handling into separate file 

Pull all of the video handling into a separate file, since a lot
more code will be added and such code would polute the board file.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Sean Cross <xobs@kosagi.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>

Showing 4 changed files with 106 additions and 78 deletions Side-by-side Diff

board/kosagi/novena/Makefile
Diff comments   View file @ f2e4d6a
... ... @@ -8,5 +8,6 @@
8 8 obj-y := novena_spl.o
9 9 else
10 10 obj-y := novena.o
  11 +obj-$(CONFIG_VIDEO_IPUV3) += video.o
11 12 endif
board/kosagi/novena/novena.c
Diff comments   View file @ f2e4d6a
... ... @@ -152,87 +152,10 @@
152 152 }
153 153 #endif
154 154  
155   -/*
156   - * Video over HDMI
157   - */
158   -#if defined(CONFIG_VIDEO_IPUV3)
159   -static void enable_hdmi(struct display_info_t const *dev)
160   -{
161   - imx_enable_hdmi_phy();
162   -}
163   -
164   -struct display_info_t const displays[] = {
165   - {
166   - /* HDMI Output */
167   - .bus = -1,
168   - .addr = 0,
169   - .pixfmt = IPU_PIX_FMT_RGB24,
170   - .detect = detect_hdmi,
171   - .enable = enable_hdmi,
172   - .mode = {
173   - .name = "HDMI",
174   - .refresh = 60,
175   - .xres = 1024,
176   - .yres = 768,
177   - .pixclock = 15385,
178   - .left_margin = 220,
179   - .right_margin = 40,
180   - .upper_margin = 21,
181   - .lower_margin = 7,
182   - .hsync_len = 60,
183   - .vsync_len = 10,
184   - .sync = FB_SYNC_EXT,
185   - .vmode = FB_VMODE_NONINTERLACED
186   - }
187   - }
188   -};
189   -
190   -size_t display_count = ARRAY_SIZE(displays);
191   -
192   -static void setup_display(void)
193   -{
194   - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
195   - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
196   -
197   - enable_ipu_clock();
198   - imx_setup_hdmi();
199   -
200   - /* Turn on LDB0,IPU,IPU DI0 clocks */
201   - setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
202   -
203   - /* set LDB0, LDB1 clk select to 011/011 */
204   - clrsetbits_le32(&mxc_ccm->cs2cdr,
205   - MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
206   - MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK,
207   - (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
208   - (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET));
209   -
210   - setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
211   -
212   - setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 <<
213   - MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
214   -
215   - writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
216   - IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
217   - IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
218   - IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
219   - IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
220   - IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
221   - IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
222   - IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
223   - IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
224   - &iomux->gpr[2]);
225   -
226   - clrsetbits_le32(&iomux->gpr[3], IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
227   - IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
228   - IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
229   -}
230   -#endif
231   -
232 155 int board_early_init_f(void)
233 156 {
234 157 #if defined(CONFIG_VIDEO_IPUV3)
235   - setup_display();
  158 + setup_display_clock();
236 159 #endif
237 160  
238 161 return 0;
board/kosagi/novena/novena.h
Diff comments   View file @ f2e4d6a
... ... @@ -20,5 +20,7 @@
20 20 #define NOVENA_SD_CD IMX_GPIO_NR(1, 4)
21 21 #define NOVENA_SD_WP IMX_GPIO_NR(1, 2)
22 22  
  23 +void setup_display_clock(void);
  24 +
23 25 #endif /* __BOARD_KOSAGI_NOVENA_NOVENA_H__ */
board/kosagi/novena/video.c
Diff comments   View file @ f2e4d6a
  1 +/*
  2 + * Novena video output support
  3 + *
  4 + * Copyright (C) 2014 Marek Vasut <marex@denx.de>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <asm/errno.h>
  11 +#include <asm/gpio.h>
  12 +#include <asm/io.h>
  13 +#include <asm/arch/clock.h>
  14 +#include <asm/arch/crm_regs.h>
  15 +#include <asm/arch/imx-regs.h>
  16 +#include <asm/arch/iomux.h>
  17 +#include <asm/arch/mxc_hdmi.h>
  18 +#include <asm/arch/sys_proto.h>
  19 +#include <asm/imx-common/iomux-v3.h>
  20 +#include <asm/imx-common/mxc_i2c.h>
  21 +#include <asm/imx-common/video.h>
  22 +#include <i2c.h>
  23 +#include <input.h>
  24 +#include <ipu_pixfmt.h>
  25 +#include <linux/fb.h>
  26 +#include <linux/input.h>
  27 +#include <malloc.h>
  28 +#include <stdio_dev.h>
  29 +
  30 +#include "novena.h"
  31 +
  32 +static void enable_hdmi(struct display_info_t const *dev)
  33 +{
  34 + imx_enable_hdmi_phy();
  35 +}
  36 +
  37 +struct display_info_t const displays[] = {
  38 + {
  39 + /* HDMI Output */
  40 + .bus = -1,
  41 + .addr = 0,
  42 + .pixfmt = IPU_PIX_FMT_RGB24,
  43 + .detect = detect_hdmi,
  44 + .enable = enable_hdmi,
  45 + .mode = {
  46 + .name = "HDMI",
  47 + .refresh = 60,
  48 + .xres = 1024,
  49 + .yres = 768,
  50 + .pixclock = 15384,
  51 + .left_margin = 220,
  52 + .right_margin = 40,
  53 + .upper_margin = 21,
  54 + .lower_margin = 7,
  55 + .hsync_len = 60,
  56 + .vsync_len = 10,
  57 + .sync = FB_SYNC_EXT,
  58 + .vmode = FB_VMODE_NONINTERLACED
  59 + },
  60 + },
  61 +};
  62 +
  63 +size_t display_count = ARRAY_SIZE(displays);
  64 +
  65 +void setup_display_clock(void)
  66 +{
  67 + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  68 + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  69 +
  70 + enable_ipu_clock();
  71 + imx_setup_hdmi();
  72 +
  73 + /* Turn on LDB0,IPU,IPU DI0 clocks */
  74 + setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
  75 +
  76 + /* set LDB0, LDB1 clk select to 011/011 */
  77 + clrsetbits_le32(&mxc_ccm->cs2cdr,
  78 + MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
  79 + MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK,
  80 + (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
  81 + (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET));
  82 +
  83 + setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
  84 +
  85 + setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 <<
  86 + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  87 +
  88 + writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
  89 + IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
  90 + IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
  91 + IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
  92 + IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
  93 + IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
  94 + IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
  95 + IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
  96 + IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
  97 + &iomux->gpr[2]);
  98 +
  99 + clrsetbits_le32(&iomux->gpr[3], IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
  100 + IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
  101 + IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  102 +}