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Commit f3b84a3032dd989a029320d9512846f48276db95

Authored by Andrew Bradford
Committed by Simon Glass
1 parent 44a8b96f64
Exists in v2017.01-smarct4x and in 30 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

x86: baytrail: Configure FSP UPD from device tree 

Allow for configuration of FSP UPD from the device tree which will
override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD
settings from the Intel FSPv4 Gold release to the respective dts files,
with the condition that the memory-down parameters for MinnowMax are
also used.

Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Removed fsp,mrc-debug-msg and fsp,enable-xhci for minnowmax, bayleybay
Fixed lines >80col
Signed-off-by: Simon Glass <sjg@chromium.org>

Showing 6 changed files with 388 additions and 30 deletions Side-by-side Diff

arch/x86/cpu/baytrail/fsp_configs.c
Diff comments   View file @ f3b84a3
1 1 /*
2 2 * Copyright (C) 2013, Intel Corporation
3 3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
  4 + * Copyright (C) 2015, Kodak Alaris, Inc
4 5 *
5 6 * SPDX-License-Identifier: Intel
6 7 */
7 8  
8 9 #include <common.h>
  10 +#include <fdtdec.h>
9 11 #include <asm/arch/fsp/azalia.h>
10 12 #include <asm/fsp/fsp_support.h>
11 13  
  14 +DECLARE_GLOBAL_DATA_PTR;
  15 +
12 16 /* ALC262 Verb Table - 10EC0262 */
13 17 static const uint32_t verb_table_data13[] = {
14 18 /* Pin Complex (NID 0x11) */
15 19  
16 20  
17 21  
18 22  
19 23  
... ... @@ -116,42 +120,140 @@
116 120 .reset_wait_timer_us = 300
117 121 };
118 122  
  123 +/**
  124 + * Override the FSP's UPD.
  125 + * If the device tree does not specify an integer setting, use the default
  126 + * provided in Intel's Baytrail_FSP_Gold4.tgz release FSP/BayleyBayFsp.bsf file.
  127 + */
119 128 void update_fsp_upd(struct upd_region *fsp_upd)
120 129 {
121 130 struct memory_down_data *mem;
  131 + const void *blob = gd->fdt_blob;
  132 + int node;
122 133  
123   - /*
124   - * Configure everything here to avoid the poor hard-pressed user
125   - * needing to run Intel's binary configuration tool. It may also allow
126   - * us to support the 1GB single core variant easily.
127   - *
128   - * TODO(sjg@chromium.org): Move to device tree
129   - */
130   - fsp_upd->mrc_init_tseg_size = 8;
131   - fsp_upd->mrc_init_mmio_size = 0x800;
132   - fsp_upd->emmc_boot_mode = 0xff;
133   - fsp_upd->enable_sdio = 1;
134   - fsp_upd->enable_sdcard = 1;
135   - fsp_upd->enable_hsuart0 = 1;
136 134 fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
137   - fsp_upd->enable_i2_c0 = 0;
138   - fsp_upd->enable_i2_c2 = 0;
139   - fsp_upd->enable_i2_c3 = 0;
140   - fsp_upd->enable_i2_c4 = 0;
141   - fsp_upd->enable_xhci = 0;
142   - fsp_upd->igd_render_standby = 1;
143 135  
  136 + node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BAYTRAIL_FSP);
  137 + if (node < 0) {
  138 + debug("%s: Cannot find FSP node\n", __func__);
  139 + return;
  140 + }
  141 +
  142 + fsp_upd->mrc_init_tseg_size = fdtdec_get_int(blob, node,
  143 + "fsp,mrc-init-tseg-size",
  144 + 0);
  145 + fsp_upd->mrc_init_mmio_size = fdtdec_get_int(blob, node,
  146 + "fsp,mrc-init-mmio-size",
  147 + 0x800);
  148 + fsp_upd->mrc_init_spd_addr1 = fdtdec_get_int(blob, node,
  149 + "fsp,mrc-init-spd-addr1",
  150 + 0xa0);
  151 + fsp_upd->mrc_init_spd_addr2 = fdtdec_get_int(blob, node,
  152 + "fsp,mrc-init-spd-addr2",
  153 + 0xa2);
  154 + fsp_upd->emmc_boot_mode = fdtdec_get_int(blob, node,
  155 + "fsp,emmc-boot-mode", 2);
  156 + fsp_upd->enable_sdio = fdtdec_get_bool(blob, node, "fsp,enable-sdio");
  157 + fsp_upd->enable_sdcard = fdtdec_get_bool(blob, node,
  158 + "fsp,enable-sdcard");
  159 + fsp_upd->enable_hsuart0 = fdtdec_get_bool(blob, node,
  160 + "fsp,enable-hsuart0");
  161 + fsp_upd->enable_hsuart1 = fdtdec_get_bool(blob, node,
  162 + "fsp,enable-hsuart1");
  163 + fsp_upd->enable_spi = fdtdec_get_bool(blob, node, "fsp,enable-spi");
  164 + fsp_upd->enable_sata = fdtdec_get_bool(blob, node, "fsp,enable-sata");
  165 + fsp_upd->sata_mode = fdtdec_get_int(blob, node, "fsp,sata-mode", 1);
  166 + fsp_upd->enable_azalia = fdtdec_get_bool(blob, node,
  167 + "fsp,enable-azalia");
  168 + fsp_upd->enable_xhci = fdtdec_get_bool(blob, node, "fsp,enable-xhci");
  169 + fsp_upd->enable_lpe = fdtdec_get_bool(blob, node, "fsp,enable-lpe");
  170 + fsp_upd->lpss_sio_enable_pci_mode = fdtdec_get_bool(blob, node,
  171 + "fsp,lpss-sio-enable-pci-mode");
  172 + fsp_upd->enable_dma0 = fdtdec_get_bool(blob, node, "fsp,enable-dma0");
  173 + fsp_upd->enable_dma1 = fdtdec_get_bool(blob, node, "fsp,enable-dma1");
  174 + fsp_upd->enable_i2_c0 = fdtdec_get_bool(blob, node, "fsp,enable-i2c0");
  175 + fsp_upd->enable_i2_c1 = fdtdec_get_bool(blob, node, "fsp,enable-i2c1");
  176 + fsp_upd->enable_i2_c2 = fdtdec_get_bool(blob, node, "fsp,enable-i2c2");
  177 + fsp_upd->enable_i2_c3 = fdtdec_get_bool(blob, node, "fsp,enable-i2c3");
  178 + fsp_upd->enable_i2_c4 = fdtdec_get_bool(blob, node, "fsp,enable-i2c4");
  179 + fsp_upd->enable_i2_c5 = fdtdec_get_bool(blob, node, "fsp,enable-i2c5");
  180 + fsp_upd->enable_i2_c6 = fdtdec_get_bool(blob, node, "fsp,enable-i2c6");
  181 + fsp_upd->enable_pwm0 = fdtdec_get_bool(blob, node, "fsp,enable-pwm0");
  182 + fsp_upd->enable_pwm1 = fdtdec_get_bool(blob, node, "fsp,enable-pwm1");
  183 + fsp_upd->enable_hsi = fdtdec_get_bool(blob, node, "fsp,enable-hsi");
  184 + fsp_upd->igd_dvmt50_pre_alloc = fdtdec_get_int(blob, node,
  185 + "fsp,igd-dvmt50-pre-alloc", 2);
  186 + fsp_upd->aperture_size = fdtdec_get_int(blob, node, "fsp,aperture-size",
  187 + 2);
  188 + fsp_upd->gtt_size = fdtdec_get_int(blob, node, "fsp,gtt-size", 2);
  189 + fsp_upd->serial_debug_port_address = fdtdec_get_int(blob, node,
  190 + "fsp,serial-debug-port-address", 0x3f8);
  191 + fsp_upd->serial_debug_port_type = fdtdec_get_int(blob, node,
  192 + "fsp,serial-debug-port-type", 1);
  193 + fsp_upd->mrc_debug_msg = fdtdec_get_bool(blob, node,
  194 + "fsp,mrc-debug-msg");
  195 + fsp_upd->isp_enable = fdtdec_get_bool(blob, node, "fsp,isp-enable");
  196 + fsp_upd->scc_enable_pci_mode = fdtdec_get_bool(blob, node,
  197 + "fsp,scc-enable-pci-mode");
  198 + fsp_upd->igd_render_standby = fdtdec_get_bool(blob, node,
  199 + "fsp,igd-render-standby");
  200 + fsp_upd->txe_uma_enable = fdtdec_get_bool(blob, node,
  201 + "fsp,txe-uma-enable");
  202 + fsp_upd->os_selection = fdtdec_get_int(blob, node, "fsp,os-selection",
  203 + 4);
  204 + fsp_upd->emmc45_ddr50_enabled = fdtdec_get_bool(blob, node,
  205 + "fsp,emmc45-ddr50-enabled");
  206 + fsp_upd->emmc45_hs200_enabled = fdtdec_get_bool(blob, node,
  207 + "fsp,emmc45-hs200-enabled");
  208 + fsp_upd->emmc45_retune_timer_value = fdtdec_get_int(blob, node,
  209 + "fsp,emmc45-retune-timer-value", 8);
  210 + fsp_upd->enable_igd = fdtdec_get_bool(blob, node, "fsp,enable-igd");
  211 +
144 212 mem = &fsp_upd->memory_params;
145   - mem->enable_memory_down = 1;
146   - mem->dram_speed = 1;
147   - mem->dimm_width = 1;
148   - mem->dimm_density = 2;
149   - mem->dimm_tcl = 0xb;
150   - mem->dimm_trpt_rcd = 0xb;
151   - mem->dimm_twr = 0xc;
152   - mem->dimm_twtr = 6;
153   - mem->dimm_trrd = 6;
154   - mem->dimm_trtp = 6;
155   - mem->dimm_tfaw = 0x14;
  213 + mem->enable_memory_down = fdtdec_get_bool(blob, node,
  214 + "fsp,enable-memory-down");
  215 + if (mem->enable_memory_down) {
  216 + node = fdtdec_next_compatible(blob, node,
  217 + COMPAT_INTEL_BAYTRAIL_FSP_MDP);
  218 + if (node < 0) {
  219 + debug("%s: Cannot find FSP memory-down-params node\n",
  220 + __func__);
  221 + } else {
  222 + mem->dram_speed = fdtdec_get_int(blob, node,
  223 + "fsp,dram-speed",
  224 + 0x02);
  225 + mem->dram_type = fdtdec_get_int(blob, node,
  226 + "fsp,dram-type", 0x01);
  227 + mem->dimm_0_enable = fdtdec_get_bool(blob, node,
  228 + "fsp,dimm-0-enable");
  229 + mem->dimm_1_enable = fdtdec_get_bool(blob, node,
  230 + "fsp,dimm-1-enable");
  231 + mem->dimm_width = fdtdec_get_int(blob, node,
  232 + "fsp,dimm-width",
  233 + 0x00);
  234 + mem->dimm_density = fdtdec_get_int(blob, node,
  235 + "fsp,dimm-density",
  236 + 0x01);
  237 + mem->dimm_bus_width = fdtdec_get_int(blob, node,
  238 + "fsp,dimm-bus-width", 0x03);
  239 + mem->dimm_sides = fdtdec_get_int(blob, node,
  240 + "fsp,dimm-sides",
  241 + 0x00);
  242 + mem->dimm_tcl = fdtdec_get_int(blob, node,
  243 + "fsp,dimm-tcl", 0x09);
  244 + mem->dimm_trpt_rcd = fdtdec_get_int(blob, node,
  245 + "fsp,dimm-trpt-rcd", 0x09);
  246 + mem->dimm_twr = fdtdec_get_int(blob, node,
  247 + "fsp,dimm-twr", 0x0A);
  248 + mem->dimm_twtr = fdtdec_get_int(blob, node,
  249 + "fsp,dimm-twtr", 0x05);
  250 + mem->dimm_trrd = fdtdec_get_int(blob, node,
  251 + "fsp,dimm-trrd", 0x04);
  252 + mem->dimm_trtp = fdtdec_get_int(blob, node,
  253 + "fsp,dimm-trtp", 0x05);
  254 + mem->dimm_tfaw = fdtdec_get_int(blob, node,
  255 + "fsp,dimm-tfaw", 0x14);
  256 + }
  257 + }
156 258 }
arch/x86/dts/bayleybay.dts
Diff comments   View file @ f3b84a3
... ... @@ -188,6 +188,44 @@
188 188 };
189 189 };
190 190  
  191 + fsp {
  192 + compatible = "intel,baytrail-fsp";
  193 + fsp,mrc-init-tseg-size = <0>;
  194 + fsp,mrc-init-mmio-size = <0x800>;
  195 + fsp,mrc-init-spd-addr1 = <0xa0>;
  196 + fsp,mrc-init-spd-addr2 = <0xa2>;
  197 + fsp,emmc-boot-mode = <2>;
  198 + fsp,enable-sdio;
  199 + fsp,enable-sdcard;
  200 + fsp,enable-hsuart1;
  201 + fsp,enable-spi;
  202 + fsp,enable-sata;
  203 + fsp,sata-mode = <1>;
  204 + fsp,enable-lpe;
  205 + fsp,lpss-sio-enable-pci-mode;
  206 + fsp,enable-dma0;
  207 + fsp,enable-dma1;
  208 + fsp,enable-i2c0;
  209 + fsp,enable-i2c1;
  210 + fsp,enable-i2c2;
  211 + fsp,enable-i2c3;
  212 + fsp,enable-i2c4;
  213 + fsp,enable-i2c5;
  214 + fsp,enable-i2c6;
  215 + fsp,enable-pwm0;
  216 + fsp,enable-pwm1;
  217 + fsp,igd-dvmt50-pre-alloc = <2>;
  218 + fsp,aperture-size = <2>;
  219 + fsp,gtt-size = <2>;
  220 + fsp,serial-debug-port-address = <0x3f8>;
  221 + fsp,serial-debug-port-type = <1>;
  222 + fsp,scc-enable-pci-mode;
  223 + fsp,os-selection = <4>;
  224 + fsp,emmc45-ddr50-enabled;
  225 + fsp,emmc45-retune-timer-value = <8>;
  226 + fsp,enable-igd;
  227 + };
  228 +
191 229 microcode {
192 230 update@0 {
193 231 #include "microcode/m0230671117.dtsi"
arch/x86/dts/minnowmax.dts
Diff comments   View file @ f3b84a3
... ... @@ -122,6 +122,62 @@
122 122 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
123 123 };
124 124  
  125 + fsp {
  126 + compatible = "intel,baytrail-fsp";
  127 + fsp,mrc-init-tseg-size = <0>;
  128 + fsp,mrc-init-mmio-size = <0x800>;
  129 + fsp,mrc-init-spd-addr1 = <0xa0>;
  130 + fsp,mrc-init-spd-addr2 = <0xa2>;
  131 + fsp,emmc-boot-mode = <2>;
  132 + fsp,enable-sdio;
  133 + fsp,enable-sdcard;
  134 + fsp,enable-hsuart1;
  135 + fsp,enable-spi;
  136 + fsp,enable-sata;
  137 + fsp,sata-mode = <1>;
  138 + fsp,enable-lpe;
  139 + fsp,lpss-sio-enable-pci-mode;
  140 + fsp,enable-dma0;
  141 + fsp,enable-dma1;
  142 + fsp,enable-i2c0;
  143 + fsp,enable-i2c1;
  144 + fsp,enable-i2c2;
  145 + fsp,enable-i2c3;
  146 + fsp,enable-i2c4;
  147 + fsp,enable-i2c5;
  148 + fsp,enable-i2c6;
  149 + fsp,enable-pwm0;
  150 + fsp,enable-pwm1;
  151 + fsp,igd-dvmt50-pre-alloc = <2>;
  152 + fsp,aperture-size = <2>;
  153 + fsp,gtt-size = <2>;
  154 + fsp,serial-debug-port-address = <0x3f8>;
  155 + fsp,serial-debug-port-type = <1>;
  156 + fsp,scc-enable-pci-mode;
  157 + fsp,os-selection = <4>;
  158 + fsp,emmc45-ddr50-enabled;
  159 + fsp,emmc45-retune-timer-value = <8>;
  160 + fsp,enable-igd;
  161 + fsp,enable-memory-down;
  162 + fsp,memory-down-params {
  163 + compatible = "intel,baytrail-fsp-mdp";
  164 + fsp,dram-speed = <1>;
  165 + fsp,dram-type = <1>;
  166 + fsp,dimm-0-enable;
  167 + fsp,dimm-width = <1>;
  168 + fsp,dimm-density = <2>;
  169 + fsp,dimm-bus-width = <3>;
  170 + fsp,dimm-sides = <0>;
  171 + fsp,dimm-tcl = <0xb>;
  172 + fsp,dimm-trpt-rcd = <0xb>;
  173 + fsp,dimm-twr = <0xc>;
  174 + fsp,dimm-twtr = <6>;
  175 + fsp,dimm-trrd = <6>;
  176 + fsp,dimm-trtp = <6>;
  177 + fsp,dimm-tfaw = <0x14>;
  178 + };
  179 + };
  180 +
125 181 spi {
126 182 #address-cells = <1>;
127 183 #size-cells = <0>;
doc/device-tree-bindings/misc/intel,baytrail-fsp.txt
Diff comments   View file @ f3b84a3
  1 +Intel Bay Trail FSP UPD Binding
  2 +===============================
  3 +
  4 +The device tree node which describes the overriding of the Intel Bay Trail FSP
  5 +UPD data for configuring the SoC.
  6 +
  7 +All properties can be found within the `upd-region` struct in
  8 +arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h, under the same names, and in
  9 +Intel's FSP Binary Configuration Tool for Bay Trail. This list of properties is
  10 +matched up to Intel's E3800 FSPv4 release.
  11 +
  12 +# Boolean properties:
  13 +
  14 +- fsp,enable-sdio
  15 +- fsp,enable-sdcard
  16 +- fsp,enable-hsuart0
  17 +- fsp,enable-hsuart1
  18 +- fsp,enable-spi
  19 +- fsp,enable-sata
  20 +- fsp,enable-azalia
  21 +- fsp,enable-xhci
  22 +- fsp,enable-lpe
  23 +- fsp,lpss-sio-enable-pci-mode
  24 +- fsp,enable-dma0
  25 +- fsp,enable-dma1
  26 +- fsp,enable-i2-c0
  27 +- fsp,enable-i2-c1
  28 +- fsp,enable-i2-c2
  29 +- fsp,enable-i2-c3
  30 +- fsp,enable-i2-c4
  31 +- fsp,enable-i2-c5
  32 +- fsp,enable-i2-c6
  33 +- fsp,enable-pwm0
  34 +- fsp,enable-pwm1
  35 +- fsp,enable-hsi
  36 +- fsp,mrc-debug-msg
  37 +- fsp,isp-enable
  38 +- fsp,scc-enable-pci-mode
  39 +- fsp,igd-render-standby
  40 +- fsp,txe-uma-enable
  41 +- fsp,emmc45-ddr50-enabled
  42 +- fsp,emmc45-hs200-enabled
  43 +- fsp,enable-igd
  44 +- fsp,enable-memory-down
  45 +
  46 +If you set "fsp,enable-memory-down" you are strongly encouraged to provide an
  47 +"fsp,memory-down-params{};" to specify how your memory is configured. If you do
  48 +not set "fsp,enable-memory-down", then the DIMM SPD information will be
  49 +discovered by the FSP and used to setup main memory.
  50 +
  51 +
  52 +# Integer properties:
  53 +
  54 +- fsp,mrc-init-tseg-size
  55 +- fsp,mrc-init-mmio-size
  56 +- fsp,mrc-init-spd-addr1
  57 +- fsp,mrc-init-spd-addr2
  58 +- fsp,emmc-boot-mode
  59 +- fsp,sata-mode
  60 +- fsp,igd-dvmt50-pre-alloc
  61 +- fsp,aperture-size
  62 +- fsp,gtt-size
  63 +- fsp,serial-debug-port-address
  64 +- fsp,serial-debug-port-type
  65 +- fsp,os-selection
  66 +- fsp,emmc45-retune-timer-value
  67 +
  68 +- fsp,memory-down-params {
  69 +
  70 + # Boolean properties:
  71 +
  72 + - fsp,dimm-0-enable
  73 + - fsp,dimm-1-enable
  74 +
  75 + # Integer properties:
  76 +
  77 + - fsp,dram-speed
  78 + - fsp,dram-type
  79 + - fsp,dimm-width
  80 + - fsp,dimm-density
  81 + - fsp,dimm-bus-width
  82 + - fsp,dimm-sides
  83 + - fsp,dimm-tcl
  84 + - fsp,dimm-trpt-rcd
  85 + - fsp,dimm-twr
  86 + - fsp,dimm-twtr
  87 + - fsp,dimm-trrd
  88 + - fsp,dimm-trtp
  89 + - fsp,dimm-tfaw
  90 +};
  91 +
  92 +
  93 +Example (from MinnowMax Dual Core):
  94 +-----------------------------------
  95 +
  96 +/ {
  97 + ...
  98 +
  99 + fsp {
  100 + compatible = "intel,baytrail-fsp";
  101 + fsp,mrc-init-tseg-size = <0>;
  102 + fsp,mrc-init-mmio-size = <0x800>;
  103 + fsp,mrc-init-spd-addr1 = <0xa0>;
  104 + fsp,mrc-init-spd-addr2 = <0xa2>;
  105 + fsp,emmc-boot-mode = <2>;
  106 + fsp,enable-sdio;
  107 + fsp,enable-sdcard;
  108 + fsp,enable-hsuart1;
  109 + fsp,enable-spi;
  110 + fsp,enable-sata;
  111 + fsp,sata-mode = <1>;
  112 + fsp,enable-xhci;
  113 + fsp,enable-lpe;
  114 + fsp,lpss-sio-enable-pci-mode;
  115 + fsp,enable-dma0;
  116 + fsp,enable-dma1;
  117 + fsp,enable-i2c0;
  118 + fsp,enable-i2c1;
  119 + fsp,enable-i2c2;
  120 + fsp,enable-i2c3;
  121 + fsp,enable-i2c4;
  122 + fsp,enable-i2c5;
  123 + fsp,enable-i2c6;
  124 + fsp,enable-pwm0;
  125 + fsp,enable-pwm1;
  126 + fsp,igd-dvmt50-pre-alloc = <2>;
  127 + fsp,aperture-size = <2>;
  128 + fsp,gtt-size = <2>;
  129 + fsp,serial-debug-port-address = <0x3f8>;
  130 + fsp,serial-debug-port-type = <1>;
  131 + fsp,mrc-debug-msg;
  132 + fsp,scc-enable-pci-mode;
  133 + fsp,os-selection = <4>;
  134 + fsp,emmc45-ddr50-enabled;
  135 + fsp,emmc45-retune-timer-value = <8>;
  136 + fsp,enable-igd;
  137 + fsp,enable-memory-down;
  138 + fsp,memory-down-params {
  139 + compatible = "intel,baytrail-fsp-mdp";
  140 + fsp,dram-speed = <1>;
  141 + fsp,dram-type = <1>;
  142 + fsp,dimm-0-enable;
  143 + fsp,dimm-width = <1>;
  144 + fsp,dimm-density = <2>;
  145 + fsp,dimm-bus-width = <3>;
  146 + fsp,dimm-sides = <0>;
  147 + fsp,dimm-tcl = <0xb>;
  148 + fsp,dimm-trpt-rcd = <0xb>;
  149 + fsp,dimm-twr = <0xc>;
  150 + fsp,dimm-twtr = <6>;
  151 + fsp,dimm-trrd = <6>;
  152 + fsp,dimm-trtp = <6>;
  153 + fsp,dimm-tfaw = <0x14>;
  154 + };
  155 + };
  156 +
  157 + ...
  158 +};
... ... @@ -182,6 +182,8 @@
182 182 COMPAT_INTEL_PCH, /* Intel PCH */
183 183 COMPAT_INTEL_IRQ_ROUTER, /* Intel Interrupt Router */
184 184 COMPAT_ALTERA_SOCFPGA_DWMAC, /* SoCFPGA Ethernet controller */
  185 + COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */
  186 + COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */
185 187  
186 188 COMPAT_COUNT,
187 189 };
... ... @@ -76,6 +76,8 @@
76 76 COMPAT(COMPAT_INTEL_PCH, "intel,bd82x6x"),
77 77 COMPAT(COMPAT_INTEL_IRQ_ROUTER, "intel,irq-router"),
78 78 COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"),
  79 + COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
  80 + COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
79 81 };
80 82  
81 83 const char *fdtdec_get_compatible(enum fdt_compat_id id)