Commit f3ce250d96588d96bd4148883455e00ea14adca5
Committed by
Wolfgang Denk
Wolfgang Denk
1 parent
f1371048ab
Exists in
master
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54 other branches
mpc8308: add SICR{L,H} fields definitions
This patch adds defines to set supported fields in System I/O Configuration Registers High and Low on Freescale MPC8308 CPU. Signed-off-by: Ilya Yanok <yanok@emcraft.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Showing 1 changed file with 48 additions and 0 deletions Side-by-side Diff
include/mpc83xx.h
| ... | ... | @@ -319,6 +319,54 @@ |
| 319 | 319 | #define SICRH_GPIO2_H 0x00000030 |
| 320 | 320 | #define SICRH_SPI 0x00000003 |
| 321 | 321 | #define SICRH_SPI_SD 0x00000001 |
| 322 | + | |
| 323 | +#elif defined(CONFIG_MPC8308) | |
| 324 | +/* SICRL bits - MPC8308 specific */ | |
| 325 | +#define SICRL_SPI_PF0 (0 << 28) | |
| 326 | +#define SICRL_SPI_PF1 (1 << 28) | |
| 327 | +#define SICRL_SPI_PF3 (3 << 28) | |
| 328 | +#define SICRL_UART_PF0 (0 << 26) | |
| 329 | +#define SICRL_UART_PF1 (1 << 26) | |
| 330 | +#define SICRL_UART_PF3 (3 << 26) | |
| 331 | +#define SICRL_IRQ_PF0 (0 << 24) | |
| 332 | +#define SICRL_IRQ_PF1 (1 << 24) | |
| 333 | +#define SICRL_I2C2_PF0 (0 << 20) | |
| 334 | +#define SICRL_I2C2_PF1 (1 << 20) | |
| 335 | +#define SICRL_ETSEC1_TX_CLK (0 << 6) | |
| 336 | +#define SICRL_ETSEC1_GTX_CLK125 (1 << 6) | |
| 337 | + | |
| 338 | +/* SICRH bits - MPC8308 specific */ | |
| 339 | +#define SICRH_ESDHC_A_SD (0 << 30) | |
| 340 | +#define SICRH_ESDHC_A_GTM (1 << 30) | |
| 341 | +#define SICRH_ESDHC_A_GPIO (3 << 30) | |
| 342 | +#define SICRH_ESDHC_B_SD (0 << 28) | |
| 343 | +#define SICRH_ESDHC_B_GTM (1 << 28) | |
| 344 | +#define SICRH_ESDHC_B_GPIO (3 << 28) | |
| 345 | +#define SICRH_ESDHC_C_SD (0 << 26) | |
| 346 | +#define SICRH_ESDHC_C_GTM (1 << 26) | |
| 347 | +#define SICRH_ESDHC_C_GPIO (3 << 26) | |
| 348 | +#define SICRH_GPIO_A_GPIO (0 << 24) | |
| 349 | +#define SICRH_GPIO_A_TSEC2 (1 << 24) | |
| 350 | +#define SICRH_GPIO_B_GPIO (0 << 22) | |
| 351 | +#define SICRH_GPIO_B_TSEC2_TX_CLK (1 << 22) | |
| 352 | +#define SICRH_GPIO_B_TSEC2_GTX_CLK125 (2 << 22) | |
| 353 | +#define SICRH_IEEE1588_A_TMR (1 << 20) | |
| 354 | +#define SICRH_IEEE1588_A_GPIO (3 << 20) | |
| 355 | +#define SICRH_USB (1 << 18) | |
| 356 | +#define SICRH_GTM_GTM (1 << 16) | |
| 357 | +#define SICRH_GTM_GPIO (3 << 16) | |
| 358 | +#define SICRH_IEEE1588_B_TMR (1 << 14) | |
| 359 | +#define SICRH_IEEE1588_B_GPIO (3 << 14) | |
| 360 | +#define SICRH_ETSEC2_CRS (1 << 12) | |
| 361 | +#define SICRH_ETSEC2_GPIO (3 << 12) | |
| 362 | +#define SICRH_GPIOSEL_0 (0 << 8) | |
| 363 | +#define SICRH_GPIOSEL_1 (1 << 8) | |
| 364 | +#define SICRH_TMROBI_V3P3 (0 << 4) | |
| 365 | +#define SICRH_TMROBI_V2P5 (1 << 4) | |
| 366 | +#define SICRH_TSOBI1_V3P3 (0 << 1) | |
| 367 | +#define SICRH_TSOBI1_V2P5 (1 << 1) | |
| 368 | +#define SICRH_TSOBI2_V3P3 (0 << 0) | |
| 369 | +#define SICRH_TSOBI2_V2P5 (1 << 0) | |
| 322 | 370 | #endif |
| 323 | 371 | |
| 324 | 372 | /* SWCRR - System Watchdog Control Register |