Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit f42b2f606161d0051c14ccaccdc7fdef4bb2fc96

Authored by Nikita Kiryanov
Committed by Stefano Babic
1 parent 0f3effb99f
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: mx6: cm_fx6: add i2c support 

Add support for all 3 I2C busses on Compulab CM-FX6 CoM.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>

Showing 2 changed files with 53 additions and 0 deletions Side-by-side Diff

board/compulab/cm_fx6/cm_fx6.c
Diff comments   View file @ f42b2f6
... ... @@ -16,12 +16,53 @@
16 16 #include <asm/arch/crm_regs.h>
17 17 #include <asm/arch/sys_proto.h>
18 18 #include <asm/arch/iomux.h>
  19 +#include <asm/imx-common/mxc_i2c.h>
19 20 #include <asm/io.h>
20 21 #include <asm/gpio.h>
21 22 #include "common.h"
22 23  
23 24 DECLARE_GLOBAL_DATA_PTR;
24 25  
  26 +#ifdef CONFIG_SYS_I2C_MXC
  27 +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  28 + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  29 + PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  30 +
  31 +I2C_PADS(i2c0_pads,
  32 + PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
  33 + PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  34 + IMX_GPIO_NR(3, 21),
  35 + PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
  36 + PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  37 + IMX_GPIO_NR(3, 28));
  38 +
  39 +I2C_PADS(i2c1_pads,
  40 + PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
  41 + PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  42 + IMX_GPIO_NR(4, 12),
  43 + PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
  44 + PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  45 + IMX_GPIO_NR(4, 13));
  46 +
  47 +I2C_PADS(i2c2_pads,
  48 + PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
  49 + PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  50 + IMX_GPIO_NR(1, 3),
  51 + PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
  52 + PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  53 + IMX_GPIO_NR(1, 6));
  54 +
  55 +
  56 +static void cm_fx6_setup_i2c(void)
  57 +{
  58 + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c0_pads));
  59 + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c1_pads));
  60 + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c2_pads));
  61 +}
  62 +#else
  63 +static void cm_fx6_setup_i2c(void) { }
  64 +#endif
  65 +
25 66 #ifdef CONFIG_USB_EHCI_MX6
26 67 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
27 68 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
... ... @@ -259,6 +300,7 @@
259 300 {
260 301 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
261 302 cm_fx6_setup_gpmi_nand();
  303 + cm_fx6_setup_i2c();
262 304  
263 305 return 0;
264 306 }
include/configs/cm_fx6.h
Diff comments   View file @ f42b2f6
... ... @@ -210,6 +210,17 @@
210 210 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
211 211 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
212 212  
  213 +/* I2C */
  214 +#define CONFIG_CMD_I2C
  215 +#define CONFIG_SYS_I2C
  216 +#define CONFIG_SYS_I2C_MXC
  217 +#define CONFIG_SYS_I2C_SPEED 100000
  218 +#define CONFIG_SYS_MXC_I2C3_SPEED 400000
  219 +
  220 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  221 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  222 +#define CONFIG_SYS_I2C_EEPROM_BUS 2
  223 +
213 224 /* GPIO */
214 225 #define CONFIG_MXC_GPIO
215 226