Eric Lee / smarc-uboot

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Commit f4733a0764741966a5e842968166b40fb062d577

Authored by wdenk
1 parent b05dcb58fe
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Add port initialization for digital I/O on INKA4x0

Showing 5 changed files with 59 additions and 17 deletions Side-by-side Diff

... ... @@ -2,6 +2,8 @@
2 2 Changes for U-Boot 1.1.3:
3 3 ======================================================================
4 4  
  5 +* Add port initialization for digital I/O on INKA4x0
  6 +
5 7 * Patch by Stefan Roese, 01 March 2005:
6 8 Update for esd boards dp405 and hub405
7 9  
board/inka4x0/inka4x0.c
Diff comments   View file @ f4733a0
... ... @@ -43,13 +43,11 @@
43 43 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
44 44  
45 45 /* unlock mode register */
46   - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
47   - hi_addr_bit;
  46 + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
48 47 __asm__ volatile ("sync");
49 48  
50 49 /* precharge all banks */
51   - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
52   - hi_addr_bit;
  50 + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
53 51 __asm__ volatile ("sync");
54 52  
55 53 #if SDRAM_DDR
56 54  
... ... @@ -63,13 +61,11 @@
63 61 #endif
64 62  
65 63 /* precharge all banks */
66   - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
67   - hi_addr_bit;
  64 + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
68 65 __asm__ volatile ("sync");
69 66  
70 67 /* auto refresh */
71   - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
72   - hi_addr_bit;
  68 + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
73 69 __asm__ volatile ("sync");
74 70  
75 71 /* set mode register */
76 72  
77 73  
78 74  
79 75  
... ... @@ -177,27 +173,51 @@
177 173 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
178 174 }
179 175  
180   -#define GPIO_PSC3_9 0x04000000UL
  176 +#define GPIO_PSC3_9 0x04000000UL
181 177  
182 178 int misc_init_f (void)
183 179 {
  180 + /* Initialize GPIO output pins.
  181 + */
  182 + /* Configure GPT as GPIO output */
  183 + *(vu_long *)MPC5XXX_GPT0_ENABLE =
  184 + *(vu_long *)MPC5XXX_GPT1_ENABLE =
  185 + *(vu_long *)MPC5XXX_GPT2_ENABLE =
  186 + *(vu_long *)MPC5XXX_GPT3_ENABLE =
  187 + *(vu_long *)MPC5XXX_GPT4_ENABLE =
  188 + *(vu_long *)MPC5XXX_GPT5_ENABLE = 0x24;
  189 +
  190 +
  191 + /* Configure PSC3_6,7 as GPIO output */
  192 + *(vu_long *)MPC5XXX_GPIO_ENABLE |= 0x00003000;
  193 + *(vu_long *)MPC5XXX_GPIO_DIR |= 0x00003000;
  194 +
  195 + /* Configure PSC3_8 as GPIO output, no interrupt */
  196 + *(vu_long *)MPC5XXX_GPIO_SI_ENABLE |= 0x04000000;
  197 + *(vu_long *)MPC5XXX_GPIO_SI_DIR |= 0x04000000;
  198 + *(vu_long *)MPC5XXX_GPIO_SI_IEN &= ~0x04000000;
  199 +
  200 + /* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
  201 + *(vu_long *)MPC5XXX_WU_GPIO_ENABLE |= 0xc4000000;
  202 + *(vu_long *)MPC5XXX_WU_GPIO_DIR |= 0xc4000000;
  203 +
184 204 /*
185 205 * Reset Coral-P graphics controller
186 206 */
187   - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
188   - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
189   - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC3_9;
190   - return 0;
  207 + *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
  208 + *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
  209 + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC3_9;
  210 + return 0;
191 211 }
192 212  
193   -#ifdef CONFIG_PCI
  213 +#ifdef CONFIG_PCI
194 214 static struct pci_controller hose;
195 215  
196 216 extern void pci_mpc5xxx_init(struct pci_controller *);
197 217  
198 218 void pci_init_board(void)
199 219 {
200   - pci_mpc5xxx_init(&hose);
  220 + pci_mpc5xxx_init(&hose);
201 221 }
202 222 #endif
203 223  
... ... @@ -209,7 +229,7 @@
209 229 {
210 230 debug ("init_ide_reset\n");
211 231  
212   - /* Configure PSC1_4 as GPIO output for ATA reset */
  232 + /* Configure PSC1_4 as GPIO output for ATA reset */
213 233 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
214 234 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
215 235 /* Deassert reset */
... ... @@ -871,7 +871,7 @@
871 871 dbuf+=1;
872 872 }
873 873 }
874   -#else
  874 +#else
875 875 volatile ushort *pbuf = (ushort *)(ATA_CURR_BASE(dev)+ATA_DATA_REG);
876 876 ushort *dbuf = (ushort *)sect_buf;
877 877  
include/configs/inka4x0.h
Diff comments   View file @ f4733a0
... ... @@ -274,6 +274,11 @@
274 274 #define CFG_CS2_SIZE 0x0001000
275 275 #define CFG_CS2_CFG 0x21800 /* for pci_clk = 33 MHz */
276 276  
  277 +/* GPIO in @0x30400000 */
  278 +#define CFG_CS3_START 0x30400000
  279 +#define CFG_CS3_SIZE 0x00100000
  280 +#define CFG_CS3_CFG 0x31800 /* for pci_clk = 33 MHz */
  281 +
277 282 #define CFG_CS_BURST 0x00000000
278 283 #define CFG_CS_DEADCYCLE 0x33333333
279 284  
... ... @@ -233,6 +233,21 @@
233 233 /* General Purpose Timers registers */
234 234 #define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0)
235 235 #define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4)
  236 +#define MPC5XXX_GPT1_ENABLE (MPC5XXX_GPT + 0x10)
  237 +#define MPC5XXX_GPT1_COUNTER (MPC5XXX_GPT + 0x14)
  238 +#define MPC5XXX_GPT2_ENABLE (MPC5XXX_GPT + 0x20)
  239 +#define MPC5XXX_GPT2_COUNTER (MPC5XXX_GPT + 0x24)
  240 +#define MPC5XXX_GPT3_ENABLE (MPC5XXX_GPT + 0x30)
  241 +#define MPC5XXX_GPT3_COUNTER (MPC5XXX_GPT + 0x34)
  242 +#define MPC5XXX_GPT4_ENABLE (MPC5XXX_GPT + 0x40)
  243 +#define MPC5XXX_GPT4_COUNTER (MPC5XXX_GPT + 0x44)
  244 +#define MPC5XXX_GPT5_ENABLE (MPC5XXX_GPT + 0x50)
  245 +#define MPC5XXX_GPT5_COUNTER (MPC5XXX_GPT + 0x54)
  246 +#define MPC5XXX_GPT6_ENABLE (MPC5XXX_GPT + 0x60)
  247 +#define MPC5XXX_GPT6_COUNTER (MPC5XXX_GPT + 0x64)
  248 +#define MPC5XXX_GPT7_ENABLE (MPC5XXX_GPT + 0x70)
  249 +#define MPC5XXX_GPT7_COUNTER (MPC5XXX_GPT + 0x74)
  250 +
236 251  
237 252 /* ATA registers */
238 253 #define MPC5XXX_ATA_HOST_CONFIG (MPC5XXX_ATA + 0x0000)