Eric Lee / smarc-uboot

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Commit f49b8c1b5d9db6d349000b25312c672a1f6627b8

Authored by tang yuantian
Committed by York Sun
1 parent 026f64f636
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

mpc85xx/t102xrdb: convert deep sleep to generic board interface 

A new deep sleep interface is introduced to support generic
board structure. Converts it to use new interface.

Besides, added SPI/SD/NAND boot deep sleep support.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

Showing 4 changed files with 49 additions and 21 deletions Side-by-side Diff

board/freescale/t102xrdb/ddr.c
Diff comments   View file @ f49b8c1
... ... @@ -11,6 +11,7 @@
11 11 #include <fsl_ddr_sdram.h>
12 12 #include <fsl_ddr_dimm_params.h>
13 13 #include <asm/fsl_law.h>
  14 +#include <asm/mpc85xx_gpio.h>
14 15  
15 16 DECLARE_GLOBAL_DATA_PTR;
16 17  
... ... @@ -136,6 +137,19 @@
136 137 #endif
137 138 }
138 139  
  140 +#if defined(CONFIG_DEEP_SLEEP)
  141 +void board_mem_sleep_setup(void)
  142 +{
  143 + void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
  144 +
  145 + /* does not provide HW signals for power management */
  146 + clrbits_8(cpld_base + 0x17, 0x40);
  147 + /* Disable MCKE isolation */
  148 + gpio_set_value(2, 0);
  149 + udelay(1);
  150 +}
  151 +#endif
  152 +
139 153 phys_size_t initdram(int board_type)
140 154 {
141 155 phys_size_t dram_size;
... ... @@ -150,6 +164,11 @@
150 164 /* DDR has been initialised by first stage boot loader */
151 165 dram_size = fsl_ddr_sdram_size();
152 166 #endif
  167 +
  168 +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
  169 + fsl_dp_resume();
  170 +#endif
  171 +
153 172 return dram_size;
154 173 }
board/freescale/t102xrdb/spl.c
Diff comments   View file @ f49b8c1
... ... @@ -11,6 +11,7 @@
11 11 #include <mmc.h>
12 12 #include <fsl_esdhc.h>
13 13 #include <spi_flash.h>
  14 +#include "../common/sleep.h"
14 15  
15 16 DECLARE_GLOBAL_DATA_PTR;
16 17  
... ... @@ -41,6 +42,12 @@
41 42 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
42 43  
43 44 console_init_f();
  45 +
  46 +#ifdef CONFIG_DEEP_SLEEP
  47 + /* disable the console if boot from deep sleep */
  48 + if (is_warm_boot())
  49 + fsl_dp_disable_console();
  50 +#endif
44 51  
45 52 /* initialize selected port with appropriate baud rate */
46 53 sys_clk = get_board_sys_clk();
board/freescale/t102xrdb/t102xrdb.c
Diff comments   View file @ f49b8c1
... ... @@ -16,10 +16,10 @@
16 16 #include <asm/fsl_serdes.h>
17 17 #include <asm/fsl_portals.h>
18 18 #include <asm/fsl_liodn.h>
19   -#include <asm/mpc85xx_gpio.h>
20 19 #include <fm_eth.h>
21 20 #include "t102xrdb.h"
22 21 #include "cpld.h"
  22 +#include "../common/sleep.h"
23 23  
24 24 DECLARE_GLOBAL_DATA_PTR;
25 25  
... ... @@ -55,6 +55,16 @@
55 55 return 0;
56 56 }
57 57  
  58 +int board_early_init_f(void)
  59 +{
  60 +#if defined(CONFIG_DEEP_SLEEP)
  61 + if (is_warm_boot())
  62 + fsl_dp_disable_console();
  63 +#endif
  64 +
  65 + return 0;
  66 +}
  67 +
58 68 int board_early_init_r(void)
59 69 {
60 70 #ifdef CONFIG_SYS_FLASH_BASE
... ... @@ -131,15 +141,4 @@
131 141  
132 142 return 0;
133 143 }
134   -
135   -#ifdef CONFIG_DEEP_SLEEP
136   -void board_mem_sleep_setup(void)
137   -{
138   - /* does not provide HW signals for power management */
139   - CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) & ~0x40));
140   - /* Disable MCKE isolation */
141   - gpio_set_value(2, 0);
142   - udelay(1);
143   -}
144   -#endif
include/configs/T102xRDB.h
Diff comments   View file @ f49b8c1
... ... @@ -36,7 +36,10 @@
36 36  
37 37 /* support deep sleep */
38 38 #define CONFIG_DEEP_SLEEP
  39 +#if defined(CONFIG_DEEP_SLEEP)
39 40 #define CONFIG_SILENT_CONSOLE
  41 +#define CONFIG_BOARD_EARLY_INIT_F
  42 +#endif
40 43  
41 44 #ifdef CONFIG_RAMBOOT_PBL
42 45 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
... ... @@ -51,7 +54,7 @@
51 54 #define CONFIG_SPL_I2C_SUPPORT
52 55 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
53 56 #define CONFIG_FSL_LAW /* Use common FSL init code */
54   -#define CONFIG_SYS_TEXT_BASE 0x00201000
  57 +#define CONFIG_SYS_TEXT_BASE 0x30001000
55 58 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
56 59 #define CONFIG_SPL_PAD_TO 0x40000
57 60 #define CONFIG_SPL_MAX_SIZE 0x28000
58 61  
59 62  
... ... @@ -67,21 +70,21 @@
67 70 #ifdef CONFIG_NAND
68 71 #define CONFIG_SPL_NAND_SUPPORT
69 72 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
70   -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
71   -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
  73 +#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
  74 +#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
72 75 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
73 76 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
74 77 #define CONFIG_SPL_NAND_BOOT
75 78 #endif
76 79  
77 80 #ifdef CONFIG_SPIFLASH
78   -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  81 +#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
79 82 #define CONFIG_SPL_SPI_SUPPORT
80 83 #define CONFIG_SPL_SPI_FLASH_SUPPORT
81 84 #define CONFIG_SPL_SPI_FLASH_MINIMAL
82 85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
83   -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
84   -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
  86 +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
  87 +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
85 88 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
86 89 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
87 90 #ifndef CONFIG_SPL_BUILD
88 91  
... ... @@ -91,12 +94,12 @@
91 94 #endif
92 95  
93 96 #ifdef CONFIG_SDCARD
94   -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  97 +#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
95 98 #define CONFIG_SPL_MMC_SUPPORT
96 99 #define CONFIG_SPL_MMC_MINIMAL
97 100 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
98   -#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
99   -#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
  101 +#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
  102 +#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
100 103 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
101 104 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
102 105 #ifndef CONFIG_SPL_BUILD