armv8/cache: Consolidate setting for MAIR and TCR

Move setting for MAIR and TCR to cache_v8.c, to avoid conflict with sub-architecture. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn>

armv8/cache: Consolidate setting for MAIR and TCR
Move setting for MAIR and TCR to cache_v8.c, to avoid conflict with sub-architecture. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn>
York Sun · Albert ARIBAUD
1 parent 2c67e0e7cf
Showing 2 changed files with 19 additions and 25 deletions Side-by-side Diff
arch/arm/cpu/armv8/cache_v8.c
arch/arm/cpu/armv8/start.S
@@ -45,15 +45,31 @@
  
 	/* load TTBR0 */
 	el = current_el();
-	if (el == 1)
+	if (el == 1) {
 		asm volatile("msr ttbr0_el1, %0"
 			     : : "r" (gd->arch.tlb_addr) : "memory");
-	else if (el == 2)
+		asm volatile("msr tcr_el1, %0"
+			     : : "r" (TCR_FLAGS | TCR_EL1_IPS_BITS)
+			     : "memory");
+		asm volatile("msr mair_el1, %0"
+			     : : "r" (MEMORY_ATTRIBUTES) : "memory");
+	} else if (el == 2) {
 		asm volatile("msr ttbr0_el2, %0"
 			     : : "r" (gd->arch.tlb_addr) : "memory");
-	else
+		asm volatile("msr tcr_el2, %0"
+			     : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS)
+			     : "memory");
+		asm volatile("msr mair_el2, %0"
+			     : : "r" (MEMORY_ATTRIBUTES) : "memory");
+	} else {
 		asm volatile("msr ttbr0_el3, %0"
 			     : : "r" (gd->arch.tlb_addr) : "memory");
+		asm volatile("msr tcr_el3, %0"
+			     : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS)
+			     : "memory");
+		asm volatile("msr mair_el3, %0"
+			     : : "r" (MEMORY_ATTRIBUTES) : "memory");
+	}
  
 	/* enable the mmu */
 	set_sctlr(get_sctlr() | CR_M);
@@ -128,28 +128,6 @@
 	isb	sy
 #endif
  
-#ifndef CONFIG_SYS_DCACHE_OFF
-	/*
-	 * Setup MAIR and TCR.
-	 */
-	ldr	x0, =MEMORY_ATTRIBUTES
-	ldr	x1, =TCR_FLAGS
-
-	switch_el x2, 3f, 2f, 1f
-3:	orr	x1, x1, TCR_EL3_IPS_BITS
-	msr	mair_el3, x0
-	msr	tcr_el3, x1
-	b	0f
-2:	orr	x1, x1, TCR_EL2_IPS_BITS
-	msr	mair_el2, x0
-	msr	tcr_el2, x1
-	b	0f
-1:	orr	x1, x1, TCR_EL1_IPS_BITS
-	msr	mair_el1, x0
-	msr	tcr_el1, x1
-0:
-#endif
-
 	/* Relocate vBAR */
 	adr	x0, vectors
 	switch_el x1, 3f, 2f, 1f
...	...	@@ -45,15 +45,31 @@
45	45
46	46	/* load TTBR0 */
47	47	el = current_el();
48		- if (el == 1)
	48	+ if (el == 1) {
49	49	asm volatile("msr ttbr0_el1, %0"
50	50	: : "r" (gd->arch.tlb_addr) : "memory");
51		- else if (el == 2)
	51	+ asm volatile("msr tcr_el1, %0"
	52	+ : : "r" (TCR_FLAGS \| TCR_EL1_IPS_BITS)
	53	+ : "memory");
	54	+ asm volatile("msr mair_el1, %0"
	55	+ : : "r" (MEMORY_ATTRIBUTES) : "memory");
	56	+ } else if (el == 2) {
52	57	asm volatile("msr ttbr0_el2, %0"
53	58	: : "r" (gd->arch.tlb_addr) : "memory");
54		- else
	59	+ asm volatile("msr tcr_el2, %0"
	60	+ : : "r" (TCR_FLAGS \| TCR_EL2_IPS_BITS)
	61	+ : "memory");
	62	+ asm volatile("msr mair_el2, %0"
	63	+ : : "r" (MEMORY_ATTRIBUTES) : "memory");
	64	+ } else {
55	65	asm volatile("msr ttbr0_el3, %0"
56	66	: : "r" (gd->arch.tlb_addr) : "memory");
	67	+ asm volatile("msr tcr_el3, %0"
	68	+ : : "r" (TCR_FLAGS \| TCR_EL2_IPS_BITS)
	69	+ : "memory");
	70	+ asm volatile("msr mair_el3, %0"
	71	+ : : "r" (MEMORY_ATTRIBUTES) : "memory");
	72	+ }
57	73
58	74	/* enable the mmu */
59	75	set_sctlr(get_sctlr() \| CR_M);
...	...	@@ -128,28 +128,6 @@
128	128	isb sy
129	129	#endif
130	130
131		-#ifndef CONFIG_SYS_DCACHE_OFF
132		- /*
133		- * Setup MAIR and TCR.
134		- */
135		- ldr x0, =MEMORY_ATTRIBUTES
136		- ldr x1, =TCR_FLAGS
137		-
138		- switch_el x2, 3f, 2f, 1f
139		-3: orr x1, x1, TCR_EL3_IPS_BITS
140		- msr mair_el3, x0
141		- msr tcr_el3, x1
142		- b 0f
143		-2: orr x1, x1, TCR_EL2_IPS_BITS
144		- msr mair_el2, x0
145		- msr tcr_el2, x1
146		- b 0f
147		-1: orr x1, x1, TCR_EL1_IPS_BITS
148		- msr mair_el1, x0
149		- msr tcr_el1, x1
150		-0:
151		-#endif
152		-
153	131	/* Relocate vBAR */
154	132	adr x0, vectors
155	133	switch_el x1, 3f, 2f, 1f