mmc: fsl: reset to normal boot mode when eMMC fast boot

When booting in eMMC fast boot, MMC host does not exit from boot mode after bootrom loading image. So the first command 'CMD0' sent in uboot will pull down the CMD line to low and cause errors. This patch cleans the MMC boot register in "mmc_init" to put the MMC host back to normal mode. Also clear DLL_CTRL delay line settings at USDHC initialization to eliminate the pre-settings from boot rom. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: York Sun <york.sun@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>

mmc: fsl: reset to normal boot mode when eMMC fast boot
When booting in eMMC fast boot, MMC host does not exit from boot mode after bootrom loading image. So the first command 'CMD0' sent in uboot will pull down the CMD line to low and cause errors. This patch cleans the MMC boot register in "mmc_init" to put the MMC host back to normal mode. Also clear DLL_CTRL delay line settings at USDHC initialization to eliminate the pre-settings from boot rom. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: York Sun <york.sun@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Peng Fan · York Sun
1 parent 68aaa980c4
Showing 2 changed files with 35 additions and 9 deletions Side-by-side Diff
drivers/mmc/fsl_esdhc.c
include/fsl_esdhc.h
@@ -56,21 +56,27 @@
 	uint    fevt;		/* Force event register */
 	uint    admaes;		/* ADMA error status register */
 	uint    adsaddr;	/* ADMA system address register */
-	char    reserved2[100];	/* reserved */
-	uint    vendorspec;	/* Vendor Specific register */
-	char    reserved3[56];	/* reserved */
+	char    reserved2[4];
+	uint    dllctrl;
+	uint    dllstat;
+	uint    clktunectrlstatus;
+	char    reserved3[84];
+	uint    vendorspec;
+	uint    mmcboot;
+	uint    vendorspec2;
+	char	reserved4[48];
 	uint    hostver;	/* Host controller version register */
-	char    reserved4[4];	/* reserved */
-	uint    dmaerraddr;	/* DMA error address register */
 	char    reserved5[4];	/* reserved */
-	uint    dmaerrattr;	/* DMA error attribute register */
+	uint    dmaerraddr;	/* DMA error address register */
 	char    reserved6[4];	/* reserved */
+	uint    dmaerrattr;	/* DMA error attribute register */
+	char    reserved7[4];	/* reserved */
 	uint    hostcapblt2;	/* Host controller capabilities register 2 */
-	char    reserved7[8];	/* reserved */
+	char    reserved8[8];	/* reserved */
 	uint    tcr;		/* Tuning control register */
-	char    reserved8[28];	/* reserved */
+	char    reserved9[28];	/* reserved */
 	uint    sddirctl;	/* SD direction control register */
-	char    reserved9[712];	/* reserved */
+	char    reserved10[712];/* reserved */
 	uint    scr;		/* eSDHC control register */
 };
  
@@ -615,6 +621,20 @@
 	/* Wait until the controller is available */
 	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
 		udelay(1000);
+
+#if defined(CONFIG_FSL_USDHC)
+	/* RSTA doesn't reset MMC_BOOT register, so manually reset it */
+	esdhc_write32(&regs->mmcboot, 0x0);
+	/* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
+	esdhc_write32(&regs->mixctrl, 0x0);
+	esdhc_write32(&regs->clktunectrlstatus, 0x0);
+
+	/* Put VEND_SPEC to default value */
+	esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
+
+	/* Disable DLL_CTRL delay line */
+	esdhc_write32(&regs->dllctrl, 0x0);
+#endif
  
 #ifndef ARCH_MXC
 	/* Enable cache snooping */
@@ -35,6 +35,12 @@
 #define SYSCTL_RSTC		0x02000000
 #define SYSCTL_RSTD		0x04000000
  
+#define VENDORSPEC_CKEN		0x00004000
+#define VENDORSPEC_PEREN	0x00002000
+#define VENDORSPEC_HCKEN	0x00001000
+#define VENDORSPEC_IPGEN	0x00000800
+#define VENDORSPEC_INIT		0x20007809
+
 #define IRQSTAT			0x0002e030
 #define IRQSTAT_DMAE		(0x10000000)
 #define IRQSTAT_AC12E		(0x01000000)
...	...	@@ -56,21 +56,27 @@
56	56	uint fevt; /* Force event register */
57	57	uint admaes; /* ADMA error status register */
58	58	uint adsaddr; /* ADMA system address register */
59		- char reserved2[100]; /* reserved */
60		- uint vendorspec; /* Vendor Specific register */
61		- char reserved3[56]; /* reserved */
	59	+ char reserved2[4];
	60	+ uint dllctrl;
	61	+ uint dllstat;
	62	+ uint clktunectrlstatus;
	63	+ char reserved3[84];
	64	+ uint vendorspec;
	65	+ uint mmcboot;
	66	+ uint vendorspec2;
	67	+ char reserved4[48];
62	68	uint hostver; /* Host controller version register */
63		- char reserved4[4]; /* reserved */
64		- uint dmaerraddr; /* DMA error address register */
65	69	char reserved5[4]; /* reserved */
66		- uint dmaerrattr; /* DMA error attribute register */
	70	+ uint dmaerraddr; /* DMA error address register */
67	71	char reserved6[4]; /* reserved */
	72	+ uint dmaerrattr; /* DMA error attribute register */
	73	+ char reserved7[4]; /* reserved */
68	74	uint hostcapblt2; /* Host controller capabilities register 2 */
69		- char reserved7[8]; /* reserved */
	75	+ char reserved8[8]; /* reserved */
70	76	uint tcr; /* Tuning control register */
71		- char reserved8[28]; /* reserved */
	77	+ char reserved9[28]; /* reserved */
72	78	uint sddirctl; /* SD direction control register */
73		- char reserved9[712]; /* reserved */
	79	+ char reserved10[712];/* reserved */
74	80	uint scr; /* eSDHC control register */
75	81	};
76	82
...	...	@@ -615,6 +621,20 @@
615	621	/* Wait until the controller is available */
616	622	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
617	623	udelay(1000);
	624	+
	625	+#if defined(CONFIG_FSL_USDHC)
	626	+ /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
	627	+ esdhc_write32(&regs->mmcboot, 0x0);
	628	+ /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
	629	+ esdhc_write32(&regs->mixctrl, 0x0);
	630	+ esdhc_write32(&regs->clktunectrlstatus, 0x0);
	631	+
	632	+ /* Put VEND_SPEC to default value */
	633	+ esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
	634	+
	635	+ /* Disable DLL_CTRL delay line */
	636	+ esdhc_write32(&regs->dllctrl, 0x0);
	637	+#endif
618	638
619	639	#ifndef ARCH_MXC
620	640	/* Enable cache snooping */
...	...	@@ -35,6 +35,12 @@
35	35	#define SYSCTL_RSTC 0x02000000
36	36	#define SYSCTL_RSTD 0x04000000
37	37
	38	+#define VENDORSPEC_CKEN 0x00004000
	39	+#define VENDORSPEC_PEREN 0x00002000
	40	+#define VENDORSPEC_HCKEN 0x00001000
	41	+#define VENDORSPEC_IPGEN 0x00000800
	42	+#define VENDORSPEC_INIT 0x20007809
	43	+
38	44	#define IRQSTAT 0x0002e030
39	45	#define IRQSTAT_DMAE (0x10000000)
40	46	#define IRQSTAT_AC12E (0x01000000)