Commit f7749fbe5c10b582d9282eb3e4388a0e3ca44d48
Committed by
Lokesh Vutla
1 parent
f6a20e64be
Exists in
v2015.07-smarct4x
and in
3 other branches
ARM: AM43xx: Add functions to enable and disable USB clocks
Added functions to enable and disable USB clocks which can be invoked during USB init and USB exit respectively. Cc: Roger Quadros <rogerq@ti.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: Nishanth Menon <nm@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Showing 2 changed files with 75 additions and 0 deletions Side-by-side Diff
arch/arm/cpu/armv7/am33xx/clock_am43xx.c
... | ... | @@ -191,4 +191,74 @@ |
191 | 191 | 1); |
192 | 192 | } |
193 | 193 | #endif |
194 | + | |
195 | +#ifdef CONFIG_USB_DWC3 | |
196 | +void enable_usb_clocks(int index) | |
197 | +{ | |
198 | + u32 *usbclkctrl = 0; | |
199 | + u32 *usbphyocp2scpclkctrl = 0; | |
200 | + | |
201 | + if (index == 0) { | |
202 | + usbclkctrl = &cmper->usb0clkctrl; | |
203 | + usbphyocp2scpclkctrl = &cmper->usbphyocp2scp0clkctrl; | |
204 | + setbits_le32(&cmper->usb0clkctrl, | |
205 | + USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960); | |
206 | + setbits_le32(&cmwkup->usbphy0clkctrl, | |
207 | + USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K); | |
208 | + } else if (index == 1) { | |
209 | + usbclkctrl = &cmper->usb1clkctrl; | |
210 | + usbphyocp2scpclkctrl = &cmper->usbphyocp2scp1clkctrl; | |
211 | + setbits_le32(&cmper->usb1clkctrl, | |
212 | + USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960); | |
213 | + setbits_le32(&cmwkup->usbphy1clkctrl, | |
214 | + USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K); | |
215 | + } | |
216 | + | |
217 | + u32 *const clk_domains_usb[] = { | |
218 | + 0 | |
219 | + }; | |
220 | + | |
221 | + u32 *const clk_modules_explicit_en_usb[] = { | |
222 | + usbclkctrl, | |
223 | + usbphyocp2scpclkctrl, | |
224 | + 0 | |
225 | + }; | |
226 | + | |
227 | + do_enable_clocks(clk_domains_usb, clk_modules_explicit_en_usb, 1); | |
228 | +} | |
229 | + | |
230 | +void disable_usb_clocks(int index) | |
231 | +{ | |
232 | + u32 *usbclkctrl = 0; | |
233 | + u32 *usbphyocp2scpclkctrl = 0; | |
234 | + | |
235 | + if (index == 0) { | |
236 | + usbclkctrl = &cmper->usb0clkctrl; | |
237 | + usbphyocp2scpclkctrl = &cmper->usbphyocp2scp0clkctrl; | |
238 | + clrbits_le32(&cmper->usb0clkctrl, | |
239 | + USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960); | |
240 | + clrbits_le32(&cmwkup->usbphy0clkctrl, | |
241 | + USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K); | |
242 | + } else if (index == 1) { | |
243 | + usbclkctrl = &cmper->usb1clkctrl; | |
244 | + usbphyocp2scpclkctrl = &cmper->usbphyocp2scp1clkctrl; | |
245 | + clrbits_le32(&cmper->usb1clkctrl, | |
246 | + USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960); | |
247 | + clrbits_le32(&cmwkup->usbphy1clkctrl, | |
248 | + USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K); | |
249 | + } | |
250 | + | |
251 | + u32 *const clk_domains_usb[] = { | |
252 | + 0 | |
253 | + }; | |
254 | + | |
255 | + u32 *const clk_modules_disable_usb[] = { | |
256 | + usbclkctrl, | |
257 | + usbphyocp2scpclkctrl, | |
258 | + 0 | |
259 | + }; | |
260 | + | |
261 | + do_disable_clocks(clk_domains_usb, clk_modules_disable_usb, 1); | |
262 | +} | |
263 | +#endif |
arch/arm/include/asm/arch-am33xx/sys_proto.h