Commit f78b505f81334bb7a49d5807e007790d336340c4
Committed by
Marek Vasut
Marek Vasut
1 parent
5c2ae96b60
Exists in
smarc_8mq_lf_v2020.04
and in
9 other branches
ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK
Add default fitImage file bundling FPGA bitstreams for Arria10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Showing 1 changed file with 38 additions and 0 deletions Side-by-side Diff
board/altera/arria10-socdk/fit_spl_fpga.its
| 1 | +// SPDX-License-Identifier: GPL-2.0 | |
| 2 | + /* | |
| 3 | + * Copyright (C) 2019 Intel Corporation <www.intel.com> | |
| 4 | + * | |
| 5 | + */ | |
| 6 | + | |
| 7 | +/dts-v1/; | |
| 8 | + | |
| 9 | +/ { | |
| 10 | + description = "FIT image with FPGA bistream"; | |
| 11 | + #address-cells = <1>; | |
| 12 | + | |
| 13 | + images { | |
| 14 | + fpga-periph-1 { | |
| 15 | + description = "FPGA peripheral bitstream"; | |
| 16 | + data = /incbin/("../../../ghrd_10as066n2.periph.rbf"); | |
| 17 | + type = "fpga"; | |
| 18 | + arch = "arm"; | |
| 19 | + compression = "none"; | |
| 20 | + }; | |
| 21 | + | |
| 22 | + fpga-core-1 { | |
| 23 | + description = "FPGA core bitstream"; | |
| 24 | + data = /incbin/("../../../ghrd_10as066n2.core.rbf"); | |
| 25 | + type = "fpga"; | |
| 26 | + arch = "arm"; | |
| 27 | + compression = "none"; | |
| 28 | + }; | |
| 29 | + }; | |
| 30 | + | |
| 31 | + configurations { | |
| 32 | + default = "config-1"; | |
| 33 | + config-1 { | |
| 34 | + description = "Boot with FPGA early IO release config"; | |
| 35 | + fpga = "fpga-periph-1", "fpga-core-1"; | |
| 36 | + }; | |
| 37 | + }; | |
| 38 | +}; |