Eric Lee / smarc-uboot

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Commit f7dc4ac37c8e2448aa88209e5d00fa377ca98ced

Authored by Tom Warren
Committed by Tom Warren
1 parent a57c5846a2
Exists in master and in 49 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ARM: tegra: add Venice2 (Tegra124) board 

These are the board files for Venice2 (Tegra124), plus the AS3722 PMIC
files. PMIC init will be moved to pmic_common_init later.

This builds/boots on Venice2, SPI/MMC/USB/I2C all work. Audio, display
and WB/LP0 are not supported yet.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

Showing 8 changed files with 672 additions and 0 deletions Side-by-side Diff

board/nvidia/venice2/Makefile
Diff comments   View file @ f7dc4ac
  1 +#
  2 +# (C) Copyright 2013-2014
  3 +# NVIDIA Corporation <www.nvidia.com>
  4 +#
  5 +# SPDX-License-Identifier: GPL-2.0+
  6 +#
  7 +
  8 +obj-y += as3722_init.o
  9 +obj-y += venice2.o
board/nvidia/venice2/as3722_init.c
Diff comments   View file @ f7dc4ac
  1 +/*
  2 + * (C) Copyright 2013
  3 + * NVIDIA Corporation <www.nvidia.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <asm/io.h>
  10 +#include <asm/arch-tegra/tegra_i2c.h>
  11 +#include "as3722_init.h"
  12 +
  13 +/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
  14 +
  15 +void tegra_i2c_ll_write_addr(uint addr, uint config)
  16 +{
  17 + struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
  18 +
  19 + writel(addr, &reg->cmd_addr0);
  20 + writel(config, &reg->cnfg);
  21 +}
  22 +
  23 +void tegra_i2c_ll_write_data(uint data, uint config)
  24 +{
  25 + struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
  26 +
  27 + writel(data, &reg->cmd_data1);
  28 + writel(config, &reg->cnfg);
  29 +}
  30 +
  31 +void pmic_enable_cpu_vdd(void)
  32 +{
  33 + debug("%s entry\n", __func__);
  34 +
  35 + /* Don't need to set up VDD_CORE - already done - by OTP */
  36 +
  37 + debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
  38 + /*
  39 + * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
  40 + * First set VDD to 1.0V, then enable the VDD regulator.
  41 + */
  42 + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  43 + tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
  44 + /*
  45 + * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
  46 + * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
  47 + */
  48 + udelay(10 * 1000);
  49 +
  50 + debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
  51 + /*
  52 + * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
  53 + * First set VDD to 1.0V, then enable the VDD regulator.
  54 + */
  55 + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  56 + tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
  57 + /*
  58 + * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
  59 + * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
  60 + */
  61 + udelay(10 * 1000);
  62 +
  63 + debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
  64 + /*
  65 + * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
  66 + * First set VDD to 1.2V, then enable the VDD regulator.
  67 + */
  68 + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  69 + tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
  70 + /*
  71 + * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
  72 + * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
  73 + */
  74 + udelay(10 * 1000);
  75 +
  76 + debug("%s: Set VDD_SDMMC to 3.3V via AS3722 reg 0x16/4E\n", __func__);
  77 + /*
  78 + * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.
  79 + * First set it to bypass 3.3V straight thru, then enable the regulator
  80 + *
  81 + * NOTE: We do this early because doing it later seems to hose the CPU
  82 + * power rail/partition startup. Need to debug.
  83 + */
  84 + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  85 + tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
  86 + /*
  87 + * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
  88 + * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
  89 + */
  90 + udelay(10 * 1000);
  91 +}
board/nvidia/venice2/as3722_init.h
Diff comments   View file @ f7dc4ac
  1 +/*
  2 + * (C) Copyright 2013
  3 + * NVIDIA Corporation <www.nvidia.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +/* AS3722-PMIC-specific early init regs */
  9 +
  10 +#define AS3722_I2C_ADDR 0x80
  11 +
  12 +#define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */
  13 +#define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */
  14 +#define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */
  15 +#define AS3722_SDCONTROL_REG 0x4D
  16 +
  17 +#define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */
  18 +#define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC */
  19 +#define AS3722_LDCONTROL_REG 0x4E
  20 +
  21 +#define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG)
  22 +#define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG)
  23 +
  24 +#define AS3722_SD1VOLTAGE_DATA (0x3200 | AS3722_SD1VOLTAGE_REG)
  25 +#define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG)
  26 +
  27 +#define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG)
  28 +#define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG)
  29 +
  30 +#define AS3722_LDO2CONTROL_DATA (0x0400 | AS3722_LDCONTROL_REG)
  31 +#define AS3722_LDO2VOLTAGE_DATA (0x1000 | AS3722_LDO2VOLTAGE_REG)
  32 +
  33 +#define AS3722_LDO6CONTROL_DATA (0x4000 | AS3722_LDCONTROL_REG)
  34 +#define AS3722_LDO6VOLTAGE_DATA (0x3F00 | AS3722_LDO6VOLTAGE_REG)
  35 +
  36 +#define I2C_SEND_2_BYTES 0x0A02
  37 +
  38 +void pmic_enable_cpu_vdd(void);
board/nvidia/venice2/pinmux-config-venice2.h
Diff comments   View file @ f7dc4ac
  1 +/*
  2 + * (C) Copyright 2013
  3 + * NVIDIA Corporation <www.nvidia.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef _PINMUX_CONFIG_VENICE2_H_
  9 +#define _PINMUX_CONFIG_VENICE2_H_
  10 +
  11 +#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \
  12 + { \
  13 + .pingroup = PINGRP_##_pingroup, \
  14 + .func = PMUX_FUNC_##_mux, \
  15 + .pull = PMUX_PULL_##_pull, \
  16 + .tristate = PMUX_TRI_##_tri, \
  17 + .io = PMUX_PIN_##_io, \
  18 + .lock = PMUX_PIN_LOCK_DEFAULT, \
  19 + .od = PMUX_PIN_OD_DEFAULT, \
  20 + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
  21 + }
  22 +
  23 +#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
  24 + { \
  25 + .pingroup = PINGRP_##_pingroup, \
  26 + .func = PMUX_FUNC_##_mux, \
  27 + .pull = PMUX_PULL_##_pull, \
  28 + .tristate = PMUX_TRI_##_tri, \
  29 + .io = PMUX_PIN_##_io, \
  30 + .lock = PMUX_PIN_LOCK_##_lock, \
  31 + .od = PMUX_PIN_OD_##_od, \
  32 + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
  33 + }
  34 +
  35 +#define DDC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
  36 + { \
  37 + .pingroup = PINGRP_##_pingroup, \
  38 + .func = PMUX_FUNC_##_mux, \
  39 + .pull = PMUX_PULL_##_pull, \
  40 + .tristate = PMUX_TRI_##_tri, \
  41 + .io = PMUX_PIN_##_io, \
  42 + .lock = PMUX_PIN_LOCK_##_lock, \
  43 + .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \
  44 + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
  45 + }
  46 +
  47 +#define VI_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
  48 + { \
  49 + .pingroup = PINGRP_##_pingroup, \
  50 + .func = PMUX_FUNC_##_mux, \
  51 + .pull = PMUX_PULL_##_pull, \
  52 + .tristate = PMUX_TRI_##_tri, \
  53 + .io = PMUX_PIN_##_io, \
  54 + .lock = PMUX_PIN_LOCK_##_lock, \
  55 + .od = PMUX_PIN_OD_DEFAULT, \
  56 + .ioreset = PMUX_PIN_IO_RESET_##_ioreset \
  57 + }
  58 +
  59 +#define CEC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
  60 + { \
  61 + .pingroup = PINGRP_##_pingroup, \
  62 + .func = PMUX_FUNC_##_mux, \
  63 + .pull = PMUX_PULL_##_pull, \
  64 + .tristate = PMUX_TRI_##_tri, \
  65 + .io = PMUX_PIN_##_io, \
  66 + .lock = PMUX_PIN_LOCK_##_lock, \
  67 + .od = PMUX_PIN_OD_##_od, \
  68 + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
  69 + }
  70 +
  71 +#define USB_PINMUX CEC_PINMUX
  72 +
  73 +#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
  74 + { \
  75 + .padgrp = PDRIVE_PINGROUP_##_padgrp, \
  76 + .slwf = _slwf, \
  77 + .slwr = _slwr, \
  78 + .drvup = _drvup, \
  79 + .drvdn = _drvdn, \
  80 + .lpmd = PGRP_LPMD_##_lpmd, \
  81 + .schmt = PGRP_SCHMT_##_schmt, \
  82 + .hsm = PGRP_HSM_##_hsm, \
  83 + }
  84 +
  85 +static struct pingroup_config tegra124_pinmux_common[] = {
  86 + /* EXTPERIPH1 pinmux */
  87 + DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
  88 +
  89 + /* I2S0 pinmux */
  90 + DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, TRISTATE, INPUT),
  91 + DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT),
  92 + DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT),
  93 + DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT),
  94 +
  95 + /* I2S1 pinmux */
  96 + DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, TRISTATE, INPUT),
  97 + DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
  98 + DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT),
  99 + DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
  100 +
  101 + /* I2S3 pinmux */
  102 + DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT),
  103 + DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
  104 + DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT),
  105 + DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
  106 +
  107 + /* CLDVFS pinmux */
  108 + DEFAULT_PINMUX(DVFS_PWM, CLDVFS, NORMAL, NORMAL, OUTPUT),
  109 + DEFAULT_PINMUX(DVFS_CLK, CLDVFS, NORMAL, NORMAL, OUTPUT),
  110 +
  111 + /* ULPI pinmux */
  112 + DEFAULT_PINMUX(ULPI_DATA0, ULPI, NORMAL, NORMAL, INPUT),
  113 + DEFAULT_PINMUX(ULPI_DATA1, ULPI, NORMAL, NORMAL, INPUT),
  114 + DEFAULT_PINMUX(ULPI_DATA2, ULPI, NORMAL, NORMAL, INPUT),
  115 + DEFAULT_PINMUX(ULPI_DATA3, ULPI, NORMAL, NORMAL, INPUT),
  116 + DEFAULT_PINMUX(ULPI_DATA4, ULPI, UP, NORMAL, INPUT),
  117 + DEFAULT_PINMUX(ULPI_DATA5, ULPI, UP, NORMAL, INPUT),
  118 + DEFAULT_PINMUX(ULPI_DATA6, ULPI, NORMAL, NORMAL, INPUT),
  119 +
  120 + /* EC KBC/SPI */
  121 + DEFAULT_PINMUX(ULPI_CLK, SPI1, UP, NORMAL, INPUT),
  122 + DEFAULT_PINMUX(ULPI_DIR, SPI1, UP, NORMAL, INPUT),
  123 + DEFAULT_PINMUX(ULPI_NXT, SPI1, NORMAL, NORMAL, INPUT),
  124 + DEFAULT_PINMUX(ULPI_STP, SPI1, NORMAL, NORMAL, INPUT),
  125 +
  126 + /* I2C3 (TPM) pinmux */
  127 + I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
  128 + I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
  129 +
  130 + /* I2C2 pinmux */
  131 + I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
  132 + I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
  133 +
  134 + /* UARTD pinmux (UART4 on Servo board, unused) */
  135 + DEFAULT_PINMUX(GPIO_PJ7, UARTD, NORMAL, NORMAL, OUTPUT),
  136 + DEFAULT_PINMUX(GPIO_PB0, UARTD, NORMAL, TRISTATE, INPUT),
  137 + DEFAULT_PINMUX(GPIO_PB1, UARTD, NORMAL, TRISTATE, INPUT),
  138 + DEFAULT_PINMUX(GPIO_PK7, UARTD, NORMAL, NORMAL, OUTPUT),
  139 +
  140 + /* SPI4 (Winbond 'boot ROM') */
  141 + DEFAULT_PINMUX(GPIO_PG5, SPI4, NORMAL, NORMAL, INPUT),
  142 + DEFAULT_PINMUX(GPIO_PG6, SPI4, UP, NORMAL, INPUT),
  143 + DEFAULT_PINMUX(GPIO_PG7, SPI4, UP, NORMAL, INPUT),
  144 + DEFAULT_PINMUX(GPIO_PI3, SPI4, NORMAL, NORMAL, INPUT),
  145 +
  146 + /* Touch IRQ */
  147 + DEFAULT_PINMUX(GPIO_W3_AUD, RSVD1, NORMAL, NORMAL, INPUT),
  148 +
  149 + /* PWM1 pinmux */
  150 + DEFAULT_PINMUX(GPIO_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
  151 +
  152 + /* SDMMC1 pinmux */
  153 + DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
  154 + DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
  155 + DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT),
  156 + DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT),
  157 + DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT),
  158 + DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT),
  159 +
  160 + /* SDMMC3 pinmux */
  161 + DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
  162 + DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT),
  163 + DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT),
  164 + DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT),
  165 + DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT),
  166 + DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT),
  167 + DEFAULT_PINMUX(SDMMC3_CLK_LB_IN, SDMMC3, UP, TRISTATE, INPUT),
  168 + DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3, DOWN, NORMAL, INPUT),
  169 +
  170 + /* SDMMC4 pinmux */
  171 + DEFAULT_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT),
  172 + DEFAULT_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT),
  173 + DEFAULT_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT),
  174 + DEFAULT_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT),
  175 + DEFAULT_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT),
  176 + DEFAULT_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT),
  177 + DEFAULT_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT),
  178 + DEFAULT_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT),
  179 + DEFAULT_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT),
  180 + DEFAULT_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT),
  181 +
  182 + /* BLINK pinmux */
  183 + DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT),
  184 +
  185 + /* KBC pinmux */
  186 + DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT),
  187 + DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT),
  188 + DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT),
  189 + DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT),
  190 + DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT),
  191 +
  192 + /* Misc */
  193 + DEFAULT_PINMUX(GPIO_PV0, RSVD1, NORMAL, TRISTATE, OUTPUT),
  194 + DEFAULT_PINMUX(KB_ROW7, RSVD1, UP, NORMAL, INPUT),
  195 +
  196 + /* UARTA pinmux (BR_UART_TXD/RXD on Servo board) */
  197 + DEFAULT_PINMUX(KB_ROW9, UARTA, UP, NORMAL, OUTPUT),
  198 + DEFAULT_PINMUX(KB_ROW10, UARTA, UP, TRISTATE, INPUT),
  199 +
  200 + /* I2CPWR pinmux (I2C5) */
  201 + I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
  202 + I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
  203 +
  204 + /* RTCK pinmux */
  205 + DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, INPUT),
  206 +
  207 + /* CLK pinmux */
  208 + DEFAULT_PINMUX(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT),
  209 +
  210 + /* PWRON pinmux */
  211 + DEFAULT_PINMUX(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT),
  212 +
  213 + /* CPU pinmux */
  214 + DEFAULT_PINMUX(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT),
  215 +
  216 + /* PMI pinmux */
  217 + DEFAULT_PINMUX(PWR_INT_N, PMI, NORMAL, TRISTATE, INPUT),
  218 +
  219 + /* RESET_OUT_N pinmux */
  220 + DEFAULT_PINMUX(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT),
  221 +
  222 + /* EXTPERIPH3 pinmux */
  223 + DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
  224 +
  225 + /* I2C1 pinmux */
  226 + I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
  227 + I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
  228 +
  229 + /* UARTB, GPS */
  230 + DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, TRISTATE, INPUT),
  231 + DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT),
  232 + DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, TRISTATE, INPUT),
  233 + DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT),
  234 +
  235 + /* UARTC (WIFI/BT) */
  236 + DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, TRISTATE, INPUT),
  237 + DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
  238 + DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, TRISTATE, INPUT),
  239 + DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
  240 +
  241 + /* CEC pinmux */
  242 + CEC_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
  243 +
  244 + /* I2C4 (HDMI_DDC) pinmux */
  245 + DDC_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
  246 + DDC_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
  247 +
  248 + /* USB pinmux */
  249 + USB_PINMUX(USB_VBUS_EN0, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
  250 + USB_PINMUX(USB_VBUS_EN1, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
  251 +
  252 + /* Unused, marked SNN_ on schematic, TRISTATE 'em */
  253 + DEFAULT_PINMUX(GPIO_PBB0, RSVD3, NORMAL, TRISTATE, INPUT),
  254 + DEFAULT_PINMUX(GPIO_PBB3, RSVD3, NORMAL, TRISTATE, INPUT),
  255 + DEFAULT_PINMUX(GPIO_PBB4, RSVD3, NORMAL, TRISTATE, INPUT),
  256 + DEFAULT_PINMUX(GPIO_PBB5, RSVD2, NORMAL, TRISTATE, INPUT),
  257 + DEFAULT_PINMUX(GPIO_PBB6, RSVD1, NORMAL, TRISTATE, INPUT),
  258 + DEFAULT_PINMUX(GPIO_PBB7, RSVD1, NORMAL, TRISTATE, INPUT),
  259 + DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, TRISTATE, INPUT),
  260 + DEFAULT_PINMUX(GPIO_PCC2, RSVD1, NORMAL, TRISTATE, INPUT),
  261 + DEFAULT_PINMUX(GPIO_PH3, GMI, NORMAL, TRISTATE, INPUT),
  262 + DEFAULT_PINMUX(GPIO_PI7, GMI, NORMAL, TRISTATE, INPUT),
  263 + DEFAULT_PINMUX(GPIO_PJ2, RSVD1, NORMAL, TRISTATE, INPUT),
  264 + DEFAULT_PINMUX(GPIO_X5_AUD, RSVD3, NORMAL, TRISTATE, INPUT),
  265 + DEFAULT_PINMUX(GPIO_X6_AUD, GMI, NORMAL, TRISTATE, INPUT),
  266 + DEFAULT_PINMUX(GPIO_W2_AUD, RSVD1, NORMAL, TRISTATE, INPUT),
  267 + DEFAULT_PINMUX(GPIO_PFF2, RSVD1, NORMAL, TRISTATE, INPUT),
  268 + DEFAULT_PINMUX(USB_VBUS_EN2, RSVD1, NORMAL, TRISTATE, INPUT),
  269 + DEFAULT_PINMUX(KB_COL5, RSVD1, NORMAL, TRISTATE, INPUT),
  270 + DEFAULT_PINMUX(KB_ROW2, RSVD1, NORMAL, TRISTATE, INPUT),
  271 + DEFAULT_PINMUX(KB_ROW3, KBC, NORMAL, TRISTATE, INPUT),
  272 + DEFAULT_PINMUX(KB_ROW5, RSVD2, NORMAL, TRISTATE, INPUT),
  273 + DEFAULT_PINMUX(KB_ROW6, KBC, NORMAL, TRISTATE, INPUT),
  274 + DEFAULT_PINMUX(KB_ROW13, RSVD1, NORMAL, TRISTATE, INPUT),
  275 + DEFAULT_PINMUX(KB_ROW14, RSVD1, NORMAL, TRISTATE, INPUT),
  276 + DEFAULT_PINMUX(KB_ROW16, RSVD1, NORMAL, TRISTATE, INPUT),
  277 + DEFAULT_PINMUX(OWR, RSVD1, NORMAL, TRISTATE, INPUT),
  278 + DEFAULT_PINMUX(ULPI_DATA7, ULPI, NORMAL, TRISTATE, INPUT),
  279 + DEFAULT_PINMUX(DAP3_DIN, RSVD1, NORMAL, TRISTATE, INPUT),
  280 + DEFAULT_PINMUX(DAP3_FS, RSVD1, NORMAL, TRISTATE, INPUT),
  281 + DEFAULT_PINMUX(DAP3_SCLK, RSVD2, NORMAL, TRISTATE, INPUT),
  282 + DEFAULT_PINMUX(CLK2_OUT, RSVD1, NORMAL, TRISTATE, INPUT),
  283 + DEFAULT_PINMUX(SDMMC1_WP_N, RSVD1, NORMAL, TRISTATE, INPUT),
  284 + DEFAULT_PINMUX(CAM_MCLK, RSVD1, NORMAL, TRISTATE, INPUT),
  285 + DEFAULT_PINMUX(CLK3_REQ, RSVD1, NORMAL, TRISTATE, INPUT),
  286 + DEFAULT_PINMUX(SPDIF_OUT, RSVD1, NORMAL, TRISTATE, INPUT),
  287 +};
  288 +
  289 +static struct pingroup_config unused_pins_lowpower[] = {
  290 + DEFAULT_PINMUX(CLK1_REQ, RSVD3, DOWN, TRISTATE, OUTPUT),
  291 +};
  292 +
  293 +/* Initially setting all used GPIO's to non-TRISTATE */
  294 +static struct pingroup_config tegra124_pinmux_set_nontristate[] = {
  295 + DEFAULT_PINMUX(GPIO_X4_AUD, RSVD1, DOWN, NORMAL, OUTPUT),
  296 + DEFAULT_PINMUX(GPIO_X7_AUD, RSVD1, DOWN, NORMAL, OUTPUT),
  297 + DEFAULT_PINMUX(GPIO_W2_AUD, RSVD1, UP, NORMAL, INPUT),
  298 + DEFAULT_PINMUX(GPIO_X3_AUD, RSVD3, UP, NORMAL, INPUT),
  299 +
  300 + /* EN_VDD_BL */
  301 + DEFAULT_PINMUX(DAP3_DOUT, I2S2, DOWN, NORMAL, OUTPUT),
  302 +
  303 + /* MODEM */
  304 + DEFAULT_PINMUX(GPIO_PV0, RSVD3, NORMAL, NORMAL, INPUT),
  305 + DEFAULT_PINMUX(GPIO_PV1, RSVD1, NORMAL, NORMAL, INPUT),
  306 +
  307 + /* BOOT_SEL0-3 */
  308 + DEFAULT_PINMUX(GPIO_PG0, GMI, NORMAL, NORMAL, INPUT),
  309 + DEFAULT_PINMUX(GPIO_PG1, GMI, NORMAL, NORMAL, INPUT),
  310 + DEFAULT_PINMUX(GPIO_PG2, GMI, NORMAL, NORMAL, INPUT),
  311 + DEFAULT_PINMUX(GPIO_PG3, GMI, NORMAL, NORMAL, INPUT),
  312 +
  313 + DEFAULT_PINMUX(CLK2_REQ, RSVD3, NORMAL, NORMAL, OUTPUT),
  314 +
  315 + DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, OUTPUT),
  316 + DEFAULT_PINMUX(KB_COL4, SDMMC3, UP, NORMAL, INPUT),
  317 + DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, OUTPUT),
  318 + DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, OUTPUT),
  319 + DEFAULT_PINMUX(KB_ROW4, KBC, DOWN, NORMAL, INPUT),
  320 + DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
  321 +
  322 + DEFAULT_PINMUX(GPIO_PU4, RSVD3, NORMAL, NORMAL, INPUT),
  323 + DEFAULT_PINMUX(GPIO_PU5, RSVD3, NORMAL, NORMAL, OUTPUT),
  324 + DEFAULT_PINMUX(GPIO_PU6, RSVD3, NORMAL, NORMAL, INPUT),
  325 +
  326 + DEFAULT_PINMUX(HDMI_INT, RSVD1, DOWN, NORMAL, INPUT),
  327 + DEFAULT_PINMUX(SPDIF_IN, USB, NORMAL, NORMAL, INPUT),
  328 + DEFAULT_PINMUX(SDMMC3_CD_N, SDMMC3, UP, NORMAL, INPUT),
  329 +
  330 + /* TS_SHDN_L */
  331 + DEFAULT_PINMUX(GPIO_PK1, GMI, NORMAL, NORMAL, OUTPUT),
  332 +};
  333 +
  334 +static struct padctrl_config venice2_padctrl[] = {
  335 + /* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
  336 + DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR,
  337 + SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE),
  338 +};
  339 +#endif /* PINMUX_CONFIG_VENICE2_H */
board/nvidia/venice2/venice2.c
Diff comments   View file @ f7dc4ac
  1 +/*
  2 + * (C) Copyright 2013-2014
  3 + * NVIDIA Corporation <www.nvidia.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <asm-generic/gpio.h>
  10 +#include <asm/arch/gpio.h>
  11 +#include <asm/arch/gp_padctrl.h>
  12 +#include <asm/arch/pinmux.h>
  13 +#include "pinmux-config-venice2.h"
  14 +#include <i2c.h>
  15 +
  16 +/*
  17 + * Routine: pinmux_init
  18 + * Description: Do individual peripheral pinmux configs
  19 + */
  20 +void pinmux_init(void)
  21 +{
  22 + pinmux_config_table(tegra124_pinmux_set_nontristate,
  23 + ARRAY_SIZE(tegra124_pinmux_set_nontristate));
  24 +
  25 + pinmux_config_table(tegra124_pinmux_common,
  26 + ARRAY_SIZE(tegra124_pinmux_common));
  27 +
  28 + pinmux_config_table(unused_pins_lowpower,
  29 + ARRAY_SIZE(unused_pins_lowpower));
  30 +
  31 + /* Initialize any non-default pad configs (APB_MISC_GP regs) */
  32 + padgrp_config_table(venice2_padctrl, ARRAY_SIZE(venice2_padctrl));
  33 +}
... ... @@ -364,6 +364,7 @@
364 364 Active arm armv7 zynq xilinx zynq zynq_zc770_xm013 zynq_zc770:ZC770_XM013 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
365 365 Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
366 366 Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren <twarren@nvidia.com>
  367 +Active arm armv7:arm720t tegra124 nvidia venice2 venice2 - Tom Warren <twarren@nvidia.com>
367 368 Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Alban Bedel <alban.bedel@avionic-design.de>
368 369 Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Alban Bedel <alban.bedel@avionic-design.de>
369 370 Active arm armv7:arm720t tegra20 avionic-design tec tec - Alban Bedel <alban.bedel@avionic-design.de>
include/configs/tegra124-common.h
Diff comments   View file @ f7dc4ac
  1 +/*
  2 + * (C) Copyright 2013
  3 + * NVIDIA Corporation <www.nvidia.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef _TEGRA124_COMMON_H_
  9 +#define _TEGRA124_COMMON_H_
  10 +
  11 +#include "tegra-common.h"
  12 +
  13 +/* Cortex-A15 uses a cache line size of 64 bytes */
  14 +#define CONFIG_SYS_CACHELINE_SIZE 64
  15 +
  16 +/*
  17 + * NS16550 Configuration
  18 + */
  19 +#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
  20 +
  21 +/*
  22 + * High Level Configuration Options
  23 + */
  24 +#define CONFIG_TEGRA124 /* is an NVIDIA Tegra124 core */
  25 +
  26 +/* Environment information, boards can override if required */
  27 +#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
  28 +
  29 +/*
  30 + * Miscellaneous configurable options
  31 + */
  32 +#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */
  33 +#define CONFIG_STACKBASE 0x82800000 /* 40MB */
  34 +
  35 +/*-----------------------------------------------------------------------
  36 + * Physical Memory Map
  37 + */
  38 +#define CONFIG_SYS_TEXT_BASE 0x8010E000
  39 +
  40 +/*
  41 + * Memory layout for where various images get loaded by boot scripts:
  42 + *
  43 + * scriptaddr can be pretty much anywhere that doesn't conflict with something
  44 + * else. Put it above BOOTMAPSZ to eliminate conflicts.
  45 + *
  46 + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
  47 + * something else. Put it above BOOTMAPSZ to eliminate conflicts.
  48 + *
  49 + * kernel_addr_r must be within the first 128M of RAM in order for the
  50 + * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  51 + * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
  52 + * should not overlap that area, or the kernel will have to copy itself
  53 + * somewhere else before decompression. Similarly, the address of any other
  54 + * data passed to the kernel shouldn't overlap the start of RAM. Pushing
  55 + * this up to 16M allows for a sizable kernel to be decompressed below the
  56 + * compressed load address.
  57 + *
  58 + * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
  59 + * the compressed kernel to be up to 16M too.
  60 + *
  61 + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
  62 + * for the FDT/DTB to be up to 1M, which is hopefully plenty.
  63 + */
  64 +#define MEM_LAYOUT_ENV_SETTINGS \
  65 + "scriptaddr=0x90000000\0" \
  66 + "pxefile_addr_r=0x90100000\0" \
  67 + "kernel_addr_r=0x81000000\0" \
  68 + "fdt_addr_r=0x82000000\0" \
  69 + "ramdisk_addr_r=0x82100000\0"
  70 +
  71 +/* Defines for SPL */
  72 +#define CONFIG_SPL_TEXT_BASE 0x80108000
  73 +#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
  74 +#define CONFIG_SPL_STACK 0x800ffffc
  75 +
  76 +/* Total I2C ports on Tegra124 */
  77 +#define TEGRA_I2C_NUM_CONTROLLERS 5
  78 +
  79 +/* For USB EHCI controller */
  80 +#define CONFIG_EHCI_IS_TDI
  81 +
  82 +#endif /* _TEGRA124_COMMON_H_ */
include/configs/venice2.h
Diff comments   View file @ f7dc4ac
  1 +/*
  2 + * (C) Copyright 2013-2014
  3 + * NVIDIA Corporation <www.nvidia.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef __CONFIG_H
  9 +#define __CONFIG_H
  10 +
  11 +#include <asm/sizes.h>
  12 +
  13 +#include "tegra124-common.h"
  14 +
  15 +/* Enable fdt support for Venice2. Flash the image in u-boot-dtb.bin */
  16 +#define CONFIG_DEFAULT_DEVICE_TREE tegra124-venice2
  17 +#define CONFIG_OF_CONTROL
  18 +#define CONFIG_OF_SEPARATE
  19 +
  20 +/* High-level configuration options */
  21 +#define V_PROMPT "Tegra124 (Venice2) # "
  22 +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Venice2"
  23 +
  24 +/* Board-specific serial config */
  25 +#define CONFIG_SERIAL_MULTI
  26 +#define CONFIG_TEGRA_ENABLE_UARTA
  27 +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
  28 +
  29 +#define CONFIG_BOARD_EARLY_INIT_F
  30 +
  31 +/* I2C */
  32 +#define CONFIG_SYS_I2C_TEGRA
  33 +#define CONFIG_SYS_I2C_INIT_BOARD
  34 +#define CONFIG_I2C_MULTI_BUS
  35 +#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS
  36 +#define CONFIG_SYS_I2C_SPEED 100000
  37 +#define CONFIG_CMD_I2C
  38 +#define CONFIG_SYS_I2C
  39 +
  40 +/* SD/MMC */
  41 +#define CONFIG_MMC
  42 +#define CONFIG_GENERIC_MMC
  43 +#define CONFIG_TEGRA_MMC
  44 +#define CONFIG_CMD_MMC
  45 +
  46 +/* Environment in eMMC, at the end of 2nd "boot sector" */
  47 +#define CONFIG_ENV_IS_IN_MMC
  48 +#define CONFIG_SYS_MMC_ENV_DEV 0
  49 +#define CONFIG_SYS_MMC_ENV_PART 2
  50 +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
  51 +
  52 +/* SPI */
  53 +#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */
  54 +#define CONFIG_TEGRA114_SPI_CTRLS 6
  55 +#define CONFIG_SPI_FLASH
  56 +#define CONFIG_SPI_FLASH_WINBOND
  57 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
  58 +#define CONFIG_SF_DEFAULT_SPEED 24000000
  59 +#define CONFIG_CMD_SPI
  60 +#define CONFIG_CMD_SF
  61 +#define CONFIG_SPI_FLASH_SIZE (4 << 20)
  62 +
  63 +/* USB Host support */
  64 +#define CONFIG_USB_EHCI
  65 +#define CONFIG_USB_EHCI_TEGRA
  66 +#define CONFIG_USB_STORAGE
  67 +#define CONFIG_CMD_USB
  68 +
  69 +/* USB networking support */
  70 +#define CONFIG_USB_HOST_ETHER
  71 +#define CONFIG_USB_ETHER_ASIX
  72 +
  73 +/* General networking support */
  74 +#define CONFIG_CMD_NET
  75 +#define CONFIG_CMD_DHCP
  76 +
  77 +#include "tegra-common-post.h"
  78 +
  79 +#endif /* __CONFIG_H */