Eric Lee / smarc-uboot | Embedian Git Server

Commit f83ef0dac83110d20389eb71f09285f009f3d198

Authored by Tom Rini 2019-01-18 08:12:55 +0800

Exists in smarc_8mq_lf_v2020.04 and in 11 other branches

Merge tag 'mips-pull-2019-11-16' of git://git.denx.de/u-boot-mips

- MIPS: mscc: various enhancements for Luton and Ocelot platforms
- MIPS: mscc: added support for Jaguar2 platform
- MIPS: optimised SPL linker script
- MIPS: bcm6368: fix restart flow issues
- MIPS: fixed CONFIG_OF_EMBED warnings for all MIPS boards
- MIPS: mt7688: small fixes and enhancements
- mmc: compile-out write support if disabled

Showing 91 changed files Inline Diff

MAINTAINERS
arch/mips/cpu/u-boot-spl.lds
arch/mips/cpu/u-boot.lds
arch/mips/dts/Makefile
arch/mips/dts/gardena-smart-gateway-mt7688.dts
arch/mips/dts/jr2_pcb110.dts
arch/mips/dts/jr2_pcb111.dts
arch/mips/dts/luton_pcb090.dts
arch/mips/dts/luton_pcb091.dts
arch/mips/dts/mscc,jr2.dtsi
arch/mips/dts/mscc,luton.dtsi
arch/mips/dts/mscc,ocelot.dtsi
arch/mips/dts/ocelot_pcb120.dts
arch/mips/dts/ocelot_pcb123.dts
arch/mips/dts/serval2_pcb112.dts
arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds
arch/mips/mach-mscc/Kconfig
arch/mips/mach-mscc/Makefile
arch/mips/mach-mscc/cpu.c
arch/mips/mach-mscc/dram.c
arch/mips/mach-mscc/gpio.c
arch/mips/mach-mscc/include/mach/common.h
arch/mips/mach-mscc/include/mach/ddr.h
arch/mips/mach-mscc/include/mach/jr2/jr2.h
arch/mips/mach-mscc/include/mach/jr2/jr2_devcpu_gcb.h
arch/mips/mach-mscc/include/mach/jr2/jr2_devcpu_gcb_miim_regs.h
arch/mips/mach-mscc/include/mach/jr2/jr2_icpu_cfg.h
arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h
arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h
arch/mips/mach-mscc/phy.c
arch/mips/mach-mscc/reset.c
board/mscc/common/Makefile
board/mscc/common/spi.c
board/mscc/jr2/Kconfig
board/mscc/jr2/Makefile
board/mscc/jr2/jr2.c
board/mscc/luton/luton.c
board/mscc/ocelot/ocelot.c
configs/bcm968380gerg_ram_defconfig
configs/boston32r2_defconfig
configs/boston32r2el_defconfig
configs/boston32r6_defconfig
configs/boston32r6el_defconfig
configs/boston64r2_defconfig
configs/boston64r2el_defconfig
configs/boston64r6_defconfig
configs/boston64r6el_defconfig
configs/ci20_mmc_defconfig
configs/comtrend_ar5315u_ram_defconfig
configs/comtrend_ar5387un_ram_defconfig
configs/comtrend_ct5361_ram_defconfig
configs/comtrend_vr3032u_ram_defconfig
configs/comtrend_wap5813n_ram_defconfig
configs/gardena-smart-gateway-mt7688-ram_defconfig
configs/gardena-smart-gateway-mt7688_defconfig
configs/huawei_hg556a_ram_defconfig
configs/imgtec_xilfpga_defconfig
configs/malta64_defconfig
configs/malta64el_defconfig
configs/malta_defconfig
configs/maltael_defconfig
configs/mscc_jr2_defconfig
configs/mscc_luton_defconfig
configs/mscc_ocelot_defconfig
configs/mscc_ocelot_pcb120_defconfig
configs/netgear_cg3100d_ram_defconfig
configs/netgear_dgnd3700v2_ram_defconfig
configs/pic32mzdask_defconfig
configs/sagem_f@st1704_ram_defconfig
configs/sfr_nb4-ser_ram_defconfig
doc/device-tree-bindings/gpio/mscc_sgpio.txt
drivers/gpio/Kconfig
drivers/gpio/Makefile
drivers/gpio/gpio-mscc-bitbang-spi.c
drivers/gpio/mscc_sgpio.c
drivers/mmc/jz_mmc.c
drivers/mmc/mmc_write.c
drivers/net/bcm6368-eth.c
drivers/pinctrl/mscc/Kconfig
drivers/pinctrl/mscc/Makefile
drivers/pinctrl/mscc/mscc-common.c
drivers/pinctrl/mscc/mscc-common.h
drivers/pinctrl/mscc/pinctrl-jr2.c
drivers/pinctrl/mscc/pinctrl-luton.c
drivers/pinctrl/mscc/pinctrl-ocelot.c
drivers/spi/Kconfig
drivers/spi/Makefile
drivers/spi/mscc_bb_spi.c
include/configs/vcoreiii.h

MAINTAINERS

Diff comments View file @ f83ef0d

 Descriptions of section entries:
 	P: Person (obsolete)
 	M: Mail patches to: FullName <address@domain>
 	R: Designated reviewer: FullName <address@domain>
 	   These reviewers should be CCed on patches.
 	L: Mailing list that is relevant to this area
 	W: Web-page with status/info
 	Q: Patchwork web based patch tracking system site
 	T: SCM tree type and location.
 	   Type is one of: git, hg, quilt, stgit, topgit
 	S: Status, one of the following:
 	   Supported:	Someone is actually paid to look after this.
 	   Maintained:	Someone actually looks after it.
 	   Odd Fixes:	It has a maintainer but they don't have time to do
 			much other than throw the odd patch in. See below..
 	   Orphan:	No current maintainer [but maybe you could take the
 			role as you write your new code].
 	   Obsolete:	Old code. Something tagged obsolete generally means
 			it has been replaced by a better system and you
 			should be using that.
 	F: Files and directories with wildcard patterns.
 	   A trailing slash includes all files and subdirectory files.
 	   F:	drivers/net/	all files in and below drivers/net
 	   F:	drivers/net/*	all files in drivers/net, but not below
 	   F:	*/net/*		all files in "any top level directory"/net
 	   One pattern per line.  Multiple F: lines acceptable.
 	N: Files and directories with regex patterns.
 	   N:	[^a-z]tegra	all files whose path contains the word tegra
 	   One pattern per line.  Multiple N: lines acceptable.
 	   scripts/get_maintainer.pl has different behavior for files that
 	   match F: pattern and matches of N: patterns.  By default,
 	   get_maintainer will not look at git log history when an F: pattern
 	   match occurs.  When an N: match occurs, git log history is used
 	   to also notify the people that have git commit signatures.
 	X: Files and directories that are NOT maintained, same rules as F:
 	   Files exclusions are tested before file matches.
 	   Can be useful for excluding a specific subdirectory, for instance:
 	   F:	net/
 	   X:	net/ipv6/
 	   matches all files in and below net excluding net/ipv6/
 	K: Keyword perl extended regex pattern to match content in a
 	   patch or file.  For instance:
 	   K: of_get_profile
 	      matches patches or files that contain "of_get_profile"
 	   K: \b(printk|pr_(info|err))\b
 	      matches patches or files that contain one or more of the words
 	      printk, pr_info or pr_err
 	   One regex pattern per line.  Multiple K: lines acceptable.
 Note: For the hard of thinking, this list is meant to remain in alphabetical
 order. If you could add yourselves to it in alphabetical order that would be
 so much easier [Ed]
 Maintainers List (try to look for most precise areas first)
 		-----------------------------------
 ARC
 M:	Alexey Brodkin <alexey.brodkin@synopsys.com>
 M:	Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
 S:	Maintained
 L:	uboot-snps-arc@synopsys.com
 T:	git git://git.denx.de/u-boot-arc.git
 F:	arch/arc/
 F:	board/synopsys/
 ARC HSDK CGU CLOCK
 M:	Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
 S:	Maintained
 L:	uboot-snps-arc@synopsys.com
 F:	drivers/clk/clk-hsdk-cgu.c
 F:	include/dt-bindings/clock/snps,hsdk-cgu.h
 F:	doc/device-tree-bindings/clock/snps,hsdk-cgu.txt
 ARC HSDK CREG GPIO
 M:	Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
 S:	Maintained
 L:	uboot-snps-arc@synopsys.com
 F:	doc/device-tree-bindings/gpio/snps,creg-gpio.txt
 F:	drivers/gpio/hsdk-creg-gpio.c
 ARM
 M:	Albert Aribaud <albert.u.boot@aribaud.net>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-arm.git
 F:	arch/arm/
 ARM ALTERA SOCFPGA
 M:	Marek Vasut <marex@denx.de>
 S:	Maintainted
 T:	git git://git.denx.de/u-boot-socfpga.git
 F:	arch/arm/mach-socfpga/
 ARM ATMEL AT91
 M:	Andreas Bießmann <andreas@biessmann.org>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-atmel.git
 F:	arch/arm/mach-at91/
 ARM BROADCOM BCM283X
 M:	Alexander Graf <agraf@suse.de>
 S:	Maintained
 F:	arch/arm/mach-bcm283x/
 F:	drivers/gpio/bcm2835_gpio.c
 F:	drivers/mmc/bcm2835_sdhci.c
 F:	drivers/mmc/bcm2835_sdhost.c
 F:	drivers/serial/serial_bcm283x_mu.c
 F:	drivers/serial/serial_bcm283x_pl011.c
 F:	drivers/video/bcm2835.c
 F:	include/dm/platform_data/serial_bcm283x_mu.h
 F:	drivers/pinctrl/broadcom/
 ARM BROADCOM BCMSTB
 M:	Thomas Fitzsimmons <fitzsim@fitzsim.org>
 S:	Maintained
 F:	arch/arm/mach-bcmstb/
 F:	board/broadcom/bcmstb/
 F:	configs/bcm7*_defconfig
 F:	doc/README.bcm7xxx
 F:	drivers/mmc/bcmstb_sdhci.c
 F:	drivers/spi/bcmstb_spi.c
 ARM FREESCALE IMX
 M:	Stefano Babic <sbabic@denx.de>
 M:	Fabio Estevam <fabio.estevam@nxp.com>
 R:	NXP i.MX U-Boot Team <uboot-imx@nxp.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-imx.git
 F:	arch/arm/cpu/arm1136/mx*/
 F:	arch/arm/cpu/arm926ejs/mx*/
 F:	arch/arm/cpu/armv7/vf610/
 F:	arch/arm/mach-imx/
 F:	arch/arm/include/asm/arch-imx/
 F:	arch/arm/include/asm/arch-mx*/
 F:	arch/arm/include/asm/arch-vf610/
 F:	arch/arm/include/asm/mach-imx/
 F:	board/freescale/*mx*/
 ARM HISILICON
 M:	Peter Griffin <peter.griffin@linaro.org>
 S:	Maintained
 F:	arch/arm/cpu/armv8/hisilicon
 F:	arch/arm/include/asm/arch-hi6220/
 ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX
 M:	Prafulla Wadaskar <prafulla@marvell.com>
 M:	Luka Perkov <luka.perkov@sartura.hr>
 M:	Stefan Roese <sr@denx.de>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-marvell.git
 F:	arch/arm/mach-kirkwood/
 F:	arch/arm/mach-mvebu/
 F:	drivers/ata/ahci_mvebu.c
 F:	drivers/phy/marvell/
 ARM MARVELL PXA
 M:	Marek Vasut <marex@denx.de>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-pxa.git
 F:	arch/arm/cpu/pxa/
 F:	arch/arm/include/asm/arch-pxa/
 ARM MEDIATEK
 M:	Ryder Lee <ryder.lee@mediatek.com>
 M:	Weijie Gao <weijie.gao@mediatek.com>
 S:	Maintained
 F:	arch/arm/mach-mediatek/
 F:	arch/arm/include/asm/arch-mediatek/
 F:	board/mediatek/
 F:	doc/README.mediatek
 F:	drivers/clk/mediatek/
 F:	drivers/mmc/mtk-sd.c
 F:	drivers/pinctrl/mediatek/
 F:	drivers/power/domain/mtk-power-domain.c
 F:	drivers/ram/mediatek/
 F:	drivers/spi/mtk_qspi.c
 F:	drivers/timer/mtk_timer.c
 F:	drivers/watchdog/mtk_wdt.c
 F:	drivers/net/mtk_eth.c
 F:	drivers/reset/reset-mediatek.c
 F:	tools/mtk_image.c
 F:	tools/mtk_image.h
 N:	mediatek
 ARM OWL
 M:	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
 S:	Maintained
 F:	arch/arm/include/asm/arch-owl/
 F:	arch/arm/mach-owl/
 F:	board/ucRobotics/
 F:	drivers/clk/owl/
 F:	drivers/serial/serial_owl.c
 ARM RENESAS RMOBILE/R-CAR
 M:	Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 M:	Marek Vasut <marek.vasut+renesas@gmail.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-sh.git
 F:	arch/arm/mach-rmobile/
 ARM ROCKCHIP
 M:	Simon Glass <sjg@chromium.org>
 M:	Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-rockchip.git
 F:	arch/arm/include/asm/arch-rockchip/
 F:	arch/arm/mach-rockchip/
 F:	board/rockchip/
 F:	drivers/clk/rockchip/
 F:	drivers/gpio/rk_gpio.c
 F:	drivers/misc/rockchip-efuse.c
 F:	drivers/mmc/rockchip_sdhci.c
 F:	drivers/mmc/rockchip_dw_mmc.c
 F:	drivers/pinctrl/rockchip/
 F:	drivers/ram/rockchip/
 F:	drivers/sysreset/sysreset_rockchip.c
 F:	drivers/video/rockchip/
 F:	tools/rkcommon.c
 F:	tools/rkcommon.h
 F:	tools/rkimage.c
 F:	tools/rksd.c
 F:	tools/rkspi.c
 ARM SAMSUNG
 M:	Minkyu Kang <mk7.kang@samsung.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-samsung.git
 F:	arch/arm/mach-exynos/
 F:	arch/arm/mach-s5pc1xx/
 F:	arch/arm/cpu/armv7/s5p-common/
 ARM SNAPDRAGON
 M:	Ramon Fried <ramon.fried@gmail.com>
 S:	Maintained
 F:	arch/arm/mach-snapdragon/
 F:	drivers/gpio/msm_gpio.c
 F:	drivers/mmc/msm_sdhci.c
 F:	drivers/phy/msm8916-usbh-phy.c
 F:	drivers/serial/serial_msm.c
 F:	drivers/smem/msm_smem.c
 F:	drivers/usb/host/ehci-msm.c
 ARM STI
 M:	Patrice Chotard <patrice.chotard@st.com>
 S:	Maintained
 F:	arch/arm/mach-sti/
 F:	arch/arm/include/asm/arch-sti*/
 ARM STM SPEAR
 #M:	Vipin Kumar <vipin.kumar@st.com>
 S:	Orphaned (Since 2016-02)
 T:	git git://git.denx.de/u-boot-stm.git
 F:	arch/arm/cpu/arm926ejs/spear/
 F:	arch/arm/include/asm/arch-spear/
 ARM STM STM32MP
 M:	Patrick Delaunay <patrick.delaunay@st.com>
 M:	Christophe Kerello <christophe.kerello@st.com>
 M:	Patrice Chotard <patrice.chotard@st.com>
 L:	uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
 S:	Maintained
 F:	arch/arm/mach-stm32mp
 F:	drivers/clk/clk_stm32mp1.c
 F:	drivers/i2c/stm32f7_i2c.c
 F:	drivers/misc/stm32mp_fuse.c
 F:	drivers/mmc/stm32_sdmmc2.c
 F:	drivers/phy/phy-stm32-usbphyc.c
 F:	drivers/pinctrl/pinctrl_stm32.c
 F:	drivers/power/regulator/stm32-vrefbuf.c
 F:	drivers/ram/stm32mp1/
 F:	drivers/misc/stm32_rcc.c
 F:	drivers/reset/stm32-reset.c
 F:	drivers/spi/stm32_qspi.c
 ARM STM STV0991
 M:	Vikas Manocha <vikas.manocha@st.com>
 S:	Maintained
 F:	arch/arm/cpu/armv7/stv0991/
 F:	arch/arm/include/asm/arch-stv0991/
 ARM SUNXI
 M:	Jagan Teki <jagan@openedev.com>
 M:	Maxime Ripard <maxime.ripard@bootlin.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-sunxi.git
 F:	arch/arm/cpu/armv7/sunxi/
 F:	arch/arm/include/asm/arch-sunxi/
 F:	arch/arm/mach-sunxi/
 F:	board/sunxi/
 ARM TEGRA
 M:	Tom Warren <twarren@nvidia.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-tegra.git
 F:	arch/arm/mach-tegra/
 F:	arch/arm/include/asm/arch-tegra*/
 ARM TI
 M:	Tom Rini <trini@konsulko.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-ti.git
 F:	arch/arm/mach-davinci/
 F:	arch/arm/mach-k3/
 F:	arch/arm/mach-keystone/
 F:	arch/arm/include/asm/arch-omap*/
 F:	arch/arm/include/asm/ti-common/
 ARM UNIPHIER
 M:	Masahiro Yamada <yamada.masahiro@socionext.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-uniphier.git
 F:	arch/arm/mach-uniphier/
 F:	configs/uniphier_*_defconfig
 N:	uniphier
 ARM VERSAL
 M:	Michal Simek <michal.simek@xilinx.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-microblaze.git
 F:	arch/arm/mach-versal/
 ARM VERSATILE EXPRESS DRIVERS
 M:	Liviu Dudau <liviu.dudau@foss.arm.com>
 S:	Maintained
 T:	git git://github.com/ARM-software/u-boot.git
 F:	drivers/misc/vexpress_config.c
 N:	vexpress
 ARM ZYNQ
 M:	Michal Simek <monstr@monstr.eu>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-microblaze.git
 F:	arch/arm/mach-zynq/
 F:	drivers/clk/clk_zynq.c
 F:	drivers/fpga/zynqpl.c
 F:	drivers/gpio/zynq_gpio.c
 F:	drivers/i2c/i2c-cdns.c
 F:	drivers/i2c/muxes/pca954x.c
 F:	drivers/i2c/zynq_i2c.c
 F:	drivers/mmc/zynq_sdhci.c
 F:	drivers/mtd/nand/raw/zynq_nand.c
 F:	drivers/net/phy/xilinx_phy.c
 F:	drivers/net/zynq_gem.c
 F:	drivers/serial/serial_zynq.c
 F:	drivers/spi/zynq_qspi.c
 F:	drivers/spi/zynq_spi.c
 F:	drivers/usb/host/ehci-zynq.c
 F:	drivers/watchdog/cdns_wdt.c
 F:	include/zynqpl.h
 F:	tools/zynqimage.c
 N:	zynq
 ARM ZYNQMP
 M:	Michal Simek <michal.simek@xilinx.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-microblaze.git
 F:	arch/arm/cpu/armv8/zynqmp/
 F:	drivers/clk/clk_zynqmp.c
 F:	drivers/fpga/zynqpl.c
 F:	drivers/gpio/zynq_gpio.c
 F:	drivers/i2c/i2c-cdns.c
 F:	drivers/i2c/muxes/pca954x.c
 F:	drivers/i2c/zynq_i2c.c
 F:	drivers/mmc/zynq_sdhci.c
 F:	drivers/mtd/nand/raw/zynq_nand.c
 F:	drivers/net/phy/xilinx_phy.c
 F:	drivers/net/zynq_gem.c
 F:	drivers/serial/serial_zynq.c
 F:	drivers/spi/zynq_qspi.c
 F:	drivers/spi/zynq_spi.c
 F:	drivers/timer/cadence-ttc.c
 F:	drivers/usb/host/ehci-zynq.c
 F:	drivers/watchdog/cdns_wdt.c
 F:	include/zynqmppl.h
 F:	tools/zynqmp*
 N:	ultra96
 N:	zynqmp
 ARM ZYNQMP R5
 M:	Michal Simek <michal.simek@xilinx.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-microblaze.git
 F:	arch/arm/mach-zynqmp-r5/
 BINMAN
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
 F:	tools/binman/
 BUILDMAN
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
 F:	tools/buildman/
 CFI FLASH
 M:	Stefan Roese <sr@denx.de>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-cfi-flash.git
 F:	drivers/mtd/cfi_flash.c
 F:	drivers/mtd/jedec_flash.c
 COLDFIRE
 M:	Huan Wang <alison.wang@nxp.com>
 M:	Angelo Dureghello <angelo@sysam.it>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-coldfire.git
 F:	arch/m68k/
 DFU
 M:	Lukasz Majewski <lukma@denx.de>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-dfu.git
 F:	drivers/dfu/
 F:	drivers/usb/gadget/
 DRIVER MODEL
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-dm.git
 F:	drivers/core/
 F:	include/dm/
 F:	test/dm/
 EFI PAYLOAD
 M:	Alexander Graf <agraf@suse.de>
 R:	Heinrich Schuchardt <xypron.glpk@gmx.de>
 S:	Maintained
 T:	git git://github.com/agraf/u-boot.git
 F:	doc/README.uefi
 F:	doc/README.iscsi
 F:	Documentation/efi.rst
 F:	include/capitalization.h
 F:	include/cp1250.h
 F:	include/cp437.h
 F:	include/efi*
 F:	include/pe.h
 F:	include/asm-generic/pe.h
 F:	lib/charset.c
 F:	lib/efi*/
 F:	test/py/tests/test_efi*
 F:	test/unicode_ut.c
 F:	cmd/bootefi.c
 F:	tools/file2include.c
 FPGA
 M:	Michal Simek <michal.simek@xilinx.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-microblaze.git
 F:	drivers/fpga/
 F:	cmd/fpga.c
 F:	include/fpga.h
 FLATTENED DEVICE TREE
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-fdt.git
 F:	lib/fdtdec*
 F:	lib/libfdt/
 F:	include/fdt*
 F:	include/linux/libfdt*
 F:	cmd/fdt.c
 F:	common/fdt_support.c
 FREEBSD
 M:	Rafal Jaworowski <raj@semihalf.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-freebsd.git
 FREESCALE QORIQ
 M:	York Sun <york.sun@nxp.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-fsl-qoriq.git
 I2C
 M:	Heiko Schocher <hs@denx.de>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-i2c.git
 F:	drivers/i2c/
 LOGGING
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
 T:	git git://git.denx.de/u-boot.git
 F:	common/log.c
 F:	cmd/log.c
 F:	test/log/log_test.c
 F:	test/py/tests/test_log.py
 MALI DISPLAY PROCESSORS
 M:	Liviu Dudau <liviu.dudau@foss.arm.com>
 S:	Supported
 T:	git git://github.com/ARM-software/u-boot.git
 F:	drivers/video/mali_dp.c
 F:	drivers/i2c/i2c-versatile.c
 MICROBLAZE
 M:	Michal Simek <monstr@monstr.eu>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-microblaze.git
 F:	arch/microblaze/
 F:	cmd/mfsl.c
 F:	drivers/gpio/xilinx_gpio.c
 F:	drivers/net/xilinx_axi_emac.c
 F:	drivers/net/xilinx_emaclite.c
 F:	drivers/serial/serial_xuartlite.c
 F:	drivers/spi/xilinx_spi.c
 F:	drivers/sysreset/sysreset_gpio.c
 F:	drivers/watchdog/xilinx_tb_wdt.c
 N:	xilinx
 MIPS
 M:	Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-mips.git
 F:	arch/mips/
 MIPS MSCC
 M:	Gregory CLEMENT <gregory.clement@bootlin.com>
 M:	Lars Povlsen <lars.povlsen@microchip.com>
 M:	Horatiu Vultur <horatiu.vultur@microchip.com>
 S:	Maintained
 F:	arch/mips/mach-mscc/
 F:	arch/mips/dts/luton*
 F:	arch/mips/dts/mscc*
 F:	arch/mips/dts/ocelot*
+F:	arch/mips/dts/jr2*
+F:	arch/mips/dts/serval*
 F:	board/mscc/
 F:	configs/mscc*
+F:	drivers/gpio/mscc_sgpio.c
+F:	drivers/spi/mscc_bb_spi.c
 F:	include/configs/vcoreiii.h
+F:	drivers/pinctrl/mscc/
 MIPS JZ4780
 M:	Ezequiel Garcia <ezequiel@collabora.com>
 S:	Maintained
 F:	arch/mips/mach-jz47xx/
 MMC
 M:	Jaehoon Chung <jh80.chung@samsung.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-mmc.git
 F:	drivers/mmc/
 NAND FLASH
 #M:	Scott Wood <oss@buserror.net>
 S:	Orphaned (Since 2018-07)
 T:	git git://git.denx.de/u-boot-nand-flash.git
 F:	drivers/mtd/nand/raw/
 NDS32
 M:	Macpaul Lin <macpaul@andestech.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-nds32.git
 F:	arch/nds32/
 NETWORK
 M:	Joe Hershberger <joe.hershberger@ni.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-net.git
 F:	drivers/net/
 F:	net/
 NIOS
 M:	Thomas Chou <thomas@wytron.com.tw>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-nios.git
 F:	arch/nios2/
 ONENAND
 #M:	Lukasz Majewski <l.majewski@majess.pl>
 S:	Orphaned (Since 2017-01)
 T:	git git://git.denx.de/u-boot-onenand.git
 F:	drivers/mtd/onenand/
 PATMAN
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
 F:	tools/patman/
 POWER
 M:	Jaehoon Chung <jh80.chung@samsung.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-pmic.git
 F:	drivers/power/
 POWERPC
 M:	Wolfgang Denk <wd@denx.de>
 S:	Maintained
 F:	arch/powerpc/
 POWERPC MPC8XX
 M:	Christophe Leroy <christophe.leroy@c-s.fr>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-mpc8xx.git
 F:	arch/powerpc/cpu/mpc8xx/
 POWERPC MPC83XX
 M:	Mario Six <mario.six@gdsys.cc>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-mpc83xx.git
 F:	drivers/ram/mpc83xx_sdram.c
 F:	include/dt-bindings/memory/mpc83xx-sdram.h
 F:	drivers/sysreset/sysreset_mpc83xx.c
 F:	drivers/sysreset/sysreset_mpc83xx.h
 F:	drivers/clk/mpc83xx_clk.c
 F:	drivers/clk/mpc83xx_clk.h
 F:	include/dt-bindings/clk/mpc83xx-clk.h
 F:	drivers/timer/mpc83xx_timer.c
 F:	drivers/cpu/mpc83xx_cpu.c
 F:	drivers/cpu/mpc83xx_cpu.h
 F:	drivers/misc/mpc83xx_serdes.c
 F:	arch/powerpc/cpu/mpc83xx/
 F:	arch/powerpc/include/asm/arch-mpc83xx/
 POWERPC MPC85XX
 M:	York Sun <york.sun@nxp.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-mpc85xx.git
 F:	arch/powerpc/cpu/mpc85xx/
 POWERPC MPC86XX
 M:	York Sun <york.sun@nxp.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-mpc86xx.git
 F:	arch/powerpc/cpu/mpc86xx/
 RISC-V
 M:	Rick Chen <rick@andestech.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-riscv.git
 F:	arch/riscv/
 F:	tools/prelink-riscv.c
 ROCKUSB
 M:	Eddie Cai <eddie.cai.linux@gmail.com>
 S:	Maintained
 F:	drivers/usb/gadget/f_rockusb.c
 F:	cmd/rockusb.c
 F:	doc/README.rockusb
 SANDBOX
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
 F:	arch/sandbox/
 SH
 M:	Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-sh.git
 F:	arch/sh/
 SPI
 M:	Jagan Teki <jagan@openedev.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-spi.git
 F:	drivers/mtd/spi/
 F:	drivers/spi/
 F:	include/spi*
 SPMI
 M:	Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
 S:	Maintained
 F:	drivers/spmi/
 F:	include/spmi/
 TDA19988 HDMI ENCODER
 M:	Liviu Dudau <liviu.dudau@foss.arm.com>
 S:	Maintained
 F:	drivers/video/tda19988.c
 TI SYSTEM SECURITY
 M:	Andrew F. Davis <afd@ti.com>
 S:	Supported
 F:	arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
 F:	arch/arm/mach-omap2/sec-common.c
 F:	arch/arm/mach-omap2/config_secure.mk
 F:	configs/am335x_hs_evm_defconfig
 F:	configs/am335x_hs_evm_uart_defconfig
 F:	configs/am43xx_hs_evm_defconfig
 F:	configs/am57xx_hs_evm_defconfig
 F:	configs/dra7xx_hs_evm_defconfig
 F:	configs/k2hk_hs_evm_defconfig
 F:	configs/k2e_hs_evm_defconfig
 F:	configs/k2g_hs_evm_defconfig
 F:	configs/k2l_hs_evm_defconfig
 TQ GROUP
 #M:	Martin Krause <martin.krause@tq-systems.de>
 S:	Orphaned (Since 2016-02)
 T:	git git://git.denx.de/u-boot-tq-group.git
 TEE
 M:	Jens Wiklander <jens.wiklander@linaro.org>
 S:	Maintained
 F:	drivers/tee/
 F:	include/tee.h
 F:	include/tee/
 UBI
 M:	Kyungmin Park <kmpark@infradead.org>
 M:	Heiko Schocher <hs@denx.de>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-ubi.git
 F:	drivers/mtd/ubi/
 USB
 M:	Marek Vasut <marex@denx.de>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-usb.git
 F:	drivers/usb/
 USB xHCI
 M:	Bin Meng <bmeng.cn@gmail.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-usb.git topic-xhci
 F:	drivers/usb/host/xhci*
 VIDEO
 M:	Anatolij Gustschin <agust@denx.de>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-video.git
 F:	drivers/video/
 F:	common/lcd*.c
 F:	include/lcd*.h
 F:	include/video*.h
 X86
 M:	Simon Glass <sjg@chromium.org>
 M:	Bin Meng <bmeng.cn@gmail.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-x86.git
 F:	arch/x86/
 XTENSA
 M:	Max Filippov <jcmvbkbc@gmail.com>
 S:	Maintained
 F:	arch/xtensa/
 THE REST
 M:	Tom Rini <trini@konsulko.com>
 L:	u-boot@lists.denx.de
 Q:	http://patchwork.ozlabs.org/project/uboot/list/
 S:	Maintained
 T:	git git://git.denx.de/u-boot.git
 F:	configs/tools-only_defconfig
 F:	*
 F:	*/

arch/mips/cpu/u-boot-spl.lds

Diff comments View file @ f83ef0d

1	/* SPDX-License-Identifier: GPL-2.0+ */	1	/* SPDX-License-Identifier: GPL-2.0+ */
2		2
3	MEMORY { .spl_mem : ORIGIN = CONFIG_SPL_TEXT_BASE, \	3	MEMORY { .spl_mem : ORIGIN = CONFIG_SPL_TEXT_BASE, \
4	LENGTH = CONFIG_SPL_MAX_SIZE }	4	LENGTH = CONFIG_SPL_MAX_SIZE }
5	MEMORY { .bss_mem : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \	5	MEMORY { .bss_mem : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
6	LENGTH = CONFIG_SPL_BSS_MAX_SIZE }	6	LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
7		7
8	OUTPUT_ARCH(mips)	8	OUTPUT_ARCH(mips)
9	ENTRY(_start)	9	ENTRY(_start)
10	SECTIONS	10	SECTIONS
11	{	11	{
12	. = 0x00000000;	12	. = 0x00000000;
13		13
14	. = ALIGN(4);	14	. = ALIGN(4);
15	.text : {	15	.text : {
16	(.text)	16	(.text)
17	} > .spl_mem	17	} > .spl_mem
18		18
19	. = ALIGN(4);	19	. = ALIGN(4);
20	.rodata : {	20	.rodata : {
21	(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata)))	21	(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata)))
22	} > .spl_mem	22	} > .spl_mem
23		23
24	. = ALIGN(4);	24	. = ALIGN(4);
25	.data : {	25	.data : {
26	(SORT_BY_ALIGNMENT(.data))	26	(SORT_BY_ALIGNMENT(.data))
27	(SORT_BY_ALIGNMENT(.sdata))	27	(SORT_BY_ALIGNMENT(.sdata))
28	} > .spl_mem	28	} > .spl_mem
29		29
30	#ifdef CONFIG_SPL_DM	30	#ifdef CONFIG_SPL_DM
31	. = ALIGN(4);	31	. = ALIGN(4);
32	.u_boot_list : {	32	.u_boot_list : {
33	KEEP((SORT(.u_boot_list)));	33	KEEP((SORT(.u_boot_list)));
34	} > .spl_mem	34	} > .spl_mem
35	#endif	35	#endif
36		36
37	. = ALIGN(4);	37	. = ALIGN(4);
38	__image_copy_end = .;	38	__image_copy_end = .;
39		39
40	.bss (NOLOAD) : {	40	.bss (NOLOAD) : {
41	__bss_start = .;	41	__bss_start = .;
42	(.bss)	42	(.bss)
43	(.sbss)	43	(.sbss)
44	*(COMMON)	44	*(COMMON)
45	. = ALIGN(4);	45	. = ALIGN(4);
46	__bss_end = .;	46	__bss_end = .;
47	} > .bss_mem	47	} > .bss_mem
48		48
49	.rel.dyn (NOLOAD) : {	49	/* These mark the ABI of U-Boot for debuggers. */
50	*(.rel.dyn)	50	.mdebug.abi32 : {
		51	KEEP(*(.mdebug.abi32))
51	}	52	}
52		53	.mdebug.abi64 : {
53	.dynsym : {	54	KEEP(*(.mdebug.abi64))
54	*(.dynsym)
55	}	55	}
56		56
57	.dynbss : {	57	/* This is the MIPS specific mdebug section. */
58	*(.dynbss)	58	.mdebug : { *(.mdebug) }
59	}
60		59
61	.dynstr : {	60	/* Stabs debugging sections. */
62	*(.dynstr)	61	.stab 0 : { *(.stab) }
63	}	62	.stabstr 0 : { *(.stabstr) }
		63	.stab.excl 0 : { *(.stab.excl) }
		64	.stab.exclstr 0 : { *(.stab.exclstr) }
		65	.stab.index 0 : { *(.stab.index) }
		66	.stab.indexstr 0 : { *(.stab.indexstr) }
		67	.comment 0 : { *(.comment) }
64		68
65	.dynamic : {	69	/*
66	*(.dynamic)	70	* DWARF debug sections.
		71	* Symbols in the DWARF debugging sections are relative to
		72	* the beginning of the section so we begin them at 0.
		73	*/
		74	/* DWARF 1 */
		75	.debug 0 : { *(.debug) }
		76	.line 0 : { *(.line) }
		77	/* GNU DWARF 1 extensions */
		78	.debug_srcinfo 0 : { *(.debug_srcinfo) }
		79	.debug_sfnames 0 : { *(.debug_sfnames) }
		80	/* DWARF 1.1 and DWARF 2 */
		81	.debug_aranges 0 : { *(.debug_aranges) }
		82	.debug_pubnames 0 : { *(.debug_pubnames) }
		83	/* DWARF 2 */
		84	.debug_info 0 : {
		85	*(.debug_info
		86	.gnu.linkonce.wi.*)
67	}	87	}
		88	.debug_abbrev 0 : { *(.debug_abbrev) }
		89	.debug_line 0 : { *(.debug_line) }
		90	.debug_frame 0 : { *(.debug_frame) }
		91	.debug_str 0 : { *(.debug_str) }
		92	.debug_loc 0 : { *(.debug_loc) }
		93	.debug_macinfo 0 : { *(.debug_macinfo) }
		94	.debug_pubtypes 0 : { *(.debug_pubtypes) }
		95	/* DWARF 3 */
		96	.debug_ranges 0 : { *(.debug_ranges) }
		97	/* SGI/MIPS DWARF 2 extensions */
		98	.debug_weaknames 0 : { *(.debug_weaknames) }
		99	.debug_funcnames 0 : { *(.debug_funcnames) }
		100	.debug_typenames 0 : { *(.debug_typenames) }
		101	.debug_varnames 0 : { *(.debug_varnames) }
		102	/* GNU DWARF 2 extensions */
		103	.debug_gnu_pubnames 0 : { *(.debug_gnu_pubnames) }
		104	.debug_gnu_pubtypes 0 : { *(.debug_gnu_pubtypes) }
		105	/* DWARF 4 */
		106	.debug_types 0 : { *(.debug_types) }
		107	/* DWARF 5 */
		108	.debug_macro 0 : { *(.debug_macro) }
		109	.debug_addr 0 : { *(.debug_addr) }
68		110
69	.plt : {	111	/DISCARD/ : {
70	*(.plt)	112	/* ABI crap starts here */
71	}	113	*(.MIPS.abiflags)
72		114	*(.MIPS.options)
73	.interp : {	115	*(.options)
74	*(.interp)	116	*(.pdr)
75	}	117	*(.reginfo)
76		118	*(.eh_frame)
77	.gnu : {

arch/mips/cpu/u-boot.lds

Diff comments View file @ f83ef0d

1	/* SPDX-License-Identifier: GPL-2.0+ */	1	/* SPDX-License-Identifier: GPL-2.0+ */
2	/*	2	/*
3	* (C) Copyright 2003	3	* (C) Copyright 2003
4	* Wolfgang Denk Engineering, <wd@denx.de>	4	* Wolfgang Denk Engineering, <wd@denx.de>
5	*/	5	*/
6		6
7	OUTPUT_ARCH(mips)	7	OUTPUT_ARCH(mips)
8	ENTRY(_start)	8	ENTRY(_start)
9	SECTIONS	9	SECTIONS
10	{	10	{
11	. = 0x00000000;	11	. = 0x00000000;
12		12
13	. = ALIGN(4);	13	. = ALIGN(4);
14	.text : {	14	.text : {
15	__text_start = .;	15	__text_start = .;
16	(.text)	16	(.text)
17	__text_end = .;	17	__text_end = .;
18	}	18	}
19		19
20	. = ALIGN(4);	20	. = ALIGN(4);
21	.rodata : {	21	.rodata : {
22	(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata)))	22	(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata)))
23	}	23	}
24		24
25	. = ALIGN(4);	25	. = ALIGN(4);
26	.data : {	26	.data : {
27	(.data)	27	(.data)
28	}	28	}
29		29
30	. = ALIGN(4);	30	. = ALIGN(4);
31	.sdata : {	31	.sdata : {
32	(.sdata)	32	(.sdata)
33	}	33	}
34		34
35	. = ALIGN(4);	35	. = ALIGN(4);
36	.u_boot_list : {	36	.u_boot_list : {
37	KEEP((SORT(.u_boot_list)));	37	KEEP((SORT(.u_boot_list)));
38	}	38	}
39		39
40	. = ALIGN(4);	40	. = ALIGN(4);
41	__image_copy_end = .;	41	__image_copy_end = .;
42	__init_end = .;	42	__init_end = .;
43		43
44	.data.reloc : {	44	.data.reloc : {
45	__rel_start = .;	45	__rel_start = .;
46	/*	46	/*
47	* Space for relocation table	47	* Space for relocation table
48	* This needs to be filled so that the	48	* This needs to be filled so that the
49	* mips-reloc tool can overwrite the content.	49	* mips-reloc tool can overwrite the content.
50	* An invalid value is left at the start of the	50	* An invalid value is left at the start of the
51	* section to abort relocation if the table	51	* section to abort relocation if the table
52	* has not been filled in.	52	* has not been filled in.
53	*/	53	*/
54	LONG(0xFFFFFFFF);	54	LONG(0xFFFFFFFF);
55	FILL(0);	55	FILL(0);
56	. += CONFIG_MIPS_RELOCATION_TABLE_SIZE - 4;	56	. += CONFIG_MIPS_RELOCATION_TABLE_SIZE - 4;
57	}	57	}
58		58
59	. = ALIGN(4);	59	. = ALIGN(4);
60	_end = .;	60	_end = .;
61		61
62	.bss __rel_start (OVERLAY) : {	62	.bss __rel_start (OVERLAY) : {
63	__bss_start = .;	63	__bss_start = .;
64	(.sbss.)	64	(.sbss.)
65	(.bss.)	65	(.bss.)
66	*(COMMON)	66	*(COMMON)
67	. = ALIGN(4);	67	. = ALIGN(4);
68	__bss_end = .;	68	__bss_end = .;
69	}	69	}
70		70
71	.dynsym _end : {	71	/* These mark the ABI of U-Boot for debuggers. */
72	*(.dynsym)	72	.mdebug.abi32 : {
		73	KEEP(*(.mdebug.abi32))
73	}	74	}
74		75	.mdebug.abi64 : {
75	.dynbss : {	76	KEEP(*(.mdebug.abi64))
76	*(.dynbss)
77	}	77	}
78		78
79	.dynstr : {	79	/* This is the MIPS specific mdebug section. */
80	*(.dynstr)	80	.mdebug : { *(.mdebug) }
81	}
82		81
83	.dynamic : {	82	/* Stabs debugging sections. */
84	*(.dynamic)	83	.stab 0 : { *(.stab) }
85	}	84	.stabstr 0 : { *(.stabstr) }
		85	.stab.excl 0 : { *(.stab.excl) }
		86	.stab.exclstr 0 : { *(.stab.exclstr) }
		87	.stab.index 0 : { *(.stab.index) }
		88	.stab.indexstr 0 : { *(.stab.indexstr) }
		89	.comment 0 : { *(.comment) }
86		90
87	.plt : {	91	/*
88	*(.plt)	92	* DWARF debug sections.
		93	* Symbols in the DWARF debugging sections are relative to
		94	* the beginning of the section so we begin them at 0.
		95	*/
		96	/* DWARF 1 */
		97	.debug 0 : { *(.debug) }
		98	.line 0 : { *(.line) }
		99	/* GNU DWARF 1 extensions */
		100	.debug_srcinfo 0 : { *(.debug_srcinfo) }
		101	.debug_sfnames 0 : { *(.debug_sfnames) }
		102	/* DWARF 1.1 and DWARF 2 */
		103	.debug_aranges 0 : { *(.debug_aranges) }
		104	.debug_pubnames 0 : { *(.debug_pubnames) }
		105	/* DWARF 2 */
		106	.debug_info 0 : {
		107	*(.debug_info
		108	.gnu.linkonce.wi.*)
89	}	109	}
		110	.debug_abbrev 0 : { *(.debug_abbrev) }
		111	.debug_line 0 : { *(.debug_line) }
		112	.debug_frame 0 : { *(.debug_frame) }
		113	.debug_str 0 : { *(.debug_str) }
		114	.debug_loc 0 : { *(.debug_loc) }
		115	.debug_macinfo 0 : { *(.debug_macinfo) }
		116	.debug_pubtypes 0 : { *(.debug_pubtypes) }
		117	/* DWARF 3 */
		118	.debug_ranges 0 : { *(.debug_ranges) }
		119	/* SGI/MIPS DWARF 2 extensions */
		120	.debug_weaknames 0 : { *(.debug_weaknames) }
		121	.debug_funcnames 0 : { *(.debug_funcnames) }
		122	.debug_typenames 0 : { *(.debug_typenames) }
		123	.debug_varnames 0 : { *(.debug_varnames) }
		124	/* GNU DWARF 2 extensions */
		125	.debug_gnu_pubnames 0 : { *(.debug_gnu_pubnames) }
		126	.debug_gnu_pubtypes 0 : { *(.debug_gnu_pubtypes) }
		127	/* DWARF 4 */
		128	.debug_types 0 : { *(.debug_types) }
		129	/* DWARF 5 */
		130	.debug_macro 0 : { *(.debug_macro) }
		131	.debug_addr 0 : { *(.debug_addr) }
90		132
91	.interp : {	133	/DISCARD/ : {
92	*(.interp)	134	/* ABI crap starts here */
93	}	135	*(.MIPS.abiflags)
94		136	*(.MIPS.options)
95	.gnu : {	137	*(.options)
96	(.gnu)	138	*(.pdr)
97	}	139	*(.reginfo)
98		140	*(.eh_frame)
99	.MIPS.stubs : {

arch/mips/dts/Makefile

Diff comments View file @ f83ef0d

 # SPDX-License-Identifier: GPL-2.0+
 dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
 dtb-$(CONFIG_TARGET_AP143) += ap143.dtb
 dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb
 dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
 dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
 dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb
 dtb-$(CONFIG_BOARD_COMTREND_AR5315U) += comtrend,ar-5315u.dtb
 dtb-$(CONFIG_BOARD_COMTREND_AR5387UN) += comtrend,ar-5387un.dtb
 dtb-$(CONFIG_BOARD_COMTREND_CT5361) += comtrend,ct-5361.dtb
 dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
 dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb
 dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
 dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
 dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
 dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb
 dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
 dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
+dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb
+dtb-$(CONFIG_SOC_OCELOT) += ocelot_pcb120.dtb ocelot_pcb123.dtb
+dtb-$(CONFIG_SOC_JR2) += jr2_pcb110.dtb jr2_pcb111.dtb serval2_pcb112.dtb
 targets += $(dtb-y)
 # Add any required device tree compiler flags here
 DTC_FLAGS +=
 PHONY += dtbs
 dtbs: $(addprefix $(obj)/, $(dtb-y))
 	@:
 clean-files := *.dtb

arch/mips/dts/gardena-smart-gateway-mt7688.dts

Diff comments View file @ f83ef0d

1	// SPDX-License-Identifier: GPL-2.0	1	// SPDX-License-Identifier: GPL-2.0
2	/*	2	/*
3	* Copyright (C) 2018 Stefan Roese <sr@denx.de>	3	* Copyright (C) 2018 Stefan Roese <sr@denx.de>
4	*/	4	*/
5		5
6	/dts-v1/;	6	/dts-v1/;
7		7
8	#include "mt7628a.dtsi"	8	#include "mt7628a.dtsi"
9	#include <dt-bindings/gpio/gpio.h>	9	#include <dt-bindings/gpio/gpio.h>
10		10
11	/ {	11	/ {
12	compatible = "gardena,smart-gateway-mt7688", "ralink,mt7628a-soc";	12	compatible = "gardena,smart-gateway-mt7688", "ralink,mt7628a-soc";
13	model = "Gardena smart-Gateway-MT7688";	13	model = "Gardena smart-Gateway-MT7688";
14		14
15	aliases {	15	aliases {
16	serial0 = &uart0;	16	serial0 = &uart0;
17	spi0 = &spi0;	17	spi0 = &spi0;
18	};	18	};
19		19
20	memory@0 {	20	memory@0 {
21	device_type = "memory";	21	device_type = "memory";
22	reg = <0x0 0x08000000>;	22	reg = <0x0 0x08000000>;
23	};	23	};
24		24
25	leds {	25	leds {
26	compatible = "gpio-leds";	26	compatible = "gpio-leds";
27		27
28	power_blue {	28	power_blue {
29	label = "smartgw:power:blue";	29	label = "smartgw:power:blue";
30	gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;	30	gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
31	default-state = "off";	31	default-state = "off";
32	};	32	};
33		33
34	power_green {	34	power_green {
35	label = "smartgw:power:green";	35	label = "smartgw:power:green";
36	gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;	36	gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
37	default-state = "off";	37	default-state = "on";
38	};	38	};
39		39
40	power_red {	40	power_red {
41	label = "smartgw:power:red";	41	label = "smartgw:power:red";
42	gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;	42	gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
43	default-state = "off";	43	default-state = "off";
44	};	44	};
45		45
46	radio_blue {	46	radio_blue {
47	label = "smartgw:radio:blue";	47	label = "smartgw:radio:blue";
48	gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;	48	gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;
49	default-state = "off";	49	default-state = "off";
50	};	50	};
51		51
52	radio_green {	52	radio_green {
53	label = "smartgw:radio:green";	53	label = "smartgw:radio:green";
54	gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;	54	gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
55	default-state = "off";	55	default-state = "off";
56	};	56	};
57		57
58	radio_red {	58	radio_red {
59	label = "smartgw:radio:red";	59	label = "smartgw:radio:red";
60	gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;	60	gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
61	default-state = "off";	61	default-state = "off";
62	};	62	};
63		63
64	internet_blue {	64	internet_blue {
65	label = "smartgw:internet:blue";	65	label = "smartgw:internet:blue";
66	gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;	66	gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
67	default-state = "off";	67	default-state = "off";
68	};	68	};
69		69
70	internet_green {	70	internet_green {
71	label = "smartgw:internet:green";	71	label = "smartgw:internet:green";
72	gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;	72	gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;
73	default-state = "off";	73	default-state = "off";
74	};	74	};
75		75
76	internet_red {	76	internet_red {
77	label = "smartgw:internet:red";	77	label = "smartgw:internet:red";
78	gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;	78	gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
79	default-state = "off";	79	default-state = "off";
80	};	80	};
81	};	81	};
82		82
83	chosen {	83	chosen {
84	stdout-path = &uart0;	84	stdout-path = &uart0;
85	};	85	};
86	};	86	};
87		87
88	&uart0 {	88	&uart0 {
89	status = "okay";	89	status = "okay";
90	clock-frequency = <40000000>;	90	clock-frequency = <40000000>;
91	};	91	};
92		92
93	&spi0 {	93	&spi0 {
94	status = "okay";	94	status = "okay";
95	num-cs = <2>;	95	num-cs = <2>;
96		96
97	spi-flash@0 {	97	spi-flash@0 {
98	#address-cells = <1>;	98	#address-cells = <1>;
99	#size-cells = <1>;	99	#size-cells = <1>;
100	compatible = "spi-flash", "jedec,spi-nor";	100	compatible = "spi-flash", "jedec,spi-nor";
101	spi-max-frequency = <40000000>;	101	spi-max-frequency = <40000000>;
102	reg = <0>;	102	reg = <0>;
103	};	103	};
104		104
105	spi-nand@1 {	105	spi-nand@1 {
106	#address-cells = <1>;	106	#address-cells = <1>;
107	#size-cells = <1>;	107	#size-cells = <1>;
108	compatible = "spi-nand";	108	compatible = "spi-nand";
109	spi-max-frequency = <40000000>;	109	spi-max-frequency = <40000000>;
110	reg = <1>;	110	reg = <1>;
111	};	111	};
112	};	112	};
113		113

arch/mips/dts/jr2_pcb110.dts

Diff comments View file @ f83ef0d

File was created	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Copyright (c) 2018 Microsemi Corporation
	4	*/
	5
	6	/dts-v1/;
	7	#include "mscc,jr2.dtsi"
	8
	9	/ {
	10	model = "Jaguar2 Cu8-Sfp16 PCB110 Reference Board";
	11	compatible = "mscc,jr2-pcb110", "mscc,jr2";
	12
	13	aliases {
	14	spi0 = &spi0;
	15	serial0 = &uart0;
	16	};
	17
	18	chosen {
	19	stdout-path = "serial0:115200n8";
	20	};
	21
	22	gpio-leds {
	23	compatible = "gpio-leds";
	24
	25	status_green {
	26	label = "pcb110:green:status";
	27	gpios = <&gpio 12 0>;
	28	default-state = "on";
	29	};
	30
	31	status_red {
	32	label = "pcb110:red:status";
	33	gpios = <&gpio 13 0>;
	34	default-state = "off";
	35	};
	36	};
	37	};
	38
	39	&uart0 {
	40	status = "okay";
	41	};
	42
	43	&spi0 {
	44	status = "okay";
	45	spi-flash@0 {
	46	compatible = "spi-flash";
	47	spi-max-frequency = <18000000>; /* input clock */
	48	reg = <0>; /* CS0 */
	49	};
	50	};
	51
	52	&gpio {
	53	/* SPIO only use DO, CLK, no inputs */
	54	sgpio1_pins: sgpio1-pins {
	55	pins = "GPIO_4", "GPIO_5";
	56	function = "sg1";
	57	};
	58	};
	59
	60	&sgpio {
	61	status = "okay";
	62	sgpio-ports = <0x00ffffff>;
	63	};
	64
	65	&sgpio1 {
	66	status = "okay";
	67	sgpio-ports = <0x00ff0000>;
	68	};
	69
	70	&sgpio2 {
	71	status = "okay";
	72	sgpio-ports = <0x3f00ffff>;
	73	gpio-ranges = <&sgpio2 0 0 96>;
	74	};
	75

arch/mips/dts/jr2_pcb111.dts

Diff comments View file @ f83ef0d

File was created	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Copyright (c) 2018 Microsemi Corporation
	4	*/
	5
	6	/dts-v1/;
	7	#include "mscc,jr2.dtsi"
	8
	9	/ {
	10	model = "Jaguar2 Cu48 PCB111 Reference Board";
	11	compatible = "mscc,jr2-pcb111", "mscc,jr2";
	12
	13	aliases {
	14	spi0 = &spi0;
	15	serial0 = &uart0;
	16	};
	17
	18	chosen {
	19	stdout-path = "serial0:115200n8";
	20	};
	21
	22	gpio-leds {
	23	compatible = "gpio-leds";
	24
	25	status_green {
	26	label = "pcb111:green:status";
	27	gpios = <&gpio 12 0>;
	28	default-state = "on";
	29	};
	30
	31	status_red {
	32	label = "pcb111:red:status";
	33	gpios = <&gpio 13 0>;
	34	default-state = "off";
	35	};
	36	};
	37	};
	38
	39	&uart0 {
	40	status = "okay";
	41	};
	42
	43	&spi0 {
	44	status = "okay";
	45	spi-flash@0 {
	46	compatible = "spi-flash";
	47	spi-max-frequency = <18000000>; /* input clock */
	48	reg = <0>; /* CS0 */
	49	};
	50	};
	51
	52	&gpio {
	53	/* SPIO only use DO, CLK, no inputs */
	54	sgpio1_pins: sgpio1-pins {
	55	pins = "GPIO_4", "GPIO_5";
	56	function = "sg1";
	57	};
	58	};
	59
	60	&sgpio {
	61	status = "okay";
	62	sgpio-ports = <0xffffffff>;
	63	};
	64
	65	&sgpio1 {
	66	status = "okay";
	67	sgpio-ports = <0x001effff>;
	68	};
	69
	70	&sgpio2 {
	71	status = "okay";
	72	sgpio-ports = <0xff000000>;
	73	gpio-ranges = <&sgpio2 0 0 96>;
	74	};
	75

arch/mips/dts/luton_pcb090.dts

Diff comments View file @ f83ef0d

File was created	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Copyright (c) 2018 Microsemi Corporation
	4	*/
	5
	6	/dts-v1/;
	7	#include "mscc,luton.dtsi"
	8
	9	/ {
	10	model = "Luton26 PCB090 Reference Board";
	11	compatible = "mscc,luton-pcb090", "mscc,luton";
	12
	13	aliases {
	14	serial0 = &uart0;
	15	spi0 = &spi0;
	16	};
	17
	18	chosen {
	19	stdout-path = "serial0:115200n8";
	20	};
	21
	22	gpio-leds {
	23	compatible = "gpio-leds";
	24
	25	status_green {
	26	label = "pcb090:green:status";
	27	gpios = <&sgpio 64 GPIO_ACTIVE_HIGH>; /* p0.2 */
	28	default-state = "on";
	29	};
	30
	31	status_red {
	32	label = "pcb090:red:status";
	33	gpios = <&sgpio 65 GPIO_ACTIVE_HIGH>; /* p1.2 */
	34	default-state = "off";
	35	};
	36	};
	37	};
	38
	39	&sgpio {
	40	status = "okay";
	41	gpio-ranges = <&sgpio 0 0 96>;
	42	};
	43
	44	&uart0 {
	45	status = "okay";
	46	};
	47
	48	&spi0 {
	49	status = "okay";
	50	spi-flash@0 {
	51	compatible = "spi-flash";
	52	spi-max-frequency = <18000000>; /* input clock */
	53	reg = <0>; /* CS0 */
	54	spi-cs-high;
	55	};
	56	};
	57
	58

arch/mips/dts/luton_pcb091.dts

Diff comments View file @ f83ef0d

 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2018 Microsemi Corporation
  */
 /dts-v1/;
 #include "mscc,luton.dtsi"
 / {
 	model = "Luton10 PCB091 Reference Board";
 	compatible = "mscc,luton-pcb091", "mscc,luton";
 	aliases {
 		serial0 = &uart0;
 		spi0 = &spi0;
 	};
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
+	gpio-leds {
+		compatible = "gpio-leds";
+		top_dimmer {
+			label = "pcb091:top:dimmer";
+			gpios = <&gpio 29 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+		};
+		status_green {
+			label = "pcb091:green:status";
+			gpios = <&sgpio 26 GPIO_ACTIVE_HIGH>; /* p26.0 */
+			default-state = "on";
+		};
+		status_red {
+			label = "pcb091:red:status";
+			gpios = <&sgpio 58 GPIO_ACTIVE_HIGH>; /* p26.1 */
+			default-state = "off";
+		};
+	};
+};
+&sgpio {
+	status = "okay";
+	mscc,sgpio-ports = <0xFFF000FF>;
 };
 &uart0 {
 	status = "okay";
 };
 &spi0 {
 	status = "okay";
 	spi-flash@0 {
 		compatible = "spi-flash";
 		spi-max-frequency = <18000000>; /* input clock */
 		reg = <0>; /* CS0 */
 		spi-cs-high;
 	};
 };

arch/mips/dts/mscc,jr2.dtsi

Diff comments View file @ f83ef0d

File was created	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Copyright (c) 2018 Microsemi Corporation
	4	*/
	5
	6	/ {
	7	#address-cells = <1>;
	8	#size-cells = <1>;
	9	compatible = "mscc,jr2";
	10
	11	cpus {
	12	#address-cells = <1>;
	13	#size-cells = <0>;
	14
	15	cpu@0 {
	16	compatible = "mips,mips24KEc";
	17	device_type = "cpu";
	18	clocks = <&cpu_clk>;
	19	reg = <0>;
	20	};
	21	};
	22
	23	aliases {
	24	serial0 = &uart0;
	25	};
	26
	27	cpuintc: interrupt-controller@0 {
	28	#address-cells = <0>;
	29	#interrupt-cells = <1>;
	30	interrupt-controller;
	31	compatible = "mti,cpu-interrupt-controller";
	32	};
	33
	34	cpu_clk: cpu-clock {
	35	compatible = "fixed-clock";
	36	#clock-cells = <0>;
	37	clock-frequency = <500000000>;
	38	};
	39
	40	ahb_clk: ahb-clk {
	41	compatible = "fixed-clock";
	42	#clock-cells = <0>;
	43	clock-frequency = <250000000>;
	44	};
	45
	46	ahb {
	47	compatible = "simple-bus";
	48	#address-cells = <1>;
	49	#size-cells = <1>;
	50	ranges = <0 0x70000000 0x2000000>;
	51
	52	interrupt-parent = <&intc>;
	53
	54	cpu_ctrl: syscon@0 {
	55	compatible = "mscc,jr2-cpu-syscon", "syscon";
	56	reg = <0x0 0x2c>;
	57	};
	58
	59	intc: interrupt-controller@70 {
	60	compatible = "mscc,jr2-icpu-intr";
	61	reg = <0x70 0x94>;
	62	#interrupt-cells = <1>;
	63	interrupt-controller;
	64	interrupt-parent = <&cpuintc>;
	65	interrupts = <2>;
	66	};
	67
	68	uart0: serial@100000 {
	69	pinctrl-0 = <&uart_pins>;
	70	pinctrl-names = "default";
	71	compatible = "ns16550a";
	72	reg = <0x100000 0x20>;
	73	interrupts = <6>;
	74	clocks = <&ahb_clk>;
	75	reg-io-width = <4>;
	76	reg-shift = <2>;
	77
	78	status = "disabled";
	79	};
	80
	81	uart2: serial@100800 {
	82	pinctrl-0 = <&uart2_pins>;
	83	pinctrl-names = "default";
	84	compatible = "ns16550a";
	85	reg = <0x100800 0x20>;
	86	interrupts = <7>;
	87	clocks = <&ahb_clk>;
	88	reg-io-width = <4>;
	89	reg-shift = <2>;
	90
	91	status = "disabled";
	92	};
	93
	94	spi0: spi-master@101000 {
	95	#address-cells = <1>;
	96	#size-cells = <0>;
	97	compatible = "snps,dw-apb-ssi";
	98	reg = <0x101000 0x40>;
	99	num-chipselect = <4>;
	100	bus-num = <0>;
	101	reg-io-width = <4>;
	102	reg-shift = <2>;
	103	spi-max-frequency = <18000000>; /* input clock */
	104	clocks = <&ahb_clk>;
	105
	106	status = "disabled";
	107	};
	108
	109	reset@1010008 {
	110	compatible = "mscc,jr2-chip-reset";
	111	reg = <0x1010008 0x4>;
	112	};
	113
	114	gpio: pinctrl@1070034 {
	115	compatible = "mscc,jaguar2-pinctrl";
	116	reg = <0x1010038 0x90>;
	117	gpio-controller;
	118	#gpio-cells = <2>;
	119	gpio-ranges = <&gpio 0 0 64>;
	120
	121	sgpio_pins: sgpio-pins {
	122	pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
	123	function = "sg0";
	124	};
	125
	126	sgpio1_pins: sgpio1-pins {
	127	pins = "GPIO_4", "GPIO_5", "GPIO_12", "GPIO_13";
	128	function = "sg1";
	129	};
	130
	131	sgpio2_pins: sgpio2-pins {
	132	pins = "GPIO_30", "GPIO_31",
	133	"GPIO_32", "GPIO_33";
	134	function = "sg2";
	135	};
	136
	137	uart_pins: uart-pins {
	138	pins = "GPIO_10", "GPIO_11";
	139	function = "uart";
	140	};
	141
	142	uart2_pins: uart2-pins {
	143	pins = "GPIO_24", "GPIO_25";
	144	function = "uart2";
	145	};
	146	};
	147
	148	sgpio: gpio@1010150 {
	149	compatible = "mscc,ocelot-sgpio";
	150	status = "disabled";
	151	pinctrl-0 = <&sgpio_pins>;
	152	pinctrl-names = "default";
	153	reg = <0x1010150 0x100>;
	154	gpio-controller;
	155	#gpio-cells = <2>;
	156	gpio-ranges = <&sgpio 0 0 64>;
	157	gpio-bank-name = "sgpio0_";
	158	sgpio-clock = <0x14>;
	159	};
	160
	161	sgpio1: gpio@101025c {
	162	compatible = "mscc,ocelot-sgpio";
	163	status = "disabled";
	164	pinctrl-0 = <&sgpio1_pins>;
	165	pinctrl-names = "default";
	166	reg = <0x101025c 0x100>;
	167	gpio-controller;
	168	#gpio-cells = <2>;
	169	gpio-ranges = <&sgpio1 0 0 64>;
	170	gpio-bank-name = "sgpio1_";
	171	sgpio-clock = <0x14>;
	172	};
	173
	174	sgpio2: gpio@1010368 {
	175	compatible = "mscc,ocelot-sgpio";
	176	status = "disabled";
	177	pinctrl-0 = <&sgpio2_pins>;
	178	pinctrl-names = "default";
	179	reg = <0x1010368 0x100>;
	180	gpio-controller;
	181	#gpio-cells = <2>;
	182	gpio-ranges = <&sgpio2 0 0 64>;
	183	gpio-bank-name = "sgpio2_";
	184	sgpio-clock = <0x14>;
	185	};
	186	};
	187	};
	188

arch/mips/dts/mscc,luton.dtsi

Diff comments View file @ f83ef0d

1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2	/*	2	/*
3	* Copyright (c) 2018 Microsemi Corporation	3	* Copyright (c) 2018 Microsemi Corporation
4	*/	4	*/
5		5
6	#include <dt-bindings/gpio/gpio.h>	6	#include <dt-bindings/gpio/gpio.h>
7		7
8	/ {	8	/ {
9	#address-cells = <1>;	9	#address-cells = <1>;
10	#size-cells = <1>;	10	#size-cells = <1>;
11	compatible = "mscc,luton";	11	compatible = "mscc,luton";
12		12
13	cpus {	13	cpus {
14	#address-cells = <1>;	14	#address-cells = <1>;
15	#size-cells = <0>;	15	#size-cells = <0>;
16		16
17	cpu@0 {	17	cpu@0 {
18	compatible = "mips,mips24KEc";	18	compatible = "mips,mips24KEc";
19	device_type = "cpu";	19	device_type = "cpu";
20	reg = <0>;	20	reg = <0>;
21	};	21	};
22	};	22	};
23		23
24	aliases {	24	aliases {
25	serial0 = &uart0;	25	serial0 = &uart0;
26	};	26	};
27		27
		28	sys_clk: sys-clk {
		29	compatible = "fixed-clock";
		30	#clock-cells = <0>;
		31	clock-frequency = <250000000>;
		32	};
28	ahb_clk: ahb-clk {	33	ahb_clk: ahb-clk {
29	compatible = "fixed-clock";	34	compatible = "fixed-clock";
30	#clock-cells = <0>;	35	#clock-cells = <0>;
31	clock-frequency = <208333333>;	36	clock-frequency = <208333333>;
32	};	37	};
33		38
34	ahb {	39	ahb {
35	compatible = "simple-bus";	40	compatible = "simple-bus";
36	#address-cells = <1>;	41	#address-cells = <1>;
37	#size-cells = <1>;	42	#size-cells = <1>;
38	ranges = <0 0x60000000 0x10200000>;	43	ranges = <0 0x60000000 0x10200000>;
39		44
40	uart0: serial@10100000 {	45	uart0: serial@10100000 {
41	pinctrl-0 = <&uart_pins>;	46	pinctrl-0 = <&uart_pins>;
42	pinctrl-names = "default";	47	pinctrl-names = "default";
43		48
44	compatible = "ns16550a";	49	compatible = "ns16550a";
45	reg = <0x10100000 0x20>;	50	reg = <0x10100000 0x20>;
46	clocks = <&ahb_clk>;	51	clocks = <&ahb_clk>;
47	reg-io-width = <4>;	52	reg-io-width = <4>;
48	reg-shift = <2>;	53	reg-shift = <2>;
49		54
50	status = "disabled";	55	status = "disabled";
51	};	56	};
52		57
53	gpio: pinctrl@70068 {	58	gpio: pinctrl@70068 {
54	compatible = "mscc,luton-pinctrl";	59	compatible = "mscc,luton-pinctrl";
55	reg = <0x70068 0x68>;	60	reg = <0x70068 0x68>;
56	gpio-controller;	61	gpio-controller;
57	#gpio-cells = <2>;	62	#gpio-cells = <2>;
58	gpio-ranges = <&gpio 0 0 32>;	63	gpio-ranges = <&gpio 0 0 32>;
59		64
		65	sgpio_pins: sgpio-pins {
		66	pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
		67	function = "sio";
		68	};
60	uart_pins: uart-pins {	69	uart_pins: uart-pins {
61	pins = "GPIO_30", "GPIO_31";	70	pins = "GPIO_30", "GPIO_31";
62	function = "uart";	71	function = "uart";
63	};	72	};
64
65	};	73	};
66		74
67	gpio_spi_bitbang: gpio@10000064 {	75	sgpio: gpio@70130 {
68	compatible = "mscc,spi-bitbang-gpio";	76	compatible = "mscc,luton-sgpio";
69	reg = <0x10000064 0x4>;	77	status = "disabled";
		78	clocks = <&sys_clk>;
		79	pinctrl-0 = <&sgpio_pins>;
		80	pinctrl-names = "default";
		81	reg = <0x0070130 0x100>;
70	gpio-controller;	82	gpio-controller;
71	#gpio-cells = <2>;	83	#gpio-cells = <2>;
72		84	gpio-ranges = <&sgpio 0 0 64>;
73	};	85	};
74		86
75	spi0: spi-bitbang {	87	spi0: spi-bitbang {
76	compatible = "spi-gpio";	88	compatible = "mscc,luton-bb-spi";
77	status = "okay";	89	status = "okay";
78	gpio-sck = <&gpio_spi_bitbang 6 0>;	90	reg = <0x10000064 0x4>;
79	gpio-miso = <&gpio_spi_bitbang 0 0>;
80	gpio-mosi = <&gpio_spi_bitbang 5 0>;
81	cs-gpios = <&gpio_spi_bitbang 1 0>;
82	num-chipselects = <1>;	91	num-chipselects = <1>;
83	#address-cells = <1>;	92	#address-cells = <1>;
84	#size-cells = <0>;	93	#size-cells = <0>;

arch/mips/dts/mscc,ocelot.dtsi

Diff comments View file @ f83ef0d

 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2018 Microsemi Corporation
  */
 / {
 	#address-cells = <1>;
 	#size-cells = <1>;
 	compatible = "mscc,ocelot";
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
 		cpu@0 {
 			compatible = "mips,mips24KEc";
 			device_type = "cpu";
 			clocks = <&cpu_clk>;
 			reg = <0>;
 		};
 	};
 	aliases {
 		serial0 = &uart0;
 	};
 	cpuintc: interrupt-controller@0 {
 		#address-cells = <0>;
 		#interrupt-cells = <1>;
 		interrupt-controller;
 		compatible = "mti,cpu-interrupt-controller";
 	};
 	cpu_clk: cpu-clock {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <500000000>;
 	};
+	sys_clk: sys-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <250000000>;
+	};
 	ahb_clk: ahb-clk {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <250000000>;
 	};
 	ahb {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges = <0 0x70000000 0x2000000>;
 		interrupt-parent = <&intc>;
 		cpu_ctrl: syscon@0 {
 			compatible = "mscc,ocelot-cpu-syscon", "syscon";
 			reg = <0x0 0x2c>;
 		};
 		intc: interrupt-controller@70 {
 			compatible = "mscc,ocelot-icpu-intr";
 			reg = <0x70 0x70>;
 			#interrupt-cells = <1>;
 			interrupt-controller;
 			interrupt-parent = <&cpuintc>;
 			interrupts = <2>;
 		};
 		uart0: serial@100000 {
 			pinctrl-0 = <&uart_pins>;
 			pinctrl-names = "default";
 			compatible = "ns16550a";
 			reg = <0x100000 0x20>;
 			interrupts = <6>;
 			clocks = <&ahb_clk>;
 			reg-io-width = <4>;
 			reg-shift = <2>;
 			status = "disabled";
 		};
 		uart2: serial@100800 {
 			pinctrl-0 = <&uart2_pins>;
 			pinctrl-names = "default";
 			compatible = "ns16550a";
 			reg = <0x100800 0x20>;
 			interrupts = <7>;
 			clocks = <&ahb_clk>;
 			reg-io-width = <4>;
 			reg-shift = <2>;
 			status = "disabled";
 		};
 		spi0: spi-master@101000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "snps,dw-apb-ssi";
 			reg = <0x101000 0x40>;
 			num-chipselect = <4>;
 			bus-num = <0>;
 			reg-io-width = <4>;
 			reg-shift = <2>;
 			spi-max-frequency = <18000000>; /* input clock */
 			clocks = <&ahb_clk>;
 			status = "disabled";
 		};
 		reset@1070008 {
 			compatible = "mscc,ocelot-chip-reset";
 			reg = <0x1070008 0x4>;
 		};
 		gpio: pinctrl@1070034 {
 			compatible = "mscc,ocelot-pinctrl";
 			reg = <0x1070034 0x68>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			gpio-ranges = <&gpio 0 0 22>;
+			sgpio_pins: sgpio-pins {
+				pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
+				function = "sg0";
+			};
 			uart_pins: uart-pins {
 				pins = "GPIO_6", "GPIO_7";
 				function = "uart";
 			};
 			uart2_pins: uart2-pins {
 				pins = "GPIO_12", "GPIO_13";
 				function = "uart2";
 			};
 			spi_cs1_pin: spi-cs1-pin {
 				pins = "GPIO_8";
 				function = "si";
 			};
 			spi_cs2_pin: spi-cs2-pin {
 				pins = "GPIO_9";
 				function = "si";
 			};
 			spi_cs3_pin: spi-cs3-pin {
 				pins = "GPIO_16";
 				function = "si";
 			};
 			spi_cs4_pin: spi-cs4-pin {
 				pins = "GPIO_17";
 				function = "si";
 			};
+		};
+		sgpio: gpio@10700f8 {
+			compatible = "mscc,ocelot-sgpio";
+			status = "disabled";
+			clocks = <&sys_clk>;
+			pinctrl-0 = <&sgpio_pins>;
+			pinctrl-names = "default";
+			reg = <0x10700f8 0x100>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&sgpio 0 0 64>;
 		};
 	};
 };

arch/mips/dts/ocelot_pcb120.dts

Diff comments View file @ f83ef0d

1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2	/*	2	/*
3	* Copyright (c) 2018 Microsemi Corporation	3	* Copyright (c) 2018 Microsemi Corporation
4	*/	4	*/
5		5
6	/dts-v1/;	6	/dts-v1/;
7	#include "mscc,ocelot_pcb.dtsi"	7	#include "mscc,ocelot_pcb.dtsi"
8		8
9	/ {	9	/ {
10	model = "Ocelot PCB120 Reference Board";	10	model = "Ocelot PCB120 Reference Board";
11	compatible = "mscc,ocelot-pcb120", "mscc,ocelot";	11	compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
		12
		13	chosen {
		14	stdout-path = "serial0:115200n8";
		15	};
		16
		17	gpio-leds {
		18	compatible = "gpio-leds";
		19
		20	poe_green {
		21	label = "pcb120:green:poe";
		22	gpios = <&sgpio 44 1>; /* p12.1 */
		23	default-state = "off";
		24	};
		25
		26	poe_red {
		27	label = "pcb120:red:poe";
		28	gpios = <&sgpio 12 1>; /* p12.0 */
		29	default-state = "off";
		30	};
		31
		32	alarm_green {
		33	label = "pcb120:green:alarm";
		34	gpios = <&sgpio 45 1>; /* p13.1 */
		35	default-state = "off";
		36	};
		37
		38	alarm_red {
		39	label = "pcb120:red:alarm";
		40	gpios = <&sgpio 13 1>; /* p13.0 */
		41	default-state = "off";
		42	};
		43
		44	dc_a_green {
		45	label = "pcb120:green:dc_a";
		46	gpios = <&sgpio 46 1>; /* p14.1 */
		47	default-state = "off";
		48	};
		49
		50	dc_a_red {
		51	label = "pcb120:red:dc_a";
		52	gpios = <&sgpio 14 1>; /* p14.0 */
		53	default-state = "off";
		54	};
		55
		56	dc_b_green {
		57	label = "pcb120:green:dc_b";
		58	gpios = <&sgpio 47 1>; /* p15.1 */
		59	default-state = "off";
		60	};
		61
		62	dc_b_red {
		63	label = "pcb120:red:dc_b";
		64	gpios = <&sgpio 15 1>; /* p15.0 */
		65	default-state = "off";
		66	};
		67
		68	status_green {
		69	label = "pcb120:green:status";
		70	gpios = <&sgpio 48 1>; /* p16.1 */
		71	default-state = "on";
		72	};
		73
		74	status_red {
		75	label = "pcb120:red:alarm";
		76	gpios = <&sgpio 16 1>; /* p16.0 */
		77	default-state = "off";
		78	};
		79
		80	};
		81
		82	};
		83
		84	&sgpio {
		85	status = "okay";
		86	mscc,sgpio-ports = <0x000FFFFF>;
12	};	87	};
13		88
		89

arch/mips/dts/ocelot_pcb123.dts

Diff comments View file @ f83ef0d

1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2	/*	2	/*
3	* Copyright (c) 2018 Microsemi Corporation	3	* Copyright (c) 2018 Microsemi Corporation
4	*/	4	*/
5		5
6	/dts-v1/;	6	/dts-v1/;
7	#include "mscc,ocelot_pcb.dtsi"	7	#include "mscc,ocelot_pcb.dtsi"
8		8
9	/ {	9	/ {
10	model = "Ocelot PCB123 Reference Board";	10	model = "Ocelot PCB123 Reference Board";
11	compatible = "mscc,ocelot-pcb123", "mscc,ocelot";	11	compatible = "mscc,ocelot-pcb123", "mscc,ocelot";
		12
		13	chosen {
		14	stdout-path = "serial0:115200n8";
		15	};
		16
		17	gpio-leds {
		18	compatible = "gpio-leds";
		19
		20	status_green {
		21	label = "pcb123:green:status";
		22	gpios = <&sgpio 43 1>; /* p11.1 */
		23	default-state = "on";
		24	};
		25
		26	status_red {
		27	label = "pcb123:red:status";
		28	gpios = <&sgpio 11 1>; /* p11.0 */
		29	default-state = "off";
		30	};
		31	};
		32	};
		33
		34	&sgpio {
		35	status = "okay";
		36	mscc,sgpio-ports = <0x00FFFFFF>;
12	};	37	};
13		38

arch/mips/dts/serval2_pcb112.dts

Diff comments View file @ f83ef0d

File was created	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Copyright (c) 2018 Microsemi Corporation
	4	*/
	5
	6	/dts-v1/;
	7	#include "mscc,jr2.dtsi"
	8
	9	/ {
	10	model = "Serval2 NID PCB112 Reference Board";
	11	compatible = "mscc,serval2-pcb110", "mscc,jr2";
	12
	13	aliases {
	14	spi0 = &spi0;
	15	serial0 = &uart0;
	16	};
	17
	18	chosen {
	19	stdout-path = "serial0:115200n8";
	20	};
	21
	22	gpio-leds {
	23	compatible = "gpio-leds";
	24
	25	status_green {
	26	label = "pcb110:green:status";
	27	gpios = <&gpio 12 0>;
	28	default-state = "on";
	29	};
	30
	31	status_red {
	32	label = "pcb110:red:status";
	33	gpios = <&gpio 13 0>;
	34	default-state = "off";
	35	};
	36	};
	37	};
	38
	39	&uart0 {
	40	status = "okay";
	41	};
	42
	43	&spi0 {
	44	status = "okay";
	45	spi-flash@0 {
	46	compatible = "spi-flash";
	47	spi-max-frequency = <18000000>; /* input clock */
	48	reg = <0>; /* CS0 */
	49	};
	50	};
	51
	52	&sgpio {
	53	status = "okay";
	54	sgpio-ports = <0x0000ffff>;
	55	};
	56
	57	&sgpio2 {
	58	status = "okay";
	59	sgpio-ports = <0x3fe0ffff>;
	60	};
	61

arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds

View file @ f83ef0d

1	/* SPDX-License-Identifier: GPL-2.0+ */		File was deleted
2
3	MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
4	LENGTH = CONFIG_SPL_MAX_SIZE }
5	MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
6	LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
7
8	OUTPUT_ARCH(mips)
9	ENTRY(_start)
10	SECTIONS
11	{
12	.text :
13	{
14	__image_copy_start = .;
15	arch/mips/mach-jz47xx/start.o (.text*)
16	(.text)
17	} >.sram
18
19	. = ALIGN(4);
20	.rodata : { (SORT_BY_ALIGNMENT(.rodata)) } >.sram
21
22	. = ALIGN(4);
23	.data : { (SORT_BY_ALIGNMENT(.data)) } >.sram
24
25	. = ALIGN(4);
26	__image_copy_end = .;
27
28	.bss : {
29	. = ALIGN(4);
30	__bss_start = .;
31	(.sbss.)
32	(.bss.)
33	*(COMMON)
34	. = ALIGN(4);
35	__bss_end = .;
36	} >.sdram
37
38	/DISCARD/ : {
39	*(.dynbss)
40	*(.dynstr)
41	*(.dynamic)
42	*(.interp)
43	*(.hash)
44	(.gnu.)
45	*(.plt)
46	*(.got.plt)
47	*(.rel.plt)
48	*(.rel.dyn)
49	}
50	}
51		1	/* SPDX-License-Identifier: GPL-2.0+ */

arch/mips/mach-mscc/Kconfig

Diff comments View file @ f83ef0d

1	# SPDX-License-Identifier: (GPL-2.0+ OR MIT)	1	# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2		2
3	menu "MSCC VCore-III platforms"	3	menu "MSCC VCore-III platforms"
4	depends on ARCH_MSCC	4	depends on ARCH_MSCC
5		5
6	config SOC_VCOREIII	6	config SOC_VCOREIII
7	select MIPS_TUNE_24KC	7	select MIPS_TUNE_24KC
8	select ROM_EXCEPTION_VECTORS	8	select ROM_EXCEPTION_VECTORS
9	select SUPPORTS_BIG_ENDIAN	9	select SUPPORTS_BIG_ENDIAN
10	select SUPPORTS_CPU_MIPS32_R1	10	select SUPPORTS_CPU_MIPS32_R1
11	select SUPPORTS_CPU_MIPS32_R2	11	select SUPPORTS_CPU_MIPS32_R2
12	select SUPPORTS_LITTLE_ENDIAN	12	select SUPPORTS_LITTLE_ENDIAN
13	bool	13	bool
14		14
15	config SYS_SOC	15	config SYS_SOC
16	default "mscc"	16	default "mscc"
17		17
		18	choice
		19
		20	prompt "SOC Family Variant"
		21
18	config SOC_OCELOT	22	config SOC_OCELOT
19	bool	23	bool "Ocelot SOC Family"
20	select SOC_VCOREIII	24	select SOC_VCOREIII
		25	select DESIGNWARE_SPI
21	help	26	help
22	This supports MSCC Ocelot family of SOCs.	27	This supports MSCC Ocelot family of SOCs.
23		28
24	config SOC_LUTON	29	config SOC_LUTON
25	bool	30	bool "Luton SOC Family"
26	select SOC_VCOREIII	31	select SOC_VCOREIII
		32	select MSCC_BITBANG_SPI_GPIO
27	help	33	help
28	This supports MSCC Luton family of SOCs.	34	This supports MSCC Luton family of SOCs.
29		35
30	config SYS_CONFIG_NAME	36	config SOC_JR2
31	default "vcoreiii"	37	bool "Jaguar2 SOC Family"
32		38	select SOC_VCOREIII
33	choice	39	select DESIGNWARE_SPI
34	prompt "Board select"
35
36	config TARGET_OCELOT_PCB120
37	bool "MSCC PCB120 Reference Board (aka VSC5635EV)"
38	select SOC_OCELOT
39	help	40	help
40	When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to	41	This supports MSCC Jaguar2 family of SOCs.
41	ocelot_pcb120
42		42
43	config TARGET_OCELOT_PCB123
44	bool "MSCC PCB123 Reference Board (aka VSC7514EV))"
45	select SOC_OCELOT
46	help
47	When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
48	ocelot_pcb123
49
50	config TARGET_LUTON_PCB091
51	bool "MSCC PCB091 Reference Board"
52	select SOC_LUTON
53	select MSCC_BITBANG_SPI_GPIO
54	help
55	When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
56	luton_pcb091
57	endchoice	43	endchoice
58		44
		45	config SYS_CONFIG_NAME
		46	default "vcoreiii"
		47
59	choice	48	choice
60	prompt "DDR type"	49	prompt "DDR type"
61		50
62	config DDRTYPE_H5TQ4G63MFR	51	config DDRTYPE_H5TQ4G63MFR
63	bool "Hynix H5TQ4G63MFR-PBC (4Gbit, DDR3-800, 256Mbitx16)"	52	bool "Hynix H5TQ4G63MFR-PBC (4Gbit, DDR3-800, 256Mbitx16)"
64		53
65	config DDRTYPE_MT41K256M16	54	config DDRTYPE_MT41K256M16
66	bool "Micron MT41K256M16 (4Gbit, DDR3L-800, 256Mbitx16)"	55	bool "Micron MT41K256M16 (4Gbit, DDR3L-800, 256Mbitx16)"
67		56
68	config DDRTYPE_H5TQ1G63BFA	57	config DDRTYPE_H5TQ1G63BFA
69	bool "Hynix H5TQ1G63BFA (1Gbit DDR3, x16)"	58	bool "Hynix H5TQ1G63BFA (1Gbit DDR3, x16)"
70		59
71	config DDRTYPE_MT41J128M16HA	60	config DDRTYPE_MT41J128M16HA
72	bool "Micron MT41J128M16HA-15E:D (2Gbit DDR3, x16)"	61	bool "Micron MT41J128M16HA-15E:D (2Gbit DDR3, x16)"
73		62
74	config DDRTYPE_MT41K128M16JT	63	config DDRTYPE_MT41K128M16JT
75	bool "Micron MT41K128M16JT-125 (2Gbit DDR3L, 128Mbitx16)"	64	bool "Micron MT41K128M16JT-125 (2Gbit DDR3L, 128Mbitx16)"
76		65
77	config DDRTYPE_MT47H128M8HQ	66	config DDRTYPE_MT47H128M8HQ
78	bool "Micron MT47H128M8-3 (1Gbit, DDR-533@CL4 @ 4.80ns 16Mbisx8x8)"	67	bool "Micron MT47H128M8-3 (1Gbit, DDR-533@CL4 @ 4.80ns 16Mbisx8x8)"

arch/mips/mach-mscc/Makefile

Diff comments View file @ f83ef0d

1	# SPDX-License-Identifier: (GPL-2.0+ OR MIT)	1	# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2		2
3	CFLAGS_cpu.o += -finline-limit=64000	3	CFLAGS_cpu.o += -finline-limit=64000
4		4
5	obj-y += cpu.o dram.o reset.o lowlevel_init.o	5	obj-y += cpu.o dram.o reset.o phy.o lowlevel_init.o
6	obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o	6	obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o gpio.o
		7	obj-$(CONFIG_SOC_OCELOT) += gpio.o
7		8

arch/mips/mach-mscc/cpu.c

Diff comments View file @ f83ef0d

 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2018 Microsemi Corporation
  */
 #include <common.h>
 #include <asm/io.h>
 #include <asm/types.h>
 #include <mach/tlb.h>
 #include <mach/ddr.h>
 DECLARE_GLOBAL_DATA_PTR;
 #if CONFIG_SYS_SDRAM_SIZE <= SZ_64M
 #define MSCC_RAM_TLB_SIZE   SZ_64M
 #define MSCC_ATTRIB2   MMU_REGIO_INVAL
 #elif CONFIG_SYS_SDRAM_SIZE <= SZ_128M
 #define MSCC_RAM_TLB_SIZE   SZ_64M
 #define MSCC_ATTRIB2   MMU_REGIO_RW
 #elif CONFIG_SYS_SDRAM_SIZE <= SZ_256M
 #define MSCC_RAM_TLB_SIZE   SZ_256M
 #define MSCC_ATTRIB2   MMU_REGIO_INVAL
 #elif CONFIG_SYS_SDRAM_SIZE <= SZ_512M
 #define MSCC_RAM_TLB_SIZE   SZ_256M
 #define MSCC_ATTRIB2   MMU_REGIO_RW
 #else
 #define MSCC_RAM_TLB_SIZE   SZ_512M
 #define MSCC_ATTRIB2   MMU_REGIO_RW
 #endif
 /* NOTE: lowlevel_init() function does not have access to the
  * stack. Thus, all called functions must be inlined, and (any) local
  * variables must be kept in registers.
  */
 void vcoreiii_tlb_init(void)
 {
 	register int tlbix = 0;
 	/*
 	 * Unlike most of the MIPS based SoCs, the IO register address
 	 * are not in KSEG0. The mainline linux kernel built in legacy
 	 * mode needs to access some of the registers very early in
 	 * the boot and make the assumption that the bootloader has
 	 * already configured them, so we have to match this
 	 * expectation.
 	 */
 	create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW,
 		   MMU_REGIO_RW);
 #ifdef CONFIG_SOC_LUTON
 	create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW,
 		   MMU_REGIO_RW);
 #endif
 #if  CONFIG_SYS_TEXT_BASE == MSCC_FLASH_TO
 	/*
 	 * If U-Boot is located in NOR then we want to be able to use
 	 * the data cache in order to boot in a decent duration
 	 */
 	create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C,
 		   MMU_REGIO_RO_C);
 	create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C,
 		   MMU_REGIO_RO_C);
 	/*
 	 * Using cache for RAM also helps to improve boot time. Thanks
 	 * to this the time to relocate U-Boot in RAM went from 2.092
 	 * secs to 0.104 secs.
 	 */
 	create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW,
 		   MSCC_ATTRIB2);
 	/* Enable caches by clearing the bit ERL, which is set on reset */
 	write_c0_status(read_c0_status() & ~BIT(2));
 #endif /* CONFIG_SYS_TEXT_BASE */
 }
 int mach_cpu_init(void)
 {
 	/* Speed up NOR flash access */
 #ifdef CONFIG_SOC_LUTON
 	writel(ICPU_PI_MST_CFG_TRISTATE_CTRL +
 	       ICPU_PI_MST_CFG_CLK_DIV(4), BASE_CFG + ICPU_PI_MST_CFG);
 	writel(ICPU_SPI_MST_CFG_FAST_READ_ENA +
 	       ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
 	       ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
 #else
+#ifdef CONFIG_SOC_OCELOT
 	writel(ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
 	       ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
+#endif
+#ifdef CONFIG_SOC_JR2
+	writel(ICPU_SPI_MST_CFG_FAST_READ_ENA +
+	       ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
+	       ICPU_SPI_MST_CFG_CLK_DIV(14), BASE_CFG + ICPU_SPI_MST_CFG);
+#endif
 	/*
 	 * Legacy and mainline linux kernel expect that the
 	 * interruption map was set as it was done by redboot.
 	 */
 	writel(~0, BASE_CFG + ICPU_DST_INTR_MAP(0));
 	writel(0, BASE_CFG + ICPU_DST_INTR_MAP(1));
 	writel(0, BASE_CFG + ICPU_DST_INTR_MAP(2));
 	writel(0, BASE_CFG + ICPU_DST_INTR_MAP(3));
 #endif
 	return 0;
 }

arch/mips/mach-mscc/dram.c

Diff comments View file @ f83ef0d

1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2	/*	2	/*
3	* Copyright (c) 2018 Microsemi Corporation	3	* Copyright (c) 2018 Microsemi Corporation
4	*/	4	*/
5		5
6	#include <common.h>	6	#include <common.h>
7		7
8	#include <asm/io.h>	8	#include <asm/io.h>
9	#include <asm/types.h>	9	#include <asm/types.h>
10		10
11	#include <mach/tlb.h>	11	#include <mach/tlb.h>
12	#include <mach/ddr.h>	12	#include <mach/ddr.h>
13		13
14	DECLARE_GLOBAL_DATA_PTR;	14	DECLARE_GLOBAL_DATA_PTR;
15		15
16	static inline int vcoreiii_train_bytelane(void)	16	static inline int vcoreiii_train_bytelane(void)
17	{	17	{
18	int ret;	18	int ret;
19		19
20	ret = hal_vcoreiii_train_bytelane(0);	20	ret = hal_vcoreiii_train_bytelane(0);
21		21
22	#ifdef CONFIG_SOC_OCELOT	22	#if defined(CONFIG_SOC_OCELOT) \|\| defined(CONFIG_SOC_JR2)
23	if (ret)	23	if (ret)
24	return ret;	24	return ret;
25	ret = hal_vcoreiii_train_bytelane(1);	25	ret = hal_vcoreiii_train_bytelane(1);
26	#endif	26	#endif
27		27
28	return ret;	28	return ret;
29	}	29	}
30		30
31	int vcoreiii_ddr_init(void)	31	int vcoreiii_ddr_init(void)
32	{	32	{
33	int res;	33	int res;
34		34
35	if (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT)	35	if (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT)
36	& ICPU_MEMCTRL_STAT_INIT_DONE)) {	36	& ICPU_MEMCTRL_STAT_INIT_DONE)) {
37	hal_vcoreiii_init_memctl();	37	hal_vcoreiii_init_memctl();
38	hal_vcoreiii_wait_memctl();	38	hal_vcoreiii_wait_memctl();
39	if (hal_vcoreiii_init_dqs() \|\| vcoreiii_train_bytelane())	39	if (hal_vcoreiii_init_dqs() \|\| vcoreiii_train_bytelane())
40	hal_vcoreiii_ddr_failed();	40	hal_vcoreiii_ddr_failed();
41	}	41	}
42	#if (CONFIG_SYS_TEXT_BASE != 0x20000000)	42	#if (CONFIG_SYS_TEXT_BASE != 0x20000000)
43	res = dram_check();	43	res = dram_check();
44	if (res == 0)	44	if (res == 0)
45	hal_vcoreiii_ddr_verified();	45	hal_vcoreiii_ddr_verified();
46	else	46	else
47	hal_vcoreiii_ddr_failed();	47	hal_vcoreiii_ddr_failed();
48		48
49	/* Clear boot-mode and read-back to activate/verify */	49	/* Clear boot-mode and read-back to activate/verify */
50	clrbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,	50	clrbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
51	ICPU_GENERAL_CTRL_BOOT_MODE_ENA);	51	ICPU_GENERAL_CTRL_BOOT_MODE_ENA);
52	readl(BASE_CFG + ICPU_GENERAL_CTRL);	52	readl(BASE_CFG + ICPU_GENERAL_CTRL);
53	#else	53	#else
54	res = 0;	54	res = 0;
55	#endif	55	#endif
56	return res;	56	return res;
57	}	57	}
58		58
59	int print_cpuinfo(void)	59	int print_cpuinfo(void)
60	{	60	{
61	printf("MSCC VCore-III MIPS 24Kec\n");	61	printf("MSCC VCore-III MIPS 24Kec\n");
62		62
63	return 0;	63	return 0;
64	}	64	}
65		65
66	int dram_init(void)	66	int dram_init(void)
67	{	67	{
68	while (vcoreiii_ddr_init())	68	while (vcoreiii_ddr_init())
69	;	69	;
70		70
71	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;	71	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
72	return 0;	72	return 0;
73	}	73	}
74		74

arch/mips/mach-mscc/gpio.c

Diff comments View file @ f83ef0d

File was created	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Copyright (c) 2018 Microsemi Corporation
	4	*/
	5
	6	#include <common.h>
	7	#include <asm/io.h>
	8
	9	void mscc_gpio_set_alternate(int gpio, int mode)
	10	{
	11	u32 mask = BIT(gpio);
	12	u32 val0, val1;
	13
	14	val0 = readl(BASE_DEVCPU_GCB + GPIO_ALT(0));
	15	val1 = readl(BASE_DEVCPU_GCB + GPIO_ALT(1));
	16
	17	if (mode == 1) {
	18	val0 \|= mask;
	19	val1 &= ~mask;
	20	} else if (mode == 2) {
	21	val0 &= ~mask;
	22	val1 \|= mask;
	23	} else if (mode == 3) {
	24	val0 \|= mask;
	25	val1 \|= mask;
	26	} else {
	27	val0 &= ~mask;
	28	val1 &= ~mask;
	29	}
	30
	31	writel(val0, BASE_DEVCPU_GCB + GPIO_ALT(0));
	32	writel(val1, BASE_DEVCPU_GCB + GPIO_ALT(1));
	33	}
	34

arch/mips/mach-mscc/include/mach/common.h

Diff comments View file @ f83ef0d

1	/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */	1	/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2	/*	2	/*
3	* Copyright (c) 2018 Microsemi Corporation	3	* Copyright (c) 2018 Microsemi Corporation
4	*/	4	*/
5		5
6	#ifndef __ASM_MACH_COMMON_H	6	#ifndef __ASM_MACH_COMMON_H
7	#define __ASM_MACH_COMMON_H	7	#define __ASM_MACH_COMMON_H
8		8
9	#if defined(CONFIG_SOC_OCELOT)	9	#if defined(CONFIG_SOC_OCELOT)
10	#include <mach/ocelot/ocelot.h>	10	#include <mach/ocelot/ocelot.h>
11	#include <mach/ocelot/ocelot_devcpu_gcb.h>	11	#include <mach/ocelot/ocelot_devcpu_gcb.h>
		12	#include <mach/ocelot/ocelot_devcpu_gcb_miim_regs.h>
12	#include <mach/ocelot/ocelot_icpu_cfg.h>	13	#include <mach/ocelot/ocelot_icpu_cfg.h>
13	#elif defined(CONFIG_SOC_LUTON)	14	#elif defined(CONFIG_SOC_LUTON)
14	#include <mach/luton/luton.h>	15	#include <mach/luton/luton.h>
15	#include <mach/luton/luton_devcpu_gcb.h>	16	#include <mach/luton/luton_devcpu_gcb.h>
		17	#include <mach/luton/luton_devcpu_gcb_miim_regs.h>
16	#include <mach/luton/luton_icpu_cfg.h>	18	#include <mach/luton/luton_icpu_cfg.h>
		19	#elif defined(CONFIG_SOC_JR2)
		20	#include <mach/jr2/jr2.h>
		21	#include <mach/jr2/jr2_devcpu_gcb.h>
		22	#include <mach/jr2/jr2_devcpu_gcb_miim_regs.h>
		23	#include <mach/jr2/jr2_icpu_cfg.h>
17	#else	24	#else
18	#error Unsupported platform	25	#error Unsupported platform
19	#endif	26	#endif
20		27
21	#define MSCC_DDR_TO 0x20000000 /* DDR RAM base offset */	28	#define MSCC_DDR_TO 0x20000000 /* DDR RAM base offset */
22	#define MSCC_MEMCTL1_TO 0x40000000 /* SPI/PI base offset */	29	#define MSCC_MEMCTL1_TO 0x40000000 /* SPI/PI base offset */
23	#define MSCC_MEMCTL2_TO 0x50000000 /* SPI/PI base offset */	30	#define MSCC_MEMCTL2_TO 0x50000000 /* SPI/PI base offset */
24	#define MSCC_FLASH_TO MSCC_MEMCTL1_TO /* Flash base offset */	31	#define MSCC_FLASH_TO MSCC_MEMCTL1_TO /* Flash base offset */
25		32
26	#define VCOREIII_TIMER_DIVIDER 25 /* Clock tick ~ 0.1 us */	33	#define VCOREIII_TIMER_DIVIDER 25 /* Clock tick ~ 0.1 us */
		34
		35	/* Common utility functions */
		36
		37	/*
		38	* Perform a number of NOP instructions, blocks of 8 instructions.
		39	* The (inlined) function will not affect cache or processor state.
		40	*/
		41	static inline void mscc_vcoreiii_nop_delay(int delay)
		42	{
		43	while (delay > 0) {
		44	#define DELAY_8_NOPS() asm volatile("nop; nop; nop; nop; nop; nop; nop; nop;")
		45	switch (delay) {
		46	case 8:
		47	DELAY_8_NOPS();
		48	/* fallthrough */
		49	case 7:
		50	DELAY_8_NOPS();
		51	/* fallthrough */
		52	case 6:
		53	DELAY_8_NOPS();
		54	/* fallthrough */
		55	case 5:
		56	DELAY_8_NOPS();
		57	/* fallthrough */
		58	case 4:
		59	DELAY_8_NOPS();
		60	/* fallthrough */
		61	case 3:
		62	DELAY_8_NOPS();
		63	/* fallthrough */
		64	case 2:
		65	DELAY_8_NOPS();
		66	/* fallthrough */
		67	case 1:
		68	DELAY_8_NOPS();
		69	}
		70	delay -= 8;
		71	#undef DELAY_8_NOPS
		72	}
		73	}
		74
		75	int mscc_phy_rd_wr(u8 read,
		76	u32 miim_controller,
		77	u8 miim_addr,
		78	u8 addr,
		79	u16 *value);
		80
		81	int mscc_phy_rd(u32 miim_controller,
		82	u8 miim_addr,
		83	u8 addr,
		84	u16 *value);
		85
		86	int mscc_phy_wr(u32 miim_controller,
		87	u8 miim_addr,
		88	u8 addr,
		89	u16 value);
		90
		91	void mscc_gpio_set_alternate(int gpio, int mode);
27		92
28	#endif /* __ASM_MACH_COMMON_H */	93	#endif /* __ASM_MACH_COMMON_H */
29		94

arch/mips/mach-mscc/include/mach/ddr.h

Diff comments View file @ f83ef0d

 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
 /*
  * Copyright (c) 2018 Microsemi Corporation
  */
 #ifndef __ASM_MACH_DDR_H
 #define __ASM_MACH_DDR_H
 #include <asm/cacheops.h>
 #include <asm/io.h>
 #include <asm/reboot.h>
 #include <mach/common.h>
 #define MIPS_VCOREIII_MEMORY_DDR3
 #define MIPS_VCOREIII_DDR_SIZE CONFIG_SYS_SDRAM_SIZE
 #if defined(CONFIG_DDRTYPE_H5TQ1G63BFA)	/* Serval1 Refboard */
 /* Hynix H5TQ1G63BFA (1Gbit DDR3, x16) @ 3.20ns */
 #define VC3_MPAR_bank_addr_cnt    3
 #define VC3_MPAR_row_addr_cnt     13
 #define VC3_MPAR_col_addr_cnt     10
 #define VC3_MPAR_tREFI            2437
 #define VC3_MPAR_tRAS_min         12
 #define VC3_MPAR_CL               6
 #define VC3_MPAR_tWTR             4
 #define VC3_MPAR_tRC              16
 #define VC3_MPR_tFAW             16
 #define VC3_MPAR_tRP              5
 #define VC3_MPAR_tRRD             4
 #define VC3_MPAR_tRCD             5
 #define VC3_MPAR_tMRD             4
 #define VC3_MPAR_tRFC             35
 #define VC3_MPAR_CWL              5
 #define VC3_MPAR_tXPR             38
 #define VC3_MPAR_tMOD             12
 #define VC3_MPAR_tDLLK            512
 #define VC3_MPAR_tWR              5
 #elif defined(CONFIG_DDRTYPE_MT41J128M16HA)	/* Validation board */
 /* Micron MT41J128M16HA-15E:D (2Gbit DDR3, x16) @ 3.20ns */
 #define VC3_MPAR_bank_addr_cnt    3
 #define VC3_MPAR_row_addr_cnt     14
 #define VC3_MPAR_col_addr_cnt     10
 #define VC3_MPAR_tREFI            2437
 #define VC3_MPAR_tRAS_min         12
 #define VC3_MPAR_CL               5
 #define VC3_MPAR_tWTR             4
 #define VC3_MPAR_tRC              16
 #define VC3_MPAR_tFAW             16
 #define VC3_MPAR_tRP              5
 #define VC3_MPAR_tRRD             4
 #define VC3_MPAR_tRCD             5
 #define VC3_MPAR_tMRD             4
 #define VC3_MPAR_tRFC             50
 #define VC3_MPAR_CWL              5
 #define VC3_MPAR_tXPR             54
 #define VC3_MPAR_tMOD             12
 #define VC3_MPAR_tDLLK            512
 #define VC3_MPAR_tWR              5
 #elif defined(CONFIG_DDRTYPE_MT41K256M16)	/* JR2 Validation board */
 /* Micron MT41K256M16 (4Gbit, DDR3L-800, 256Mbitx16) @ 3.20ns */
 #define VC3_MPAR_bank_addr_cnt    3
 #define VC3_MPAR_row_addr_cnt     15
 #define VC3_MPAR_col_addr_cnt     10
 #define VC3_MPAR_tREFI            2437
 #define VC3_MPAR_tRAS_min         12
 #define VC3_MPAR_CL               5
 #define VC3_MPAR_tWTR             4
 #define VC3_MPAR_tRC              16
 #define VC3_MPAR_tFAW             16
 #define VC3_MPAR_tRP              5
 #define VC3_MPAR_tRRD             4
 #define VC3_MPAR_tRCD             5
 #define VC3_MPAR_tMRD             4
 #define VC3_MPAR_tRFC             82
 #define VC3_MPAR_CWL              5
 #define VC3_MPAR_tXPR             85
 #define VC3_MPAR_tMOD             12
 #define VC3_MPAR_tDLLK            512
 #define VC3_MPAR_tWR              5
 #elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR)	/* JR2 Reference board */
 /* Hynix H5TQ4G63MFR-PBC (4Gbit, DDR3-800, 256Mbitx16) - 2kb pages @ 3.20ns */
 #define VC3_MPAR_bank_addr_cnt    3
 #define VC3_MPAR_row_addr_cnt     15
 #define VC3_MPAR_col_addr_cnt     10
 #define VC3_MPAR_tREFI            2437
 #define VC3_MPAR_tRAS_min         12
 #define VC3_MPAR_CL               6
 #define VC3_MPAR_tWTR             4
 #define VC3_MPAR_tRC              17
 #define VC3_MPAR_tFAW             16
 #define VC3_MPAR_tRP              5
 #define VC3_MPAR_tRRD             4
 #define VC3_MPAR_tRCD             5
 #define VC3_MPAR_tMRD             4
 #define VC3_MPAR_tRFC             82
 #define VC3_MPAR_CWL              5
 #define VC3_MPAR_tXPR             85
 #define VC3_MPAR_tMOD             12
 #define VC3_MPAR_tDLLK            512
 #define VC3_MPAR_tWR              5
 #elif defined(CONFIG_DDRTYPE_MT41K128M16JT)
 /* Micron Micron MT41K128M16JT-125 (2Gbit DDR3L, 128Mbitx16) @ 3.20ns */
 #define VC3_MPAR_bank_addr_cnt    3
 #define VC3_MPAR_row_addr_cnt     14
 #define VC3_MPAR_col_addr_cnt     10
 #define VC3_MPAR_tREFI            2437
 #define VC3_MPAR_tRAS_min         12
 #define VC3_MPAR_CL               6
 #define VC3_MPAR_tWTR             4
 #define VC3_MPAR_tRC              16
 #define VC3_MPAR_tFAW             16
 #define VC3_MPAR_tRP              5
 #define VC3_MPAR_tRRD             4
 #define VC3_MPAR_tRCD             5
 #define VC3_MPAR_tMRD             4
 #define VC3_MPAR_tRFC             82
 #define VC3_MPAR_CWL              5
 #define VC3_MPAR_tXPR             85
 #define VC3_MPAR_tMOD             12
 #define VC3_MPAR_tDLLK            512
 #define VC3_MPAR_tWR              5
 #elif defined(CONFIG_DDRTYPE_MT47H128M8HQ)	/* Luton10/26 Refboards */
 /* Micron 1Gb MT47H128M8-3 16Meg x 8 x 8 banks, DDR-533@CL4 @ 4.80ns */
 #define VC3_MPAR_bank_addr_cnt    3
 #define VC3_MPAR_row_addr_cnt     14
 #define VC3_MPAR_col_addr_cnt     10
 #define VC3_MPAR_tREFI            1625
 #define VC3_MPAR_tRAS_min         9
 #define VC3_MPAR_CL               4
 #define VC3_MPAR_tWTR             2
 #define VC3_MPAR_tRC              12
 #define VC3_MPAR_tFAW             8
 #define VC3_MPAR_tRP              4
 #define VC3_MPAR_tRRD             2
 #define VC3_MPAR_tRCD             4
 #define VC3_MPAR_tRPA             4
 #define VC3_MPAR_tRP              4
 #define VC3_MPAR_tMRD             2
 #define VC3_MPAR_tRFC             27
 #define VC3_MPAR__400_ns_dly      84
 #define VC3_MPAR_tWR              4
 #undef MIPS_VCOREIII_MEMORY_DDR3
 #else
 #error Unknown DDR system configuration - please add!
 #endif
-#ifdef CONFIG_SOC_OCELOT
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
 #define MIPS_VCOREIII_MEMORY_16BIT 1
 #endif
 #define MIPS_VCOREIII_MEMORY_SSTL_ODT 7
 #define MIPS_VCOREIII_MEMORY_SSTL_DRIVE 7
 #define VCOREIII_DDR_DQS_MODE_CALIBRATE
 #ifdef MIPS_VCOREIII_MEMORY_16BIT
 #define VC3_MPAR_16BIT       1
 #else
 #define VC3_MPAR_16BIT       0
 #endif
 #ifdef MIPS_VCOREIII_MEMORY_DDR3
 #define VC3_MPAR_DDR3_MODE    1	/* DDR3 */
 #define VC3_MPAR_BURST_LENGTH 8	/* Always 8 (1) for DDR3 */
 #ifdef MIPS_VCOREIII_MEMORY_16BIT
 #define VC3_MPAR_BURST_SIZE   1	/* Always 1 for DDR3/16bit */
 #else
 #define VC3_MPAR_BURST_SIZE   0
 #endif
 #else
 #define VC3_MPAR_DDR3_MODE    0	/* DDR2 */
 #ifdef MIPS_VCOREIII_MEMORY_16BIT
 #define VC3_MPAR_BURST_LENGTH 4	/* in DDR2 16-bit mode, use burstlen 4 */
 #else
 #define VC3_MPAR_BURST_LENGTH 8	/* For 8-bit IF we must run burst-8 */
 #endif
 #define VC3_MPAR_BURST_SIZE   0	/* Always 0 for DDR2 */
 #endif
 #define VC3_MPAR_RL VC3_MPAR_CL
 #if !defined(MIPS_VCOREIII_MEMORY_DDR3)
 #define VC3_MPAR_WL (VC3_MPAR_RL - 1)
 #define VC3_MPAR_MD VC3_MPAR_tMRD
 #define VC3_MPAR_ID VC3_MPAR__400_ns_dly
 #define VC3_MPAR_SD VC3_MPAR_tXSRD
 #define VC3_MPAR_OW (VC3_MPAR_WL - 2)
 #define VC3_MPAR_OR (VC3_MPAR_WL - 3)
 #define VC3_MPAR_RP (VC3_MPAR_bank_addr_cnt < 3 ? VC3_MPAR_tRP : VC3_MPAR_tRPA)
 #define VC3_MPAR_FAW (VC3_MPAR_bank_addr_cnt < 3 ? 1 : VC3_MPAR_tFAW)
 #define VC3_MPAR_BL (VC3_MPAR_BURST_LENGTH == 4 ? 2 : 4)
 #define MSCC_MEMPARM_MR0 \
 	(VC3_MPAR_BURST_LENGTH == 8 ? 3 : 2) | (VC3_MPAR_CL << 4) | \
 	((VC3_MPAR_tWR - 1) << 9)
 /* DLL-on, Full-OD, AL=0, RTT=off, nDQS-on, RDQS-off, out-en */
 #define MSCC_MEMPARM_MR1 0x382
 #define MSCC_MEMPARM_MR2 0
 #define MSCC_MEMPARM_MR3 0
 #else
 #define VC3_MPAR_WL VC3_MPAR_CWL
 #define VC3_MPAR_MD VC3_MPAR_tMOD
 #define VC3_MPAR_ID VC3_MPAR_tXPR
 #define VC3_MPAR_SD VC3_MPAR_tDLLK
 #define VC3_MPAR_OW 2
 #define VC3_MPAR_OR 2
 #define VC3_MPAR_RP VC3_MPAR_tRP
 #define VC3_MPAR_FAW VC3_MPAR_tFAW
 #define VC3_MPAR_BL 4
 #define MSCC_MEMPARM_MR0 ((VC3_MPAR_RL - 4) << 4) | ((VC3_MPAR_tWR - 4) << 9)
 /* ODT_RTT: “0x0040” for 120ohm, and “0x0004” for 60ohm. */
 #define MSCC_MEMPARM_MR1 0x0040
 #define MSCC_MEMPARM_MR2 ((VC3_MPAR_WL - 5) << 3)
 #define MSCC_MEMPARM_MR3 0
 #endif				/* MIPS_VCOREIII_MEMORY_DDR3 */
 #define MSCC_MEMPARM_MEMCFG                                             \
 	((MIPS_VCOREIII_DDR_SIZE > SZ_512M) ?				\
 	 ICPU_MEMCTRL_CFG_DDR_512MBYTE_PLUS : 0) |			\
 	(VC3_MPAR_16BIT ? ICPU_MEMCTRL_CFG_DDR_WIDTH : 0) |		\
 	(VC3_MPAR_DDR3_MODE ? ICPU_MEMCTRL_CFG_DDR_MODE : 0) |		\
 	(VC3_MPAR_BURST_SIZE ? ICPU_MEMCTRL_CFG_BURST_SIZE : 0) |	\
 	(VC3_MPAR_BURST_LENGTH == 8 ? ICPU_MEMCTRL_CFG_BURST_LEN : 0) | \
 	(VC3_MPAR_bank_addr_cnt == 3 ? ICPU_MEMCTRL_CFG_BANK_CNT : 0) | \
 	ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(VC3_MPAR_row_addr_cnt - 1) |	\
 	ICPU_MEMCTRL_CFG_MSB_COL_ADDR(VC3_MPAR_col_addr_cnt - 1)
-#ifdef CONFIG_SOC_OCELOT
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
 #define MSCC_MEMPARM_PERIOD					\
 	ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(8) |		\
 	ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(VC3_MPAR_tREFI)
 #define MSCC_MEMPARM_TIMING0                                            \
 	ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(VC3_MPAR_RL + VC3_MPAR_BL + 1 - \
 					  VC3_MPAR_WL) |		\
 	ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY(VC3_MPAR_BL - 1) |	\
 	ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY(VC3_MPAR_BL) |		\
 	ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(VC3_MPAR_tRAS_min - 1) |	\
 	ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(VC3_MPAR_WL +		\
 					     VC3_MPAR_BL +		\
 					     VC3_MPAR_tWR - 1) |	\
 	ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(VC3_MPAR_BL - 1) |		\
 		ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(VC3_MPAR_WL - 1) |	\
 	ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(VC3_MPAR_RL - 3)
 #define MSCC_MEMPARM_TIMING1                                            \
 	ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(VC3_MPAR_tRC - 1) | \
 	ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(VC3_MPAR_FAW - 1) |		\
 	ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(VC3_MPAR_RP - 1) |	\
 	ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(VC3_MPAR_tRRD - 1) |	\
 	ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(VC3_MPAR_tRCD - 1) |	\
 	ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(VC3_MPAR_WL +			\
 					  VC3_MPAR_BL +			\
 					  VC3_MPAR_tWTR - 1)
 #define MSCC_MEMPARM_TIMING2					\
 	ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(VC3_MPAR_RP - 1) |	\
 	ICPU_MEMCTRL_TIMING2_MDSET_DLY(VC3_MPAR_MD - 1) |		\
 	ICPU_MEMCTRL_TIMING2_REF_DLY(VC3_MPAR_tRFC - 1) |		\
 	ICPU_MEMCTRL_TIMING2_INIT_DLY(VC3_MPAR_ID - 1)
 #define MSCC_MEMPARM_TIMING3						\
 	ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(VC3_MPAR_WL +	\
 						    VC3_MPAR_tWTR - 1) |\
 	ICPU_MEMCTRL_TIMING3_ODT_RD_DLY(VC3_MPAR_OR - 1) |		\
 	ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(VC3_MPAR_OW - 1) |		\
 	ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(VC3_MPAR_RL - 3)
 #else
 #define MSCC_MEMPARM_PERIOD					\
 	ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(1) |		\
 	ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(VC3_MPAR_tREFI)
 #define MSCC_MEMPARM_TIMING0                                            \
 	ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(VC3_MPAR_tRAS_min - 1) |	\
 	ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(VC3_MPAR_CL +		\
 					     (VC3_MPAR_BURST_LENGTH == 8 ? 2 : 0) + \
 					     VC3_MPAR_tWR) |		\
 	ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(VC3_MPAR_BURST_LENGTH == 8 ? 3 : 1) | \
 	ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(VC3_MPAR_CL - 3) |		\
 	ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(VC3_MPAR_CL - 3)
 #define MSCC_MEMPARM_TIMING1                                            \
 	ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(VC3_MPAR_tRC - 1) | \
 	ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(VC3_MPAR_tFAW - 1) |		\
 	ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(VC3_MPAR_tRP - 1) |	\
 	ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(VC3_MPAR_tRRD - 1) |	\
 	ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(VC3_MPAR_tRCD - 1) |	\
 	ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(VC3_MPAR_CL +			\
 					  (VC3_MPAR_BURST_LENGTH == 8 ? 2 : 0) + \
 					  VC3_MPAR_tWTR)
 #define MSCC_MEMPARM_TIMING2                                            \
 	ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(VC3_MPAR_tRPA - 1) |		\
 	ICPU_MEMCTRL_TIMING2_MDSET_DLY(VC3_MPAR_tMRD - 1) |		\
 	ICPU_MEMCTRL_TIMING2_REF_DLY(VC3_MPAR_tRFC - 1) |		\
 	ICPU_MEMCTRL_TIMING2_FOUR_HUNDRED_NS_DLY(VC3_MPAR__400_ns_dly)
 #define MSCC_MEMPARM_TIMING3						\
 	ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(VC3_MPAR_CL - 1) |	\
 	ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(VC3_MPAR_CL - 1) |		\
 	ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(VC3_MPAR_CL - 1)
 #endif
 enum {
 	DDR_TRAIN_OK,
 	DDR_TRAIN_CONTINUE,
 	DDR_TRAIN_ERROR,
 };
 /*
  * We actually have very few 'pause' possibilities apart from
  * these assembly nops (at this very early stage).
  */
 #define PAUSE() asm volatile("nop; nop; nop; nop; nop; nop; nop; nop")
 /* NB: Assumes inlining as no stack is available! */
 static inline void set_dly(u32 bytelane, u32 dly)
 {
 	register u32 r = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane));
 	r &= ~ICPU_MEMCTRL_DQS_DLY_DQS_DLY_M;
 	r |= ICPU_MEMCTRL_DQS_DLY_DQS_DLY(dly);
 	writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane));
 }
 static inline bool incr_dly(u32 bytelane)
 {
 	register u32 r = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane));
 	if (ICPU_MEMCTRL_DQS_DLY_DQS_DLY(r) < 31) {
 		writel(r + 1, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane));
 		return true;
 	}
 	return false;
 }
 static inline bool adjust_dly(int adjust)
 {
 	register u32 r = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(0));
 	if (ICPU_MEMCTRL_DQS_DLY_DQS_DLY(r) < 31) {
 		writel(r + adjust, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(0));
 		return true;
 	}
 	return false;
 }
 /* NB: Assumes inlining as no stack is available! */
 static inline void center_dly(u32 bytelane, u32 start)
 {
 	register u32 r = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)) - start;
 	writel(start + (r >> 1), BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane));
 }
 static inline void memphy_soft_reset(void)
 {
 	setbits_le32(BASE_CFG + ICPU_MEMPHY_CFG, ICPU_MEMPHY_CFG_PHY_FIFO_RST);
 	PAUSE();
 	clrbits_le32(BASE_CFG + ICPU_MEMPHY_CFG, ICPU_MEMPHY_CFG_PHY_FIFO_RST);
 	PAUSE();
 }
-#ifdef CONFIG_SOC_OCELOT
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
 static u8 training_data[] = { 0xfe, 0x11, 0x33, 0x55, 0x77, 0x99, 0xbb, 0xdd };
 static inline void sleep_100ns(u32 val)
 {
 	/* Set the timer tick generator to 100 ns */
 	writel(VCOREIII_TIMER_DIVIDER - 1, BASE_CFG + ICPU_TIMER_TICK_DIV);
 	/* Set the timer value */
 	writel(val, BASE_CFG + ICPU_TIMER_VALUE(0));
 	/* Enable timer 0 for one-shot */
 	writel(ICPU_TIMER_CTRL_ONE_SHOT_ENA | ICPU_TIMER_CTRL_TIMER_ENA,
 	       BASE_CFG + ICPU_TIMER_CTRL(0));
 	/* Wait for timer 0 to reach 0 */
 	while (readl(BASE_CFG + ICPU_TIMER_VALUE(0)) != 0)
 		;
 }
+#if defined(CONFIG_SOC_OCELOT)
 static inline void hal_vcoreiii_ddr_reset_assert(void)
 {
 	/* DDR has reset pin on GPIO 19 toggle Low-High to release */
 	setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
 	writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_CLR);
 	sleep_100ns(10000);
 }
 static inline void hal_vcoreiii_ddr_reset_release(void)
 {
 	/* DDR has reset pin on GPIO 19 toggle Low-High to release */
 	setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
 	writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
 	sleep_100ns(10000);
 }
 /*
  * DDR memory sanity checking failed, tally and do hard reset
  *
  * NB: Assumes inlining as no stack is available!
  */
 static inline void hal_vcoreiii_ddr_failed(void)
 {
 	register u32 reset;
 	writel(readl(BASE_CFG + ICPU_GPR(6)) + 1, BASE_CFG + ICPU_GPR(6));
 	clrbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
 	/* We have to execute the reset function from cache. Indeed,
 	 * the reboot workaround in _machine_restart() will change the
 	 * SPI NOR into SW bitbang.
 	 *
 	 * This will render the CPU unable to execute directly from
 	 * the NOR, which is why the reset instructions are prefetched
 	 * into the I-cache.
 	 *
 	 * When failing the DDR initialization we are executing from
 	 * NOR.
 	 *
 	 * The last instruction in _machine_restart() will reset the
 	 * MIPS CPU (and the cache), and the CPU will start executing
 	 * from the reset vector.
 	 */
 	reset = KSEG0ADDR(_machine_restart);
 	icache_lock((void *)reset, 128);
 	asm volatile ("jr %0"::"r" (reset));
 	panic("DDR init failed\n");
 }
+#else				/* JR2 */
+static inline void hal_vcoreiii_ddr_reset_assert(void)
+{
+	/* Ensure the memory controller physical iface is forced reset */
+	writel(readl(BASE_CFG + ICPU_MEMPHY_CFG) |
+	       ICPU_MEMPHY_CFG_PHY_RST, BASE_CFG + ICPU_MEMPHY_CFG);
+	/* Ensure the memory controller is forced reset */
+	writel(readl(BASE_CFG + ICPU_RESET) |
+	       ICPU_RESET_MEM_RST_FORCE, BASE_CFG + ICPU_RESET);
+}
+static inline void hal_vcoreiii_ddr_failed(void)
+{
+	writel(0, BASE_CFG + ICPU_RESET);
+	writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_CFG + PERF_SOFT_RST);
+	panic("DDR init failed\n");
+}
+#endif
 /*
  * DDR memory sanity checking done, possibly enable ECC.
  *
  * NB: Assumes inlining as no stack is available!
  */
 static inline void hal_vcoreiii_ddr_verified(void)
 {
 #ifdef MIPS_VCOREIII_MEMORY_ECC
 	/* Finally, enable ECC */
 	register u32 val = readl(BASE_CFG + ICPU_MEMCTRL_CFG);
 	val |= ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA;
 	val &= ~ICPU_MEMCTRL_CFG_BURST_SIZE;
 	writel(val, BASE_CFG + ICPU_MEMCTRL_CFG);
 #endif
 	/* Reset Status register - sticky bits */
 	writel(readl(BASE_CFG + ICPU_MEMCTRL_STAT), BASE_CFG + ICPU_MEMCTRL_STAT);
 }
 /* NB: Assumes inlining as no stack is available! */
 static inline int look_for(u32 bytelane)
 {
 	register u32 i;
 	/* Reset FIFO in case any previous access failed */
 	for (i = 0; i < sizeof(training_data); i++) {
 		register u32 byte;
 		memphy_soft_reset();
 		/* Reset sticky bits */
 		writel(readl(BASE_CFG + ICPU_MEMCTRL_STAT),
 		       BASE_CFG + ICPU_MEMCTRL_STAT);
 		/* Read data */
 		byte = __raw_readb((void __iomem *)MSCC_DDR_TO + bytelane +
 				   (i * 4));
 		/*
 		 * Prevent the compiler reordering the instruction so
 		 * the read of RAM happens after the check of the
 		 * errors.
 		 */
 		rmb();
 		if (readl(BASE_CFG + ICPU_MEMCTRL_STAT) &
 		    (ICPU_MEMCTRL_STAT_RDATA_MASKED |
 		     ICPU_MEMCTRL_STAT_RDATA_DUMMY)) {
 			/* Noise on the line */
 			goto read_error;
 		}
 		/* If mismatch, increment DQS - if possible */
 		if (byte != training_data[i]) {
  read_error:
 			if (!incr_dly(bytelane))
 				return DDR_TRAIN_ERROR;
 			return DDR_TRAIN_CONTINUE;
 		}
 	}
 	return DDR_TRAIN_OK;
 }
 /* NB: Assumes inlining as no stack is available! */
 static inline int look_past(u32 bytelane)
 {
 	register u32 i;
 	/* Reset FIFO in case any previous access failed */
 	for (i = 0; i < sizeof(training_data); i++) {
 		register u32 byte;
 		memphy_soft_reset();
 		/* Ack sticky bits */
 		writel(readl(BASE_CFG + ICPU_MEMCTRL_STAT),
 		       BASE_CFG + ICPU_MEMCTRL_STAT);
 		byte = __raw_readb((void __iomem *)MSCC_DDR_TO + bytelane +
 				   (i * 4));
 		/*
 		 * Prevent the compiler reordering the instruction so
 		 * the read of RAM happens after the check of the
 		 * errors.
 		 */
 		rmb();
 		if (readl(BASE_CFG + ICPU_MEMCTRL_STAT) &
 		    (ICPU_MEMCTRL_STAT_RDATA_MASKED |
 		     ICPU_MEMCTRL_STAT_RDATA_DUMMY)) {
 			/* Noise on the line */
 			goto read_error;
 		}
 		/* Bail out when we see first mismatch */
 		if (byte != training_data[i]) {
  read_error:
 			return DDR_TRAIN_OK;
 		}
 	}
 	/* All data compares OK, increase DQS and retry */
 	if (!incr_dly(bytelane))
 		return DDR_TRAIN_ERROR;
 	return DDR_TRAIN_CONTINUE;
 }
 static inline int hal_vcoreiii_train_bytelane(u32 bytelane)
 {
 	register int res;
 	register u32 dqs_s;
 	set_dly(bytelane, 0);	/* Start training at DQS=0 */
 	while ((res = look_for(bytelane)) == DDR_TRAIN_CONTINUE)
 		;
 	if (res != DDR_TRAIN_OK)
 		return res;
 	dqs_s = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane));
 	while ((res = look_past(bytelane)) == DDR_TRAIN_CONTINUE)
 		;
 	if (res != DDR_TRAIN_OK)
 		return res;
 	/* Reset FIFO - for good measure */
 	memphy_soft_reset();
 	/* Adjust to center [dqs_s;cur] */
 	center_dly(bytelane, dqs_s);
 	return DDR_TRAIN_OK;
 }
 /* This algorithm is converted from the TCL training algorithm used
  * during silicon simulation.
  * NB: Assumes inlining as no stack is available!
  */
 static inline int hal_vcoreiii_init_dqs(void)
 {
 #define MAX_DQS 32
 	register u32 i, j;
 	for (i = 0; i < MAX_DQS; i++) {
 		set_dly(0, i);	/* Byte-lane 0 */
 		for (j = 0; j < MAX_DQS; j++) {
 			__maybe_unused register u32  byte;
 			set_dly(1, j);	/* Byte-lane 1 */
 			/* Reset FIFO in case any previous access failed */
 			memphy_soft_reset();
 			writel(readl(BASE_CFG + ICPU_MEMCTRL_STAT),
 			       BASE_CFG + ICPU_MEMCTRL_STAT);
 			byte = __raw_readb((void __iomem *)MSCC_DDR_TO);
 			byte = __raw_readb((void __iomem *)(MSCC_DDR_TO + 1));
 			if (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT) &
 			    (ICPU_MEMCTRL_STAT_RDATA_MASKED |
 			     ICPU_MEMCTRL_STAT_RDATA_DUMMY)))
 				return 0;
 		}
 	}
 	return -1;
 }
 static inline int dram_check(void)
 {
 	register u32 i;
 	for (i = 0; i < 8; i++) {
 		__raw_writel(~i, (void __iomem *)(MSCC_DDR_TO + (i * 4)));
 		if (__raw_readl((void __iomem *)(MSCC_DDR_TO + (i * 4))) != ~i)
 			return 1;
 	}
 	return 0;
 }
 #else				/* Luton */
 static inline void sleep_100ns(u32 val)
 {
 }
 static inline void hal_vcoreiii_ddr_reset_assert(void)
 {
 	setbits_le32(BASE_CFG + ICPU_MEMPHY_CFG, ICPU_MEMPHY_CFG_PHY_RST);
 	setbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_MEM_RST_FORCE);
 }
 static inline void hal_vcoreiii_ddr_reset_release(void)
 {
 }
 static inline void hal_vcoreiii_ddr_failed(void)
 {
 	register u32 memphy_cfg = readl(BASE_CFG + ICPU_MEMPHY_CFG);
 	/* Do a fifo reset and start over */
 	writel(memphy_cfg | ICPU_MEMPHY_CFG_PHY_FIFO_RST,
 	       BASE_CFG + ICPU_MEMPHY_CFG);
 	writel(memphy_cfg & ~ICPU_MEMPHY_CFG_PHY_FIFO_RST,
 	       BASE_CFG + ICPU_MEMPHY_CFG);
 	writel(memphy_cfg | ICPU_MEMPHY_CFG_PHY_FIFO_RST,
 	       BASE_CFG + ICPU_MEMPHY_CFG);
 }
 static inline void hal_vcoreiii_ddr_verified(void)
 {
 }
 static inline int look_for(u32 data)
 {
 	register u32 byte = __raw_readb((void __iomem *)MSCC_DDR_TO);
 	if (data != byte) {
 		if (!incr_dly(0))
 			return DDR_TRAIN_ERROR;
 		return DDR_TRAIN_CONTINUE;
 	}
 	return DDR_TRAIN_OK;
 }
 /* This algorithm is converted from the TCL training algorithm used
  * during silicon simulation.
  * NB: Assumes inlining as no stack is available!
  */
 static inline int hal_vcoreiii_train_bytelane(u32 bytelane)
 {
 	register int res;
 	set_dly(bytelane, 0);	/* Start training at DQS=0 */
 	while ((res = look_for(0xff)) == DDR_TRAIN_CONTINUE)
 		;
 	if (res != DDR_TRAIN_OK)
 		return res;
 	set_dly(bytelane, 0);	/* Start training at DQS=0 */
 	while ((res = look_for(0x00)) == DDR_TRAIN_CONTINUE)
 		;
 	if (res != DDR_TRAIN_OK)
 		return res;
 	adjust_dly(-3);
 	return DDR_TRAIN_OK;
 }
 static inline int hal_vcoreiii_init_dqs(void)
 {
 	return 0;
 }
 static inline int dram_check(void)
 {
 	register u32 i;
 	for (i = 0; i < 8; i++) {
 		__raw_writel(~i, (void __iomem *)(MSCC_DDR_TO + (i * 4)));
 		if (__raw_readl((void __iomem *)(MSCC_DDR_TO + (i * 4))) != ~i)
 			return 1;
 	}
 	return 0;
 }
 #endif
 /*
  * NB: Called *early* to init memory controller - assumes inlining as
  * no stack is available!
  */
 static inline void hal_vcoreiii_init_memctl(void)
 {
 	/* Ensure DDR is in reset */
 	hal_vcoreiii_ddr_reset_assert();
 	/* Wait maybe not needed, but ... */
 	PAUSE();
 	/* Drop sys ctl memory controller forced reset */
 	clrbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_MEM_RST_FORCE);
 	PAUSE();
 	/* Drop Reset, enable SSTL */
 	writel(ICPU_MEMPHY_CFG_PHY_SSTL_ENA, BASE_CFG + ICPU_MEMPHY_CFG);
 	PAUSE();
 	/* Start the automatic SSTL output and ODT drive-strength calibration */
 	writel(ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT(MIPS_VCOREIII_MEMORY_SSTL_ODT) |
 	       /* drive strength */
 	       ICPU_MEMPHY_ZCAL_ZCAL_PROG(MIPS_VCOREIII_MEMORY_SSTL_DRIVE) |
 	       /* Start calibration process */
 	       ICPU_MEMPHY_ZCAL_ZCAL_ENA, BASE_CFG + ICPU_MEMPHY_ZCAL);
 	/* Wait for ZCAL to clear */
 	while (readl(BASE_CFG + ICPU_MEMPHY_ZCAL) & ICPU_MEMPHY_ZCAL_ZCAL_ENA)
 		;
-#ifdef CONFIG_SOC_OCELOT
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
 	/* Check no ZCAL_ERR */
 	if (readl(BASE_CFG + ICPU_MEMPHY_ZCAL_STAT)
 	    & ICPU_MEMPHY_ZCAL_STAT_ZCAL_ERR)
 		hal_vcoreiii_ddr_failed();
 #endif
 	/* Drive CL, CK, ODT */
 	setbits_le32(BASE_CFG + ICPU_MEMPHY_CFG, ICPU_MEMPHY_CFG_PHY_ODT_OE |
 		     ICPU_MEMPHY_CFG_PHY_CK_OE | ICPU_MEMPHY_CFG_PHY_CL_OE);
 	/* Initialize memory controller */
 	writel(MSCC_MEMPARM_MEMCFG, BASE_CFG + ICPU_MEMCTRL_CFG);
 	writel(MSCC_MEMPARM_PERIOD, BASE_CFG + ICPU_MEMCTRL_REF_PERIOD);
-#ifdef CONFIG_SOC_OCELOT
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
 	writel(MSCC_MEMPARM_TIMING0, BASE_CFG + ICPU_MEMCTRL_TIMING0);
 #else /* Luton */
 	clrbits_le32(BASE_CFG + ICPU_MEMCTRL_TIMING0, ((1 << 20) - 1));
 	setbits_le32(BASE_CFG + ICPU_MEMCTRL_TIMING0, MSCC_MEMPARM_TIMING0);
 #endif
 	writel(MSCC_MEMPARM_TIMING1, BASE_CFG + ICPU_MEMCTRL_TIMING1);
 	writel(MSCC_MEMPARM_TIMING2, BASE_CFG + ICPU_MEMCTRL_TIMING2);
 	writel(MSCC_MEMPARM_TIMING3, BASE_CFG + ICPU_MEMCTRL_TIMING3);
 	writel(MSCC_MEMPARM_MR0, BASE_CFG + ICPU_MEMCTRL_MR0_VAL);
 	writel(MSCC_MEMPARM_MR1, BASE_CFG + ICPU_MEMCTRL_MR1_VAL);
 	writel(MSCC_MEMPARM_MR2, BASE_CFG + ICPU_MEMCTRL_MR2_VAL);
 	writel(MSCC_MEMPARM_MR3, BASE_CFG + ICPU_MEMCTRL_MR3_VAL);
-#ifdef CONFIG_SOC_OCELOT
+#if defined(CONFIG_SOC_OCELOT)
 	/* Termination setup - enable ODT */
 	writel(ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA |
 	       /* Assert ODT0 for any write */
 	       ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(3),
 	       BASE_CFG + ICPU_MEMCTRL_TERMRES_CTRL);
 	/* Release Reset from DDR */
 	hal_vcoreiii_ddr_reset_release();
 	writel(readl(BASE_CFG + ICPU_GPR(7)) + 1, BASE_CFG + ICPU_GPR(7));
+#elif defined(CONFIG_SOC_JR2)
+	writel(ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(3),
+	       BASE_CFG + ICPU_MEMCTRL_TERMRES_CTRL);
 #else				/* Luton */
 	/* Termination setup - disable ODT */
 	writel(0, BASE_CFG + ICPU_MEMCTRL_TERMRES_CTRL);
 #endif
 }
 static inline void hal_vcoreiii_wait_memctl(void)
 {
 	/* Now, rip it! */
 	writel(ICPU_MEMCTRL_CTRL_INITIALIZE, BASE_CFG + ICPU_MEMCTRL_CTRL);
 	while (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT)
 		 & ICPU_MEMCTRL_STAT_INIT_DONE))
 		;
 	/* Settle...? */
 	sleep_100ns(10000);
-#ifdef CONFIG_SOC_OCELOT
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
 	/* Establish data contents in DDR RAM for training */
 	__raw_writel(0xcacafefe, ((void __iomem *)MSCC_DDR_TO));
 	__raw_writel(0x22221111, ((void __iomem *)MSCC_DDR_TO + 0x4));
 	__raw_writel(0x44443333, ((void __iomem *)MSCC_DDR_TO + 0x8));
 	__raw_writel(0x66665555, ((void __iomem *)MSCC_DDR_TO + 0xC));
 	__raw_writel(0x88887777, ((void __iomem *)MSCC_DDR_TO + 0x10));
 	__raw_writel(0xaaaa9999, ((void __iomem *)MSCC_DDR_TO + 0x14));
 	__raw_writel(0xccccbbbb, ((void __iomem *)MSCC_DDR_TO + 0x18));
 	__raw_writel(0xeeeedddd, ((void __iomem *)MSCC_DDR_TO + 0x1C));
 #else
 	__raw_writel(0xff, ((void __iomem *)MSCC_DDR_TO));
 #endif
 }
 #endif				/* __ASM_MACH_DDR_H */

arch/mips/mach-mscc/include/mach/jr2/jr2.h

Diff comments View file @ f83ef0d

File was created	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Microsemi Jaguar2 Switch driver
	4	*
	5	* Copyright (c) 2018 Microsemi Corporation
	6	*/
	7
	8	#ifndef _MSCC_JR2_H_
	9	#define _MSCC_JR2_H_
	10
	11	#include <linux/bitops.h>
	12	#include <dm.h>
	13
	14	/*
	15	* Target offset base(s)
	16	*/
	17	#define MSCC_IO_ORIGIN1_OFFSET 0x70000000
	18	#define MSCC_IO_ORIGIN1_SIZE 0x00200000
	19	#define MSCC_IO_ORIGIN2_OFFSET 0x71000000
	20	#define MSCC_IO_ORIGIN2_SIZE 0x01000000
	21	#define BASE_CFG ((void __iomem *)0x70000000)
	22	#define BASE_DEVCPU_GCB ((void __iomem *)0x71010000)
	23
	24	#endif
	25

arch/mips/mach-mscc/include/mach/jr2/jr2_devcpu_gcb.h

Diff comments View file @ f83ef0d

File was created	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Copyright (c) 2018 Microsemi Corporation
	4	*/
	5
	6	#ifndef _MSCC_JR2_DEVCPU_GCB_H_
	7	#define _MSCC_JR2_DEVCPU_GCB_H_
	8
	9	#define PERF_GPR 0x4
	10
	11	#define PERF_SOFT_RST 0x8
	12
	13	#define PERF_SOFT_RST_SOFT_NON_CFG_RST BIT(2)
	14	#define PERF_SOFT_RST_SOFT_SWC_RST BIT(1)
	15	#define PERF_SOFT_RST_SOFT_CHIP_RST BIT(0)
	16
	17	#define GPIO_GPIO_ALT(x) (0x78 + 4 * (x))
	18	#define GPIO_GPIO_ALT1(x) (0x80 + 4 * (x))
	19
	20	#endif
	21

arch/mips/mach-mscc/include/mach/jr2/jr2_devcpu_gcb_miim_regs.h

Diff comments View file @ f83ef0d

File was created	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Copyright (c) 2018 Microsemi Corporation
	4	*/
	5
	6	#ifndef _MSCC_JR2_DEVCPU_GCB_MIIM_REGS_H_
	7	#define _MSCC_JR2_DEVCPU_GCB_MIIM_REGS_H_
	8
	9	#define MIIM_MII_STATUS(gi) (0xc8 + (gi * 36))
	10	#define MIIM_MII_CMD(gi) (0xd0 + (gi * 36))
	11	#define MIIM_MII_DATA(gi) (0xd4 + (gi * 36))
	12
	13	#define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0)
	14
	15	#define MSCC_F_MII_CMD_MIIM_CMD_VLD(x) ((x) ? BIT(31) : 0)
	16	#define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & ((x) << 25))
	17	#define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & ((x) << 20))
	18	#define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & ((x) << 4))
	19	#define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & ((x) << 1))
	20	#define MSCC_F_MII_CMD_MIIM_CMD_SCAN(x) ((x) ? BIT(0) : 0)
	21
	22	#define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS GENMASK(17, 16)
	23	#define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) (((x) >> 0) & GENMASK(15, 0))
	24
	25	#endif
	26

arch/mips/mach-mscc/include/mach/jr2/jr2_icpu_cfg.h

Diff comments View file @ f83ef0d

File was created	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Copyright (c) 2018 Microsemi Corporation
	4	*/
	5
	6	#ifndef _MSCC_JR2_ICPU_CFG_H_
	7	#define _MSCC_JR2_ICPU_CFG_H_
	8
	9	#define ICPU_GPR(x) (0x4 * (x))
	10	#define ICPU_GPR_RSZ 0x4
	11
	12	#define ICPU_RESET 0x20
	13
	14	#define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
	15	#define ICPU_RESET_CORE_RST_PROTECT BIT(2)
	16	#define ICPU_RESET_CORE_RST_FORCE BIT(1)
	17	#define ICPU_RESET_MEM_RST_FORCE BIT(0)
	18
	19	#define ICPU_GENERAL_CTRL 0x24
	20
	21	#define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(15)
	22	#define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(14)
	23	#define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(13)
	24	#define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(12)
	25	#define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ENA BIT(11)
	26	#define ICPU_GENERAL_CTRL_IF_PI_SLV_DONEPOL BIT(10)
	27	#define ICPU_GENERAL_CTRL_IF_PI_MST_ENA BIT(9)
	28	#define ICPU_GENERAL_CTRL_IF_PI_SLV_ENA BIT(8)
	29	#define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 6) & GENMASK(7, 6))
	30	#define ICPU_GENERAL_CTRL_IF_SI_OWNER_M GENMASK(7, 6)
	31	#define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(7, 6)) >> 4)
	32	#define ICPU_GENERAL_CTRL_IF_SI1_OWNER(x) (((x) << 4) & GENMASK(5, 4))
	33	#define ICPU_GENERAL_CTRL_IF_SI1_OWNER_M GENMASK(5, 4)
	34	#define ICPU_GENERAL_CTRL_IF_SI1_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4)
	35	#define ICPU_GENERAL_CTRL_SSI_MST_CONTENTION BIT(3)
	36	#define ICPU_GENERAL_CTRL_CPU_BE_ENA BIT(2)
	37	#define ICPU_GENERAL_CTRL_CPU_DIS BIT(1)
	38	#define ICPU_GENERAL_CTRL_BOOT_MODE_ENA BIT(0)
	39
	40	#define ICPU_SPI_MST_CFG 0x3c
	41
	42	#define ICPU_SPI_MST_CFG_A32B_ENA BIT(11)
	43	#define ICPU_SPI_MST_CFG_FAST_READ_ENA BIT(10)
	44	#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5))
	45	#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5)
	46	#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5)
	47	#define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
	48	#define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
	49
	50	#define ICPU_SW_MODE 0x50
	51
	52	#define ICPU_SW_MODE_SW_PIN_CTRL_MODE BIT(13)
	53	#define ICPU_SW_MODE_SW_SPI_SCK BIT(12)
	54	#define ICPU_SW_MODE_SW_SPI_SCK_OE BIT(11)
	55	#define ICPU_SW_MODE_SW_SPI_SDO BIT(10)
	56	#define ICPU_SW_MODE_SW_SPI_SDO_OE BIT(9)
	57	#define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5))
	58	#define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5)
	59	#define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5)
	60	#define ICPU_SW_MODE_SW_SPI_CS_OE(x) (((x) << 1) & GENMASK(4, 1))
	61	#define ICPU_SW_MODE_SW_SPI_CS_OE_M GENMASK(4, 1)
	62	#define ICPU_SW_MODE_SW_SPI_CS_OE_X(x) (((x) & GENMASK(4, 1)) >> 1)
	63	#define ICPU_SW_MODE_SW_SPI_SDI BIT(0)
	64
	65	#define ICPU_INTR_ENA 0x88
	66
	67	#define ICPU_DST_INTR_MAP(x) (0x98 + 0x4 * (x))
	68	#define ICPU_DST_INTR_MAP_RSZ 0x4
	69
	70	#define ICPU_TIMER_TICK_DIV 0x108
	71
	72	#define ICPU_TIMER_VALUE(x) (0x10c + 0x4 * (x))
	73	#define ICPU_TIMER_VALUE_RSZ 0x4
	74
	75	#define ICPU_TIMER_CTRL(x) (0x124 + 0x4 * (x))
	76	#define ICPU_TIMER_CTRL_RSZ 0x4
	77
	78	#define ICPU_TIMER_CTRL_MAX_FREQ_ENA BIT(3)
	79	#define ICPU_TIMER_CTRL_ONE_SHOT_ENA BIT(2)
	80	#define ICPU_TIMER_CTRL_TIMER_ENA BIT(1)
	81	#define ICPU_TIMER_CTRL_FORCE_RELOAD BIT(0)
	82
	83	#define ICPU_MEMCTRL_CTRL 0x130
	84
	85	#define ICPU_MEMCTRL_CTRL_PWR_DOWN BIT(3)
	86	#define ICPU_MEMCTRL_CTRL_MDSET BIT(2)
	87	#define ICPU_MEMCTRL_CTRL_STALL_REF_ENA BIT(1)
	88	#define ICPU_MEMCTRL_CTRL_INITIALIZE BIT(0)
	89
	90	#define ICPU_MEMCTRL_CFG 0x134
	91
	92	#define ICPU_MEMCTRL_CFG_DDR_512MBYTE_PLUS BIT(16)
	93	#define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15)
	94	#define ICPU_MEMCTRL_CFG_DDR_ECC_COR_ENA BIT(14)
	95	#define ICPU_MEMCTRL_CFG_DDR_ECC_ENA BIT(13)
	96	#define ICPU_MEMCTRL_CFG_DDR_WIDTH BIT(12)
	97	#define ICPU_MEMCTRL_CFG_DDR_MODE BIT(11)
	98	#define ICPU_MEMCTRL_CFG_BURST_SIZE BIT(10)
	99	#define ICPU_MEMCTRL_CFG_BURST_LEN BIT(9)
	100	#define ICPU_MEMCTRL_CFG_BANK_CNT BIT(8)
	101	#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(x) (((x) << 4) & GENMASK(7, 4))
	102	#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_M GENMASK(7, 4)
	103	#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_X(x) (((x) & GENMASK(7, 4)) >> 4)
	104	#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0))
	105	#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR_M GENMASK(3, 0)
	106
	107	#define ICPU_MEMCTRL_STAT 0x138
	108
	109	#define ICPU_MEMCTRL_STAT_RDATA_MASKED BIT(5)
	110	#define ICPU_MEMCTRL_STAT_RDATA_DUMMY BIT(4)
	111	#define ICPU_MEMCTRL_STAT_RDATA_ECC_ERR BIT(3)
	112	#define ICPU_MEMCTRL_STAT_RDATA_ECC_COR BIT(2)
	113	#define ICPU_MEMCTRL_STAT_PWR_DOWN_ACK BIT(1)
	114	#define ICPU_MEMCTRL_STAT_INIT_DONE BIT(0)
	115
	116	#define ICPU_MEMCTRL_REF_PERIOD 0x13c
	117
	118	#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(x) (((x) << 16) & GENMASK(19, 16))
	119	#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_M GENMASK(19, 16)
	120	#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_X(x) (((x) & GENMASK(19, 16)) >> 16)
	121	#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x) ((x) & GENMASK(15, 0))
	122	#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD_M GENMASK(15, 0)
	123
	124	#define ICPU_MEMCTRL_ZQCAL 0x140
	125
	126	#define ICPU_MEMCTRL_ZQCAL_ZQCAL_LONG BIT(1)
	127	#define ICPU_MEMCTRL_ZQCAL_ZQCAL_SHORT BIT(0)
	128
	129	#define ICPU_MEMCTRL_TIMING0 0x144
	130
	131	#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(x) (((x) << 28) & GENMASK(31, 28))
	132	#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_M GENMASK(31, 28)
	133	#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28)
	134	#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY(x) (((x) << 24) & GENMASK(27, 24))
	135	#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_M GENMASK(27, 24)
	136	#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24)
	137	#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY(x) (((x) << 20) & GENMASK(23, 20))
	138	#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_M GENMASK(23, 20)
	139	#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_X(x) (((x) & GENMASK(23, 20)) >> 20)
	140	#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(x) (((x) << 16) & GENMASK(19, 16))
	141	#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_M GENMASK(19, 16)
	142	#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16)
	143	#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(x) (((x) << 12) & GENMASK(15, 12))
	144	#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_M GENMASK(15, 12)
	145	#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
	146	#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(x) (((x) << 8) & GENMASK(11, 8))
	147	#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_M GENMASK(11, 8)
	148	#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
	149	#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(x) (((x) << 4) & GENMASK(7, 4))
	150	#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_M GENMASK(7, 4)
	151	#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
	152	#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0))
	153	#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY_M GENMASK(3, 0)
	154
	155	#define ICPU_MEMCTRL_TIMING1 0x148
	156
	157	#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(x) (((x) << 24) & GENMASK(31, 24))
	158	#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_M GENMASK(31, 24)
	159	#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_X(x) (((x) & GENMASK(31, 24)) >> 24)
	160	#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(x) (((x) << 16) & GENMASK(23, 16))
	161	#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_M GENMASK(23, 16)
	162	#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16)
	163	#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(x) (((x) << 12) & GENMASK(15, 12))
	164	#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_M GENMASK(15, 12)
	165	#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
	166	#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(x) (((x) << 8) & GENMASK(11, 8))
	167	#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_M GENMASK(11, 8)
	168	#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
	169	#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(x) (((x) << 4) & GENMASK(7, 4))
	170	#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_M GENMASK(7, 4)
	171	#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
	172	#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0))
	173	#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY_M GENMASK(3, 0)
	174
	175	#define ICPU_MEMCTRL_TIMING2 0x14c
	176
	177	#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(x) (((x) << 28) & GENMASK(31, 28))
	178	#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_M GENMASK(31, 28)
	179	#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28)
	180	#define ICPU_MEMCTRL_TIMING2_MDSET_DLY(x) (((x) << 24) & GENMASK(27, 24))
	181	#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_M GENMASK(27, 24)
	182	#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24)
	183	#define ICPU_MEMCTRL_TIMING2_REF_DLY(x) (((x) << 16) & GENMASK(23, 16))
	184	#define ICPU_MEMCTRL_TIMING2_REF_DLY_M GENMASK(23, 16)
	185	#define ICPU_MEMCTRL_TIMING2_REF_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16)
	186	#define ICPU_MEMCTRL_TIMING2_INIT_DLY(x) ((x) & GENMASK(15, 0))
	187	#define ICPU_MEMCTRL_TIMING2_INIT_DLY_M GENMASK(15, 0)
	188
	189	#define ICPU_MEMCTRL_TIMING3 0x150
	190
	191	#define ICPU_MEMCTRL_TIMING3_RMW_DLY(x) (((x) << 16) & GENMASK(19, 16))
	192	#define ICPU_MEMCTRL_TIMING3_RMW_DLY_M GENMASK(19, 16)
	193	#define ICPU_MEMCTRL_TIMING3_RMW_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16)
	194	#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY(x) (((x) << 12) & GENMASK(15, 12))
	195	#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_M GENMASK(15, 12)
	196	#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
	197	#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(x) (((x) << 8) & GENMASK(11, 8))
	198	#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_M GENMASK(11, 8)
	199	#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
	200	#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(x) (((x) << 4) & GENMASK(7, 4))
	201	#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_M GENMASK(7, 4)
	202	#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
	203	#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(x) ((x) & GENMASK(3, 0))
	204	#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY_M GENMASK(3, 0)
	205
	206	#define ICPU_MEMCTRL_TIMING4 0x154
	207
	208	#define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY(x) (((x) << 20) & GENMASK(31, 20))
	209	#define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY_M GENMASK(31, 20)
	210	#define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY_X(x) (((x) & GENMASK(31, 20)) >> 20)
	211	#define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY(x) (((x) << 8) & GENMASK(19, 8))
	212	#define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY_M GENMASK(19, 8)
	213	#define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY_X(x) (((x) & GENMASK(19, 8)) >> 8)
	214	#define ICPU_MEMCTRL_TIMING4_ZQCAL_SHORT_DLY(x) ((x) & GENMASK(7, 0))
	215	#define ICPU_MEMCTRL_TIMING4_ZQCAL_SHORT_DLY_M GENMASK(7, 0)
	216
	217	#define ICPU_MEMCTRL_MR0_VAL 0x158
	218
	219	#define ICPU_MEMCTRL_MR1_VAL 0x15c
	220
	221	#define ICPU_MEMCTRL_MR2_VAL 0x160
	222
	223	#define ICPU_MEMCTRL_MR3_VAL 0x164
	224
	225	#define ICPU_MEMCTRL_TERMRES_CTRL 0x168
	226
	227	#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_EXT BIT(11)
	228	#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA(x) (((x) << 7) & GENMASK(10, 7))
	229	#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_M GENMASK(10, 7)
	230	#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_X(x) (((x) & GENMASK(10, 7)) >> 7)
	231	#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_EXT BIT(6)
	232	#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(x) (((x) << 2) & GENMASK(5, 2))
	233	#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_M GENMASK(5, 2)
	234	#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_X(x) (((x) & GENMASK(5, 2)) >> 2)
	235	#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_EXT BIT(1)
	236	#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA BIT(0)
	237
	238	#define ICPU_MEMCTRL_DFT 0x16c
	239
	240	#define ICPU_MEMCTRL_DFT_DDRDFT_LBW BIT(7)
	241	#define ICPU_MEMCTRL_DFT_DDRDFT_GATE_ENA BIT(6)
	242	#define ICPU_MEMCTRL_DFT_DDRDFT_TERM_ENA BIT(5)
	243	#define ICPU_MEMCTRL_DFT_DDRDFT_A10 BIT(4)
	244	#define ICPU_MEMCTRL_DFT_DDRDFT_STAT BIT(3)
	245	#define ICPU_MEMCTRL_DFT_DDRDFT_MODE(x) (((x) << 1) & GENMASK(2, 1))
	246	#define ICPU_MEMCTRL_DFT_DDRDFT_MODE_M GENMASK(2, 1)
	247	#define ICPU_MEMCTRL_DFT_DDRDFT_MODE_X(x) (((x) & GENMASK(2, 1)) >> 1)
	248	#define ICPU_MEMCTRL_DFT_DDRDFT_ENA BIT(0)
	249
	250	#define ICPU_MEMCTRL_DQS_DLY(x) (0x170 + 0x4 * (x))
	251	#define ICPU_MEMCTRL_DQS_DLY_RSZ 0x4
	252
	253	#define ICPU_MEMCTRL_DQS_DLY_TRAIN_DQ_ENA BIT(11)
	254	#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1(x) (((x) << 8) & GENMASK(10, 8))
	255	#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_M GENMASK(10, 8)
	256	#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_X(x) (((x) & GENMASK(10, 8)) >> 8)
	257	#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0(x) (((x) << 5) & GENMASK(7, 5))
	258	#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_M GENMASK(7, 5)
	259	#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_X(x) (((x) & GENMASK(7, 5)) >> 5)
	260	#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY(x) ((x) & GENMASK(4, 0))
	261	#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_M GENMASK(4, 0)
	262
	263	#define ICPU_MEMCTRL_DQS_AUTO (0x178 + 0x4 * (x))
	264	#define ICPU_MEMCTRL_DQS_AUTO_RSZ 0x4
	265
	266	#define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT(x) (((x) << 6) & GENMASK(7, 6))
	267	#define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT_M GENMASK(7, 6)
	268	#define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT_X(x) (((x) & GENMASK(7, 6)) >> 6)
	269	#define ICPU_MEMCTRL_DQS_AUTO_DQS_OVERFLOW BIT(5)
	270	#define ICPU_MEMCTRL_DQS_AUTO_DQS_UNDERFLOW BIT(4)
	271	#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_SRC BIT(3)
	272	#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_UP BIT(2)
	273	#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_DOWN BIT(1)
	274	#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_ENA BIT(0)
	275
	276	#define ICPU_MEMPHY_CFG 0x180
	277
	278	#define ICPU_MEMPHY_CFG_PHY_FLUSH_DIS BIT(10)
	279	#define ICPU_MEMPHY_CFG_PHY_RD_ADJ_DIS BIT(9)
	280	#define ICPU_MEMPHY_CFG_PHY_DQS_EXT BIT(8)
	281	#define ICPU_MEMPHY_CFG_PHY_FIFO_RST BIT(7)
	282	#define ICPU_MEMPHY_CFG_PHY_DLL_BL_RST BIT(6)
	283	#define ICPU_MEMPHY_CFG_PHY_DLL_CL_RST BIT(5)
	284	#define ICPU_MEMPHY_CFG_PHY_ODT_OE BIT(4)
	285	#define ICPU_MEMPHY_CFG_PHY_CK_OE BIT(3)
	286	#define ICPU_MEMPHY_CFG_PHY_CL_OE BIT(2)
	287	#define ICPU_MEMPHY_CFG_PHY_SSTL_ENA BIT(1)
	288	#define ICPU_MEMPHY_CFG_PHY_RST BIT(0)
	289
	290	#define ICPU_MEMPHY_ZCAL 0x1a8
	291
	292	#define ICPU_MEMPHY_ZCAL_ZCAL_CLK_SEL BIT(9)
	293	#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT(x) (((x) << 5) & GENMASK(8, 5))
	294	#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_M GENMASK(8, 5)
	295	#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_X(x) (((x) & GENMASK(8, 5)) >> 5)
	296	#define ICPU_MEMPHY_ZCAL_ZCAL_PROG(x) (((x) << 1) & GENMASK(4, 1))
	297	#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_M GENMASK(4, 1)
	298	#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_X(x) (((x) & GENMASK(4, 1)) >> 1)
	299	#define ICPU_MEMPHY_ZCAL_ZCAL_ENA BIT(0)
	300	//
	301	#define ICPU_MEMPHY_ZCAL_STAT 0x1ac
	302
	303	#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL(x) (((x) << 12) & GENMASK(31, 12))
	304	#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL_M GENMASK(31, 12)
	305	#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL_X(x) (((x) & GENMASK(31, 12)) >> 12)
	306	#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU(x) (((x) << 8) & GENMASK(9, 8))
	307	#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU_M GENMASK(9, 8)
	308	#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU_X(x) (((x) & GENMASK(9, 8)) >> 8)
	309	#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD(x) (((x) << 6) & GENMASK(7, 6))
	310	#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD_M GENMASK(7, 6)
	311	#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD_X(x) (((x) & GENMASK(7, 6)) >> 6)
	312	#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU(x) (((x) << 4) & GENMASK(5, 4))
	313	#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU_M GENMASK(5, 4)
	314	#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU_X(x) (((x) & GENMASK(5, 4)) >> 4)
	315	#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD(x) (((x) << 2) & GENMASK(3, 2))
	316	#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD_M GENMASK(3, 2)
	317	#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD_X(x) (((x) & GENMASK(3, 2)) >> 2)
	318	#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ERR BIT(1)
	319	#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_DONE BIT(0)
	320
	321	#endif
	322

arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h

Diff comments View file @ f83ef0d

 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
 /*
  * Copyright (c) 2018 Microsemi Corporation
  */
 #ifndef _MSCC_OCELOT_DEVCPU_GCB_H_
 #define _MSCC_OCELOT_DEVCPU_GCB_H_
 #define PERF_SOFT_RST                                     0x90
 #define PERF_SOFT_RST_SOFT_SWC_RST                        BIT(1)
 #define PERF_SOFT_RST_SOFT_CHIP_RST                       BIT(0)
+#define GPIO_ALT(x)				(0x88 + 4 * (x))
+#define CHIP_ID					(0x08)
 #endif

arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h

Diff comments View file @ f83ef0d

File was created	1	/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
	2	/*
	3	* Microsemi Ocelot Switch driver
	4	*
	5	* Copyright (c) 2018 Microsemi Corporation
	6	*/
	7
	8	#ifndef _MSCC_LUTON_MIIM_REGS_H_
	9	#define _MSCC_LUTON_MIIM_REGS_H_
	10
	11	#define MIIM_MII_STATUS(gi) (0xa0 + (gi * 36))
	12	#define MIIM_MII_CMD(gi) (0xa8 + (gi * 36))
	13	#define MIIM_MII_DATA(gi) (0xac + (gi * 36))
	14
	15	#define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) (x ? BIT(3) : 0)
	16
	17	#define MSCC_F_MII_CMD_MIIM_CMD_VLD(x) (x ? BIT(31) : 0)
	18	#define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & (x << 25))
	19	#define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & (x << 20))
	20	#define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & (x << 4))
	21	#define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & (x << 1))
	22
	23	#define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS GENMASK(17, 16)
	24	#define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) ((x >> 0) & GENMASK(15, 0))
	25
	26	#endif
	27

arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h

Diff comments View file @ f83ef0d

 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
 /*
  * Copyright (c) 2018 Microsemi Corporation
  */
 #ifndef _MSCC_OCELOT_DEVCPU_GCB_H_
 #define _MSCC_OCELOT_DEVCPU_GCB_H_
 #define PERF_SOFT_RST                                     0x8
 #define PERF_SOFT_RST_SOFT_NON_CFG_RST                    BIT(2)
 #define PERF_SOFT_RST_SOFT_SWC_RST                        BIT(1)
 #define PERF_SOFT_RST_SOFT_CHIP_RST                       BIT(0)
 #define PERF_GPIO_OUT_SET                                 0x34
 #define PERF_GPIO_OUT_CLR                                 0x38
 #define PERF_GPIO_OE                                      0x44
+#define GPIO_ALT(x)				(0x54 + 4 * (x))
 #endif

arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h

Diff comments View file @ f83ef0d

File was created	1	/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
	2	/*
	3	* Copyright (c) 2018 Microsemi Corporation
	4	*/
	5
	6	#ifndef _MSCC_OCELOT_DEVCPU_GCB_MIIM_REGS_H_
	7	#define _MSCC_OCELOT_DEVCPU_GCB_MIIM_REGS_H_
	8
	9	#define MIIM_MII_STATUS(gi) (0x9c + (gi * 36))
	10	#define MIIM_MII_CMD(gi) (0xa4 + (gi * 36))
	11	#define MIIM_MII_DATA(gi) (0xa8 + (gi * 36))
	12
	13	#define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0)
	14
	15	#define MSCC_F_MII_CMD_MIIM_CMD_VLD(x) ((x) ? BIT(31) : 0)
	16	#define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & ((x) << 25))
	17	#define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & ((x) << 20))
	18	#define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & ((x) << 4))
	19	#define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & ((x) << 1))
	20	#define MSCC_F_MII_CMD_MIIM_CMD_SCAN(x) ((x) ? BIT(0) : 0)
	21
	22	#define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS GENMASK(17, 16)
	23	#define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) (((x) >> 0) & GENMASK(15, 0))
	24
	25	#endif
	26

arch/mips/mach-mscc/phy.c

Diff comments View file @ f83ef0d

File was created	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Copyright (c) 2018 Microsemi Corporation
	4	*/
	5
	6	#include <common.h>
	7	#include <asm/io.h>
	8
	9	int mscc_phy_rd_wr(u8 read,
	10	u32 miimdev,
	11	u8 miim_addr,
	12	u8 addr,
	13	u16 *value)
	14	{
	15	u32 data;
	16	int i;
	17
	18	/* Command part */
	19	data = (read ? MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(2) : /* Read */
	20	MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(1) \| /* Write */
	21	MSCC_F_MII_CMD_MIIM_CMD_WRDATA(value)); / value */
	22
	23	/* Addressing part */
	24	data \|=
	25	MSCC_F_MII_CMD_MIIM_CMD_VLD(1) \| /* Valid command */
	26	MSCC_F_MII_CMD_MIIM_CMD_REGAD(addr) \| /* Reg addr */
	27	MSCC_F_MII_CMD_MIIM_CMD_PHYAD(miim_addr); /* Miim addr */
	28
	29	/* Enqueue MIIM operation to be executed */
	30	writel(data, BASE_DEVCPU_GCB + MIIM_MII_CMD(miimdev));
	31
	32	/* Wait for MIIM operation to finish */
	33	i = 0;
	34	do {
	35	if (i++ > 100) {
	36	debug("Miim timeout");
	37	return -1;
	38	}
	39	data = readl(BASE_DEVCPU_GCB + MIIM_MII_STATUS(miimdev));
	40	debug("Read status miim(%d): 0x%08x\n", miimdev, data);
	41	} while (data & MSCC_F_MII_STATUS_MIIM_STAT_BUSY(1));
	42
	43	if (read) {
	44	data = readl(BASE_DEVCPU_GCB + MIIM_MII_DATA(miimdev));
	45	if (data & MSCC_M_MII_DATA_MIIM_DATA_SUCCESS) {
	46	debug("Read(%d, %d) returned 0x%08x\n",
	47	miim_addr, addr, data);
	48	return -1;
	49	}
	50	*value = MSCC_X_MII_DATA_MIIM_DATA_RDDATA(data);
	51	}
	52
	53	return 0;
	54	}
	55
	56	int mscc_phy_rd(u32 miimdev,
	57	u8 miim_addr,
	58	u8 addr,
	59	u16 *value)
	60	{
	61	if (mscc_phy_rd_wr(1, miimdev, miim_addr, addr, value) == 0)
	62	return 0;
	63	debug("Read(%d, %d) returned error\n", miim_addr, addr);
	64	return -1;
	65	}
	66
	67	int mscc_phy_wr(u32 miimdev,
	68	u8 miim_addr,
	69	u8 addr,
	70	u16 value)
	71	{
	72	return mscc_phy_rd_wr(0, miimdev, miim_addr, addr, &value);
	73	}
	74

arch/mips/mach-mscc/reset.c

Diff comments View file @ f83ef0d

 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2018 Microsemi Corporation
  */
 #include <common.h>
 #include <asm/sections.h>
 #include <asm/io.h>
 #include <asm/reboot.h>
 void _machine_restart(void)
 {
+#if defined(CONFIG_SOC_JR2)
+	register u32 reg = readl(BASE_CFG + ICPU_GENERAL_CTRL);
+	/* Set owner */
+	reg &= ~ICPU_GENERAL_CTRL_IF_SI_OWNER_M;
+	reg |= ICPU_GENERAL_CTRL_IF_SI_OWNER(1);
+	/* Set boot mode */
+	reg |= ICPU_GENERAL_CTRL_BOOT_MODE_ENA;
+	writel(reg, BASE_CFG + ICPU_GENERAL_CTRL);
+	/* Read back in order to make BOOT mode setting active */
+	reg = readl(BASE_CFG + ICPU_GENERAL_CTRL);
+	/* Reset CPU only - still executing _here_. but from cache */
+	writel(readl(BASE_CFG + ICPU_RESET) |
+	       ICPU_RESET_CORE_RST_CPU_ONLY |
+	       ICPU_RESET_CORE_RST_FORCE,
+	       BASE_CFG + ICPU_RESET);
+#else
 	register u32 resetbits = PERF_SOFT_RST_SOFT_CHIP_RST;
 	(void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST);
 	/* Make sure VCore is NOT protected from reset */
 	clrbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_CORE_RST_PROTECT);
 	/* Change to SPI bitbang for SPI reset workaround... */
 	writel(ICPU_SW_MODE_SW_SPI_CS_OE(1) | ICPU_SW_MODE_SW_SPI_CS(1) |
 	       ICPU_SW_MODE_SW_PIN_CTRL_MODE, BASE_CFG + ICPU_SW_MODE);
 	/* Do the global reset */
 	writel(resetbits, BASE_DEVCPU_GCB + PERF_SOFT_RST);
+#endif
 	while (1)
 		; /* NOP */
 }

board/mscc/common/Makefile

Diff comments View file @ f83ef0d

File was created	1	# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2
	3	obj-$(CONFIG_SOC_JR2) := spi.o
	4	obj-$(CONFIG_SOC_OCELOT) := spi.o
	5

board/mscc/common/spi.c

Diff comments View file @ f83ef0d

File was created	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Copyright (c) 2018 Microsemi Coprporation
	4	*/
	5
	6	#include <common.h>
	7	#include <asm/io.h>
	8	#include <spi.h>
	9
	10	void external_cs_manage(struct udevice *dev, bool enable)
	11	{
	12	u32 cs = spi_chip_select(dev);
	13	/* IF_SI0_OWNER, select the owner of the SI interface
	14	* Encoding: 0: SI Slave
	15	* 1: SI Boot Master
	16	* 2: SI Master Controller
	17	*/
	18	if (!enable) {
	19	writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE \|
	20	ICPU_SW_MODE_SW_SPI_CS(BIT(cs)),
	21	BASE_CFG + ICPU_SW_MODE);
	22	clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
	23	ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
	24	ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
	25	} else {
	26	writel(0, BASE_CFG + ICPU_SW_MODE);
	27	clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
	28	ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
	29	ICPU_GENERAL_CTRL_IF_SI_OWNER(1));
	30	}
	31	}
	32

board/mscc/jr2/Kconfig

Diff comments View file @ f83ef0d

File was created	1	# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2
	3	config SYS_VENDOR
	4	default "mscc"
	5
	6	if SOC_JR2
	7
	8	config SYS_BOARD
	9	default "jr2"
	10
	11	config SYS_CONFIG_NAME
	12	default "jr2"
	13
	14	endif
	15
	16

board/mscc/jr2/Makefile

Diff comments View file @ f83ef0d

File was created	1	# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2
	3	obj-$(CONFIG_SOC_JR2) := jr2.o
	4
	5

board/mscc/jr2/jr2.c

Diff comments View file @ f83ef0d

File was created	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Copyright (c) 2018 Microsemi Corporation
	4	*/
	5
	6	#include <common.h>
	7	#include <asm/io.h>
	8	#include <led.h>
	9
	10	enum {
	11	BOARD_TYPE_PCB110 = 0xAABBCE00,
	12	BOARD_TYPE_PCB111,
	13	BOARD_TYPE_PCB112,
	14	};
	15
	16	int board_early_init_r(void)
	17	{
	18	/* Prepare SPI controller to be used in master mode */
	19	writel(0, BASE_CFG + ICPU_SW_MODE);
	20	clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
	21	ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
	22	ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
	23
	24	/* Address of boot parameters */
	25	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
	26
	27	/* LED setup */
	28	if (IS_ENABLED(CONFIG_LED))
	29	led_default_state();
	30
	31	return 0;
	32	}
	33
	34	static void vcoreiii_gpio_set_alternate(int gpio, int mode)
	35	{
	36	u32 mask;
	37	u32 val0, val1;
	38	void __iomem reg0, reg1;
	39
	40	if (gpio < 32) {
	41	mask = BIT(gpio);
	42	reg0 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT(0);
	43	reg1 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT(1);
	44	} else {
	45	gpio -= 32;
	46	mask = BIT(gpio);
	47	reg0 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT1(0);
	48	reg1 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT1(1);
	49	}
	50	val0 = readl(reg0);
	51	val1 = readl(reg1);
	52	if (mode == 1) {
	53	writel(val0 \| mask, reg0);
	54	writel(val1 & ~mask, reg1);
	55	} else if (mode == 2) {
	56	writel(val0 & ~mask, reg0);
	57	writel(val1 \| mask, reg1);
	58	} else if (mode == 3) {
	59	writel(val0 \| mask, reg0);
	60	writel(val1 \| mask, reg1);
	61	} else {
	62	writel(val0 & ~mask, reg0);
	63	writel(val1 & ~mask, reg1);
	64	}
	65	}
	66
	67	static void do_board_detect(void)
	68	{
	69	int i;
	70	u16 pval;
	71
	72	/* MIIM 1 + 2 MDC/MDIO */
	73	for (i = 56; i < 60; i++)
	74	vcoreiii_gpio_set_alternate(i, 1);
	75
	76	if (mscc_phy_rd(0, 0x10, 0x3, &pval) == 0 &&
	77	((pval >> 4) & 0x3F) == 0x3c) {
	78	gd->board_type = BOARD_TYPE_PCB112; /* Serval2-NID */
	79	} else if (mscc_phy_rd(1, 0x0, 0x3, &pval) == 0 &&
	80	((pval >> 4) & 0x3F) == 0x3c) {
	81	gd->board_type = BOARD_TYPE_PCB110; /* Jr2-24 */
	82	} else {
	83	/* Fall-back */
	84	gd->board_type = BOARD_TYPE_PCB111; /* Jr2-48 */
	85	}
	86	}
	87
	88	#if defined(CONFIG_MULTI_DTB_FIT)
	89	int board_fit_config_name_match(const char *name)
	90	{
	91	if (gd->board_type == BOARD_TYPE_PCB110 &&
	92	strcmp(name, "jr2_pcb110") == 0)
	93	return 0;
	94
	95	if (gd->board_type == BOARD_TYPE_PCB111 &&
	96	strcmp(name, "jr2_pcb111") == 0)
	97	return 0;
	98
	99	if (gd->board_type == BOARD_TYPE_PCB112 &&
	100	strcmp(name, "serval2_pcb112") == 0)
	101	return 0;
	102
	103	return -1;
	104	}
	105	#endif
	106
	107	#if defined(CONFIG_DTB_RESELECT)
	108	int embedded_dtb_select(void)
	109	{
	110	do_board_detect();
	111	fdtdec_setup();
	112
	113	return 0;
	114	}
	115	#endif
	116

board/mscc/luton/luton.c

Diff comments View file @ f83ef0d

1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2	/*	2	/*
3	* Copyright (c) 2018 Microsemi Corporation	3	* Copyright (c) 2018 Microsemi Corporation
4	*/	4	*/
5		5
6	#include <common.h>	6	#include <common.h>
7	#include <asm/io.h>	7	#include <asm/io.h>
		8	#include <led.h>
8		9
9	#define MSCC_GPIO_ALT0 0x88
10	#define MSCC_GPIO_ALT1 0x8C
11
12	DECLARE_GLOBAL_DATA_PTR;	10	DECLARE_GLOBAL_DATA_PTR;
13		11
		12	enum {
		13	BOARD_TYPE_PCB090 = 0xAABBCD00,
		14	BOARD_TYPE_PCB091,
		15	};
		16
14	void board_debug_uart_init(void)	17	void board_debug_uart_init(void)
15	{	18	{
16	/* too early for the pinctrl driver, so configure the UART pins here */	19	/* too early for the pinctrl driver, so configure the UART pins here */
17	setbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT0, BIT(30) \| BIT(31));	20	mscc_gpio_set_alternate(30, 1);
		21	mscc_gpio_set_alternate(31, 1);
18	}	22	}
19		23
20	int board_early_init_r(void)	24	int board_early_init_r(void)
21	{	25	{
22	/* Prepare SPI controller to be used in master mode */	26	/* Prepare SPI controller to be used in master mode */
23	writel(0, BASE_CFG + ICPU_SW_MODE);	27	writel(0, BASE_CFG + ICPU_SW_MODE);
24		28
25	/* Address of boot parameters */	29	/* Address of boot parameters */
26	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;	30	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
		31
		32	/* LED setup */
		33	if (IS_ENABLED(CONFIG_LED))
		34	led_default_state();
		35
27	return 0;	36	return 0;
28	}	37	}
		38
		39	static void do_board_detect(void)
		40	{
		41	u32 chipid = (readl(BASE_DEVCPU_GCB + CHIP_ID) >> 12) & 0xFFFF;
		42
		43	if (chipid == 0x7428 \|\| chipid == 0x7424)
		44	gd->board_type = BOARD_TYPE_PCB091; // Lu10
		45	else
		46	gd->board_type = BOARD_TYPE_PCB090; // Lu26
		47	}
		48
		49	#if defined(CONFIG_MULTI_DTB_FIT)
		50	int board_fit_config_name_match(const char *name)
		51	{
		52	if (gd->board_type == BOARD_TYPE_PCB090 &&
		53	strcmp(name, "luton_pcb090") == 0)
		54	return 0;
		55
		56	if (gd->board_type == BOARD_TYPE_PCB091 &&
		57	strcmp(name, "luton_pcb091") == 0)
		58	return 0;
		59
		60	return -1;
		61	}
		62	#endif
		63
		64	#if defined(CONFIG_DTB_RESELECT)
		65	int embedded_dtb_select(void)
		66	{
		67	do_board_detect();
		68	fdtdec_setup();
		69
		70	return 0;

board/mscc/ocelot/ocelot.c

Diff comments View file @ f83ef0d

 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2018 Microsemi Corporation
  */
 #include <common.h>
 #include <asm/io.h>
 #include <asm/addrspace.h>
 #include <asm/types.h>
 #include <environment.h>
 #include <spi.h>
+#include <led.h>
 DECLARE_GLOBAL_DATA_PTR;
-#define MSCC_GPIO_ALT0		0x54
+enum {
-#define MSCC_GPIO_ALT1		0x58
+	BOARD_TYPE_PCB120 = 0xAABBCC00,
+	BOARD_TYPE_PCB123,
+};
-void external_cs_manage(struct udevice *dev, bool enable)
-{
-	u32 cs = spi_chip_select(dev);
-	/* IF_SI0_OWNER, select the owner of the SI interface
-	 * Encoding: 0: SI Slave
-	 *           1: SI Boot Master
-	 *           2: SI Master Controller
-	 */
-	if (!enable) {
-		writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE |
-		       ICPU_SW_MODE_SW_SPI_CS(BIT(cs)), BASE_CFG + ICPU_SW_MODE);
-		clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
-				ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
-				ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
-	} else {
-		writel(0, BASE_CFG + ICPU_SW_MODE);
-		clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
-				ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
-				ICPU_GENERAL_CTRL_IF_SI_OWNER(1));
-	}
-}
 void board_debug_uart_init(void)
 {
 	/* too early for the pinctrl driver, so configure the UART pins here */
-	setbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT0, BIT(6) | BIT(7));
+	mscc_gpio_set_alternate(6, 1);
-	clrbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT1, BIT(6) | BIT(7));
+	mscc_gpio_set_alternate(7, 1);
 }
 int board_early_init_r(void)
 {
 	/* Prepare SPI controller to be used in master mode */
 	writel(0, BASE_CFG + ICPU_SW_MODE);
 	clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
 			ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
 			ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
 	/* Address of boot parameters */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+	/* LED setup */
+	if (IS_ENABLED(CONFIG_LED))
+		led_default_state();
 	return 0;
 }
+static void do_board_detect(void)
+{
+	u16 dummy = 0;
+	/* Enable MIIM */
+	mscc_gpio_set_alternate(14, 1);
+	mscc_gpio_set_alternate(15, 1);
+	if (mscc_phy_rd(1, 0, 0, &dummy) == 0)
+		gd->board_type = BOARD_TYPE_PCB120;
+	else
+		gd->board_type = BOARD_TYPE_PCB123;
+}
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{

configs/bcm968380gerg_ram_defconfig

Diff comments View file @ f83ef0d

 CONFIG_MIPS=y
 CONFIG_SYS_TEXT_BASE=0x80010000
 CONFIG_ARCH_BMIPS=y
 CONFIG_SOC_BMIPS_BCM6838=y
 # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_CPUINFO=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="bcm968380gerg # "
 CONFIG_CMD_CPU=y
 CONFIG_CMD_LICENSE=y
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
 # CONFIG_CMD_EDITENV is not set
 # CONFIG_CMD_SAVEENV is not set
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_CRC32 is not set
 CONFIG_CMD_MEMINFO=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_MISC is not set
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="brcm,bcm968380gerg"
 # CONFIG_NET is not set
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_HAVE_BLOCK_DEVICE=y
 CONFIG_DM_GPIO=y
 CONFIG_LED=y
 CONFIG_LED_BCM6328=y
 CONFIG_LED_BLINK=y
 CONFIG_SPI_FLASH=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHY=y
 CONFIG_BCM6368_USBH_PHY=y
 CONFIG_PINCTRL=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_BCM6328_POWER_DOMAIN=y
 CONFIG_DM_RESET=y
 CONFIG_RESET_BCM6345=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 CONFIG_DM_SERIAL=y
 CONFIG_BCM6345_SERIAL=y
 CONFIG_LZO=y

configs/boston32r2_defconfig

Diff comments View file @ f83ef0d

 CONFIG_MIPS=y
 CONFIG_SYS_TEXT_BASE=0x9FC00000
 CONFIG_TARGET_BOSTON=y
 # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_BEST_MATCH=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_PROMPT="boston # "
 # CONFIG_CMD_ELF is not set
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="img,boston"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CLK=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_DM_ETH=y
 CONFIG_PCH_GBE=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_PCI_XILINX=y
 CONFIG_SYS_NS16550=y
 CONFIG_LZ4=y

configs/boston32r2el_defconfig

Diff comments View file @ f83ef0d

 CONFIG_MIPS=y
 CONFIG_SYS_TEXT_BASE=0x9FC00000
 CONFIG_TARGET_BOSTON=y
 CONFIG_SYS_LITTLE_ENDIAN=y
 # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_BEST_MATCH=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_PROMPT="boston # "
 # CONFIG_CMD_ELF is not set
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="img,boston"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CLK=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_DM_ETH=y
 CONFIG_PCH_GBE=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_PCI_XILINX=y
 CONFIG_SYS_NS16550=y
 CONFIG_LZ4=y

configs/boston32r6_defconfig

Diff comments View file @ f83ef0d

 CONFIG_MIPS=y
 CONFIG_SYS_TEXT_BASE=0x9FC00000
 CONFIG_TARGET_BOSTON=y
 CONFIG_CPU_MIPS32_R6=y
 # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_BEST_MATCH=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_PROMPT="boston # "
 # CONFIG_CMD_ELF is not set
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="img,boston"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CLK=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_DM_ETH=y
 CONFIG_PCH_GBE=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_PCI_XILINX=y
 CONFIG_SYS_NS16550=y
 CONFIG_LZ4=y

configs/boston32r6el_defconfig

Diff comments View file @ f83ef0d

 CONFIG_MIPS=y
 CONFIG_SYS_TEXT_BASE=0x9FC00000
 CONFIG_TARGET_BOSTON=y
 CONFIG_SYS_LITTLE_ENDIAN=y
 CONFIG_CPU_MIPS32_R6=y
 # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_BEST_MATCH=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_PROMPT="boston # "
 # CONFIG_CMD_ELF is not set
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="img,boston"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CLK=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_DM_ETH=y
 CONFIG_PCH_GBE=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_PCI_XILINX=y
 CONFIG_SYS_NS16550=y
 CONFIG_LZ4=y

configs/boston64r2_defconfig

Diff comments View file @ f83ef0d

 CONFIG_MIPS=y
 CONFIG_SYS_TEXT_BASE=0xFFFFFFFF9FC00000
 CONFIG_TARGET_BOSTON=y
 CONFIG_CPU_MIPS64_R2=y
 # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_BEST_MATCH=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_PROMPT="boston # "
 # CONFIG_CMD_ELF is not set
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="img,boston"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CLK=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_DM_ETH=y
 CONFIG_PCH_GBE=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_PCI_XILINX=y
 CONFIG_SYS_NS16550=y
 CONFIG_LZ4=y

configs/boston64r2el_defconfig

Diff comments View file @ f83ef0d

 CONFIG_MIPS=y
 CONFIG_SYS_TEXT_BASE=0xFFFFFFFF9FC00000
 CONFIG_TARGET_BOSTON=y
 CONFIG_SYS_LITTLE_ENDIAN=y
 CONFIG_CPU_MIPS64_R2=y
 # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_BEST_MATCH=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_PROMPT="boston # "
 # CONFIG_CMD_ELF is not set
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="img,boston"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CLK=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_DM_ETH=y
 CONFIG_PCH_GBE=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_PCI_XILINX=y
 CONFIG_SYS_NS16550=y
 CONFIG_LZ4=y

configs/boston64r6_defconfig

Diff comments View file @ f83ef0d

 CONFIG_MIPS=y
 CONFIG_SYS_TEXT_BASE=0xFFFFFFFF9FC00000
 CONFIG_TARGET_BOSTON=y
 CONFIG_CPU_MIPS64_R6=y
 # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_BEST_MATCH=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_PROMPT="boston # "
 # CONFIG_CMD_ELF is not set
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="img,boston"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CLK=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_DM_ETH=y
 CONFIG_PCH_GBE=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_PCI_XILINX=y
 CONFIG_SYS_NS16550=y
 CONFIG_LZ4=y

configs/boston64r6el_defconfig

Diff comments View file @ f83ef0d

 CONFIG_MIPS=y
 CONFIG_SYS_TEXT_BASE=0xFFFFFFFF9FC00000
 CONFIG_TARGET_BOSTON=y
 CONFIG_SYS_LITTLE_ENDIAN=y
 CONFIG_CPU_MIPS64_R6=y
 # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_BEST_MATCH=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_PROMPT="boston # "
 # CONFIG_CMD_ELF is not set
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="img,boston"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CLK=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_DM_ETH=y
 CONFIG_PCH_GBE=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_PCI_XILINX=y
 CONFIG_SYS_NS16550=y
 CONFIG_LZ4=y

configs/ci20_mmc_defconfig

Diff comments View file @ f83ef0d

 CONFIG_MIPS=y
-CONFIG_SPL_LDSCRIPT="arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds"
 CONFIG_SYS_TEXT_BASE=0x80010000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_ARCH_JZ47XX=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_FIT=y
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS4,115200 rw rootwait root=/dev/mmcblk0p1"
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="ext4load mmc 0:1 0x88000000 /boot/uImage; bootm 0x88000000"
 CONFIG_MISC_INIT_R=y
 CONFIG_DISPLAY_CPUINFO=y
 CONFIG_BOARD_EARLY_INIT_F=y
 # CONFIG_SPL_BANNER_PRINT is not set
 # CONFIG_TPL_BANNER_PRINT is not set
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_DM=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="ci20"
 CONFIG_ENV_IS_IN_MMC=y
 # CONFIG_DM_WARN is not set
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_JZ4780_EFUSE=y
 CONFIG_MMC=y
 CONFIG_MMC_BROKEN_CD=y
 CONFIG_DM_MMC=y
 # CONFIG_MMC_HW_PARTITIONING is not set
 CONFIG_MMC_IO_VOLTAGE=y
 CONFIG_MMC_UHS_SUPPORT=y
 CONFIG_MMC_HS400_SUPPORT=y
 # CONFIG_MMC_VERBOSE is not set
 CONFIG_SPL_MMC_TINY=y
 CONFIG_JZ47XX_MMC=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL_TINY_MEMSET=y
 CONFIG_LZO=y

configs/comtrend_ar5315u_ram_defconfig

Diff comments View file @ f83ef0d

 CONFIG_MIPS=y
 CONFIG_SYS_TEXT_BASE=0x80010000
 CONFIG_ARCH_BMIPS=y
 CONFIG_SOC_BMIPS_BCM6318=y
 # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_CPUINFO=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="AR-5315un # "
 CONFIG_CMD_CPU=y
 CONFIG_CMD_LICENSE=y
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
 # CONFIG_CMD_EDITENV is not set
 # CONFIG_CMD_SAVEENV is not set
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_CRC32 is not set
 CONFIG_CMD_MEMINFO=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5315u"
 CONFIG_NET_RANDOM_ETHADDR=y
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_BCM6348_IUDMA=y
 CONFIG_DM_GPIO=y
 CONFIG_LED=y
 CONFIG_LED_BCM6328=y
 CONFIG_LED_BLINK=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_DM_ETH=y
 CONFIG_BCM6368_ETH=y
 CONFIG_PHY=y
 CONFIG_BCM6318_USBH_PHY=y
 CONFIG_BCM6328_POWER_DOMAIN=y
 CONFIG_DM_RESET=y
 CONFIG_RESET_BCM6345=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 CONFIG_DM_SERIAL=y
 CONFIG_BCM6345_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_BCM63XX_HSSPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_GENERIC=y

configs/comtrend_ar5387un_ram_defconfig

Diff comments View file @ f83ef0d

 CONFIG_MIPS=y
 CONFIG_SYS_TEXT_BASE=0x80010000
 CONFIG_ARCH_BMIPS=y
 CONFIG_SOC_BMIPS_BCM6328=y
 # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_CPUINFO=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="AR-5387un # "
 CONFIG_CMD_CPU=y
 CONFIG_CMD_LICENSE=y
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
 # CONFIG_CMD_EDITENV is not set
 # CONFIG_CMD_SAVEENV is not set
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_CRC32 is not set
 CONFIG_CMD_MEMINFO=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5387un"
 CONFIG_NET_RANDOM_ETHADDR=y
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_BCM6348_IUDMA=y
 CONFIG_DM_GPIO=y
 CONFIG_LED=y
 CONFIG_LED_BCM6328=y
 CONFIG_LED_BLINK=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_DM_ETH=y
 CONFIG_BCM6368_ETH=y
 CONFIG_PHY=y
 CONFIG_BCM6368_USBH_PHY=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_BCM6328_POWER_DOMAIN=y
 CONFIG_DM_RESET=y
 CONFIG_RESET_BCM6345=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 CONFIG_DM_SERIAL=y
 CONFIG_BCM6345_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_BCM63XX_HSSPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_GENERIC=y

configs/comtrend_ct5361_ram_defconfig

Diff comments View file @ f83ef0d

 CONFIG_MIPS=y
 CONFIG_SYS_TEXT_BASE=0x80010000
 CONFIG_ARCH_BMIPS=y
 CONFIG_SOC_BMIPS_BCM6348=y
 # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_CPUINFO=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CT-5361 # "
 CONFIG_CMD_CPU=y
 CONFIG_CMD_LICENSE=y
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
 # CONFIG_CMD_EDITENV is not set
 # CONFIG_CMD_SAVEENV is not set
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_CRC32 is not set
 CONFIG_CMD_MEMINFO=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_USB=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="comtrend,ct-5361"
 CONFIG_NET_RANDOM_ETHADDR=y
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_BCM6348_IUDMA=y
 CONFIG_DM_GPIO=y
 CONFIG_BCM6345_GPIO=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_FIXED=y
 CONFIG_DM_ETH=y
 CONFIG_BCM6348_ETH=y
 CONFIG_PHY=y
 CONFIG_BCM6348_USBH_PHY=y
 CONFIG_DM_RESET=y
 CONFIG_RESET_BCM6345=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 CONFIG_DM_SERIAL=y
 CONFIG_BCM6345_SERIAL=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_GENERIC=y
 CONFIG_WDT_BCM6345=y

configs/comtrend_vr3032u_ram_defconfig

Diff comments View file @ f83ef0d

 CONFIG_MIPS=y
 CONFIG_SYS_TEXT_BASE=0x80010000
 CONFIG_ARCH_BMIPS=y
 CONFIG_SOC_BMIPS_BCM63268=y
 # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_CPUINFO=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="VR-3032u # "
 CONFIG_CMD_CPU=y
 CONFIG_CMD_LICENSE=y
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
 # CONFIG_CMD_EDITENV is not set
 # CONFIG_CMD_SAVEENV is not set
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_CRC32 is not set
 CONFIG_CMD_MEMINFO=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_USB=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="comtrend,vr-3032u"
 CONFIG_NET_RANDOM_ETHADDR=y
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_BCM6348_IUDMA=y
 CONFIG_DM_GPIO=y
 CONFIG_LED=y
 CONFIG_LED_BCM6328=y
 CONFIG_LED_BLINK=y
 CONFIG_DM_ETH=y
 CONFIG_BCM6368_ETH=y
 CONFIG_PHY=y
 CONFIG_BCM6368_USBH_PHY=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_BCM6328_POWER_DOMAIN=y
 CONFIG_DM_RESET=y
 CONFIG_RESET_BCM6345=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 CONFIG_DM_SERIAL=y
 CONFIG_BCM6345_SERIAL=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_GENERIC=y

configs/comtrend_wap5813n_ram_defconfig

Diff comments View file @ f83ef0d

 CONFIG_MIPS=y
 CONFIG_SYS_TEXT_BASE=0x80010000
 CONFIG_ARCH_BMIPS=y
 CONFIG_SOC_BMIPS_BCM6368=y
 # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_CPUINFO=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="WAP-5813n # "
 CONFIG_CMD_CPU=y
 CONFIG_CMD_LICENSE=y
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
 # CONFIG_CMD_EDITENV is not set
 # CONFIG_CMD_SAVEENV is not set
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_CRC32 is not set
 CONFIG_CMD_MEMINFO=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_USB=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="comtrend,wap-5813n"
 CONFIG_NET_RANDOM_ETHADDR=y
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_BCM6348_IUDMA=y
 CONFIG_DM_GPIO=y
 CONFIG_BCM6345_GPIO=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_DM_ETH=y
 CONFIG_PHY_GIGE=y
 CONFIG_BCM6368_ETH=y
 CONFIG_PHY=y
 CONFIG_BCM6368_USBH_PHY=y
 CONFIG_DM_RESET=y
 CONFIG_RESET_BCM6345=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 CONFIG_DM_SERIAL=y
 CONFIG_BCM6345_SERIAL=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_GENERIC=y

configs/gardena-smart-gateway-mt7688-ram_defconfig

Diff comments View file @ f83ef0d

1	CONFIG_MIPS=y	1	CONFIG_MIPS=y
2	CONFIG_SYS_TEXT_BASE=0x80010000	2	CONFIG_SYS_TEXT_BASE=0x80010000
3	CONFIG_ARCH_MT7620=y	3	CONFIG_ARCH_MT7620=y
4	# CONFIG_MIPS_BOOT_ENV_LEGACY is not set	4	# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
5	CONFIG_MIPS_BOOT_FDT=y	5	CONFIG_MIPS_BOOT_FDT=y
6	CONFIG_ENV_VARS_UBOOT_CONFIG=y	6	CONFIG_ENV_VARS_UBOOT_CONFIG=y
7	CONFIG_NR_DRAM_BANKS=1	7	CONFIG_NR_DRAM_BANKS=1
8	# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set	8	# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
9	CONFIG_FIT=y	9	CONFIG_FIT=y
10	CONFIG_FIT_SIGNATURE=y	10	CONFIG_FIT_SIGNATURE=y
11	CONFIG_IMAGE_FORMAT_LEGACY=y	11	CONFIG_IMAGE_FORMAT_LEGACY=y
12	CONFIG_OF_STDOUT_VIA_ALIAS=y	12	CONFIG_OF_STDOUT_VIA_ALIAS=y
13	CONFIG_USE_BOOTCOMMAND=y	13	CONFIG_USE_BOOTCOMMAND=y
14	CONFIG_BOOTCOMMAND="cp.b 83000000 84000000 10000 && dhcp uEnv.txt && env import -t ${fileaddr} ${filesize} && run do_u_boot_init; reset"	14	CONFIG_BOOTCOMMAND="cp.b 83000000 84000000 10000 && dhcp uEnv.txt && env import -t ${fileaddr} ${filesize} && run do_u_boot_init; reset"
15	CONFIG_SYS_CONSOLE_INFO_QUIET=y	15	CONFIG_SYS_CONSOLE_INFO_QUIET=y
16	CONFIG_VERSION_VARIABLE=y	16	CONFIG_VERSION_VARIABLE=y
17	CONFIG_BOARD_EARLY_INIT_F=y	17	CONFIG_BOARD_EARLY_INIT_F=y
18	CONFIG_HUSH_PARSER=y	18	CONFIG_HUSH_PARSER=y
19	CONFIG_CMD_LICENSE=y	19	CONFIG_CMD_LICENSE=y
20	# CONFIG_CMD_ELF is not set	20	# CONFIG_CMD_ELF is not set
21	# CONFIG_CMD_XIMG is not set	21	# CONFIG_CMD_XIMG is not set
22	CONFIG_CMD_MEMINFO=y	22	CONFIG_CMD_MEMINFO=y
23	# CONFIG_CMD_FLASH is not set	23	# CONFIG_CMD_FLASH is not set
24	CONFIG_CMD_GPIO=y	24	CONFIG_CMD_GPIO=y
25	# CONFIG_CMD_LOADS is not set	25	# CONFIG_CMD_LOADS is not set
26	CONFIG_CMD_MTD=y	26	CONFIG_CMD_MTD=y
27	CONFIG_CMD_SF=y	27	CONFIG_CMD_SF=y
28	CONFIG_CMD_SPI=y	28	CONFIG_CMD_SPI=y
29	CONFIG_CMD_DHCP=y	29	CONFIG_CMD_DHCP=y
30	CONFIG_CMD_MII=y	30	CONFIG_CMD_MII=y
31	CONFIG_CMD_PING=y	31	CONFIG_CMD_PING=y
32	CONFIG_CMD_BOOTCOUNT=y	32	CONFIG_CMD_BOOTCOUNT=y
33	CONFIG_CMD_TIME=y	33	CONFIG_CMD_TIME=y
34	CONFIG_CMD_UUID=y	34	CONFIG_CMD_UUID=y
35	CONFIG_CMD_MTDPARTS=y	35	CONFIG_CMD_MTDPARTS=y
36	CONFIG_MTDIDS_DEFAULT="spi-nand0=gd5f,nor0=spi0.0"	36	CONFIG_MTDIDS_DEFAULT="spi-nand0=spi0.1,nor0=spi0.0"
37	CONFIG_MTDPARTS_DEFAULT="spi0.0:640k(uboot),64k(uboot_env0),64k(uboot_env1),64k(factory),-(unused);gd5f:-(nand)"	37	CONFIG_MTDPARTS_DEFAULT="spi0.0:640k(uboot),64k(uboot_env0),64k(uboot_env1),64k(factory),-(unused);spi0.1:-(nand)"
38	CONFIG_CMD_UBI=y	38	CONFIG_CMD_UBI=y
39	CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688"	39	CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688"
40	CONFIG_ENV_IS_IN_SPI_FLASH=y	40	CONFIG_ENV_IS_IN_SPI_FLASH=y
41	CONFIG_NET_RANDOM_ETHADDR=y	41	CONFIG_NET_RANDOM_ETHADDR=y
42	# CONFIG_DM_DEVICE_REMOVE is not set	42	# CONFIG_DM_DEVICE_REMOVE is not set
43	CONFIG_HAVE_BLOCK_DEVICE=y	43	CONFIG_HAVE_BLOCK_DEVICE=y
44	CONFIG_BOOTCOUNT_LIMIT=y	44	CONFIG_BOOTCOUNT_LIMIT=y
45	CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y	45	CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
46	CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c	46	CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c
47	CONFIG_CLK=y	47	CONFIG_CLK=y
48	CONFIG_LED=y	48	CONFIG_LED=y
49	CONFIG_LED_BLINK=y	49	CONFIG_LED_BLINK=y
50	CONFIG_LED_GPIO=y	50	CONFIG_LED_GPIO=y
51	CONFIG_MTD=y	51	CONFIG_MTD=y
52	CONFIG_MTD_SPI_NAND=y	52	CONFIG_MTD_SPI_NAND=y
53	CONFIG_SPI_FLASH=y	53	CONFIG_SPI_FLASH=y
54	CONFIG_SPI_FLASH_GIGADEVICE=y	54	CONFIG_SPI_FLASH_GIGADEVICE=y
55	CONFIG_SPI_FLASH_MACRONIX=y	55	CONFIG_SPI_FLASH_MACRONIX=y
56	CONFIG_SPI_FLASH_SPANSION=y	56	CONFIG_SPI_FLASH_SPANSION=y
57	CONFIG_SPI_FLASH_STMICRO=y	57	CONFIG_SPI_FLASH_STMICRO=y
58	CONFIG_SPI_FLASH_WINBOND=y	58	CONFIG_SPI_FLASH_WINBOND=y
59	CONFIG_SPI_FLASH_XMC=y	59	CONFIG_SPI_FLASH_XMC=y
60	CONFIG_SPI_FLASH_MTD=y	60	CONFIG_SPI_FLASH_MTD=y
61	CONFIG_MTD_UBI_BEB_LIMIT=22	61	CONFIG_MTD_UBI_BEB_LIMIT=22
62	CONFIG_PHYLIB=y	62	CONFIG_PHYLIB=y
63	CONFIG_PHY_FIXED=y	63	CONFIG_PHY_FIXED=y
64	CONFIG_MT7628_ETH=y	64	CONFIG_MT7628_ETH=y
65	CONFIG_PHY=y	65	CONFIG_PHY=y
66	CONFIG_POWER_DOMAIN=y	66	CONFIG_POWER_DOMAIN=y
67	CONFIG_RAM=y	67	CONFIG_RAM=y
68	CONFIG_DM_RESET=y	68	CONFIG_DM_RESET=y
69	# CONFIG_SPL_SERIAL_PRESENT is not set	69	# CONFIG_SPL_SERIAL_PRESENT is not set
70	CONFIG_SYS_NS16550=y	70	CONFIG_SYS_NS16550=y
71	CONFIG_SPI=y	71	CONFIG_SPI=y
72	CONFIG_MT7621_SPI=y	72	CONFIG_MT7621_SPI=y
73	CONFIG_SYSRESET_SYSCON=y	73	CONFIG_SYSRESET_SYSCON=y
74	CONFIG_WATCHDOG=y	74	CONFIG_WATCHDOG=y
75	CONFIG_WDT=y	75	CONFIG_WDT=y
76	CONFIG_WDT_MT7621=y	76	CONFIG_WDT_MT7621=y
77	CONFIG_LZMA=y	77	CONFIG_LZMA=y
78		78

configs/gardena-smart-gateway-mt7688_defconfig

Diff comments View file @ f83ef0d

1	CONFIG_MIPS=y	1	CONFIG_MIPS=y
2	CONFIG_SYS_TEXT_BASE=0x9c000000	2	CONFIG_SYS_TEXT_BASE=0x9c000000
3	CONFIG_ARCH_MT7620=y	3	CONFIG_ARCH_MT7620=y
4	CONFIG_BOOT_ROM=y	4	CONFIG_BOOT_ROM=y
5	CONFIG_ONBOARD_DDR2_SIZE_1024MBIT=y	5	CONFIG_ONBOARD_DDR2_SIZE_1024MBIT=y
6	CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT=y	6	CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT=y
7	# CONFIG_MIPS_BOOT_ENV_LEGACY is not set	7	# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
8	CONFIG_MIPS_BOOT_FDT=y	8	CONFIG_MIPS_BOOT_FDT=y
9	CONFIG_ENV_VARS_UBOOT_CONFIG=y	9	CONFIG_ENV_VARS_UBOOT_CONFIG=y
10	CONFIG_NR_DRAM_BANKS=1	10	CONFIG_NR_DRAM_BANKS=1
11	# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set	11	# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
12	CONFIG_FIT=y	12	CONFIG_FIT=y
13	CONFIG_FIT_SIGNATURE=y	13	CONFIG_FIT_SIGNATURE=y
14	CONFIG_IMAGE_FORMAT_LEGACY=y	14	CONFIG_IMAGE_FORMAT_LEGACY=y
15	CONFIG_OF_STDOUT_VIA_ALIAS=y	15	CONFIG_OF_STDOUT_VIA_ALIAS=y
16	CONFIG_USE_BOOTCOMMAND=y	16	CONFIG_USE_BOOTCOMMAND=y
17	CONFIG_BOOTCOMMAND="cp.b 83000000 84000000 10000 && dhcp uEnv.txt && env import -t ${fileaddr} ${filesize} && run do_u_boot_init; reset"	17	CONFIG_BOOTCOMMAND="cp.b 83000000 84000000 10000 && dhcp uEnv.txt && env import -t ${fileaddr} ${filesize} && run do_u_boot_init; reset"
18	CONFIG_SYS_CONSOLE_INFO_QUIET=y	18	CONFIG_SYS_CONSOLE_INFO_QUIET=y
19	CONFIG_VERSION_VARIABLE=y	19	CONFIG_VERSION_VARIABLE=y
20	CONFIG_BOARD_EARLY_INIT_F=y	20	CONFIG_BOARD_EARLY_INIT_F=y
21	CONFIG_HUSH_PARSER=y	21	CONFIG_HUSH_PARSER=y
22	CONFIG_CMD_LICENSE=y	22	CONFIG_CMD_LICENSE=y
23	# CONFIG_CMD_ELF is not set	23	# CONFIG_CMD_ELF is not set
24	# CONFIG_CMD_XIMG is not set	24	# CONFIG_CMD_XIMG is not set
25	CONFIG_CMD_MEMINFO=y	25	CONFIG_CMD_MEMINFO=y
26	# CONFIG_CMD_FLASH is not set	26	# CONFIG_CMD_FLASH is not set
27	CONFIG_CMD_GPIO=y	27	CONFIG_CMD_GPIO=y
28	# CONFIG_CMD_LOADS is not set	28	# CONFIG_CMD_LOADS is not set
29	CONFIG_CMD_MTD=y	29	CONFIG_CMD_MTD=y
30	CONFIG_CMD_SF=y	30	CONFIG_CMD_SF=y
31	CONFIG_CMD_SPI=y	31	CONFIG_CMD_SPI=y
32	CONFIG_CMD_DHCP=y	32	CONFIG_CMD_DHCP=y
33	CONFIG_CMD_MII=y	33	CONFIG_CMD_MII=y
34	CONFIG_CMD_PING=y	34	CONFIG_CMD_PING=y
35	CONFIG_CMD_BOOTCOUNT=y	35	CONFIG_CMD_BOOTCOUNT=y
36	CONFIG_CMD_TIME=y	36	CONFIG_CMD_TIME=y
37	CONFIG_CMD_UUID=y	37	CONFIG_CMD_UUID=y
38	CONFIG_CMD_MTDPARTS=y	38	CONFIG_CMD_MTDPARTS=y
39	CONFIG_MTDIDS_DEFAULT="spi-nand0=gd5f,nor0=spi0.0"	39	CONFIG_MTDIDS_DEFAULT="spi-nand0=spi0.1,nor0=spi0.0"
40	CONFIG_MTDPARTS_DEFAULT="spi0.0:640k(uboot),64k(uboot_env0),64k(uboot_env1),64k(factory),-(unused);gd5f:-(nand)"	40	CONFIG_MTDPARTS_DEFAULT="spi0.0:640k(uboot),64k(uboot_env0),64k(uboot_env1),64k(factory),-(unused);spi0.1:-(nand)"
41	CONFIG_CMD_UBI=y	41	CONFIG_CMD_UBI=y
42	CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688"	42	CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688"
43	CONFIG_ENV_IS_IN_SPI_FLASH=y	43	CONFIG_ENV_IS_IN_SPI_FLASH=y
44	CONFIG_NET_RANDOM_ETHADDR=y	44	CONFIG_NET_RANDOM_ETHADDR=y
45	# CONFIG_DM_DEVICE_REMOVE is not set	45	# CONFIG_DM_DEVICE_REMOVE is not set
46	CONFIG_HAVE_BLOCK_DEVICE=y	46	CONFIG_HAVE_BLOCK_DEVICE=y
47	CONFIG_BOOTCOUNT_LIMIT=y	47	CONFIG_BOOTCOUNT_LIMIT=y
48	CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y	48	CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
49	CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c	49	CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c
50	CONFIG_CLK=y	50	CONFIG_CLK=y
51	CONFIG_LED=y	51	CONFIG_LED=y
52	CONFIG_LED_BLINK=y	52	CONFIG_LED_BLINK=y
53	CONFIG_LED_GPIO=y	53	CONFIG_LED_GPIO=y
54	CONFIG_MTD=y	54	CONFIG_MTD=y
55	CONFIG_MTD_SPI_NAND=y	55	CONFIG_MTD_SPI_NAND=y
56	CONFIG_SPI_FLASH=y	56	CONFIG_SPI_FLASH=y
57	CONFIG_SPI_FLASH_GIGADEVICE=y	57	CONFIG_SPI_FLASH_GIGADEVICE=y
58	CONFIG_SPI_FLASH_MACRONIX=y	58	CONFIG_SPI_FLASH_MACRONIX=y
59	CONFIG_SPI_FLASH_SPANSION=y	59	CONFIG_SPI_FLASH_SPANSION=y
60	CONFIG_SPI_FLASH_STMICRO=y	60	CONFIG_SPI_FLASH_STMICRO=y
61	CONFIG_SPI_FLASH_WINBOND=y	61	CONFIG_SPI_FLASH_WINBOND=y
62	CONFIG_SPI_FLASH_XMC=y	62	CONFIG_SPI_FLASH_XMC=y
63	CONFIG_SPI_FLASH_MTD=y	63	CONFIG_SPI_FLASH_MTD=y
64	CONFIG_MTD_UBI_BEB_LIMIT=22	64	CONFIG_MTD_UBI_BEB_LIMIT=22
65	CONFIG_PHYLIB=y	65	CONFIG_PHYLIB=y
66	CONFIG_PHY_FIXED=y	66	CONFIG_PHY_FIXED=y
67	CONFIG_MT7628_ETH=y	67	CONFIG_MT7628_ETH=y
68	CONFIG_PHY=y	68	CONFIG_PHY=y
69	CONFIG_POWER_DOMAIN=y	69	CONFIG_POWER_DOMAIN=y
70	CONFIG_RAM=y	70	CONFIG_RAM=y
71	CONFIG_DM_RESET=y	71	CONFIG_DM_RESET=y
72	# CONFIG_SPL_SERIAL_PRESENT is not set	72	# CONFIG_SPL_SERIAL_PRESENT is not set
73	CONFIG_SYS_NS16550=y	73	CONFIG_SYS_NS16550=y
74	CONFIG_SPI=y	74	CONFIG_SPI=y
75	CONFIG_MT7621_SPI=y	75	CONFIG_MT7621_SPI=y
76	CONFIG_SYSRESET_SYSCON=y	76	CONFIG_SYSRESET_SYSCON=y
77	CONFIG_WATCHDOG=y	77	CONFIG_WATCHDOG=y
78	CONFIG_WDT=y	78	CONFIG_WDT=y
79	CONFIG_WDT_MT7621=y	79	CONFIG_WDT_MT7621=y
80	CONFIG_LZMA=y	80	CONFIG_LZMA=y
81		81

configs/huawei_hg556a_ram_defconfig

Diff comments View file @ f83ef0d

 CONFIG_MIPS=y
 CONFIG_SYS_TEXT_BASE=0x80010000
 CONFIG_ARCH_BMIPS=y
 CONFIG_SOC_BMIPS_BCM6358=y
 # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_CPUINFO=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="HG556a # "
 CONFIG_CMD_CPU=y
 CONFIG_CMD_LICENSE=y
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
 # CONFIG_CMD_EDITENV is not set
 # CONFIG_CMD_SAVEENV is not set
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_CRC32 is not set
 CONFIG_CMD_MEMINFO=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_USB=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="huawei,hg556a"
 CONFIG_NET_RANDOM_ETHADDR=y
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_BCM6348_IUDMA=y
 CONFIG_DM_GPIO=y
 CONFIG_BCM6345_GPIO=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_FIXED=y
 CONFIG_DM_ETH=y
 CONFIG_BCM6348_ETH=y
 CONFIG_PHY=y
 CONFIG_BCM6358_USBH_PHY=y
 CONFIG_DM_RESET=y
 CONFIG_RESET_BCM6345=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 CONFIG_DM_SERIAL=y
 CONFIG_BCM6345_SERIAL=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_GENERIC=y

configs/imgtec_xilfpga_defconfig

Diff comments View file @ f83ef0d

 CONFIG_MIPS=y
 CONFIG_SYS_MALLOC_F_LEN=0x600
 CONFIG_TARGET_XILFPGA=y
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_BOOTDELAY=5
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMDLINE_EDITING is not set
 # CONFIG_AUTO_COMPLETE is not set
 CONFIG_SYS_PROMPT="MIPSfpga # "
 # CONFIG_CMD_SAVEENV is not set
 CONFIG_CMD_MEMINFO=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 # CONFIG_ISO_PARTITION is not set
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="nexys4ddr"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
 CONFIG_CLK=y
 CONFIG_XILINX_EMACLITE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CMD_DHRYSTONE=y

configs/malta64_defconfig

Diff comments View file @ f83ef0d

 CONFIG_MIPS=y
 CONFIG_SYS_TEXT_BASE=0xFFFFFFFFBE000000
 CONFIG_TARGET_MALTA=y
 CONFIG_CPU_MIPS64_R2=y
 CONFIG_MISC_INIT_R=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="malta # "
 # CONFIG_AUTOBOOT is not set
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_IDE=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_PCI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_DATE=y
 # CONFIG_ISO_PARTITION is not set
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PCI=y
 CONFIG_RTC_MC146818=y
 CONFIG_SYS_NS16550=y

configs/malta64el_defconfig

Diff comments View file @ f83ef0d

 CONFIG_MIPS=y
 CONFIG_SYS_TEXT_BASE=0xFFFFFFFFBE000000
 CONFIG_TARGET_MALTA=y
 CONFIG_SYS_LITTLE_ENDIAN=y
 CONFIG_CPU_MIPS64_R2=y
 CONFIG_MISC_INIT_R=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="maltael # "
 # CONFIG_AUTOBOOT is not set
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_IDE=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_PCI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_DATE=y
 # CONFIG_ISO_PARTITION is not set
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PCI=y
 CONFIG_RTC_MC146818=y
 CONFIG_SYS_NS16550=y

configs/malta_defconfig

Diff comments View file @ f83ef0d

 CONFIG_MIPS=y
 CONFIG_SYS_TEXT_BASE=0xBE000000
 CONFIG_TARGET_MALTA=y
 CONFIG_MISC_INIT_R=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="malta # "
 # CONFIG_AUTOBOOT is not set
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_IDE=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_PCI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_DATE=y
 # CONFIG_ISO_PARTITION is not set
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PCI=y
 CONFIG_RTC_MC146818=y
 CONFIG_SYS_NS16550=y

configs/maltael_defconfig

Diff comments View file @ f83ef0d

 CONFIG_MIPS=y
 CONFIG_SYS_TEXT_BASE=0xBE000000
 CONFIG_TARGET_MALTA=y
 CONFIG_SYS_LITTLE_ENDIAN=y
 CONFIG_MISC_INIT_R=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="maltael # "
 # CONFIG_AUTOBOOT is not set
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_IDE=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_PCI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_DATE=y
 # CONFIG_ISO_PARTITION is not set
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PCI=y
 CONFIG_RTC_MC146818=y
 CONFIG_SYS_NS16550=y

configs/mscc_jr2_defconfig

Diff comments View file @ f83ef0d

File was created	1	CONFIG_MIPS=y
	2	CONFIG_SYS_TEXT_BASE=0x40000000
	3	CONFIG_SYS_MALLOC_F_LEN=0x2000
	4	CONFIG_ARCH_MSCC=y
	5	CONFIG_SOC_JR2=y
	6	CONFIG_SYS_LITTLE_ENDIAN=y
	7	CONFIG_FIT=y
	8	CONFIG_BOOTDELAY=3
	9	CONFIG_USE_BOOTARGS=y
	10	CONFIG_BOOTARGS="console=ttyS0,115200"
	11	CONFIG_LOGLEVEL=7
	12	CONFIG_DISPLAY_CPUINFO=y
	13	CONFIG_SYS_PROMPT="jr2 # "
	14	# CONFIG_CMD_BDI is not set
	15	# CONFIG_CMD_CONSOLE is not set
	16	# CONFIG_CMD_ELF is not set
	17	# CONFIG_CMD_EXPORTENV is not set
	18	# CONFIG_CMD_IMPORTENV is not set
	19	# CONFIG_CMD_CRC32 is not set
	20	CONFIG_CMD_MD5SUM=y
	21	CONFIG_CMD_MEMINFO=y
	22	CONFIG_CMD_MEMTEST=y
	23	# CONFIG_CMD_FLASH is not set
	24	CONFIG_CMD_GPIO=y
	25	CONFIG_CMD_SF=y
	26	CONFIG_CMD_SPI=y
	27	# CONFIG_CMD_NET is not set
	28	CONFIG_CMD_MTDPARTS=y
	29	CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
	30	CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:1m(UBoot),256k(Env),256k(Env.bk)"
	31	# CONFIG_ISO_PARTITION is not set
	32	CONFIG_DEFAULT_DEVICE_TREE="jr2_pcb110"
	33	CONFIG_OF_LIST="jr2_pcb110 jr2_pcb111 serval2_pcb112"
	34	CONFIG_DTB_RESELECT=y
	35	CONFIG_MULTI_DTB_FIT=y
	36	CONFIG_ENV_IS_IN_SPI_FLASH=y
	37	CONFIG_NET_RANDOM_ETHADDR=y
	38	CONFIG_CLK=y
	39	CONFIG_DM_GPIO=y
	40	CONFIG_MSCC_SGPIO=y
	41	CONFIG_LED=y
	42	CONFIG_LED_GPIO=y
	43	CONFIG_DM_SPI_FLASH=y
	44	CONFIG_SPI_FLASH=y
	45	CONFIG_SPI_FLASH_BAR=y
	46	CONFIG_SPI_FLASH_GIGADEVICE=y
	47	CONFIG_SPI_FLASH_MACRONIX=y
	48	CONFIG_SPI_FLASH_SPANSION=y
	49	CONFIG_SPI_FLASH_WINBOND=y
	50	CONFIG_SPI_FLASH_MTD=y
	51	CONFIG_DM_ETH=y
	52	CONFIG_PINCTRL=y
	53	CONFIG_PINCONF=y
	54	CONFIG_DM_SERIAL=y
	55	CONFIG_SYS_NS16550=y
	56	CONFIG_SPI=y
	57	CONFIG_DM_SPI=y
	58	CONFIG_LZMA=y
	59	CONFIG_XZ=y
	60

configs/mscc_luton_defconfig

Diff comments View file @ f83ef0d

 CONFIG_MIPS=y
 CONFIG_SYS_TEXT_BASE=0x40000000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0x70100000
 CONFIG_DEBUG_UART_CLOCK=208333333
 CONFIG_ARCH_MSCC=y
-CONFIG_TARGET_LUTON_PCB091=y
+CONFIG_SOC_LUTON=y
 CONFIG_DDRTYPE_MT47H128M8HQ=y
 CONFIG_SYS_LITTLE_ENDIAN=y
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_BOOTDELAY=3
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200"
 CONFIG_LOGLEVEL=7
 CONFIG_DISPLAY_CPUINFO=y
-CONFIG_SYS_PROMPT="pcb091 # "
+CONFIG_SYS_PROMPT="luton # "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
 # CONFIG_CMD_CRC32 is not set
 CONFIG_CMD_MD5SUM=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_DHCP=y
 # CONFIG_NET_TFTP_VARS is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),6m@1m(linux)"
 # CONFIG_ISO_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="luton_pcb091"
+CONFIG_OF_LIST="luton_pcb090 luton_pcb091"
+CONFIG_DTB_RESELECT=y
+CONFIG_MULTI_DTB_FIT=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CLK=y
 CONFIG_DM_GPIO=y
+CONFIG_MSCC_SGPIO=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_DM_ETH=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
-CONFIG_SOFT_SPI=y
+CONFIG_MSCC_BB_SPI=y
 CONFIG_LZMA=y

configs/mscc_ocelot_defconfig

Diff comments View file @ f83ef0d

 CONFIG_MIPS=y
 CONFIG_SYS_TEXT_BASE=0x40000000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0x70100000
 CONFIG_DEBUG_UART_CLOCK=250000000
 CONFIG_ARCH_MSCC=y
-CONFIG_TARGET_OCELOT_PCB123=y
 CONFIG_SYS_LITTLE_ENDIAN=y
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_BOOTDELAY=3
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200"
 CONFIG_LOGLEVEL=7
 CONFIG_DISPLAY_CPUINFO=y
-CONFIG_SYS_PROMPT="pcb123 # "
+CONFIG_SYS_PROMPT="ocelot # "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
 # CONFIG_CMD_CRC32 is not set
 CONFIG_CMD_MD5SUM=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MTD=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_DHCP=y
 # CONFIG_NET_TFTP_VARS is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),15m(linux),15m(linux.bk)"
 CONFIG_CMD_UBI=y
 # CONFIG_CMD_UBIFS is not set
 # CONFIG_ISO_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="ocelot_pcb123"
+CONFIG_OF_LIST="ocelot_pcb120 ocelot_pcb123"
+CONFIG_DTB_RESELECT=y
+CONFIG_MULTI_DTB_FIT=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CLK=y
 CONFIG_DM_GPIO=y
 CONFIG_MTD=y
 CONFIG_MTD_SPI_NAND=y
+CONFIG_MSCC_SGPIO=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_DM_ETH=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
-CONFIG_DESIGNWARE_SPI=y

configs/mscc_ocelot_pcb120_defconfig

View file @ f83ef0d

1	CONFIG_MIPS=y		File was deleted
2	CONFIG_SYS_TEXT_BASE=0x40000000
3	CONFIG_SYS_MALLOC_F_LEN=0x2000
4	CONFIG_ARCH_MSCC=y
5	CONFIG_SYS_LITTLE_ENDIAN=y
6	CONFIG_FIT=y
7	CONFIG_BOOTDELAY=3
8	CONFIG_USE_BOOTARGS=y
9	CONFIG_BOOTARGS="console=ttyS0,115200"
10	CONFIG_LOGLEVEL=7
11	CONFIG_DISPLAY_CPUINFO=y
12	CONFIG_SYS_PROMPT="pcb120 # "
13	# CONFIG_CMD_BDI is not set
14	# CONFIG_CMD_CONSOLE is not set
15	# CONFIG_CMD_ELF is not set
16	# CONFIG_CMD_EXPORTENV is not set
17	# CONFIG_CMD_IMPORTENV is not set
18	# CONFIG_CMD_CRC32 is not set
19	CONFIG_CMD_MD5SUM=y
20	CONFIG_CMD_MEMINFO=y
21	CONFIG_CMD_MEMTEST=y
22	# CONFIG_CMD_FLASH is not set
23	CONFIG_CMD_GPIO=y
24	CONFIG_CMD_MTD=y
25	CONFIG_CMD_SF=y
26	CONFIG_CMD_SPI=y
27	CONFIG_CMD_DHCP=y
28	# CONFIG_NET_TFTP_VARS is not set
29	# CONFIG_CMD_NFS is not set
30	CONFIG_CMD_PING=y
31	CONFIG_CMD_MTDPARTS=y
32	CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
33	CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),15m(linux),15m(linux.bk)"
34	CONFIG_CMD_UBI=y
35	# CONFIG_CMD_UBIFS is not set
36	# CONFIG_ISO_PARTITION is not set
37	CONFIG_DEFAULT_DEVICE_TREE="ocelot_pcb120"
38	CONFIG_ENV_IS_IN_SPI_FLASH=y
39	CONFIG_NET_RANDOM_ETHADDR=y
40	CONFIG_CLK=y
41	CONFIG_DM_GPIO=y
42	CONFIG_MTD=y
43	CONFIG_MTD_SPI_NAND=y
44	CONFIG_DM_SPI_FLASH=y
45	CONFIG_SPI_FLASH=y
46	CONFIG_SPI_FLASH_BAR=y
47	CONFIG_SPI_FLASH_GIGADEVICE=y
48	CONFIG_SPI_FLASH_MACRONIX=y
49	CONFIG_SPI_FLASH_SPANSION=y
50	CONFIG_SPI_FLASH_WINBOND=y
51	CONFIG_SPI_FLASH_MTD=y
52	CONFIG_DM_ETH=y
53	CONFIG_PINCTRL=y
54	CONFIG_PINCONF=y
55	CONFIG_DM_SERIAL=y
56	CONFIG_SYS_NS16550=y
57	CONFIG_SPI=y
58	CONFIG_DM_SPI=y
59	CONFIG_DESIGNWARE_SPI=y
60	CONFIG_LZMA=y
61		1	CONFIG_MIPS=y

configs/netgear_cg3100d_ram_defconfig

Diff comments View file @ f83ef0d

 CONFIG_MIPS=y
 CONFIG_SYS_TEXT_BASE=0x80010000
 CONFIG_ARCH_BMIPS=y
 # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_CPUINFO=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CG3100D # "
 CONFIG_CMD_CPU=y
 CONFIG_CMD_LICENSE=y
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
 # CONFIG_CMD_EDITENV is not set
 # CONFIG_CMD_SAVEENV is not set
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_CRC32 is not set
 CONFIG_CMD_MEMINFO=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 # CONFIG_CMD_MISC is not set
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="netgear,cg3100d"
 # CONFIG_NET is not set
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_DM_GPIO=y
 CONFIG_BCM6345_GPIO=y
 CONFIG_LED=y
 CONFIG_LED_BCM6328=y
 CONFIG_LED_BLINK=y
 CONFIG_LED_GPIO=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_DM_RESET=y
 CONFIG_RESET_BCM6345=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 CONFIG_DM_SERIAL=y
 CONFIG_BCM6345_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_BCM63XX_SPI=y
 CONFIG_WDT_BCM6345=y

configs/netgear_dgnd3700v2_ram_defconfig

Diff comments View file @ f83ef0d

 CONFIG_MIPS=y
 CONFIG_SYS_TEXT_BASE=0x80010000
 CONFIG_ARCH_BMIPS=y
 CONFIG_SOC_BMIPS_BCM6362=y
 # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_CPUINFO=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="DGND3700v2 # "
 CONFIG_CMD_CPU=y
 CONFIG_CMD_LICENSE=y
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
 # CONFIG_CMD_EDITENV is not set
 # CONFIG_CMD_SAVEENV is not set
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_CRC32 is not set
 CONFIG_CMD_MEMINFO=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_USB=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="netgear,dgnd3700v2"
 CONFIG_NET_RANDOM_ETHADDR=y
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_BCM6348_IUDMA=y
 CONFIG_DM_GPIO=y
 CONFIG_BCM6345_GPIO=y
 CONFIG_LED=y
 CONFIG_LED_BCM6328=y
 CONFIG_LED_BLINK=y
 CONFIG_LED_GPIO=y
 CONFIG_DM_ETH=y
 CONFIG_PHY_GIGE=y
 CONFIG_BCM6368_ETH=y
 CONFIG_PHY=y
 CONFIG_BCM6368_USBH_PHY=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_BCM6328_POWER_DOMAIN=y
 CONFIG_DM_RESET=y
 CONFIG_RESET_BCM6345=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 CONFIG_DM_SERIAL=y
 CONFIG_BCM6345_SERIAL=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_GENERIC=y

configs/pic32mzdask_defconfig

Diff comments View file @ f83ef0d

 CONFIG_MIPS=y
 CONFIG_SYS_TEXT_BASE=0x9D004000
 CONFIG_SYS_MALLOC_F_LEN=0x600
 CONFIG_MACH_PIC32=y
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="dask # "
 # CONFIG_CMD_SAVEENV is not set
 CONFIG_LOOPW=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_CLK=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_RARP=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_ISO_PARTITION is not set
 # CONFIG_EFI_PARTITION is not set
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="pic32mzda_sk"
 CONFIG_NET_RANDOM_ETHADDR=y
 # CONFIG_BLK is not set
 CONFIG_CLK=y
 CONFIG_DM_GPIO=y
 CONFIG_MMC=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PIC32=y
 CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_PIC32_ETH=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_FULL is not set
 CONFIG_DM_SERIAL=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_PIC32=y
 CONFIG_FAT_WRITE=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y

configs/sagem_f@st1704_ram_defconfig

Diff comments View file @ f83ef0d

 CONFIG_MIPS=y
 CONFIG_SYS_TEXT_BASE=0x80010000
 CONFIG_ARCH_BMIPS=y
 CONFIG_SOC_BMIPS_BCM6338=y
 # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_CPUINFO=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="F@ST1704 # "
 CONFIG_CMD_CPU=y
 CONFIG_CMD_LICENSE=y
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
 # CONFIG_CMD_EDITENV is not set
 # CONFIG_CMD_SAVEENV is not set
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_CRC32 is not set
 CONFIG_CMD_MEMINFO=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="sagem,f@st1704"
 CONFIG_NET_RANDOM_ETHADDR=y
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_BCM6348_IUDMA=y
 CONFIG_DM_GPIO=y
 CONFIG_BCM6345_GPIO=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_PHY_FIXED=y
 CONFIG_DM_ETH=y
 CONFIG_BCM6348_ETH=y
 CONFIG_DM_RESET=y
 CONFIG_RESET_BCM6345=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 CONFIG_DM_SERIAL=y
 CONFIG_BCM6345_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_BCM63XX_SPI=y

configs/sfr_nb4-ser_ram_defconfig

Diff comments View file @ f83ef0d

 CONFIG_MIPS=y
 CONFIG_SYS_TEXT_BASE=0x80010000
 CONFIG_ARCH_BMIPS=y
 CONFIG_SOC_BMIPS_BCM6358=y
 CONFIG_BOARD_SFR_NB4_SER=y
 # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DISPLAY_CPUINFO=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="NB4-SER # "
 CONFIG_CMD_CPU=y
 CONFIG_CMD_LICENSE=y
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
 # CONFIG_CMD_EDITENV is not set
 # CONFIG_CMD_SAVEENV is not set
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_CRC32 is not set
 CONFIG_CMD_MEMINFO=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_USB=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="sfr,nb4-ser"
 CONFIG_NET_RANDOM_ETHADDR=y
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_BCM6348_IUDMA=y
 CONFIG_DM_GPIO=y
 CONFIG_BCM6345_GPIO=y
 CONFIG_LED=y
 CONFIG_LED_BCM6358=y
 CONFIG_LED_GPIO=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_FIXED=y
 CONFIG_DM_ETH=y
 CONFIG_BCM6348_ETH=y
 CONFIG_PHY=y
 CONFIG_BCM6358_USBH_PHY=y
 CONFIG_DM_RESET=y
 CONFIG_RESET_BCM6345=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 CONFIG_DM_SERIAL=y
 CONFIG_BCM6345_SERIAL=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_GENERIC=y

doc/device-tree-bindings/gpio/mscc_sgpio.txt

Diff comments View file @ f83ef0d

File was created	1	Microsemi Corporation (MSCC) Serial GPIO driver
	2
	3	The MSCC serial GPIO extends the number or GPIO's on the system by
	4	means of 4 dedicated pins: one input, one output, one clock and one
	5	strobe pin. By attaching a number of (external) shift registers, the
	6	effective GPIO count can be extended by up to 128 GPIO's per
	7	controller.
	8
	9	Required properties:
	10	- compatible : "mscc,luton-sgpio" or "mscc,ocelot-sgpio"
	11	- clock: Reference clock used to generate clock divider setting. See
	12	mscc,sgpio-frequency property.
	13	- reg : Physical base address and length of the controller's registers.
	14	- #gpio-cells : Should be two. The first cell is the pin number and the
	15	second cell is used to specify optional parameters:
	16	- bit 0 specifies polarity (0 for normal, 1 for inverted)
	17	- gpio-controller : Marks the device node as a GPIO controller.
	18	- gpio-ranges: Standard gpio range(s): phandle, gpio base, pinctrl base
	19	and count.
	20
	21	Optional properties:
	22	- ngpios: See gpio.txt
	23	- mscc,sgpio-frequency: The frequency at which the serial bitstream is
	24	generated and sampled. Default: 12500000 (Hz).
	25	- mscc,sgpio-ports: A bitmask (32 bits) of which ports are enabled in
	26	the serialized gpio stream. One 'port' will transport from 1 to 4
	27	gpio bits. Default: 0xFFFFFFFF.
	28
	29	Typically the pinctrl-0 and pinctrl-names properties will also be
	30	present to enable the use of the SIO CLK, LD, DI and DO for some
	31	regular GPIO pins.
	32
	33	Example:
	34
	35	sgpio: gpio@10700f8 {
	36	compatible = "mscc,ocelot-sgpio";
	37	pinctrl-0 = <&sgpio_pins>;
	38	pinctrl-names = "default";
	39	reg = <0x10700f8 0x100>;
	40	gpio-controller;
	41	#gpio-cells = <2>;
	42	gpio-ranges = <&sgpio 0 0 64>;
	43	mscc,sgpio-frequency = <12500>;
	44	mscc,sgpio-ports = <0x000FFFFF>;
	45	};
	46

drivers/gpio/Kconfig

Diff comments View file @ f83ef0d

 #
 # GPIO infrastructure and drivers
 #
 menu "GPIO Support"
 config DM_GPIO
 	bool "Enable Driver Model for GPIO drivers"
 	depends on DM
 	help
 	  Enable driver model for GPIO access. The standard GPIO
 	  interface (gpio_get_value(), etc.) is then implemented by
 	  the GPIO uclass. Drivers provide methods to query the
 	  particular GPIOs that they provide. The uclass interface
 	  is defined in include/asm-generic/gpio.h.
 config ALTERA_PIO
 	bool "Altera PIO driver"
 	depends on DM_GPIO
 	help
 	  Select this to enable PIO for Altera devices. Please find
 	  details on the "Embedded Peripherals IP User Guide" of Altera.
 config BCM6345_GPIO
 	bool "BCM6345 GPIO driver"
 	depends on DM_GPIO && ARCH_BMIPS
 	help
 	  This driver supports the GPIO banks on BCM6345 SoCs.
 config DWAPB_GPIO
 	bool "DWAPB GPIO driver"
 	depends on DM && DM_GPIO
 	default n
 	help
 	  Support for the Designware APB GPIO driver.
 config AT91_GPIO
 	bool "AT91 PIO GPIO driver"
 	depends on DM_GPIO
 	default n
 	help
 	  Say yes here to select AT91 PIO GPIO driver. AT91 PIO
 	  controller manages up to 32 fully programmable input/output
 	  lines. Each I/O line may be dedicated as a general-purpose
 	  I/O or be assigned to a function of an embedded peripheral.
 	  The assignment to a function of an embedded peripheral is
 	  the responsibility of AT91 Pinctrl driver. This driver is
 	  responsible for the general-purpose I/O.
 config ATMEL_PIO4
 	bool "ATMEL PIO4 driver"
 	depends on DM_GPIO
 	default n
 	help
 	  Say yes here to support the Atmel PIO4 driver.
 	  The PIO4 is new version of Atmel PIO controller, which manages
 	  up to 128 fully programmable input/output lines. Each I/O line
 	  may be dedicated as a general purpose I/O or be assigned to
 	  a function of an embedded peripheral.
 config DA8XX_GPIO
 	bool "DA8xx GPIO Driver"
 	help
 	  This driver supports the DA8xx GPIO controller
 config INTEL_BROADWELL_GPIO
 	bool "Intel Broadwell GPIO driver"
 	depends on DM
 	help
 	  This driver supports Broadwell U devices which have an expanded
 	  GPIO feature set. The difference is large enough to merit a separate
 	  driver from the common Intel ICH6 driver. It supports a total of
 	  95 GPIOs which can be configured from the device tree.
 config INTEL_ICH6_GPIO
 	bool "Intel ICH6 compatible legacy GPIO driver"
 	depends on DM_GPIO
 	help
 	  Say yes here to select Intel ICH6 compatible legacy GPIO driver.
 config IMX_RGPIO2P
 	bool "i.MX7ULP RGPIO2P driver"
 	depends on DM
 	default n
 	help
 	  This driver supports i.MX7ULP Rapid GPIO2P controller.
 config HSDK_CREG_GPIO
 	bool "HSDK CREG GPIO griver"
 	depends on DM_GPIO
 	default n
 	help
 	  This driver supports CREG GPIOs on Synopsys HSDK SOC.
 config LPC32XX_GPIO
 	bool "LPC32XX GPIO driver"
 	depends on DM
 	default n
 	help
 	  Support for the LPC32XX GPIO driver.
-config MSCC_BITBANG_SPI_GPIO
+config MSCC_SGPIO
-	bool "Microsemi bitbang spi GPIO driver"
+	bool "Microsemi Serial GPIO driver"
 	depends on DM_GPIO && SOC_VCOREIII
 	help
-	  Support controlling the GPIO used for SPI bitbang by software. Can
+	  Support for the VCoreIII SoC serial GPIO device. By using a
-	  be used by the VCoreIII SoCs, but it was mainly useful for Luton.
+          serial interface, the SIO controller significantly extends
+          the number of available GPIOs with a minimum number of
+          additional pins on the device. The primary purpose of the
+          SIO controller is to connect control signals from SFP
+          modules and to act as an LED controller.
 config MSM_GPIO
 	bool "Qualcomm GPIO driver"
 	depends on DM_GPIO
 	default n
 	help
 	  Support GPIO controllers on Qualcomm Snapdragon family of SoCs.
 	  This controller have single bank (default name "soc"), every
 	  gpio has it's own set of registers.
 	  Only simple GPIO operations are supported (get/set, change of
 	  direction and checking pin function).
 	  Supported devices:
 	  - APQ8016
 	  - MSM8916
 config MXC_GPIO
 	bool "Freescale/NXP MXC GPIO driver"
 	help
 	  Support GPIO controllers on various i.MX platforms
 config OMAP_GPIO
 	bool "TI OMAP GPIO driver"
 	depends on ARCH_OMAP2PLUS
 	default y
 	help
 	  Support GPIO controllers on the TI OMAP3/4/5 and related (such as
 	  AM335x/AM43xx/AM57xx/DRA7xx/etc) families of SoCs.
 config CMD_PCA953X
 	bool "Enable the pca953x command"
 	help
 	  Deprecated: This should be converted to driver model.
 	  This command provides access to a pca953x GPIO device using the
 	  legacy GPIO interface. Several subcommands are provided which mirror
 	  the standard 'gpio' command. It should use that instead.
 config PM8916_GPIO
 	bool "Qualcomm PM8916 PMIC GPIO/keypad driver"
 	depends on DM_GPIO && PMIC_PM8916
 	help
 	  Support for GPIO pins and power/reset buttons found on
 	  Qualcomm PM8916 PMIC.
 	  Default name for GPIO bank is "pm8916".
 	  Power and reset buttons are placed in "pm8916_key" bank and
           have gpio numbers 0 and 1 respectively.
 config PCF8575_GPIO
 	bool "PCF8575 I2C GPIO Expander driver"
 	depends on DM_GPIO && DM_I2C
 	help
 	 Support for PCF8575 I2C 16-bit GPIO expander. Most of these
 	 chips are from NXP and TI.
 config RCAR_GPIO
 	bool "Renesas RCar GPIO driver"
 	depends on DM_GPIO && ARCH_RMOBILE
 	help
 	  This driver supports the GPIO banks on Renesas RCar SoCs.
 config ROCKCHIP_GPIO
 	bool "Rockchip GPIO driver"
 	depends on DM_GPIO
 	help
 	  Support GPIO access on Rockchip SoCs. The GPIOs are arranged into
 	  a number of banks (different for each SoC type) each with 32 GPIOs.
 	  The GPIOs for a device are defined in the device tree with one node
 	  for each bank.
 config SANDBOX_GPIO
 	bool "Enable sandbox GPIO driver"
 	depends on SANDBOX && DM && DM_GPIO
 	help
 	  This driver supports some simulated GPIOs which can be adjusted
 	  using 'back door' functions like sandbox_gpio_set_value(). Then the
 	  GPIOs can be inspected through the normal get_get_value()
 	  interface. The purpose of this is to allow GPIOs to be used as
 	  normal in sandbox, perhaps with test code actually driving the
 	  behaviour of those GPIOs.
 config SANDBOX_GPIO_COUNT
 	int "Number of sandbox GPIOs"
 	depends on SANDBOX_GPIO
 	default 128
 	help
 	  The sandbox driver can support any number of GPIOs. Generally these
 	  are specified using the device tree. But you can also have a number
 	  of 'anonymous' GPIOs that do not belong to any device or bank.
 	  Select a suitable value depending on your needs.
 config XILINX_GPIO
 	bool "Xilinx GPIO driver"
 	depends on DM_GPIO
 	help
 	  This config enable the Xilinx GPIO driver for Microblaze.
 config CMD_TCA642X
 	bool "tca642x - Command to access tca642x state"
 	help
 	  DEPRECATED - This needs conversion to driver model
 	  This provides a way to looking at the pin state of this device.
 	  This mirrors the 'gpio' command and that should be used in preference
 	  to custom code.
 config TEGRA_GPIO
 	bool "Tegra20..210 GPIO driver"
 	depends on DM_GPIO
 	help
 	  Support for the GPIO controller contained in NVIDIA Tegra20 through
 	  Tegra210.
 config TEGRA186_GPIO
 	bool "Tegra186 GPIO driver"
 	depends on DM_GPIO
 	help
 	  Support for the GPIO controller contained in NVIDIA Tegra186. This
 	  covers both the "main" and "AON" controller instances, even though
 	  they have slightly different register layout.
 config GPIO_UNIPHIER
 	bool "UniPhier GPIO"
 	depends on ARCH_UNIPHIER
 	help
 	  Say yes here to support UniPhier GPIOs.
 config VYBRID_GPIO
 	bool "Vybrid GPIO driver"
 	depends on DM
 	default n
 	help
 	  Say yes here to support Vybrid vf610 GPIOs.
 config PIC32_GPIO
 	bool "Microchip PIC32 GPIO driver"
 	depends on DM_GPIO && MACH_PIC32
 	default y
 	help
 	  Say yes here to support Microchip PIC32 GPIOs.
 config STM32F7_GPIO
 	bool "ST STM32 GPIO driver"
 	depends on DM_GPIO && (STM32 || ARCH_STM32MP)
 	default y
 	help
 	  Device model driver support for STM32 GPIO controller. It should be
 	  usable on many stm32 families like stm32f4 & stm32H7.
 	  Tested on STM32F7.
 config MVEBU_GPIO
 	bool "Marvell MVEBU GPIO driver"
 	depends on DM_GPIO && ARCH_MVEBU
 	default y
 	help
 	  Say yes here to support Marvell MVEBU (Armada XP/38x) GPIOs.
 config ZYNQ_GPIO
 	bool "Zynq GPIO driver"
 	depends on DM_GPIO && (ARCH_ZYNQ || ARCH_ZYNQMP)
 	default y
 	help
 	  Supports GPIO access on Zynq SoC.
 config DM_74X164
 	bool "74x164 serial-in/parallel-out 8-bits shift register"
 	depends on DM_GPIO
 	help
 	  Driver for 74x164 compatible serial-in/parallel-out 8-outputs
 	  shift registers, such as 74lv165, 74hc595.
 	  This driver can be used to provide access to more gpio outputs.
 config DM_PCA953X
 	bool "PCA95[357]x, PCA9698, TCA64xx, and MAX7310 I/O ports"
 	depends on DM_GPIO
 	help
 	  Say yes here to provide access to several register-oriented
 	  SMBus I/O expanders, made mostly by NXP or TI.  Compatible
 	  models include:
 	  4 bits:	pca9536, pca9537
 	  8 bits:	max7310, max7315, pca6107, pca9534, pca9538, pca9554,
 			pca9556, pca9557, pca9574, tca6408, xra1202
 	  16 bits:	max7312, max7313, pca9535, pca9539, pca9555, pca9575,
 			tca6416
 	  24 bits:	tca6424
 	  40 bits:	pca9505, pca9698
 	  Now, max 24 bits chips and PCA953X compatible chips are
 	  supported
 config MPC8XXX_GPIO
 	bool "Freescale MPC8XXX GPIO driver"
 	depends on DM_GPIO
 	help
 	  This driver supports the built-in GPIO controller of MPC8XXX CPUs.
 	  Each GPIO bank is identified by its own entry in the device tree,
 	  i.e.
 	  gpio-controller@fc00 {
 		#gpio-cells = <2>;
 		compatible = "fsl,pq3-gpio";
 		reg = <0xfc00 0x100>
 	  }
 	  By default, each bank is assumed to have 32 GPIOs, but the ngpios
 	  setting is honored, so the number of GPIOs for each bank is
 	  configurable to match the actual GPIO count of the SoC (e.g. the
 	  32/32/23 banks of the P1022 SoC).
 	  Aside from the standard functions of input/output mode, and output
 	  value setting, the open-drain feature, which can configure individual
 	  GPIOs to work as open-drain outputs, is supported.
 config MT7621_GPIO
 	bool "MediaTek MT7621 GPIO driver"
 	depends on DM_GPIO && ARCH_MT7620
 	default y
 	help
 	  Say yes here to support MediaTek MT7621 compatible GPIOs.
 endmenu

drivers/gpio/Makefile

Diff comments View file @ f83ef0d

drivers/gpio/gpio-mscc-bitbang-spi.c

View file @ f83ef0d

1	// SPDX-License-Identifier: (GPL-2.0 OR MIT)		File was deleted
2	/*
3	* Microsemi SoCs pinctrl driver
4	*
5	* Author: <gregory.clement@bootlin.com>
6	* License: Dual MIT/GPL
7	* Copyright (c) 2018 Microsemi Corporation
8	*/
9
10	#include <common.h>
11	#include <asm-generic/gpio.h>
12	#include <asm/io.h>
13	#include <dm.h>
14	#include <errno.h>
15
16	enum {
17	SDI,
18	CS0,
19	CS1,
20	CS2,
21	CS3,
22	SDO,
23	SCK
24	};
25
26	static const int pinmap[] = { 0, 5, 6, 7, 8, 10, 12 };
27
28	#define SW_SPI_CSn_OE 0x1E /* bits 1 to 4 */
29	#define SW_SPI_CS0_OE BIT(1)
30	#define SW_SPI_SDO_OE BIT(9)
31	#define SW_SPI_SCK_OE BIT(11)
32	#define SW_PIN_CTRL_MODE BIT(13)
33
34	struct mscc_bb_spi_gpio {
35	void __iomem *regs;
36	u32 cache_val;
37	};
38
39	static int mscc_bb_spi_gpio_set(struct udevice *dev, unsigned oft, int val)
40	{
41	struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
42
43	if (val)
44	gpio->cache_val \|= BIT(pinmap[oft]);
45	else
46	gpio->cache_val &= ~BIT(pinmap[oft]);
47
48	writel(gpio->cache_val, gpio->regs);
49
50	return 0;
51	}
52
53	static int mscc_bb_spi_gpio_direction_output(struct udevice *dev, unsigned oft,
54	int val)
55	{
56	if (oft == 0) {
57	pr_err("SW_SPI_DSI can't be used as output\n");
58	return -ENOTSUPP;
59	}
60
61	mscc_bb_spi_gpio_set(dev, oft, val);
62
63	return 0;
64	}
65
66	static int mscc_bb_spi_gpio_direction_input(struct udevice *dev, unsigned oft)
67	{
68	return 0;
69	}
70
71	static int mscc_bb_spi_gpio_get(struct udevice *dev, unsigned int oft)
72	{
73	struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
74	u32 val = readl(gpio->regs);
75
76	return !!(val & BIT(pinmap[oft]));
77	}
78
79	static const struct dm_gpio_ops mscc_bb_spi_gpio_ops = {
80	.direction_output = mscc_bb_spi_gpio_direction_output,
81	.direction_input = mscc_bb_spi_gpio_direction_input,
82	.set_value = mscc_bb_spi_gpio_set,
83	.get_value = mscc_bb_spi_gpio_get,
84	};
85
86	static int mscc_bb_spi_gpio_probe(struct udevice *dev)
87	{
88	struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
89	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
90
91	gpio->regs = dev_remap_addr(dev);
92	if (!gpio->regs)
93	return -EINVAL;
94
95	uc_priv->bank_name = dev->name;
96	uc_priv->gpio_count = ARRAY_SIZE(pinmap);
97	/*
98	* Enable software mode to control the SPI pin, enables the
99	* output mode for most of the pin and initialize the cache
100	* value in the same time
101	*/
102
103	gpio->cache_val = SW_PIN_CTRL_MODE \| SW_SPI_SCK_OE \| SW_SPI_SDO_OE \|
104	SW_SPI_CS0_OE;
105	writel(gpio->cache_val, gpio->regs);
106
107	return 0;
108	}
109
110	static const struct udevice_id mscc_bb_spi_gpio_ids[] = {
111	{.compatible = "mscc,spi-bitbang-gpio"},
112	{}
113	};
114
115	U_BOOT_DRIVER(gpio_mscc_bb_spi) = {
116	.name = "gpio-mscc-spi-bitbang",
117	.id = UCLASS_GPIO,
118	.ops = &mscc_bb_spi_gpio_ops,
119	.probe = mscc_bb_spi_gpio_probe,
120	.of_match = of_match_ptr(mscc_bb_spi_gpio_ids),
121	.priv_auto_alloc_size = sizeof(struct mscc_bb_spi_gpio),
122	};
123		1	// SPDX-License-Identifier: (GPL-2.0 OR MIT)

drivers/gpio/mscc_sgpio.c

Diff comments View file @ f83ef0d

File was created	1	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	2	/*
	3	* Microsemi SoCs serial gpio driver
	4	*
	5	* Author: <lars.povlsen@microchip.com>
	6	*
	7	* Copyright (c) 2018 Microsemi Corporation
	8	*/
	9
	10	#include <common.h>
	11	#include <dm.h>
	12	#include <asm/gpio.h>
	13	#include <asm/io.h>
	14	#include <errno.h>
	15	#include <clk.h>
	16
	17	#define MSCC_SGPIOS_PER_BANK 32
	18	#define MSCC_SGPIO_BANK_DEPTH 4
	19
	20	enum {
	21	REG_INPUT_DATA,
	22	REG_PORT_CONFIG,
	23	REG_PORT_ENABLE,
	24	REG_SIO_CONFIG,
	25	REG_SIO_CLOCK,
	26	MAXREG
	27	};
	28
	29	struct mscc_sgpio_bf {
	30	u8 beg;
	31	u8 end;
	32	};
	33
	34	struct mscc_sgpio_props {
	35	u8 regoff[MAXREG];
	36	struct mscc_sgpio_bf auto_repeat;
	37	struct mscc_sgpio_bf port_width;
	38	struct mscc_sgpio_bf clk_freq;
	39	struct mscc_sgpio_bf bit_source;
	40	};
	41
	42	#define __M(bf) GENMASK((bf).end, (bf).beg)
	43	#define __F(bf, x) (__M(bf) & ((x) << (bf).beg))
	44	#define __X(bf, x) (((x) >> (bf).beg) & GENMASK(((bf).end - (bf).beg), 0))
	45
	46	#define MSCC_M_CFG_SIO_AUTO_REPEAT(p) BIT(p->props->auto_repeat.beg)
	47	#define MSCC_F_CFG_SIO_PORT_WIDTH(p, x) __F(p->props->port_width, x)
	48	#define MSCC_M_CFG_SIO_PORT_WIDTH(p) __M(p->props->port_width)
	49	#define MSCC_F_CLOCK_SIO_CLK_FREQ(p, x) __F(p->props->clk_freq, x)
	50	#define MSCC_M_CLOCK_SIO_CLK_FREQ(p) __M(p->props->clk_freq)
	51	#define MSCC_F_PORT_CFG_BIT_SOURCE(p, x) __F(p->props->bit_source, x)
	52	#define MSCC_X_PORT_CFG_BIT_SOURCE(p, x) __X(p->props->bit_source, x)
	53
	54	const struct mscc_sgpio_props props_luton = {
	55	.regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b },
	56	.auto_repeat = { 5, 5 },
	57	.port_width = { 2, 3 },
	58	.clk_freq = { 0, 11 },
	59	.bit_source = { 0, 11 },
	60	};
	61
	62	const struct mscc_sgpio_props props_ocelot = {
	63	.regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 },
	64	.auto_repeat = { 10, 10 },
	65	.port_width = { 7, 8 },
	66	.clk_freq = { 8, 19 },
	67	.bit_source = { 12, 23 },
	68	};
	69
	70	struct mscc_sgpio_priv {
	71	u32 bitcount;
	72	u32 ports;
	73	u32 clock;
	74	u32 mode[MSCC_SGPIOS_PER_BANK];
	75	u32 __iomem *regs;
	76	const struct mscc_sgpio_props *props;
	77	};
	78
	79	static inline u32 sgpio_readl(struct mscc_sgpio_priv *priv, u32 rno, u32 off)
	80	{
	81	u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
	82
	83	return readl(reg);
	84	}
	85
	86	static inline void sgpio_writel(struct mscc_sgpio_priv *priv,
	87	u32 val, u32 rno, u32 off)
	88	{
	89	u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
	90
	91	writel(val, reg);
	92	}
	93
	94	static void sgpio_clrsetbits(struct mscc_sgpio_priv *priv,
	95	u32 rno, u32 off, u32 clear, u32 set)
	96	{
	97	u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
	98
	99	clrsetbits_le32(reg, clear, set);
	100	}
	101
	102	static int mscc_sgpio_direction_input(struct udevice *dev, unsigned int gpio)
	103	{
	104	struct mscc_sgpio_priv *priv = dev_get_priv(dev);
	105
	106	u32 port = gpio % MSCC_SGPIOS_PER_BANK;
	107	u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
	108
	109	priv->mode[port] \|= BIT(bit);
	110
	111	return 0;
	112	}
	113
	114	static int mscc_sgpio_direction_output(struct udevice *dev,
	115	unsigned int gpio, int value)
	116	{
	117	struct mscc_sgpio_priv *priv = dev_get_priv(dev);
	118	u32 port = gpio % MSCC_SGPIOS_PER_BANK;
	119	u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
	120	u32 mask = 3 << (3 * bit);
	121
	122	debug("set: port %d, bit %d, mask 0x%08x, value %d\n",
	123	port, bit, mask, value);
	124
	125	value = (value & 3) << (3 * bit);
	126	sgpio_clrsetbits(priv, REG_PORT_CONFIG, port,
	127	MSCC_F_PORT_CFG_BIT_SOURCE(priv, mask),
	128	MSCC_F_PORT_CFG_BIT_SOURCE(priv, value));
	129	clrbits_le32(&priv->mode[port], BIT(bit));
	130
	131	return 0;
	132	}
	133
	134	static int mscc_sgpio_get_function(struct udevice *dev, unsigned int gpio)
	135	{
	136	struct mscc_sgpio_priv *priv = dev_get_priv(dev);
	137	u32 port = gpio % MSCC_SGPIOS_PER_BANK;
	138	u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
	139	u32 val = priv->mode[port] & BIT(bit);
	140
	141	if (val)
	142	return GPIOF_INPUT;
	143	else
	144	return GPIOF_OUTPUT;
	145	}
	146
	147	static int mscc_sgpio_set_value(struct udevice *dev,
	148	unsigned int gpio, int value)
	149	{
	150	return mscc_sgpio_direction_output(dev, gpio, value);
	151	}
	152
	153	static int mscc_sgpio_get_value(struct udevice *dev, unsigned int gpio)
	154	{
	155	struct mscc_sgpio_priv *priv = dev_get_priv(dev);
	156	u32 port = gpio % MSCC_SGPIOS_PER_BANK;
	157	u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
	158	int ret;
	159
	160	if (mscc_sgpio_get_function(dev, gpio) == GPIOF_INPUT) {
	161	ret = !!(sgpio_readl(priv, REG_INPUT_DATA, bit) & BIT(port));
	162	} else {
	163	u32 portval = sgpio_readl(priv, REG_PORT_CONFIG, port);
	164
	165	ret = MSCC_X_PORT_CFG_BIT_SOURCE(priv, portval);
	166	ret = !!(ret & (3 << (3 * bit)));
	167	}
	168
	169	debug("get: gpio %d, port %d, bit %d, value %d\n",
	170	gpio, port, bit, ret);
	171	return ret;
	172	}
	173
	174	static int mscc_sgpio_get_count(struct udevice *dev)
	175	{
	176	struct ofnode_phandle_args args;
	177	int count = 0, i = 0, ret;
	178
	179	ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3, i, &args);
	180	while (ret != -ENOENT) {
	181	count += args.args[2];
	182	ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
	183	++i, &args);
	184	}
	185	return count;
	186	}
	187
	188	static int mscc_sgpio_probe(struct udevice *dev)
	189	{
	190	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	191	struct mscc_sgpio_priv *priv = dev_get_priv(dev);
	192	int err, div_clock = 0, port;
	193	u32 val;
	194	struct clk clk;
	195
	196	err = clk_get_by_index(dev, 0, &clk);
	197	if (!err) {
	198	err = clk_get_rate(&clk);
	199	if (IS_ERR_VALUE(err)) {
	200	dev_err(dev, "Invalid clk rate\n");
	201	return -EINVAL;
	202	}
	203	div_clock = err;
	204	} else {
	205	dev_err(dev, "Failed to get clock\n");
	206	return err;
	207	}
	208
	209	priv->props = (const struct mscc_sgpio_props *)dev_get_driver_data(dev);
	210	priv->ports = dev_read_u32_default(dev, "mscc,sgpio-ports", 0xFFFFFFFF);
	211	priv->clock = dev_read_u32_default(dev, "mscc,sgpio-frequency",
	212	12500000);
	213	if (priv->clock <= 0 \|\| priv->clock > div_clock) {
	214	dev_err(dev, "Invalid frequency %d\n", priv->clock);
	215	return -EINVAL;
	216	}
	217
	218	uc_priv->gpio_count = mscc_sgpio_get_count(dev);
	219	uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios",
	220	uc_priv->gpio_count);
	221	if (uc_priv->gpio_count < 1 \|\| uc_priv->gpio_count >
	222	(4 * MSCC_SGPIOS_PER_BANK)) {
	223	dev_err(dev, "Invalid gpio count %d\n", uc_priv->gpio_count);
	224	return -EINVAL;
	225	}
	226	priv->bitcount = DIV_ROUND_UP(uc_priv->gpio_count,
	227	MSCC_SGPIOS_PER_BANK);
	228	debug("probe: gpios = %d, bit-count = %d\n",
	229	uc_priv->gpio_count, priv->bitcount);
	230
	231	priv->regs = (u32 __iomem *)dev_read_addr(dev);
	232	uc_priv->bank_name = "sgpio";
	233
	234	sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0,
	235	MSCC_M_CFG_SIO_PORT_WIDTH(priv),
	236	MSCC_F_CFG_SIO_PORT_WIDTH(priv, priv->bitcount - 1) \|
	237	MSCC_M_CFG_SIO_AUTO_REPEAT(priv));
	238	val = div_clock / priv->clock;
	239	debug("probe: div-clock = %d KHz, freq = %d KHz, div = %d\n",
	240	div_clock / 1000, priv->clock / 1000, val);
	241	sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0,
	242	MSCC_M_CLOCK_SIO_CLK_FREQ(priv),
	243	MSCC_F_CLOCK_SIO_CLK_FREQ(priv, val));
	244
	245	for (port = 0; port < 32; port++)
	246	sgpio_writel(priv, 0, REG_PORT_CONFIG, port);
	247	sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0);
	248
	249	debug("probe: sgpio regs = %p\n", priv->regs);
	250
	251	return 0;
	252	}
	253
	254	static const struct dm_gpio_ops mscc_sgpio_ops = {
	255	.direction_input = mscc_sgpio_direction_input,
	256	.direction_output = mscc_sgpio_direction_output,
	257	.get_function = mscc_sgpio_get_function,
	258	.get_value = mscc_sgpio_get_value,
	259	.set_value = mscc_sgpio_set_value,
	260	};
	261
	262	static const struct udevice_id mscc_sgpio_ids[] = {
	263	{ .compatible = "mscc,luton-sgpio", .data = (ulong)&props_luton },
	264	{ .compatible = "mscc,ocelot-sgpio", .data = (ulong)&props_ocelot },
	265	{ }
	266	};
	267
	268	U_BOOT_DRIVER(gpio_mscc_sgpio) = {
	269	.name = "mscc-sgpio",
	270	.id = UCLASS_GPIO,
	271	.of_match = mscc_sgpio_ids,
	272	.ops = &mscc_sgpio_ops,
	273	.probe = mscc_sgpio_probe,
	274	.priv_auto_alloc_size = sizeof(struct mscc_sgpio_priv),
	275	};
	276

drivers/mmc/jz_mmc.c

Diff comments View file @ f83ef0d

1	// SPDX-License-Identifier: GPL-2.0+	1	// SPDX-License-Identifier: GPL-2.0+
2	/*	2	/*
3	* Ingenic JZ MMC driver	3	* Ingenic JZ MMC driver
4	*	4	*
5	* Copyright (c) 2013 Imagination Technologies	5	* Copyright (c) 2013 Imagination Technologies
6	* Author: Paul Burton <paul.burton@imgtec.com>	6	* Author: Paul Burton <paul.burton@imgtec.com>
7	*/	7	*/
8		8
9	#include <common.h>	9	#include <common.h>
10	#include <malloc.h>	10	#include <malloc.h>
11	#include <mmc.h>	11	#include <mmc.h>
12	#include <asm/io.h>	12	#include <asm/io.h>
13	#include <asm/unaligned.h>	13	#include <asm/unaligned.h>
14	#include <errno.h>	14	#include <errno.h>
15	#include <mach/jz4780.h>	15	#include <mach/jz4780.h>
16	#include <wait_bit.h>	16	#include <wait_bit.h>
17		17
18	/* Registers */	18	/* Registers */
19	#define MSC_STRPCL 0x000	19	#define MSC_STRPCL 0x000
20	#define MSC_STAT 0x004	20	#define MSC_STAT 0x004
21	#define MSC_CLKRT 0x008	21	#define MSC_CLKRT 0x008
22	#define MSC_CMDAT 0x00c	22	#define MSC_CMDAT 0x00c
23	#define MSC_RESTO 0x010	23	#define MSC_RESTO 0x010
24	#define MSC_RDTO 0x014	24	#define MSC_RDTO 0x014
25	#define MSC_BLKLEN 0x018	25	#define MSC_BLKLEN 0x018
26	#define MSC_NOB 0x01c	26	#define MSC_NOB 0x01c
27	#define MSC_SNOB 0x020	27	#define MSC_SNOB 0x020
28	#define MSC_IMASK 0x024	28	#define MSC_IMASK 0x024
29	#define MSC_IREG 0x028	29	#define MSC_IREG 0x028
30	#define MSC_CMD 0x02c	30	#define MSC_CMD 0x02c
31	#define MSC_ARG 0x030	31	#define MSC_ARG 0x030
32	#define MSC_RES 0x034	32	#define MSC_RES 0x034
33	#define MSC_RXFIFO 0x038	33	#define MSC_RXFIFO 0x038
34	#define MSC_TXFIFO 0x03c	34	#define MSC_TXFIFO 0x03c
35	#define MSC_LPM 0x040	35	#define MSC_LPM 0x040
36	#define MSC_DMAC 0x044	36	#define MSC_DMAC 0x044
37	#define MSC_DMANDA 0x048	37	#define MSC_DMANDA 0x048
38	#define MSC_DMADA 0x04c	38	#define MSC_DMADA 0x04c
39	#define MSC_DMALEN 0x050	39	#define MSC_DMALEN 0x050
40	#define MSC_DMACMD 0x054	40	#define MSC_DMACMD 0x054
41	#define MSC_CTRL2 0x058	41	#define MSC_CTRL2 0x058
42	#define MSC_RTCNT 0x05c	42	#define MSC_RTCNT 0x05c
43	#define MSC_DBG 0x0fc	43	#define MSC_DBG 0x0fc
44		44
45	/* MSC Clock and Control Register (MSC_STRPCL) */	45	/* MSC Clock and Control Register (MSC_STRPCL) */
46	#define MSC_STRPCL_EXIT_MULTIPLE BIT(7)	46	#define MSC_STRPCL_EXIT_MULTIPLE BIT(7)
47	#define MSC_STRPCL_EXIT_TRANSFER BIT(6)	47	#define MSC_STRPCL_EXIT_TRANSFER BIT(6)
48	#define MSC_STRPCL_START_READWAIT BIT(5)	48	#define MSC_STRPCL_START_READWAIT BIT(5)
49	#define MSC_STRPCL_STOP_READWAIT BIT(4)	49	#define MSC_STRPCL_STOP_READWAIT BIT(4)
50	#define MSC_STRPCL_RESET BIT(3)	50	#define MSC_STRPCL_RESET BIT(3)
51	#define MSC_STRPCL_START_OP BIT(2)	51	#define MSC_STRPCL_START_OP BIT(2)
52	#define MSC_STRPCL_CLOCK_CONTROL_STOP BIT(0)	52	#define MSC_STRPCL_CLOCK_CONTROL_STOP BIT(0)
53	#define MSC_STRPCL_CLOCK_CONTROL_START BIT(1)	53	#define MSC_STRPCL_CLOCK_CONTROL_START BIT(1)
54		54
55	/* MSC Status Register (MSC_STAT) */	55	/* MSC Status Register (MSC_STAT) */
56	#define MSC_STAT_AUTO_CMD_DONE BIT(31)	56	#define MSC_STAT_AUTO_CMD_DONE BIT(31)
57	#define MSC_STAT_IS_RESETTING BIT(15)	57	#define MSC_STAT_IS_RESETTING BIT(15)
58	#define MSC_STAT_SDIO_INT_ACTIVE BIT(14)	58	#define MSC_STAT_SDIO_INT_ACTIVE BIT(14)
59	#define MSC_STAT_PRG_DONE BIT(13)	59	#define MSC_STAT_PRG_DONE BIT(13)
60	#define MSC_STAT_DATA_TRAN_DONE BIT(12)	60	#define MSC_STAT_DATA_TRAN_DONE BIT(12)
61	#define MSC_STAT_END_CMD_RES BIT(11)	61	#define MSC_STAT_END_CMD_RES BIT(11)
62	#define MSC_STAT_DATA_FIFO_AFULL BIT(10)	62	#define MSC_STAT_DATA_FIFO_AFULL BIT(10)
63	#define MSC_STAT_IS_READWAIT BIT(9)	63	#define MSC_STAT_IS_READWAIT BIT(9)
64	#define MSC_STAT_CLK_EN BIT(8)	64	#define MSC_STAT_CLK_EN BIT(8)
65	#define MSC_STAT_DATA_FIFO_FULL BIT(7)	65	#define MSC_STAT_DATA_FIFO_FULL BIT(7)
66	#define MSC_STAT_DATA_FIFO_EMPTY BIT(6)	66	#define MSC_STAT_DATA_FIFO_EMPTY BIT(6)
67	#define MSC_STAT_CRC_RES_ERR BIT(5)	67	#define MSC_STAT_CRC_RES_ERR BIT(5)
68	#define MSC_STAT_CRC_READ_ERROR BIT(4)	68	#define MSC_STAT_CRC_READ_ERROR BIT(4)
69	#define MSC_STAT_CRC_WRITE_ERROR BIT(2)	69	#define MSC_STAT_CRC_WRITE_ERROR BIT(2)
70	#define MSC_STAT_CRC_WRITE_ERROR_NOSTS BIT(4)	70	#define MSC_STAT_CRC_WRITE_ERROR_NOSTS BIT(4)
71	#define MSC_STAT_TIME_OUT_RES BIT(1)	71	#define MSC_STAT_TIME_OUT_RES BIT(1)
72	#define MSC_STAT_TIME_OUT_READ BIT(0)	72	#define MSC_STAT_TIME_OUT_READ BIT(0)
73		73
74	/* MSC Bus Clock Control Register (MSC_CLKRT) */	74	/* MSC Bus Clock Control Register (MSC_CLKRT) */
75	#define MSC_CLKRT_CLK_RATE_MASK 0x7	75	#define MSC_CLKRT_CLK_RATE_MASK 0x7
76		76
77	/* MSC Command Sequence Control Register (MSC_CMDAT) */	77	/* MSC Command Sequence Control Register (MSC_CMDAT) */
78	#define MSC_CMDAT_IO_ABORT BIT(11)	78	#define MSC_CMDAT_IO_ABORT BIT(11)
79	#define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << 9)	79	#define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << 9)
80	#define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << 9)	80	#define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << 9)
81	#define MSC_CMDAT_DMA_EN BIT(8)	81	#define MSC_CMDAT_DMA_EN BIT(8)
82	#define MSC_CMDAT_INIT BIT(7)	82	#define MSC_CMDAT_INIT BIT(7)
83	#define MSC_CMDAT_BUSY BIT(6)	83	#define MSC_CMDAT_BUSY BIT(6)
84	#define MSC_CMDAT_STREAM_BLOCK BIT(5)	84	#define MSC_CMDAT_STREAM_BLOCK BIT(5)
85	#define MSC_CMDAT_WRITE BIT(4)	85	#define MSC_CMDAT_WRITE BIT(4)
86	#define MSC_CMDAT_DATA_EN BIT(3)	86	#define MSC_CMDAT_DATA_EN BIT(3)
87	#define MSC_CMDAT_RESPONSE_MASK (0x7 << 0)	87	#define MSC_CMDAT_RESPONSE_MASK (0x7 << 0)
88	#define MSC_CMDAT_RESPONSE_NONE (0x0 << 0) /* No response */	88	#define MSC_CMDAT_RESPONSE_NONE (0x0 << 0) /* No response */
89	#define MSC_CMDAT_RESPONSE_R1 (0x1 << 0) /* Format R1 and R1b */	89	#define MSC_CMDAT_RESPONSE_R1 (0x1 << 0) /* Format R1 and R1b */
90	#define MSC_CMDAT_RESPONSE_R2 (0x2 << 0) /* Format R2 */	90	#define MSC_CMDAT_RESPONSE_R2 (0x2 << 0) /* Format R2 */
91	#define MSC_CMDAT_RESPONSE_R3 (0x3 << 0) /* Format R3 */	91	#define MSC_CMDAT_RESPONSE_R3 (0x3 << 0) /* Format R3 */
92	#define MSC_CMDAT_RESPONSE_R4 (0x4 << 0) /* Format R4 */	92	#define MSC_CMDAT_RESPONSE_R4 (0x4 << 0) /* Format R4 */
93	#define MSC_CMDAT_RESPONSE_R5 (0x5 << 0) /* Format R5 */	93	#define MSC_CMDAT_RESPONSE_R5 (0x5 << 0) /* Format R5 */
94	#define MSC_CMDAT_RESPONSE_R6 (0x6 << 0) /* Format R6 */	94	#define MSC_CMDAT_RESPONSE_R6 (0x6 << 0) /* Format R6 */
95		95
96	/* MSC Interrupts Mask Register (MSC_IMASK) */	96	/* MSC Interrupts Mask Register (MSC_IMASK) */
97	#define MSC_IMASK_TIME_OUT_RES BIT(9)	97	#define MSC_IMASK_TIME_OUT_RES BIT(9)
98	#define MSC_IMASK_TIME_OUT_READ BIT(8)	98	#define MSC_IMASK_TIME_OUT_READ BIT(8)
99	#define MSC_IMASK_SDIO BIT(7)	99	#define MSC_IMASK_SDIO BIT(7)
100	#define MSC_IMASK_TXFIFO_WR_REQ BIT(6)	100	#define MSC_IMASK_TXFIFO_WR_REQ BIT(6)
101	#define MSC_IMASK_RXFIFO_RD_REQ BIT(5)	101	#define MSC_IMASK_RXFIFO_RD_REQ BIT(5)
102	#define MSC_IMASK_END_CMD_RES BIT(2)	102	#define MSC_IMASK_END_CMD_RES BIT(2)
103	#define MSC_IMASK_PRG_DONE BIT(1)	103	#define MSC_IMASK_PRG_DONE BIT(1)
104	#define MSC_IMASK_DATA_TRAN_DONE BIT(0)	104	#define MSC_IMASK_DATA_TRAN_DONE BIT(0)
105		105
106	/* MSC Interrupts Status Register (MSC_IREG) */	106	/* MSC Interrupts Status Register (MSC_IREG) */
107	#define MSC_IREG_TIME_OUT_RES BIT(9)	107	#define MSC_IREG_TIME_OUT_RES BIT(9)
108	#define MSC_IREG_TIME_OUT_READ BIT(8)	108	#define MSC_IREG_TIME_OUT_READ BIT(8)
109	#define MSC_IREG_SDIO BIT(7)	109	#define MSC_IREG_SDIO BIT(7)
110	#define MSC_IREG_TXFIFO_WR_REQ BIT(6)	110	#define MSC_IREG_TXFIFO_WR_REQ BIT(6)
111	#define MSC_IREG_RXFIFO_RD_REQ BIT(5)	111	#define MSC_IREG_RXFIFO_RD_REQ BIT(5)
112	#define MSC_IREG_END_CMD_RES BIT(2)	112	#define MSC_IREG_END_CMD_RES BIT(2)
113	#define MSC_IREG_PRG_DONE BIT(1)	113	#define MSC_IREG_PRG_DONE BIT(1)
114	#define MSC_IREG_DATA_TRAN_DONE BIT(0)	114	#define MSC_IREG_DATA_TRAN_DONE BIT(0)
115		115
116	struct jz_mmc_plat {	116	struct jz_mmc_plat {
117	struct mmc_config cfg;	117	struct mmc_config cfg;
118	struct mmc mmc;	118	struct mmc mmc;
119	};	119	};
120		120
121	struct jz_mmc_priv {	121	struct jz_mmc_priv {
122	void __iomem *regs;	122	void __iomem *regs;
123	u32 flags;	123	u32 flags;
124	/* priv flags */	124	/* priv flags */
125	#define JZ_MMC_BUS_WIDTH_MASK 0x3	125	#define JZ_MMC_BUS_WIDTH_MASK 0x3
126	#define JZ_MMC_BUS_WIDTH_1 0x0	126	#define JZ_MMC_BUS_WIDTH_1 0x0
127	#define JZ_MMC_BUS_WIDTH_4 0x2	127	#define JZ_MMC_BUS_WIDTH_4 0x2
128	#define JZ_MMC_BUS_WIDTH_8 0x3	128	#define JZ_MMC_BUS_WIDTH_8 0x3
129	#define JZ_MMC_SENT_INIT BIT(2)	129	#define JZ_MMC_SENT_INIT BIT(2)
130	};	130	};
131		131
132	static int jz_mmc_clock_rate(void)	132	static int jz_mmc_clock_rate(void)
133	{	133	{
134	return 24000000;	134	return 24000000;
135	}	135	}
136		136
		137	#if CONFIG_IS_ENABLED(MMC_WRITE)
		138	static inline void jz_mmc_write_data(struct jz_mmc_priv priv, struct mmc_data data)
		139	{
		140	int sz = DIV_ROUND_UP(data->blocks * data->blocksize, 4);
		141	const void *buf = data->src;
		142
		143	while (sz--) {
		144	u32 val = get_unaligned_le32(buf);
		145
		146	wait_for_bit_le32(priv->regs + MSC_IREG,
		147	MSC_IREG_TXFIFO_WR_REQ,
		148	true, 10000, false);
		149	writel(val, priv->regs + MSC_TXFIFO);
		150	buf += 4;
		151	}
		152	}
		153	#else
		154	static void jz_mmc_write_data(struct jz_mmc_priv priv, struct mmc_data data)
		155	{}
		156	#endif
		157
		158	static inline int jz_mmc_read_data(struct jz_mmc_priv priv, struct mmc_data data)
		159	{
		160	int sz = data->blocks * data->blocksize;
		161	void *buf = data->dest;
		162	u32 stat, val;
		163
		164	do {
		165	stat = readl(priv->regs + MSC_STAT);
		166
		167	if (stat & MSC_STAT_TIME_OUT_READ)
		168	return -ETIMEDOUT;
		169	if (stat & MSC_STAT_CRC_READ_ERROR)
		170	return -EINVAL;
		171	if (stat & MSC_STAT_DATA_FIFO_EMPTY) {
		172	udelay(10);
		173	continue;
		174	}
		175	do {
		176	val = readl(priv->regs + MSC_RXFIFO);
		177	if (sz == 1)
		178	(u8 )buf = (u8)val;
		179	else if (sz == 2)
		180	put_unaligned_le16(val, buf);
		181	else if (sz >= 4)
		182	put_unaligned_le32(val, buf);
		183	buf += 4;
		184	sz -= 4;
		185	stat = readl(priv->regs + MSC_STAT);
		186	} while (!(stat & MSC_STAT_DATA_FIFO_EMPTY));
		187	} while (!(stat & MSC_STAT_DATA_TRAN_DONE));
		188	return 0;
		189	}
		190
137	static int jz_mmc_send_cmd(struct mmc mmc, struct jz_mmc_priv priv,	191	static int jz_mmc_send_cmd(struct mmc mmc, struct jz_mmc_priv priv,
138	struct mmc_cmd cmd, struct mmc_data data)	192	struct mmc_cmd cmd, struct mmc_data data)
139	{	193	{
140	u32 stat, mask, cmdat = 0;	194	u32 stat, mask, cmdat = 0;
141	int i, ret;	195	int i, ret;
142		196
143	/* stop the clock */	197	/* stop the clock */
144	writel(MSC_STRPCL_CLOCK_CONTROL_STOP, priv->regs + MSC_STRPCL);	198	writel(MSC_STRPCL_CLOCK_CONTROL_STOP, priv->regs + MSC_STRPCL);
145	ret = wait_for_bit_le32(priv->regs + MSC_STAT,	199	ret = wait_for_bit_le32(priv->regs + MSC_STAT,
146	MSC_STAT_CLK_EN, false, 10000, false);	200	MSC_STAT_CLK_EN, false, 10000, false);
147	if (ret)	201	if (ret)
148	return ret;	202	return ret;
149		203
150	writel(0, priv->regs + MSC_DMAC);	204	writel(0, priv->regs + MSC_DMAC);
151		205
152	/* setup command */	206	/* setup command */
153	writel(cmd->cmdidx, priv->regs + MSC_CMD);	207	writel(cmd->cmdidx, priv->regs + MSC_CMD);
154	writel(cmd->cmdarg, priv->regs + MSC_ARG);	208	writel(cmd->cmdarg, priv->regs + MSC_ARG);
155		209
156	if (data) {	210	if (data) {
157	/* setup data */	211	/* setup data */
158	cmdat \|= MSC_CMDAT_DATA_EN;	212	cmdat \|= MSC_CMDAT_DATA_EN;
159	if (data->flags & MMC_DATA_WRITE)	213	if (data->flags & MMC_DATA_WRITE)
160	cmdat \|= MSC_CMDAT_WRITE;	214	cmdat \|= MSC_CMDAT_WRITE;
161		215
162	writel(data->blocks, priv->regs + MSC_NOB);	216	writel(data->blocks, priv->regs + MSC_NOB);
163	writel(data->blocksize, priv->regs + MSC_BLKLEN);	217	writel(data->blocksize, priv->regs + MSC_BLKLEN);
164	} else {	218	} else {
165	writel(0, priv->regs + MSC_NOB);	219	writel(0, priv->regs + MSC_NOB);
166	writel(0, priv->regs + MSC_BLKLEN);	220	writel(0, priv->regs + MSC_BLKLEN);
167	}	221	}
168		222
169	/* setup response */	223	/* setup response */
170	switch (cmd->resp_type) {	224	switch (cmd->resp_type) {
171	case MMC_RSP_NONE:	225	case MMC_RSP_NONE:
172	break;	226	break;
173	case MMC_RSP_R1:	227	case MMC_RSP_R1:
174	case MMC_RSP_R1b:	228	case MMC_RSP_R1b:
175	cmdat \|= MSC_CMDAT_RESPONSE_R1;	229	cmdat \|= MSC_CMDAT_RESPONSE_R1;
176	break;	230	break;
177	case MMC_RSP_R2:	231	case MMC_RSP_R2:
178	cmdat \|= MSC_CMDAT_RESPONSE_R2;	232	cmdat \|= MSC_CMDAT_RESPONSE_R2;
179	break;	233	break;
180	case MMC_RSP_R3:	234	case MMC_RSP_R3:
181	cmdat \|= MSC_CMDAT_RESPONSE_R3;	235	cmdat \|= MSC_CMDAT_RESPONSE_R3;
182	break;	236	break;
183	default:	237	default:
184	break;	238	break;
185	}	239	}
186		240
187	if (cmd->resp_type & MMC_RSP_BUSY)	241	if (cmd->resp_type & MMC_RSP_BUSY)
188	cmdat \|= MSC_CMDAT_BUSY;	242	cmdat \|= MSC_CMDAT_BUSY;
189		243
190	/* set init for the first command only */	244	/* set init for the first command only */
191	if (!(priv->flags & JZ_MMC_SENT_INIT)) {	245	if (!(priv->flags & JZ_MMC_SENT_INIT)) {
192	cmdat \|= MSC_CMDAT_INIT;	246	cmdat \|= MSC_CMDAT_INIT;
193	priv->flags \|= JZ_MMC_SENT_INIT;	247	priv->flags \|= JZ_MMC_SENT_INIT;
194	}	248	}
195		249
196	cmdat \|= (priv->flags & JZ_MMC_BUS_WIDTH_MASK) << 9;	250	cmdat \|= (priv->flags & JZ_MMC_BUS_WIDTH_MASK) << 9;
197		251
198	/* write the data setup */	252	/* write the data setup */
199	writel(cmdat, priv->regs + MSC_CMDAT);	253	writel(cmdat, priv->regs + MSC_CMDAT);
200		254
201	/* unmask interrupts */	255	/* unmask interrupts */
202	mask = 0xffffffff & ~(MSC_IMASK_END_CMD_RES \| MSC_IMASK_TIME_OUT_RES);	256	mask = 0xffffffff & ~(MSC_IMASK_END_CMD_RES \| MSC_IMASK_TIME_OUT_RES);
203	if (data) {	257	if (data) {
204	mask &= ~MSC_IMASK_DATA_TRAN_DONE;	258	mask &= ~MSC_IMASK_DATA_TRAN_DONE;
205	if (data->flags & MMC_DATA_WRITE) {	259	if (data->flags & MMC_DATA_WRITE) {
206	mask &= ~MSC_IMASK_TXFIFO_WR_REQ;	260	mask &= ~MSC_IMASK_TXFIFO_WR_REQ;
207	} else {	261	} else {
208	mask &= ~(MSC_IMASK_RXFIFO_RD_REQ \|	262	mask &= ~(MSC_IMASK_RXFIFO_RD_REQ \|
209	MSC_IMASK_TIME_OUT_READ);	263	MSC_IMASK_TIME_OUT_READ);
210	}	264	}
211	}	265	}
212	writel(mask, priv->regs + MSC_IMASK);	266	writel(mask, priv->regs + MSC_IMASK);
213		267
214	/* clear interrupts */	268	/* clear interrupts */
215	writel(0xffffffff, priv->regs + MSC_IREG);	269	writel(0xffffffff, priv->regs + MSC_IREG);
216		270
217	/* start the command (& the clock) */	271	/* start the command (& the clock) */
218	writel(MSC_STRPCL_START_OP \| MSC_STRPCL_CLOCK_CONTROL_START,	272	writel(MSC_STRPCL_START_OP \| MSC_STRPCL_CLOCK_CONTROL_START,
219	priv->regs + MSC_STRPCL);	273	priv->regs + MSC_STRPCL);
220		274
221	/* wait for completion */	275	/* wait for completion */
222	for (i = 0; i < 100; i++) {	276	for (i = 0; i < 100; i++) {
223	stat = readl(priv->regs + MSC_IREG);	277	stat = readl(priv->regs + MSC_IREG);
224	stat &= MSC_IREG_END_CMD_RES \| MSC_IREG_TIME_OUT_RES;	278	stat &= MSC_IREG_END_CMD_RES \| MSC_IREG_TIME_OUT_RES;
225	if (stat)	279	if (stat)
226	break;	280	break;
227	mdelay(1);	281	mdelay(1);
228	}	282	}
229	writel(stat, priv->regs + MSC_IREG);	283	writel(stat, priv->regs + MSC_IREG);
230	if (stat & MSC_IREG_TIME_OUT_RES)	284	if (stat & MSC_IREG_TIME_OUT_RES)
231	return -ETIMEDOUT;	285	return -ETIMEDOUT;
232		286
233	if (cmd->resp_type & MMC_RSP_PRESENT) {	287	if (cmd->resp_type & MMC_RSP_PRESENT) {
234	/* read the response */	288	/* read the response */
235	if (cmd->resp_type & MMC_RSP_136) {	289	if (cmd->resp_type & MMC_RSP_136) {
236	u16 a, b, c, i;	290	u16 a, b, c, i;
237		291
238	a = readw(priv->regs + MSC_RES);	292	a = readw(priv->regs + MSC_RES);
239	for (i = 0; i < 4; i++) {	293	for (i = 0; i < 4; i++) {
240	b = readw(priv->regs + MSC_RES);	294	b = readw(priv->regs + MSC_RES);
241	c = readw(priv->regs + MSC_RES);	295	c = readw(priv->regs + MSC_RES);
242	cmd->response[i] =	296	cmd->response[i] =
243	(a << 24) \| (b << 8) \| (c >> 8);	297	(a << 24) \| (b << 8) \| (c >> 8);
244	a = c;	298	a = c;
245	}	299	}
246	} else {	300	} else {
247	cmd->response[0] = readw(priv->regs + MSC_RES) << 24;	301	cmd->response[0] = readw(priv->regs + MSC_RES) << 24;
248	cmd->response[0] \|= readw(priv->regs + MSC_RES) << 8;	302	cmd->response[0] \|= readw(priv->regs + MSC_RES) << 8;
249	cmd->response[0] \|= readw(priv->regs + MSC_RES) & 0xff;	303	cmd->response[0] \|= readw(priv->regs + MSC_RES) & 0xff;
250	}	304	}
251	}	305	}
252		306	if (data) {
253	if (data && (data->flags & MMC_DATA_WRITE)) {	307	if (data->flags & MMC_DATA_WRITE)
254	/* write the data */	308	jz_mmc_write_data(priv, data);
255	int sz = DIV_ROUND_UP(data->blocks * data->blocksize, 4);	309	else if (data->flags & MMC_DATA_READ) {
256	const void *buf = data->src;	310	ret = jz_mmc_read_data(priv, data);
257		311	if (ret)
258	while (sz--) {	312	return ret;
259	u32 val = get_unaligned_le32(buf);
260
261	wait_for_bit_le32(priv->regs + MSC_IREG,
262	MSC_IREG_TXFIFO_WR_REQ,
263	true, 10000, false);
264	writel(val, priv->regs + MSC_TXFIFO);
265	buf += 4;
266	}	313	}
267	} else if (data && (data->flags & MMC_DATA_READ)) {
268	/* read the data */
269	int sz = data->blocks * data->blocksize;
270	void *buf = data->dest;
271
272	do {
273	stat = readl(priv->regs + MSC_STAT);
274
275	if (stat & MSC_STAT_TIME_OUT_READ)
276	return -ETIMEDOUT;
277	if (stat & MSC_STAT_CRC_READ_ERROR)
278	return -EINVAL;
279	if (stat & MSC_STAT_DATA_FIFO_EMPTY) {
280	udelay(10);
281	continue;
282	}
283	do {
284	u32 val = readl(priv->regs + MSC_RXFIFO);
285
286	if (sz == 1)
287	(u8 )buf = (u8)val;
288	else if (sz == 2)
289	put_unaligned_le16(val, buf);
290	else if (sz >= 4)
291	put_unaligned_le32(val, buf);
292	buf += 4;
293	sz -= 4;
294	stat = readl(priv->regs + MSC_STAT);
295	} while (!(stat & MSC_STAT_DATA_FIFO_EMPTY));
296	} while (!(stat & MSC_STAT_DATA_TRAN_DONE));
297	}	314	}
298		315
299	return 0;	316	return 0;
300	}	317	}
301		318
302	static int jz_mmc_set_ios(struct mmc mmc, struct jz_mmc_priv priv)	319	static int jz_mmc_set_ios(struct mmc mmc, struct jz_mmc_priv priv)
303	{	320	{
304	u32 real_rate = jz_mmc_clock_rate();	321	u32 real_rate = jz_mmc_clock_rate();
305	u8 clk_div = 0;	322	u8 clk_div = 0;
306		323
307	/* calculate clock divide */	324	/* calculate clock divide */
308	while ((real_rate > mmc->clock) && (clk_div < 7)) {	325	while ((real_rate > mmc->clock) && (clk_div < 7)) {
309	real_rate >>= 1;	326	real_rate >>= 1;
310	clk_div++;	327	clk_div++;
311	}	328	}
312	writel(clk_div & MSC_CLKRT_CLK_RATE_MASK, priv->regs + MSC_CLKRT);	329	writel(clk_div & MSC_CLKRT_CLK_RATE_MASK, priv->regs + MSC_CLKRT);
313		330
314	/* set the bus width for the next command */	331	/* set the bus width for the next command */
315	priv->flags &= ~JZ_MMC_BUS_WIDTH_MASK;	332	priv->flags &= ~JZ_MMC_BUS_WIDTH_MASK;
316	if (mmc->bus_width == 8)	333	if (mmc->bus_width == 8)
317	priv->flags \|= JZ_MMC_BUS_WIDTH_8;	334	priv->flags \|= JZ_MMC_BUS_WIDTH_8;
318	else if (mmc->bus_width == 4)	335	else if (mmc->bus_width == 4)
319	priv->flags \|= JZ_MMC_BUS_WIDTH_4;	336	priv->flags \|= JZ_MMC_BUS_WIDTH_4;
320	else	337	else
321	priv->flags \|= JZ_MMC_BUS_WIDTH_1;	338	priv->flags \|= JZ_MMC_BUS_WIDTH_1;
322		339
323	return 0;	340	return 0;
324	}	341	}
325		342
326	static int jz_mmc_core_init(struct mmc *mmc)	343	static int jz_mmc_core_init(struct mmc *mmc)
327	{	344	{
328	struct jz_mmc_priv *priv = mmc->priv;	345	struct jz_mmc_priv *priv = mmc->priv;
329	int ret;	346	int ret;
330		347
331	/* Reset */	348	/* Reset */
332	writel(MSC_STRPCL_RESET, priv->regs + MSC_STRPCL);	349	writel(MSC_STRPCL_RESET, priv->regs + MSC_STRPCL);
333	ret = wait_for_bit_le32(priv->regs + MSC_STAT,	350	ret = wait_for_bit_le32(priv->regs + MSC_STAT,
334	MSC_STAT_IS_RESETTING, false, 10000, false);	351	MSC_STAT_IS_RESETTING, false, 10000, false);
335	if (ret)	352	if (ret)
336	return ret;	353	return ret;
337		354
338	/* Maximum timeouts */	355	/* Maximum timeouts */
339	writel(0xffff, priv->regs + MSC_RESTO);	356	writel(0xffff, priv->regs + MSC_RESTO);
340	writel(0xffffffff, priv->regs + MSC_RDTO);	357	writel(0xffffffff, priv->regs + MSC_RDTO);
341		358
342	/* Enable low power mode */	359	/* Enable low power mode */
343	writel(0x1, priv->regs + MSC_LPM);	360	writel(0x1, priv->regs + MSC_LPM);
344		361
345	return 0;	362	return 0;
346	}	363	}
347		364
348	#if !CONFIG_IS_ENABLED(DM_MMC)	365	#if !CONFIG_IS_ENABLED(DM_MMC)
349		366
350	static int jz_mmc_legacy_send_cmd(struct mmc mmc, struct mmc_cmd cmd,	367	static int jz_mmc_legacy_send_cmd(struct mmc mmc, struct mmc_cmd cmd,
351	struct mmc_data *data)	368	struct mmc_data *data)
352	{	369	{
353	struct jz_mmc_priv *priv = mmc->priv;	370	struct jz_mmc_priv *priv = mmc->priv;
354		371
355	return jz_mmc_send_cmd(mmc, priv, cmd, data);	372	return jz_mmc_send_cmd(mmc, priv, cmd, data);
356	}	373	}
357		374
358	static int jz_mmc_legacy_set_ios(struct mmc *mmc)	375	static int jz_mmc_legacy_set_ios(struct mmc *mmc)
359	{	376	{
360	struct jz_mmc_priv *priv = mmc->priv;	377	struct jz_mmc_priv *priv = mmc->priv;
361		378
362	return jz_mmc_set_ios(mmc, priv);	379	return jz_mmc_set_ios(mmc, priv);
363	};	380	};
364		381
365	static const struct mmc_ops jz_msc_ops = {	382	static const struct mmc_ops jz_msc_ops = {
366	.send_cmd = jz_mmc_legacy_send_cmd,	383	.send_cmd = jz_mmc_legacy_send_cmd,
367	.set_ios = jz_mmc_legacy_set_ios,	384	.set_ios = jz_mmc_legacy_set_ios,
368	.init = jz_mmc_core_init,	385	.init = jz_mmc_core_init,
369	};	386	};
370		387
371	static struct jz_mmc_priv jz_mmc_priv_static;	388	static struct jz_mmc_priv jz_mmc_priv_static;
372	static struct jz_mmc_plat jz_mmc_plat_static = {	389	static struct jz_mmc_plat jz_mmc_plat_static = {
373	.cfg = {	390	.cfg = {
374	.name = "MSC",	391	.name = "MSC",
375	.ops = &jz_msc_ops,	392	.ops = &jz_msc_ops,
376		393
377	.voltages = MMC_VDD_27_28 \| MMC_VDD_28_29 \| MMC_VDD_29_30 \|	394	.voltages = MMC_VDD_27_28 \| MMC_VDD_28_29 \| MMC_VDD_29_30 \|
378	MMC_VDD_30_31 \| MMC_VDD_31_32 \| MMC_VDD_32_33 \|	395	MMC_VDD_30_31 \| MMC_VDD_31_32 \| MMC_VDD_32_33 \|
379	MMC_VDD_33_34 \| MMC_VDD_34_35 \| MMC_VDD_35_36,	396	MMC_VDD_33_34 \| MMC_VDD_34_35 \| MMC_VDD_35_36,
380	.host_caps = MMC_MODE_4BIT \| MMC_MODE_HS_52MHz \| MMC_MODE_HS,	397	.host_caps = MMC_MODE_4BIT \| MMC_MODE_HS_52MHz \| MMC_MODE_HS,
381		398
382	.f_min = 375000,	399	.f_min = 375000,
383	.f_max = 48000000,	400	.f_max = 48000000,
384	.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,	401	.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
385	},	402	},
386	};	403	};
387		404
388	int jz_mmc_init(void __iomem *base)	405	int jz_mmc_init(void __iomem *base)
389	{	406	{
390	struct mmc *mmc;	407	struct mmc *mmc;
391		408
392	jz_mmc_priv_static.regs = base;	409	jz_mmc_priv_static.regs = base;
393		410
394	mmc = mmc_create(&jz_mmc_plat_static.cfg, &jz_mmc_priv_static);	411	mmc = mmc_create(&jz_mmc_plat_static.cfg, &jz_mmc_priv_static);
395		412
396	return mmc ? 0 : -ENODEV;	413	return mmc ? 0 : -ENODEV;
397	}	414	}
398		415
399	#else /* CONFIG_DM_MMC */	416	#else /* CONFIG_DM_MMC */
400		417
401	#include <dm.h>	418	#include <dm.h>
402	DECLARE_GLOBAL_DATA_PTR;	419	DECLARE_GLOBAL_DATA_PTR;
403		420
404	static int jz_mmc_dm_send_cmd(struct udevice dev, struct mmc_cmd cmd,	421	static int jz_mmc_dm_send_cmd(struct udevice dev, struct mmc_cmd cmd,
405	struct mmc_data *data)	422	struct mmc_data *data)
406	{	423	{
407	struct jz_mmc_priv *priv = dev_get_priv(dev);	424	struct jz_mmc_priv *priv = dev_get_priv(dev);
408	struct mmc *mmc = mmc_get_mmc_dev(dev);	425	struct mmc *mmc = mmc_get_mmc_dev(dev);
409		426
410	return jz_mmc_send_cmd(mmc, priv, cmd, data);	427	return jz_mmc_send_cmd(mmc, priv, cmd, data);
411	}	428	}
412		429
413	static int jz_mmc_dm_set_ios(struct udevice *dev)	430	static int jz_mmc_dm_set_ios(struct udevice *dev)
414	{	431	{
415	struct jz_mmc_priv *priv = dev_get_priv(dev);	432	struct jz_mmc_priv *priv = dev_get_priv(dev);
416	struct mmc *mmc = mmc_get_mmc_dev(dev);	433	struct mmc *mmc = mmc_get_mmc_dev(dev);
417		434
418	return jz_mmc_set_ios(mmc, priv);	435	return jz_mmc_set_ios(mmc, priv);
419	};	436	};
420		437
421	static const struct dm_mmc_ops jz_msc_ops = {	438	static const struct dm_mmc_ops jz_msc_ops = {
422	.send_cmd = jz_mmc_dm_send_cmd,	439	.send_cmd = jz_mmc_dm_send_cmd,
423	.set_ios = jz_mmc_dm_set_ios,	440	.set_ios = jz_mmc_dm_set_ios,
424	};	441	};
425		442
426	static int jz_mmc_ofdata_to_platdata(struct udevice *dev)	443	static int jz_mmc_ofdata_to_platdata(struct udevice *dev)
427	{	444	{
428	struct jz_mmc_priv *priv = dev_get_priv(dev);	445	struct jz_mmc_priv *priv = dev_get_priv(dev);
429	struct jz_mmc_plat *plat = dev_get_platdata(dev);	446	struct jz_mmc_plat *plat = dev_get_platdata(dev);
430	struct mmc_config *cfg;	447	struct mmc_config *cfg;
431	int ret;	448	int ret;
432		449
433	priv->regs = map_physmem(devfdt_get_addr(dev), 0x100, MAP_NOCACHE);	450	priv->regs = map_physmem(devfdt_get_addr(dev), 0x100, MAP_NOCACHE);
434	cfg = &plat->cfg;	451	cfg = &plat->cfg;
435		452
436	cfg->name = "MSC";	453	cfg->name = "MSC";
437	cfg->host_caps = MMC_MODE_HS_52MHz \| MMC_MODE_HS;	454	cfg->host_caps = MMC_MODE_HS_52MHz \| MMC_MODE_HS;
438		455
439	ret = mmc_of_parse(dev, cfg);	456	ret = mmc_of_parse(dev, cfg);
440	if (ret < 0) {	457	if (ret < 0) {
441	dev_err(dev, "failed to parse host caps\n");	458	dev_err(dev, "failed to parse host caps\n");
442	return ret;	459	return ret;
443	}	460	}
444		461
445	cfg->f_min = 400000;	462	cfg->f_min = 400000;
446	cfg->f_max = 52000000;	463	cfg->f_max = 52000000;
447		464
448	cfg->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34 \| MMC_VDD_165_195;	465	cfg->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34 \| MMC_VDD_165_195;
449	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;	466	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
450		467
451	return 0;	468	return 0;
452	}	469	}

drivers/mmc/mmc_write.c

Diff comments View file @ f83ef0d

1	// SPDX-License-Identifier: GPL-2.0+	1	// SPDX-License-Identifier: GPL-2.0+
2	/*	2	/*
3	* Copyright 2008, Freescale Semiconductor, Inc	3	* Copyright 2008, Freescale Semiconductor, Inc
4	* Andy Fleming	4	* Andy Fleming
5	*	5	*
6	* Based vaguely on the Linux code	6	* Based vaguely on the Linux code
7	*/	7	*/
8		8
9	#include <config.h>	9	#include <config.h>
10	#include <common.h>	10	#include <common.h>
11	#include <dm.h>	11	#include <dm.h>
12	#include <part.h>	12	#include <part.h>
13	#include <div64.h>	13	#include <div64.h>
14	#include <linux/math64.h>	14	#include <linux/math64.h>
15	#include "mmc_private.h"	15	#include "mmc_private.h"
16		16
17	static ulong mmc_erase_t(struct mmc *mmc, ulong start, lbaint_t blkcnt)	17	static ulong mmc_erase_t(struct mmc *mmc, ulong start, lbaint_t blkcnt)
18	{	18	{
19	struct mmc_cmd cmd;	19	struct mmc_cmd cmd;
20	ulong end;	20	ulong end;
21	int err, start_cmd, end_cmd;	21	int err, start_cmd, end_cmd;
22		22
23	if (mmc->high_capacity) {	23	if (mmc->high_capacity) {
24	end = start + blkcnt - 1;	24	end = start + blkcnt - 1;
25	} else {	25	} else {
26	end = (start + blkcnt - 1) * mmc->write_bl_len;	26	end = (start + blkcnt - 1) * mmc->write_bl_len;
27	start *= mmc->write_bl_len;	27	start *= mmc->write_bl_len;
28	}	28	}
29		29
30	if (IS_SD(mmc)) {	30	if (IS_SD(mmc)) {
31	start_cmd = SD_CMD_ERASE_WR_BLK_START;	31	start_cmd = SD_CMD_ERASE_WR_BLK_START;
32	end_cmd = SD_CMD_ERASE_WR_BLK_END;	32	end_cmd = SD_CMD_ERASE_WR_BLK_END;
33	} else {	33	} else {
34	start_cmd = MMC_CMD_ERASE_GROUP_START;	34	start_cmd = MMC_CMD_ERASE_GROUP_START;
35	end_cmd = MMC_CMD_ERASE_GROUP_END;	35	end_cmd = MMC_CMD_ERASE_GROUP_END;
36	}	36	}
37		37
38	cmd.cmdidx = start_cmd;	38	cmd.cmdidx = start_cmd;
39	cmd.cmdarg = start;	39	cmd.cmdarg = start;
40	cmd.resp_type = MMC_RSP_R1;	40	cmd.resp_type = MMC_RSP_R1;
41		41
42	err = mmc_send_cmd(mmc, &cmd, NULL);	42	err = mmc_send_cmd(mmc, &cmd, NULL);
43	if (err)	43	if (err)
44	goto err_out;	44	goto err_out;
45		45
46	cmd.cmdidx = end_cmd;	46	cmd.cmdidx = end_cmd;
47	cmd.cmdarg = end;	47	cmd.cmdarg = end;
48		48
49	err = mmc_send_cmd(mmc, &cmd, NULL);	49	err = mmc_send_cmd(mmc, &cmd, NULL);
50	if (err)	50	if (err)
51	goto err_out;	51	goto err_out;
52		52
53	cmd.cmdidx = MMC_CMD_ERASE;	53	cmd.cmdidx = MMC_CMD_ERASE;
54	cmd.cmdarg = MMC_ERASE_ARG;	54	cmd.cmdarg = MMC_ERASE_ARG;
55	cmd.resp_type = MMC_RSP_R1b;	55	cmd.resp_type = MMC_RSP_R1b;
56		56
57	err = mmc_send_cmd(mmc, &cmd, NULL);	57	err = mmc_send_cmd(mmc, &cmd, NULL);
58	if (err)	58	if (err)
59	goto err_out;	59	goto err_out;
60		60
61	return 0;	61	return 0;
62		62
63	err_out:	63	err_out:
64	puts("mmc erase failed\n");	64	puts("mmc erase failed\n");
65	return err;	65	return err;
66	}	66	}
67		67
68	#ifdef CONFIG_BLK	68	#if CONFIG_IS_ENABLED(BLK)
69	ulong mmc_berase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt)	69	ulong mmc_berase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt)
70	#else	70	#else
71	ulong mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt)	71	ulong mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt)
72	#endif	72	#endif
73	{	73	{
74	#ifdef CONFIG_BLK	74	#if CONFIG_IS_ENABLED(BLK)
75	struct blk_desc *block_dev = dev_get_uclass_platdata(dev);	75	struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
76	#endif	76	#endif
77	int dev_num = block_dev->devnum;	77	int dev_num = block_dev->devnum;
78	int err = 0;	78	int err = 0;
79	u32 start_rem, blkcnt_rem;	79	u32 start_rem, blkcnt_rem;
80	struct mmc *mmc = find_mmc_device(dev_num);	80	struct mmc *mmc = find_mmc_device(dev_num);
81	lbaint_t blk = 0, blk_r = 0;	81	lbaint_t blk = 0, blk_r = 0;
82	int timeout = 1000;	82	int timeout = 1000;
83		83
84	if (!mmc)	84	if (!mmc)
85	return -1;	85	return -1;
86		86
87	err = blk_select_hwpart_devnum(IF_TYPE_MMC, dev_num,	87	err = blk_select_hwpart_devnum(IF_TYPE_MMC, dev_num,
88	block_dev->hwpart);	88	block_dev->hwpart);
89	if (err < 0)	89	if (err < 0)
90	return -1;	90	return -1;
91		91
92	/*	92	/*
93	* We want to see if the requested start or total block count are	93	* We want to see if the requested start or total block count are
94	* unaligned. We discard the whole numbers and only care about the	94	* unaligned. We discard the whole numbers and only care about the
95	* remainder.	95	* remainder.
96	*/	96	*/
97	err = div_u64_rem(start, mmc->erase_grp_size, &start_rem);	97	err = div_u64_rem(start, mmc->erase_grp_size, &start_rem);
98	err = div_u64_rem(blkcnt, mmc->erase_grp_size, &blkcnt_rem);	98	err = div_u64_rem(blkcnt, mmc->erase_grp_size, &blkcnt_rem);
99	if (start_rem \|\| blkcnt_rem)	99	if (start_rem \|\| blkcnt_rem)
100	printf("\n\nCaution! Your devices Erase group is 0x%x\n"	100	printf("\n\nCaution! Your devices Erase group is 0x%x\n"
101	"The erase range would be change to "	101	"The erase range would be change to "
102	"0x" LBAF "~0x" LBAF "\n\n",	102	"0x" LBAF "~0x" LBAF "\n\n",
103	mmc->erase_grp_size, start & ~(mmc->erase_grp_size - 1),	103	mmc->erase_grp_size, start & ~(mmc->erase_grp_size - 1),
104	((start + blkcnt + mmc->erase_grp_size)	104	((start + blkcnt + mmc->erase_grp_size)
105	& ~(mmc->erase_grp_size - 1)) - 1);	105	& ~(mmc->erase_grp_size - 1)) - 1);
106		106
107	while (blk < blkcnt) {	107	while (blk < blkcnt) {
108	if (IS_SD(mmc) && mmc->ssr.au) {	108	if (IS_SD(mmc) && mmc->ssr.au) {
109	blk_r = ((blkcnt - blk) > mmc->ssr.au) ?	109	blk_r = ((blkcnt - blk) > mmc->ssr.au) ?
110	mmc->ssr.au : (blkcnt - blk);	110	mmc->ssr.au : (blkcnt - blk);
111	} else {	111	} else {
112	blk_r = ((blkcnt - blk) > mmc->erase_grp_size) ?	112	blk_r = ((blkcnt - blk) > mmc->erase_grp_size) ?
113	mmc->erase_grp_size : (blkcnt - blk);	113	mmc->erase_grp_size : (blkcnt - blk);
114	}	114	}
115	err = mmc_erase_t(mmc, start + blk, blk_r);	115	err = mmc_erase_t(mmc, start + blk, blk_r);
116	if (err)	116	if (err)
117	break;	117	break;
118		118
119	blk += blk_r;	119	blk += blk_r;
120		120
121	/* Waiting for the ready status */	121	/* Waiting for the ready status */
122	if (mmc_send_status(mmc, timeout))	122	if (mmc_send_status(mmc, timeout))
123	return 0;	123	return 0;
124	}	124	}
125		125
126	return blk;	126	return blk;
127	}	127	}
128		128
129	static ulong mmc_write_blocks(struct mmc *mmc, lbaint_t start,	129	static ulong mmc_write_blocks(struct mmc *mmc, lbaint_t start,
130	lbaint_t blkcnt, const void *src)	130	lbaint_t blkcnt, const void *src)
131	{	131	{
132	struct mmc_cmd cmd;	132	struct mmc_cmd cmd;
133	struct mmc_data data;	133	struct mmc_data data;
134	int timeout = 1000;	134	int timeout = 1000;
135		135
136	if ((start + blkcnt) > mmc_get_blk_desc(mmc)->lba) {	136	if ((start + blkcnt) > mmc_get_blk_desc(mmc)->lba) {
137	printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",	137	printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
138	start + blkcnt, mmc_get_blk_desc(mmc)->lba);	138	start + blkcnt, mmc_get_blk_desc(mmc)->lba);
139	return 0;	139	return 0;
140	}	140	}
141		141
142	if (blkcnt == 0)	142	if (blkcnt == 0)
143	return 0;	143	return 0;
144	else if (blkcnt == 1)	144	else if (blkcnt == 1)
145	cmd.cmdidx = MMC_CMD_WRITE_SINGLE_BLOCK;	145	cmd.cmdidx = MMC_CMD_WRITE_SINGLE_BLOCK;
146	else	146	else
147	cmd.cmdidx = MMC_CMD_WRITE_MULTIPLE_BLOCK;	147	cmd.cmdidx = MMC_CMD_WRITE_MULTIPLE_BLOCK;
148		148
149	if (mmc->high_capacity)	149	if (mmc->high_capacity)
150	cmd.cmdarg = start;	150	cmd.cmdarg = start;
151	else	151	else
152	cmd.cmdarg = start * mmc->write_bl_len;	152	cmd.cmdarg = start * mmc->write_bl_len;
153		153
154	cmd.resp_type = MMC_RSP_R1;	154	cmd.resp_type = MMC_RSP_R1;
155		155
156	data.src = src;	156	data.src = src;
157	data.blocks = blkcnt;	157	data.blocks = blkcnt;
158	data.blocksize = mmc->write_bl_len;	158	data.blocksize = mmc->write_bl_len;
159	data.flags = MMC_DATA_WRITE;	159	data.flags = MMC_DATA_WRITE;
160		160
161	if (mmc_send_cmd(mmc, &cmd, &data)) {	161	if (mmc_send_cmd(mmc, &cmd, &data)) {
162	printf("mmc write failed\n");	162	printf("mmc write failed\n");
163	return 0;	163	return 0;
164	}	164	}
165		165
166	/* SPI multiblock writes terminate using a special	166	/* SPI multiblock writes terminate using a special
167	* token, not a STOP_TRANSMISSION request.	167	* token, not a STOP_TRANSMISSION request.
168	*/	168	*/
169	if (!mmc_host_is_spi(mmc) && blkcnt > 1) {	169	if (!mmc_host_is_spi(mmc) && blkcnt > 1) {
170	cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;	170	cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
171	cmd.cmdarg = 0;	171	cmd.cmdarg = 0;
172	cmd.resp_type = MMC_RSP_R1b;	172	cmd.resp_type = MMC_RSP_R1b;
173	if (mmc_send_cmd(mmc, &cmd, NULL)) {	173	if (mmc_send_cmd(mmc, &cmd, NULL)) {
174	printf("mmc fail to send stop cmd\n");	174	printf("mmc fail to send stop cmd\n");
175	return 0;	175	return 0;
176	}	176	}
177	}	177	}
178		178
179	/* Waiting for the ready status */	179	/* Waiting for the ready status */
180	if (mmc_send_status(mmc, timeout))	180	if (mmc_send_status(mmc, timeout))
181	return 0;	181	return 0;
182		182
183	return blkcnt;	183	return blkcnt;
184	}	184	}
185		185
186	#ifdef CONFIG_BLK	186	#if CONFIG_IS_ENABLED(BLK)
187	ulong mmc_bwrite(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,	187	ulong mmc_bwrite(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
188	const void *src)	188	const void *src)
189	#else	189	#else
190	ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,	190	ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
191	const void *src)	191	const void *src)
192	#endif	192	#endif
193	{	193	{
194	#ifdef CONFIG_BLK	194	#if CONFIG_IS_ENABLED(BLK)
195	struct blk_desc *block_dev = dev_get_uclass_platdata(dev);	195	struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
196	#endif	196	#endif
197	int dev_num = block_dev->devnum;	197	int dev_num = block_dev->devnum;
198	lbaint_t cur, blocks_todo = blkcnt;	198	lbaint_t cur, blocks_todo = blkcnt;
199	int err;	199	int err;
200		200
201	struct mmc *mmc = find_mmc_device(dev_num);	201	struct mmc *mmc = find_mmc_device(dev_num);
202	if (!mmc)	202	if (!mmc)
203	return 0;	203	return 0;
204		204
205	err = blk_select_hwpart_devnum(IF_TYPE_MMC, dev_num, block_dev->hwpart);	205	err = blk_select_hwpart_devnum(IF_TYPE_MMC, dev_num, block_dev->hwpart);
206	if (err < 0)	206	if (err < 0)
207	return 0;	207	return 0;
208		208
209	if (mmc_set_blocklen(mmc, mmc->write_bl_len))	209	if (mmc_set_blocklen(mmc, mmc->write_bl_len))
210	return 0;	210	return 0;
211		211
212	do {	212	do {
213	cur = (blocks_todo > mmc->cfg->b_max) ?	213	cur = (blocks_todo > mmc->cfg->b_max) ?
214	mmc->cfg->b_max : blocks_todo;	214	mmc->cfg->b_max : blocks_todo;
215	if (mmc_write_blocks(mmc, start, cur, src) != cur)	215	if (mmc_write_blocks(mmc, start, cur, src) != cur)
216	return 0;	216	return 0;
217	blocks_todo -= cur;	217	blocks_todo -= cur;
218	start += cur;	218	start += cur;
219	src += cur * mmc->write_bl_len;	219	src += cur * mmc->write_bl_len;
220	} while (blocks_todo > 0);	220	} while (blocks_todo > 0);
221		221
222	return blkcnt;	222	return blkcnt;
223	}	223	}
224		224

drivers/net/bcm6368-eth.c

Diff comments View file @ f83ef0d

 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
  *
  * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c:
  *	Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
  */
 #include <common.h>
 #include <clk.h>
 #include <dm.h>
 #include <dma.h>
 #include <miiphy.h>
 #include <net.h>
 #include <reset.h>
 #include <wait_bit.h>
 #include <asm/io.h>
 #define ETH_PORT_STR			"brcm,enetsw-port"
 #define ETH_RX_DESC			PKTBUFSRX
 #define ETH_ZLEN			60
 #define ETH_TIMEOUT			100
 #define ETH_MAX_PORT			8
 #define ETH_RGMII_PORT0			4
 /* Port traffic control */
 #define ETH_PTCTRL_REG(x)		(0x0 + (x))
 #define ETH_PTCTRL_RXDIS_SHIFT		0
 #define ETH_PTCTRL_RXDIS_MASK		(1 << ETH_PTCTRL_RXDIS_SHIFT)
 #define ETH_PTCTRL_TXDIS_SHIFT		1
 #define ETH_PTCTRL_TXDIS_MASK		(1 << ETH_PTCTRL_TXDIS_SHIFT)
 /* Switch mode register */
 #define ETH_SWMODE_REG			0xb
 #define ETH_SWMODE_FWD_EN_SHIFT		1
 #define ETH_SWMODE_FWD_EN_MASK		(1 << ETH_SWMODE_FWD_EN_SHIFT)
 /* IMP override Register */
 #define ETH_IMPOV_REG			0xe
 #define ETH_IMPOV_LINKUP_SHIFT		0
 #define ETH_IMPOV_LINKUP_MASK		(1 << ETH_IMPOV_LINKUP_SHIFT)
 #define ETH_IMPOV_FDX_SHIFT		1
 #define ETH_IMPOV_FDX_MASK		(1 << ETH_IMPOV_FDX_SHIFT)
 #define ETH_IMPOV_100_SHIFT		2
 #define ETH_IMPOV_100_MASK		(1 << ETH_IMPOV_100_SHIFT)
 #define ETH_IMPOV_1000_SHIFT		3
 #define ETH_IMPOV_1000_MASK		(1 << ETH_IMPOV_1000_SHIFT)
 #define ETH_IMPOV_RXFLOW_SHIFT		4
 #define ETH_IMPOV_RXFLOW_MASK		(1 << ETH_IMPOV_RXFLOW_SHIFT)
 #define ETH_IMPOV_TXFLOW_SHIFT		5
 #define ETH_IMPOV_TXFLOW_MASK		(1 << ETH_IMPOV_TXFLOW_SHIFT)
 #define ETH_IMPOV_FORCE_SHIFT		7
 #define ETH_IMPOV_FORCE_MASK		(1 << ETH_IMPOV_FORCE_SHIFT)
 /* Port override Register */
 #define ETH_PORTOV_REG(x)		(0x58 + (x))
 #define ETH_PORTOV_LINKUP_SHIFT		0
 #define ETH_PORTOV_LINKUP_MASK		(1 << ETH_PORTOV_LINKUP_SHIFT)
 #define ETH_PORTOV_FDX_SHIFT		1
 #define ETH_PORTOV_FDX_MASK		(1 << ETH_PORTOV_FDX_SHIFT)
 #define ETH_PORTOV_100_SHIFT		2
 #define ETH_PORTOV_100_MASK		(1 << ETH_PORTOV_100_SHIFT)
 #define ETH_PORTOV_1000_SHIFT		3
 #define ETH_PORTOV_1000_MASK		(1 << ETH_PORTOV_1000_SHIFT)
 #define ETH_PORTOV_RXFLOW_SHIFT		4
 #define ETH_PORTOV_RXFLOW_MASK		(1 << ETH_PORTOV_RXFLOW_SHIFT)
 #define ETH_PORTOV_TXFLOW_SHIFT		5
 #define ETH_PORTOV_TXFLOW_MASK		(1 << ETH_PORTOV_TXFLOW_SHIFT)
 #define ETH_PORTOV_ENABLE_SHIFT		6
 #define ETH_PORTOV_ENABLE_MASK		(1 << ETH_PORTOV_ENABLE_SHIFT)
 /* Port RGMII control register */
 #define ETH_RGMII_CTRL_REG(x)		(0x60 + (x))
 #define ETH_RGMII_CTRL_GMII_CLK_EN	(1 << 7)
 #define ETH_RGMII_CTRL_MII_OVERRIDE_EN	(1 << 6)
 #define ETH_RGMII_CTRL_MII_MODE_MASK	(3 << 4)
 #define ETH_RGMII_CTRL_RGMII_MODE	(0 << 4)
 #define ETH_RGMII_CTRL_MII_MODE		(1 << 4)
 #define ETH_RGMII_CTRL_RVMII_MODE	(2 << 4)
 #define ETH_RGMII_CTRL_TIMING_SEL_EN	(1 << 0)
 /* Port RGMII timing register */
 #define ENETSW_RGMII_TIMING_REG(x)	(0x68 + (x))
 /* MDIO control register */
 #define MII_SC_REG			0xb0
 #define MII_SC_EXT_SHIFT		16
 #define MII_SC_EXT_MASK			(1 << MII_SC_EXT_SHIFT)
 #define MII_SC_REG_SHIFT		20
 #define MII_SC_PHYID_SHIFT		25
 #define MII_SC_RD_SHIFT			30
 #define MII_SC_RD_MASK			(1 << MII_SC_RD_SHIFT)
 #define MII_SC_WR_SHIFT			31
 #define MII_SC_WR_MASK			(1 << MII_SC_WR_SHIFT)
 /* MDIO data register */
 #define MII_DAT_REG			0xb4
 /* Global Management Configuration Register */
 #define ETH_GMCR_REG			0x200
 #define ETH_GMCR_RST_MIB_SHIFT		0
 #define ETH_GMCR_RST_MIB_MASK		(1 << ETH_GMCR_RST_MIB_SHIFT)
 /* Jumbo control register port mask register */
 #define ETH_JMBCTL_PORT_REG		0x4004
 /* Jumbo control mib good frame register */
 #define ETH_JMBCTL_MAXSIZE_REG		0x4008
 /* ETH port data */
 struct bcm_enetsw_port {
 	bool used;
 	const char *name;
 	/* Config */
 	bool bypass_link;
 	int force_speed;
 	bool force_duplex_full;
 	/* PHY */
 	int phy_id;
 };
 /* ETH data */
 struct bcm6368_eth_priv {
 	void __iomem *base;
 	/* DMA */
 	struct dma rx_dma;
 	struct dma tx_dma;
 	/* Ports */
 	uint8_t num_ports;
 	struct bcm_enetsw_port used_ports[ETH_MAX_PORT];
 	int sw_port_link[ETH_MAX_PORT];
 	bool rgmii_override;
 	bool rgmii_timing;
 	/* PHY */
 	int phy_id;
 };
 static inline bool bcm_enet_port_is_rgmii(int portid)
 {
 	return portid >= ETH_RGMII_PORT0;
 }
 static int bcm6368_mdio_read(struct bcm6368_eth_priv *priv, uint8_t ext,
 			     int phy_id, int reg)
 {
 	uint32_t val;
 	writel_be(0, priv->base + MII_SC_REG);
 	val = MII_SC_RD_MASK |
 	      (phy_id << MII_SC_PHYID_SHIFT) |
 	      (reg << MII_SC_REG_SHIFT);
 	if (ext)
 		val |= MII_SC_EXT_MASK;
 	writel_be(val, priv->base + MII_SC_REG);
 	udelay(50);
 	return readw_be(priv->base + MII_DAT_REG);
 }
 static int bcm6368_mdio_write(struct bcm6368_eth_priv *priv, uint8_t ext,
 			      int phy_id, int reg, u16 data)
 {
 	uint32_t val;
 	writel_be(0, priv->base + MII_SC_REG);
 	val = MII_SC_WR_MASK |
 	      (phy_id << MII_SC_PHYID_SHIFT) |
 	      (reg << MII_SC_REG_SHIFT);
 	if (ext)
 		val |= MII_SC_EXT_MASK;
 	val |= data;
 	writel_be(val, priv->base + MII_SC_REG);
 	udelay(50);
 	return 0;
 }
 static int bcm6368_eth_free_pkt(struct udevice *dev, uchar *packet, int len)
 {
 	struct bcm6368_eth_priv *priv = dev_get_priv(dev);
 	return dma_prepare_rcv_buf(&priv->rx_dma, packet, len);
 }
 static int bcm6368_eth_recv(struct udevice *dev, int flags, uchar **packetp)
 {
 	struct bcm6368_eth_priv *priv = dev_get_priv(dev);
 	return dma_receive(&priv->rx_dma, (void**)packetp, NULL);
 }
 static int bcm6368_eth_send(struct udevice *dev, void *packet, int length)
 {
 	struct bcm6368_eth_priv *priv = dev_get_priv(dev);
 	/* pad packets smaller than ETH_ZLEN */
 	if (length < ETH_ZLEN) {
 		memset(packet + length, 0, ETH_ZLEN - length);
 		length = ETH_ZLEN;
 	}
 	return dma_send(&priv->tx_dma, packet, length, NULL);
 }
 static int bcm6368_eth_adjust_link(struct udevice *dev)
 {
 	struct bcm6368_eth_priv *priv = dev_get_priv(dev);
 	unsigned int i;
 	for (i = 0; i < priv->num_ports; i++) {
 		struct bcm_enetsw_port *port;
 		int val, j, up, adv, lpa, speed, duplex, media;
 		int external_phy = bcm_enet_port_is_rgmii(i);
 		u8 override;
 		port = &priv->used_ports[i];
 		if (!port->used)
 			continue;
 		if (port->bypass_link)
 			continue;
 		/* dummy read to clear */
 		for (j = 0; j < 2; j++)
 			val = bcm6368_mdio_read(priv, external_phy,
 						port->phy_id, MII_BMSR);
 		if (val == 0xffff)
 			continue;
 		up = (val & BMSR_LSTATUS) ? 1 : 0;
 		if (!(up ^ priv->sw_port_link[i]))
 			continue;
 		priv->sw_port_link[i] = up;
 		/* link changed */
 		if (!up) {
 			dev_info(&priv->pdev->dev, "link DOWN on %s\n",
 				 port->name);
 			writeb_be(ETH_PORTOV_ENABLE_MASK,
 				  priv->base + ETH_PORTOV_REG(i));
 			writeb_be(ETH_PTCTRL_RXDIS_MASK |
 				  ETH_PTCTRL_TXDIS_MASK,
 				  priv->base + ETH_PTCTRL_REG(i));
 			continue;
 		}
 		adv = bcm6368_mdio_read(priv, external_phy,
 					port->phy_id, MII_ADVERTISE);
 		lpa = bcm6368_mdio_read(priv, external_phy, port->phy_id,
 					MII_LPA);
 		/* figure out media and duplex from advertise and LPA values */
 		media = mii_nway_result(lpa & adv);
 		duplex = (media & ADVERTISE_FULL) ? 1 : 0;
 		if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF))
 			speed = 100;
 		else
 			speed = 10;
 		if (val & BMSR_ESTATEN) {
 			adv = bcm6368_mdio_read(priv, external_phy,
 						port->phy_id, MII_CTRL1000);
 			lpa = bcm6368_mdio_read(priv, external_phy,
 						port->phy_id, MII_STAT1000);
 			if ((adv & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
 			    (lpa & (LPA_1000FULL | LPA_1000HALF))) {
 				speed = 1000;
 				duplex = (lpa & LPA_1000FULL);
 			}
 		}
 		pr_alert("link UP on %s, %dMbps, %s-duplex\n",
 			 port->name, speed, duplex ? "full" : "half");
 		override = ETH_PORTOV_ENABLE_MASK |
 			   ETH_PORTOV_LINKUP_MASK;
 		if (speed == 1000)
 			override |= ETH_PORTOV_1000_MASK;
 		else if (speed == 100)
 			override |= ETH_PORTOV_100_MASK;
 		if (duplex)
 			override |= ETH_PORTOV_FDX_MASK;
 		writeb_be(override, priv->base + ETH_PORTOV_REG(i));
 		writeb_be(0, priv->base + ETH_PTCTRL_REG(i));
 	}
 	return 0;
 }
 static int bcm6368_eth_start(struct udevice *dev)
 {
 	struct bcm6368_eth_priv *priv = dev_get_priv(dev);
 	uint8_t i;
+	/* disable all ports */
+	for (i = 0; i < priv->num_ports; i++) {
+		setbits_8(priv->base + ETH_PORTOV_REG(i),
+			  ETH_PORTOV_ENABLE_MASK);
+		setbits_8(priv->base + ETH_PTCTRL_REG(i),
+			  ETH_PTCTRL_RXDIS_MASK | ETH_PTCTRL_TXDIS_MASK);
+		priv->sw_port_link[i] = 0;
+	}
+	/* enable external ports */
+	for (i = ETH_RGMII_PORT0; i < priv->num_ports; i++) {
+		u8 rgmii_ctrl = ETH_RGMII_CTRL_GMII_CLK_EN;
+		if (!priv->used_ports[i].used)
+			continue;
+		if (priv->rgmii_override)
+			rgmii_ctrl |= ETH_RGMII_CTRL_MII_OVERRIDE_EN;
+		if (priv->rgmii_timing)
+			rgmii_ctrl |= ETH_RGMII_CTRL_TIMING_SEL_EN;
+		setbits_8(priv->base + ETH_RGMII_CTRL_REG(i), rgmii_ctrl);
+	}
+	/* reset mib */
+	setbits_8(priv->base + ETH_GMCR_REG, ETH_GMCR_RST_MIB_MASK);
+	mdelay(1);
+	clrbits_8(priv->base + ETH_GMCR_REG, ETH_GMCR_RST_MIB_MASK);
+	mdelay(1);
+	/* force CPU port state */
+	setbits_8(priv->base + ETH_IMPOV_REG,
+		  ETH_IMPOV_FORCE_MASK | ETH_IMPOV_LINKUP_MASK);
+	/* enable switch forward engine */
+	setbits_8(priv->base + ETH_SWMODE_REG, ETH_SWMODE_FWD_EN_MASK);
 	/* prepare rx dma buffers */
 	for (i = 0; i < ETH_RX_DESC; i++) {
 		int ret = dma_prepare_rcv_buf(&priv->rx_dma, net_rx_packets[i],
 					      PKTSIZE_ALIGN);
 		if (ret < 0)
 			break;
 	}
 	/* enable dma rx channel */
 	dma_enable(&priv->rx_dma);
 	/* enable dma tx channel */
 	dma_enable(&priv->tx_dma);
 	/* apply override config for bypass_link ports here. */
 	for (i = 0; i < priv->num_ports; i++) {
 		struct bcm_enetsw_port *port;
 		u8 override;
 		port = &priv->used_ports[i];
 		if (!port->used)
 			continue;
 		if (!port->bypass_link)
 			continue;
 		override = ETH_PORTOV_ENABLE_MASK |
 			   ETH_PORTOV_LINKUP_MASK;
 		switch (port->force_speed) {
 		case 1000:
 			override |= ETH_PORTOV_1000_MASK;
 			break;
 		case 100:
 			override |= ETH_PORTOV_100_MASK;
 			break;
 		case 10:
 			break;
 		default:
 			pr_warn("%s: invalid forced speed on port %s\n",
 				__func__, port->name);
 			break;
 		}
 		if (port->force_duplex_full)
 			override |= ETH_PORTOV_FDX_MASK;
 		writeb_be(override, priv->base + ETH_PORTOV_REG(i));
 		writeb_be(0, priv->base + ETH_PTCTRL_REG(i));
 	}
 	bcm6368_eth_adjust_link(dev);
 	return 0;
 }
 static void bcm6368_eth_stop(struct udevice *dev)
 {
 	struct bcm6368_eth_priv *priv = dev_get_priv(dev);
+	uint8_t i;
+	/* disable all ports */
+	for (i = 0; i < priv->num_ports; i++) {
+		setbits_8(priv->base + ETH_PORTOV_REG(i),
+			  ETH_PORTOV_ENABLE_MASK);
+		setbits_8(priv->base + ETH_PTCTRL_REG(i),
+			  ETH_PTCTRL_RXDIS_MASK | ETH_PTCTRL_TXDIS_MASK);
+	}
+	/* disable external ports */
+	for (i = ETH_RGMII_PORT0; i < priv->num_ports; i++) {
+		if (!priv->used_ports[i].used)
+			continue;
+		clrbits_8(priv->base + ETH_RGMII_CTRL_REG(i),
+			  ETH_RGMII_CTRL_GMII_CLK_EN);
+	}
+	/* disable CPU port */
+	clrbits_8(priv->base + ETH_IMPOV_REG,
+		  ETH_IMPOV_FORCE_MASK | ETH_IMPOV_LINKUP_MASK);
+	/* disable switch forward engine */
+	clrbits_8(priv->base + ETH_SWMODE_REG, ETH_SWMODE_FWD_EN_MASK);
 	/* disable dma rx channel */
 	dma_disable(&priv->rx_dma);
 	/* disable dma tx channel */
 	dma_disable(&priv->tx_dma);
 }
 static const struct eth_ops bcm6368_eth_ops = {
 	.free_pkt = bcm6368_eth_free_pkt,
 	.recv = bcm6368_eth_recv,
 	.send = bcm6368_eth_send,
 	.start = bcm6368_eth_start,
 	.stop = bcm6368_eth_stop,
 };
 static const struct udevice_id bcm6368_eth_ids[] = {
 	{ .compatible = "brcm,bcm6368-enet", },
 	{ /* sentinel */ }
 };
 static bool bcm6368_phy_is_external(struct bcm6368_eth_priv *priv, int phy_id)
 {
 	uint8_t i;
 	for (i = 0; i < priv->num_ports; ++i) {
 		if (!priv->used_ports[i].used)
 			continue;
 		if (priv->used_ports[i].phy_id == phy_id)
 			return bcm_enet_port_is_rgmii(i);
 	}
 	return true;
 }
 static int bcm6368_mii_mdio_read(struct mii_dev *bus, int addr, int devaddr,
 				 int reg)
 {
 	struct bcm6368_eth_priv *priv = bus->priv;
 	bool ext = bcm6368_phy_is_external(priv, addr);
 	return bcm6368_mdio_read(priv, ext, addr, reg);
 }
 static int bcm6368_mii_mdio_write(struct mii_dev *bus, int addr, int devaddr,
 				  int reg, u16 data)
 {
 	struct bcm6368_eth_priv *priv = bus->priv;
 	bool ext = bcm6368_phy_is_external(priv, addr);
 	return bcm6368_mdio_write(priv, ext, addr, reg, data);
 }
 static int bcm6368_mdio_init(const char *name, struct bcm6368_eth_priv *priv)
 {
 	struct mii_dev *bus;
 	bus = mdio_alloc();
 	if (!bus) {
 		pr_err("%s: failed to allocate MDIO bus\n", __func__);
 		return -ENOMEM;
 	}
 	bus->read = bcm6368_mii_mdio_read;
 	bus->write = bcm6368_mii_mdio_write;
 	bus->priv = priv;
 	snprintf(bus->name, sizeof(bus->name), "%s", name);
 	return mdio_register(bus);
 }
 static int bcm6368_eth_probe(struct udevice *dev)
 {
 	struct eth_pdata *pdata = dev_get_platdata(dev);
 	struct bcm6368_eth_priv *priv = dev_get_priv(dev);
 	int num_ports, ret, i;
-	uint32_t val;
 	ofnode node;
 	/* get base address */
 	priv->base = dev_remap_addr(dev);
 	if (!priv->base)
 		return -EINVAL;
 	pdata->iobase = (phys_addr_t) priv->base;
 	/* get number of ports */
 	num_ports = dev_read_u32_default(dev, "brcm,num-ports", ETH_MAX_PORT);
 	if (!num_ports || num_ports > ETH_MAX_PORT)
 		return -EINVAL;
 	/* get dma channels */
 	ret = dma_get_by_name(dev, "tx", &priv->tx_dma);
 	if (ret)
 		return -EINVAL;
 	ret = dma_get_by_name(dev, "rx", &priv->rx_dma);
 	if (ret)
 		return -EINVAL;
 	/* try to enable clocks */
 	for (i = 0; ; i++) {
 		struct clk clk;
 		int ret;
 		ret = clk_get_by_index(dev, i, &clk);
 		if (ret < 0)
 			break;
 		ret = clk_enable(&clk);
 		if (ret < 0) {
 			pr_err("%s: error enabling clock %d\n", __func__, i);
 			return ret;
 		}
 		ret = clk_free(&clk);
 		if (ret < 0) {
 			pr_err("%s: error freeing clock %d\n", __func__, i);
 			return ret;
 		}
 	}
 	/* try to perform resets */
 	for (i = 0; ; i++) {
 		struct reset_ctl reset;
 		int ret;
 		ret = reset_get_by_index(dev, i, &reset);
 		if (ret < 0)
 			break;
 		ret = reset_deassert(&reset);
 		if (ret < 0) {
 			pr_err("%s: error deasserting reset %d\n", __func__, i);
 			return ret;
 		}
 		ret = reset_free(&reset);
 		if (ret < 0) {
 			pr_err("%s: error freeing reset %d\n", __func__, i);
 			return ret;
 		}
 	}
 	/* set priv data */
 	priv->num_ports = num_ports;
 	if (dev_read_bool(dev, "brcm,rgmii-override"))
 		priv->rgmii_override = true;
 	if (dev_read_bool(dev, "brcm,rgmii-timing"))
 		priv->rgmii_timing = true;
 	/* get ports */
 	dev_for_each_subnode(node, dev) {
 		const char *comp;
 		const char *label;
 		unsigned int p;
 		int phy_id;
 		int speed;
 		comp = ofnode_read_string(node, "compatible");
 		if (!comp || memcmp(comp, ETH_PORT_STR, sizeof(ETH_PORT_STR)))
 			continue;
 		p = ofnode_read_u32_default(node, "reg", ETH_MAX_PORT);
 		if (p >= num_ports)
 			return -EINVAL;
 		label = ofnode_read_string(node, "label");
 		if (!label) {
 			debug("%s: node %s has no label\n", __func__,
 			      ofnode_get_name(node));
 			return -EINVAL;
 		}
 		phy_id = ofnode_read_u32_default(node, "brcm,phy-id", -1);
 		priv->used_ports[p].used = true;
 		priv->used_ports[p].name = label;
 		priv->used_ports[p].phy_id = phy_id;
 		if (ofnode_read_bool(node, "full-duplex"))
 			priv->used_ports[p].force_duplex_full = true;
 		if (ofnode_read_bool(node, "bypass-link"))
 			priv->used_ports[p].bypass_link = true;
 		speed = ofnode_read_u32_default(node, "speed", 0);
 		if (speed)
 			priv->used_ports[p].force_speed = speed;
 	}
 	/* init mii bus */
 	ret = bcm6368_mdio_init(dev->name, priv);
 	if (ret)
 		return ret;
-	/* disable all ports */
-	for (i = 0; i < priv->num_ports; i++) {
-		writeb_be(ETH_PORTOV_ENABLE_MASK,
-			      priv->base + ETH_PORTOV_REG(i));
-		writeb_be(ETH_PTCTRL_RXDIS_MASK |
-			      ETH_PTCTRL_TXDIS_MASK,
-			      priv->base + ETH_PTCTRL_REG(i));
-		priv->sw_port_link[i] = 0;
-	}
-	/* enable external ports */
-	for (i = ETH_RGMII_PORT0; i < priv->num_ports; i++) {
-		u8 rgmii_ctrl;
-		if (!priv->used_ports[i].used)

drivers/pinctrl/mscc/Kconfig

Diff comments View file @ f83ef0d

 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 config PINCTRL_MSCC
 	bool
 config PINCTRL_MSCC_OCELOT
 	depends on SOC_OCELOT && PINCTRL_FULL && OF_CONTROL
 	select PINCTRL_MSCC
 	default y
 	bool "Microsemi ocelot family pin control driver"
 	help
 	   Support pin multiplexing and pin configuration control on
 	   Microsemi ocelot SoCs.
 config PINCTRL_MSCC_LUTON
 	depends on SOC_LUTON && PINCTRL_FULL && OF_CONTROL
 	select PINCTRL_MSCC
 	default y
 	bool "Microsemi luton family pin control driver"
 	help
 	   Support pin multiplexing and pin configuration control on
 	   Microsemi luton SoCs.
+config PINCTRL_MSCC_JR2
+	depends on SOC_JR2 && PINCTRL_FULL && OF_CONTROL
+	select PINCTRL_MSCC
+	default y
+	bool "Microsemi jr2 family pin control driver"
+	help
+	    Support pin multiplexing and pin configuration control on
+	    Microsemi jr2 SoCs.

drivers/pinctrl/mscc/Makefile

Diff comments View file @ f83ef0d

1	# SPDX-License-Identifier: (GPL-2.0+ OR MIT)	1	# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2		2
3	obj-y += mscc-common.o	3	obj-y += mscc-common.o
4	obj-$(CONFIG_PINCTRL_MSCC_OCELOT) += pinctrl-ocelot.o	4	obj-$(CONFIG_PINCTRL_MSCC_OCELOT) += pinctrl-ocelot.o
5	obj-$(CONFIG_PINCTRL_MSCC_LUTON) += pinctrl-luton.o	5	obj-$(CONFIG_PINCTRL_MSCC_LUTON) += pinctrl-luton.o
		6	obj-$(CONFIG_PINCTRL_MSCC_JR2) += pinctrl-jr2.o
6		7

drivers/pinctrl/mscc/mscc-common.c

Diff comments View file @ f83ef0d

 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
 /*
  * Microsemi SoCs pinctrl driver
  *
  * Author: <alexandre.belloni@free-electrons.com>
  * Author: <gregory.clement@bootlin.com>
  * License: Dual MIT/GPL
  * Copyright (c) 2017 Microsemi Corporation
  */
 #include <asm/gpio.h>
 #include <asm/system.h>
 #include <common.h>
 #include <config.h>
 #include <dm.h>
 #include <dm/device-internal.h>
 #include <dm/lists.h>
 #include <dm/pinctrl.h>
 #include <dm/root.h>
 #include <errno.h>
 #include <fdtdec.h>
 #include <linux/io.h>
 #include "mscc-common.h"
-#define MSCC_GPIO_OUT_SET	0x0
+static void mscc_writel(unsigned int offset, void *addr)
-#define MSCC_GPIO_OUT_CLR	0x4
+{
-#define MSCC_GPIO_OUT		0x8
+	if (offset < 32)
-#define MSCC_GPIO_IN		0xc
+		writel(BIT(offset), addr);
-#define MSCC_GPIO_OE		0x10
+	else
-#define MSCC_GPIO_INTR		0x14
+		writel(BIT(offset % 32), addr + 4);
-#define MSCC_GPIO_INTR_ENA	0x18
+}
-#define MSCC_GPIO_INTR_IDENT	0x1c
-#define MSCC_GPIO_ALT0		0x20
-#define MSCC_GPIO_ALT1		0x24
+static unsigned int mscc_readl(unsigned int offset, void *addr)
+{
+	if (offset < 32)
+		return readl(addr);
+	else
+		return readl(addr + 4);
+}
+static void mscc_setbits(unsigned int offset, void *addr)
+{
+	if (offset < 32)
+		writel(readl(addr) | BIT(offset), addr);
+	else
+		writel(readl(addr + 4) | BIT(offset % 32), addr + 4);
+}
+static void mscc_clrbits(unsigned int offset, void *addr)
+{
+	if (offset < 32)
+		writel(readl(addr) & ~BIT(offset), addr);
+	else
+		writel(readl(addr + 4) & ~BIT(offset % 32), addr + 4);
+}
 static int mscc_get_functions_count(struct udevice *dev)
 {
 	struct mscc_pinctrl *info = dev_get_priv(dev);
 	return info->num_func;
 }
 static const char *mscc_get_function_name(struct udevice *dev,
 					  unsigned int function)
 {
 	struct mscc_pinctrl *info = dev_get_priv(dev);
 	return info->function_names[function];
 }
 static int mscc_pin_function_idx(unsigned int pin, unsigned int function,
 				 const struct mscc_pin_data *mscc_pins)
 {
 	struct mscc_pin_caps *p = mscc_pins[pin].drv_data;
 	int i;
 	for (i = 0; i < MSCC_FUNC_PER_PIN; i++) {
 		if (function == p->functions[i])
 			return i;
 	}
 	return -1;
 }
 static int mscc_pinmux_set_mux(struct udevice *dev,
 			       unsigned int pin_selector, unsigned int selector)
 {
 	struct mscc_pinctrl *info = dev_get_priv(dev);
 	struct mscc_pin_caps *pin = info->mscc_pins[pin_selector].drv_data;
-	int f;
+	int f, offset, regoff;
 	f = mscc_pin_function_idx(pin_selector, selector, info->mscc_pins);
 	if (f < 0)
 		return -EINVAL;
 	/*
 	 * f is encoded on two bits.
 	 * bit 0 of f goes in BIT(pin) of ALT0, bit 1 of f goes in BIT(pin) of
 	 * ALT1
 	 * This is racy because both registers can't be updated at the same time
 	 * but it doesn't matter much for now.
 	 */
+	offset = pin->pin;
+	regoff = info->mscc_gpios[MSCC_GPIO_ALT0];
+	if (offset >= 32) {
+		offset = offset % 32;
+		regoff = info->mscc_gpios[MSCC_GPIO_ALT1];
+	}
 	if (f & BIT(0))
-		setbits_le32(info->regs + MSCC_GPIO_ALT0, BIT(pin->pin));
+		mscc_setbits(offset, info->regs + regoff);
 	else
-		clrbits_le32(info->regs + MSCC_GPIO_ALT0, BIT(pin->pin));
+		mscc_clrbits(offset, info->regs + regoff);
 	if (f & BIT(1))
-		setbits_le32(info->regs + MSCC_GPIO_ALT1, BIT(pin->pin - 1));
+		mscc_setbits(offset, info->regs + regoff + 4);
 	else
-		clrbits_le32(info->regs + MSCC_GPIO_ALT1, BIT(pin->pin - 1));
+		mscc_clrbits(offset, info->regs + regoff + 4);
 	return 0;
 }
 static int mscc_pctl_get_groups_count(struct udevice *dev)
 {
 	struct mscc_pinctrl *info = dev_get_priv(dev);
 	return info->num_pins;
 }
 static const char *mscc_pctl_get_group_name(struct udevice *dev,
 					    unsigned int group)
 {
 	struct mscc_pinctrl *info = dev_get_priv(dev);
 	return info->mscc_pins[group].name;
 }
 static int mscc_create_group_func_map(struct udevice *dev,
 				      struct mscc_pinctrl *info)
 {
 	u16 pins[info->num_pins];
 	int f, npins, i;
 	for (f = 0; f < info->num_func; f++) {
 		for (npins = 0, i = 0; i < info->num_pins; i++) {
 			if (mscc_pin_function_idx(i, f, info->mscc_pins) >= 0)
 				pins[npins++] = i;
 		}
 		info->func[f].ngroups = npins;
-		info->func[f].groups = devm_kzalloc(dev, npins *
+		info->func[f].groups = devm_kzalloc(dev, npins * sizeof(char *),
-						    sizeof(char *), GFP_KERNEL);
+						    GFP_KERNEL);
 		if (!info->func[f].groups)
 			return -ENOMEM;
 		for (i = 0; i < npins; i++)
 			info->func[f].groups[i] = info->mscc_pins[pins[i]].name;
 	}
 	return 0;
 }
 static int mscc_pinctrl_register(struct udevice *dev, struct mscc_pinctrl *info)
 {
 	int ret;
 	ret = mscc_create_group_func_map(dev, info);
 	if (ret) {
 		dev_err(dev, "Unable to create group func map.\n");
 		return ret;
 	}
 	return 0;
 }
 static int mscc_gpio_get(struct udevice *dev, unsigned int offset)
 {
 	struct mscc_pinctrl *info = dev_get_priv(dev->parent);
 	unsigned int val;
-	val = readl(info->regs + MSCC_GPIO_IN);
+	if (mscc_readl(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]) &
+	    BIT(offset % 32))
+		val = mscc_readl(offset,
+				 info->regs + info->mscc_gpios[MSCC_GPIO_OUT]);
+	else
+		val = mscc_readl(offset,
+				 info->regs + info->mscc_gpios[MSCC_GPIO_IN]);
-	return !!(val & BIT(offset));
+	return !!(val & BIT(offset % 32));
 }
 static int mscc_gpio_set(struct udevice *dev, unsigned int offset, int value)
 {
 	struct mscc_pinctrl *info = dev_get_priv(dev->parent);
 	if (value)
-		writel(BIT(offset), info->regs + MSCC_GPIO_OUT_SET);
+		mscc_writel(offset,
+			    info->regs + info->mscc_gpios[MSCC_GPIO_OUT_SET]);
 	else
-		writel(BIT(offset), info->regs + MSCC_GPIO_OUT_CLR);
+		mscc_writel(offset,
+			    info->regs + info->mscc_gpios[MSCC_GPIO_OUT_CLR]);
 	return 0;
 }
 static int mscc_gpio_get_direction(struct udevice *dev, unsigned int offset)
 {
 	struct mscc_pinctrl *info = dev_get_priv(dev->parent);
 	unsigned int val;
-	val = readl(info->regs + MSCC_GPIO_OE);
+	val = mscc_readl(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]);
-	return (val & BIT(offset)) ? GPIOF_OUTPUT : GPIOF_INPUT;
+	return (val & BIT(offset % 32)) ? GPIOF_OUTPUT : GPIOF_INPUT;
 }
 static int mscc_gpio_direction_input(struct udevice *dev, unsigned int offset)
 {
 	struct mscc_pinctrl *info = dev_get_priv(dev->parent);
-	clrbits_le32(info->regs + MSCC_GPIO_OE, BIT(offset));
+	mscc_clrbits(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]);
 	return 0;
 }
 static int mscc_gpio_direction_output(struct udevice *dev,
 				      unsigned int offset, int value)
 {
 	struct mscc_pinctrl *info = dev_get_priv(dev->parent);
-	setbits_le32(info->regs + MSCC_GPIO_OE, BIT(offset));
+	mscc_setbits(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]);
 	return mscc_gpio_set(dev, offset, value);
 }
 const struct dm_gpio_ops mscc_gpio_ops = {
 	.set_value = mscc_gpio_set,
 	.get_value = mscc_gpio_get,
 	.get_function = mscc_gpio_get_direction,
 	.direction_input = mscc_gpio_direction_input,
 	.direction_output = mscc_gpio_direction_output,
 };
 const struct pinctrl_ops mscc_pinctrl_ops = {
 	.get_pins_count = mscc_pctl_get_groups_count,
 	.get_pin_name = mscc_pctl_get_group_name,
 	.get_functions_count = mscc_get_functions_count,
 	.get_function_name = mscc_get_function_name,
 	.pinmux_set = mscc_pinmux_set_mux,
 	.set_state = pinctrl_generic_set_state,
 };
 int mscc_pinctrl_probe(struct udevice *dev, int num_func,
 		       const struct mscc_pin_data *mscc_pins, int num_pins,
-		       char *const *function_names)
+		       char * const *function_names,
+		       const unsigned long *mscc_gpios)
 {
 	struct mscc_pinctrl *priv = dev_get_priv(dev);
 	int ret;
 	priv->regs = dev_remap_addr(dev);
 	if (!priv->regs)
 		return -EINVAL;
 	priv->func = devm_kzalloc(dev, num_func * sizeof(struct mscc_pmx_func),
 				  GFP_KERNEL);
 	priv->num_func = num_func;
 	priv->mscc_pins = mscc_pins;
 	priv->num_pins = num_pins;
 	priv->function_names = function_names;
+	priv->mscc_gpios = mscc_gpios;
 	ret = mscc_pinctrl_register(dev, priv);

drivers/pinctrl/mscc/mscc-common.h

Diff comments View file @ f83ef0d

 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
 /*
  * Microsemi SoCs pinctrl driver
  *
  * Author: <alexandre.belloni@free-electrons.com>
  * License: Dual MIT/GPL
  * Copyright (c) 2017 Microsemi Corporation
  */
 #define MSCC_FUNC_PER_PIN	4
+enum mscc_regs_gpio {
+	MSCC_GPIO_OUT_SET,
+	MSCC_GPIO_OUT_CLR,
+	MSCC_GPIO_OUT,
+	MSCC_GPIO_IN,
+	MSCC_GPIO_OE,
+	MSCC_GPIO_INTR,
+	MSCC_GPIO_INTR_ENA,
+	MSCC_GPIO_INTR_IDENT,
+	MSCC_GPIO_ALT0,
+	MSCC_GPIO_ALT1,
+};
 struct mscc_pin_caps {
 	unsigned int pin;
 	unsigned char functions[MSCC_FUNC_PER_PIN];
 };
 struct mscc_pin_data {
 	const char *name;
 	struct mscc_pin_caps *drv_data;
 };
 #define MSCC_P(p, f0, f1, f2)						\
 static struct mscc_pin_caps mscc_pin_##p = {				\
 	.pin = p,							\
 	.functions = {							\
 			FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2,	\
 	},								\
 }
 struct mscc_pmx_func {
 	const char **groups;
 	unsigned int ngroups;
 };
 struct mscc_pinctrl {
 	struct udevice *dev;
 	struct pinctrl_dev *pctl;
 	void __iomem *regs;
 	struct mscc_pmx_func *func;
 	int num_func;
 	const struct mscc_pin_data *mscc_pins;
 	int num_pins;
 	char * const *function_names;
+	const unsigned long *mscc_gpios;
 };
 int mscc_pinctrl_probe(struct udevice *dev, int num_func,
 		       const struct mscc_pin_data *mscc_pins, int num_pins,
-		       char * const *function_names);
+		       char * const *function_names,
+		       const unsigned long *mscc_gpios);
 const struct pinctrl_ops mscc_pinctrl_ops;
 const struct dm_gpio_ops mscc_gpio_ops;

drivers/pinctrl/mscc/pinctrl-jr2.c

Diff comments View file @ f83ef0d

File was created	1	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	2	/*
	3	* Microsemi SoCs pinctrl driver
	4	*
	5	* Author: <horatiu.vultur@microchip.com>
	6	* Copyright (c) 2018 Microsemi Corporation
	7	*/
	8
	9	#include <common.h>
	10	#include <config.h>
	11	#include <dm.h>
	12	#include <dm/device-internal.h>
	13	#include <dm/lists.h>
	14	#include <dm/pinctrl.h>
	15	#include <dm/root.h>
	16	#include <errno.h>
	17	#include <fdtdec.h>
	18	#include <linux/io.h>
	19	#include <asm/gpio.h>
	20	#include <asm/system.h>
	21	#include "mscc-common.h"
	22
	23	enum {
	24	FUNC_NONE,
	25	FUNC_GPIO,
	26	FUNC_IRQ0_IN,
	27	FUNC_IRQ0_OUT,
	28	FUNC_IRQ1_IN,
	29	FUNC_IRQ1_OUT,
	30	FUNC_MIIM1,
	31	FUNC_MIIM2,
	32	FUNC_PCI_WAKE,
	33	FUNC_PTP0,
	34	FUNC_PTP1,
	35	FUNC_PTP2,
	36	FUNC_PTP3,
	37	FUNC_PWM,
	38	FUNC_RECO_CLK0,
	39	FUNC_RECO_CLK1,
	40	FUNC_SFP0,
	41	FUNC_SFP1,
	42	FUNC_SFP2,
	43	FUNC_SFP3,
	44	FUNC_SFP4,
	45	FUNC_SFP5,
	46	FUNC_SFP6,
	47	FUNC_SFP7,
	48	FUNC_SFP8,
	49	FUNC_SFP9,
	50	FUNC_SFP10,
	51	FUNC_SFP11,
	52	FUNC_SFP12,
	53	FUNC_SFP13,
	54	FUNC_SFP14,
	55	FUNC_SFP15,
	56	FUNC_SG0,
	57	FUNC_SG1,
	58	FUNC_SG2,
	59	FUNC_SI,
	60	FUNC_TACHO,
	61	FUNC_TWI,
	62	FUNC_TWI2,
	63	FUNC_TWI_SCL_M,
	64	FUNC_UART,
	65	FUNC_UART2,
	66	FUNC_MAX
	67	};
	68
	69	static char * const jr2_function_names[] = {
	70	[FUNC_NONE] = "none",
	71	[FUNC_GPIO] = "gpio",
	72	[FUNC_IRQ0_IN] = "irq0_in",
	73	[FUNC_IRQ0_OUT] = "irq0_out",
	74	[FUNC_IRQ1_IN] = "irq1_in",
	75	[FUNC_IRQ1_OUT] = "irq1_out",
	76	[FUNC_MIIM1] = "miim1",
	77	[FUNC_MIIM2] = "miim2",
	78	[FUNC_PCI_WAKE] = "pci_wake",
	79	[FUNC_PTP0] = "ptp0",
	80	[FUNC_PTP1] = "ptp1",
	81	[FUNC_PTP2] = "ptp2",
	82	[FUNC_PTP3] = "ptp3",
	83	[FUNC_PWM] = "pwm",
	84	[FUNC_RECO_CLK0] = "reco_clk0",
	85	[FUNC_RECO_CLK1] = "reco_clk1",
	86	[FUNC_SFP0] = "sfp0",
	87	[FUNC_SFP1] = "sfp1",
	88	[FUNC_SFP2] = "sfp2",
	89	[FUNC_SFP3] = "sfp3",
	90	[FUNC_SFP4] = "sfp4",
	91	[FUNC_SFP5] = "sfp5",
	92	[FUNC_SFP6] = "sfp6",
	93	[FUNC_SFP7] = "sfp7",
	94	[FUNC_SFP8] = "sfp8",
	95	[FUNC_SFP9] = "sfp9",
	96	[FUNC_SFP10] = "sfp10",
	97	[FUNC_SFP11] = "sfp11",
	98	[FUNC_SFP12] = "sfp12",
	99	[FUNC_SFP13] = "sfp13",
	100	[FUNC_SFP14] = "sfp14",
	101	[FUNC_SFP15] = "sfp15",
	102	[FUNC_SG0] = "sg0",
	103	[FUNC_SG1] = "sg1",
	104	[FUNC_SG2] = "sg2",
	105	[FUNC_SI] = "si",
	106	[FUNC_TACHO] = "tacho",
	107	[FUNC_TWI] = "twi",
	108	[FUNC_TWI2] = "twi2",
	109	[FUNC_TWI_SCL_M] = "twi_scl_m",
	110	[FUNC_UART] = "uart",
	111	[FUNC_UART2] = "uart2",
	112	};
	113
	114	#define JR2_P(p, f0, f1) \
	115	static struct mscc_pin_caps jr2_pin_##p = { \
	116	.pin = p, \
	117	.functions = { \
	118	FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \
	119	}, \
	120	}
	121
	122	JR2_P(0, SG0, NONE);
	123	JR2_P(1, SG0, NONE);
	124	JR2_P(2, SG0, NONE);
	125	JR2_P(3, SG0, NONE);
	126	JR2_P(4, SG1, NONE);
	127	JR2_P(5, SG1, NONE);
	128	JR2_P(6, IRQ0_IN, IRQ0_OUT);
	129	JR2_P(7, IRQ1_IN, IRQ1_OUT);
	130	JR2_P(8, PTP0, NONE);
	131	JR2_P(9, PTP1, NONE);
	132	JR2_P(10, UART, NONE);
	133	JR2_P(11, UART, NONE);
	134	JR2_P(12, SG1, NONE);
	135	JR2_P(13, SG1, NONE);
	136	JR2_P(14, TWI, TWI_SCL_M);
	137	JR2_P(15, TWI, NONE);
	138	JR2_P(16, SI, TWI_SCL_M);
	139	JR2_P(17, SI, TWI_SCL_M);
	140	JR2_P(18, SI, TWI_SCL_M);
	141	JR2_P(19, PCI_WAKE, NONE);
	142	JR2_P(20, IRQ0_OUT, TWI_SCL_M);
	143	JR2_P(21, IRQ1_OUT, TWI_SCL_M);
	144	JR2_P(22, TACHO, NONE);
	145	JR2_P(23, PWM, NONE);
	146	JR2_P(24, UART2, NONE);
	147	JR2_P(25, UART2, SI);
	148	JR2_P(26, PTP2, SI);
	149	JR2_P(27, PTP3, SI);
	150	JR2_P(28, TWI2, SI);
	151	JR2_P(29, TWI, SI);
	152	JR2_P(30, SG2, SI);
	153	JR2_P(31, SG2, SI);
	154	JR2_P(32, SG2, SI);
	155	JR2_P(33, SG2, SI);
	156	JR2_P(34, NONE, TWI_SCL_M);
	157	JR2_P(35, NONE, TWI_SCL_M);
	158	JR2_P(36, NONE, TWI_SCL_M);
	159	JR2_P(37, NONE, TWI_SCL_M);
	160	JR2_P(38, NONE, TWI_SCL_M);
	161	JR2_P(39, NONE, TWI_SCL_M);
	162	JR2_P(40, NONE, TWI_SCL_M);
	163	JR2_P(41, NONE, TWI_SCL_M);
	164	JR2_P(42, NONE, TWI_SCL_M);
	165	JR2_P(43, NONE, TWI_SCL_M);
	166	JR2_P(44, NONE, SFP8);
	167	JR2_P(45, NONE, SFP9);
	168	JR2_P(46, NONE, SFP10);
	169	JR2_P(47, NONE, SFP11);
	170	JR2_P(48, SFP0, NONE);
	171	JR2_P(49, SFP1, SI);
	172	JR2_P(50, SFP2, SI);
	173	JR2_P(51, SFP3, SI);
	174	JR2_P(52, SFP4, NONE);
	175	JR2_P(53, SFP5, NONE);
	176	JR2_P(54, SFP6, NONE);
	177	JR2_P(55, SFP7, NONE);
	178	JR2_P(56, MIIM1, SFP12);
	179	JR2_P(57, MIIM1, SFP13);
	180	JR2_P(58, MIIM2, SFP14);
	181	JR2_P(59, MIIM2, SFP15);
	182	JR2_P(60, NONE, NONE);
	183	JR2_P(61, NONE, NONE);
	184	JR2_P(62, NONE, NONE);
	185	JR2_P(63, NONE, NONE);
	186
	187	#define JR2_PIN(n) { \
	188	.name = "GPIO_"#n, \
	189	.drv_data = &jr2_pin_##n \
	190	}
	191
	192	static const struct mscc_pin_data jr2_pins[] = {
	193	JR2_PIN(0),
	194	JR2_PIN(1),
	195	JR2_PIN(2),
	196	JR2_PIN(3),
	197	JR2_PIN(4),
	198	JR2_PIN(5),
	199	JR2_PIN(6),
	200	JR2_PIN(7),
	201	JR2_PIN(8),
	202	JR2_PIN(9),
	203	JR2_PIN(10),
	204	JR2_PIN(11),
	205	JR2_PIN(12),
	206	JR2_PIN(13),
	207	JR2_PIN(14),
	208	JR2_PIN(15),
	209	JR2_PIN(16),
	210	JR2_PIN(17),
	211	JR2_PIN(18),
	212	JR2_PIN(19),
	213	JR2_PIN(20),
	214	JR2_PIN(21),
	215	JR2_PIN(22),
	216	JR2_PIN(23),
	217	JR2_PIN(24),
	218	JR2_PIN(25),
	219	JR2_PIN(26),
	220	JR2_PIN(27),
	221	JR2_PIN(28),
	222	JR2_PIN(29),
	223	JR2_PIN(30),
	224	JR2_PIN(31),
	225	JR2_PIN(32),
	226	JR2_PIN(33),
	227	JR2_PIN(34),
	228	JR2_PIN(35),
	229	JR2_PIN(36),
	230	JR2_PIN(37),
	231	JR2_PIN(38),
	232	JR2_PIN(39),
	233	JR2_PIN(40),
	234	JR2_PIN(41),
	235	JR2_PIN(42),
	236	JR2_PIN(43),
	237	JR2_PIN(44),
	238	JR2_PIN(45),
	239	JR2_PIN(46),
	240	JR2_PIN(47),
	241	JR2_PIN(48),
	242	JR2_PIN(49),
	243	JR2_PIN(50),
	244	JR2_PIN(51),
	245	JR2_PIN(52),
	246	JR2_PIN(53),
	247	JR2_PIN(54),
	248	JR2_PIN(55),
	249	JR2_PIN(56),
	250	JR2_PIN(57),
	251	JR2_PIN(58),
	252	JR2_PIN(59),
	253	JR2_PIN(60),
	254	JR2_PIN(61),
	255	JR2_PIN(62),
	256	JR2_PIN(63),
	257	};
	258
	259	static const unsigned long jr2_gpios[] = {
	260	[MSCC_GPIO_OUT_SET] = 0x00,
	261	[MSCC_GPIO_OUT_CLR] = 0x08,
	262	[MSCC_GPIO_OUT] = 0x10,
	263	[MSCC_GPIO_IN] = 0x18,
	264	[MSCC_GPIO_OE] = 0x20,
	265	[MSCC_GPIO_INTR] = 0x28,
	266	[MSCC_GPIO_INTR_ENA] = 0x30,
	267	[MSCC_GPIO_INTR_IDENT] = 0x38,
	268	[MSCC_GPIO_ALT0] = 0x40,
	269	[MSCC_GPIO_ALT1] = 0x48,
	270	};
	271
	272	static int jr2_gpio_probe(struct udevice *dev)
	273	{
	274	struct gpio_dev_priv *uc_priv;
	275
	276	uc_priv = dev_get_uclass_priv(dev);
	277	uc_priv->bank_name = "jr2-gpio";
	278	uc_priv->gpio_count = ARRAY_SIZE(jr2_pins);
	279
	280	return 0;
	281	}
	282
	283	static struct driver jr2_gpio_driver = {
	284	.name = "jr2-gpio",
	285	.id = UCLASS_GPIO,
	286	.probe = jr2_gpio_probe,
	287	.ops = &mscc_gpio_ops,
	288	};
	289
	290	static int jr2_pinctrl_probe(struct udevice *dev)
	291	{
	292	int ret;
	293
	294	ret = mscc_pinctrl_probe(dev, FUNC_MAX, jr2_pins,
	295	ARRAY_SIZE(jr2_pins),
	296	jr2_function_names,
	297	jr2_gpios);
	298
	299	if (ret)
	300	return ret;
	301
	302	ret = device_bind(dev, &jr2_gpio_driver, "jr2-gpio", NULL,
	303	dev_of_offset(dev), NULL);
	304
	305	if (ret)
	306	return ret;
	307
	308	return 0;
	309	}
	310
	311	static const struct udevice_id jr2_pinctrl_of_match[] = {
	312	{ .compatible = "mscc,jaguar2-pinctrl" },
	313	{},
	314	};
	315
	316	U_BOOT_DRIVER(jr2_pinctrl) = {
	317	.name = "jr2-pinctrl",
	318	.id = UCLASS_PINCTRL,
	319	.of_match = of_match_ptr(jr2_pinctrl_of_match),
	320	.probe = jr2_pinctrl_probe,
	321	.priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
	322	.ops = &mscc_pinctrl_ops,
	323	};
	324

drivers/pinctrl/mscc/pinctrl-luton.c

Diff comments View file @ f83ef0d

 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
 /*
  * Microsemi SoCs pinctrl driver
  *
  * Author: <gregory.clement@bootlin.com>
  * License: Dual MIT/GPL
  * Copyright (c) 2018 Microsemi Corporation
  */
 #include <common.h>
 #include <config.h>
 #include <dm.h>
 #include <dm/device-internal.h>
 #include <dm/lists.h>
 #include <dm/pinctrl.h>
 #include <dm/root.h>
 #include <errno.h>
 #include <fdtdec.h>
 #include <linux/io.h>
 #include <asm/gpio.h>
 #include <asm/system.h>
 #include "mscc-common.h"
 enum {
 	FUNC_NONE,
 	FUNC_GPIO,
 	FUNC_SIO,
 	FUNC_TACHO,
 	FUNC_TWI,
 	FUNC_PHY_LED,
 	FUNC_EXT_IRQ,
 	FUNC_SFP,
 	FUNC_SI,
 	FUNC_PWM,
 	FUNC_UART,
 	FUNC_MAX
 };
 static char * const luton_function_names[] = {
 	[FUNC_NONE]		= "none",
 	[FUNC_GPIO]		= "gpio",
 	[FUNC_SIO]		= "sio",
 	[FUNC_TACHO]		= "tacho",
 	[FUNC_TWI]		= "twi",
 	[FUNC_PHY_LED]		= "phy_led",
 	[FUNC_EXT_IRQ]		= "ext_irq",
 	[FUNC_SFP]		= "sfp",
 	[FUNC_SI]		= "si",
 	[FUNC_PWM]		= "pwm",
 	[FUNC_UART]		= "uart",
 };
 MSCC_P(0,  SIO,       NONE,      NONE);
 MSCC_P(1,  SIO,       NONE,      NONE);
 MSCC_P(2,  SIO,       NONE,      NONE);
 MSCC_P(3,  SIO,       NONE,      NONE);
 MSCC_P(4,  TACHO,     NONE,      NONE);
 MSCC_P(5,  TWI,       PHY_LED,   NONE);
 MSCC_P(6,  TWI,       PHY_LED,   NONE);
 MSCC_P(7,  NONE,      PHY_LED,   NONE);
 MSCC_P(8,  EXT_IRQ,   PHY_LED,   NONE);
 MSCC_P(9,  EXT_IRQ,   PHY_LED,   NONE);
 MSCC_P(10, SFP,       PHY_LED,   NONE);
 MSCC_P(11, SFP,       PHY_LED,   NONE);
 MSCC_P(12, SFP,       PHY_LED,   NONE);
 MSCC_P(13, SFP,       PHY_LED,   NONE);
 MSCC_P(14, SI,        PHY_LED,   NONE);
 MSCC_P(15, SI,        PHY_LED,   NONE);
 MSCC_P(16, SI,        PHY_LED,   NONE);
 MSCC_P(17, SFP,       PHY_LED,   NONE);
 MSCC_P(18, SFP,       PHY_LED,   NONE);
 MSCC_P(19, SFP,       PHY_LED,   NONE);
 MSCC_P(20, SFP,       PHY_LED,   NONE);
 MSCC_P(21, SFP,       PHY_LED,   NONE);
 MSCC_P(22, SFP,       PHY_LED,   NONE);
 MSCC_P(23, SFP,       PHY_LED,   NONE);
 MSCC_P(24, SFP,       PHY_LED,   NONE);
 MSCC_P(25, SFP,       PHY_LED,   NONE);
 MSCC_P(26, SFP,       PHY_LED,   NONE);
 MSCC_P(27, SFP,       PHY_LED,   NONE);
 MSCC_P(28, SFP,       PHY_LED,   NONE);
 MSCC_P(29, PWM,       NONE,      NONE);
 MSCC_P(30, UART,      NONE,      NONE);
 MSCC_P(31, UART,      NONE,      NONE);
 #define LUTON_PIN(n) {						\
 	.name = "GPIO_"#n,					\
 	.drv_data = &mscc_pin_##n				\
 }
 static const struct mscc_pin_data luton_pins[] = {
 	LUTON_PIN(0),
 	LUTON_PIN(1),
 	LUTON_PIN(2),
 	LUTON_PIN(3),
 	LUTON_PIN(4),
 	LUTON_PIN(5),
 	LUTON_PIN(6),
 	LUTON_PIN(7),
 	LUTON_PIN(8),
 	LUTON_PIN(9),
 	LUTON_PIN(10),
 	LUTON_PIN(11),
 	LUTON_PIN(12),
 	LUTON_PIN(13),
 	LUTON_PIN(14),
 	LUTON_PIN(15),
 	LUTON_PIN(16),
 	LUTON_PIN(17),
 	LUTON_PIN(18),
 	LUTON_PIN(19),
 	LUTON_PIN(20),
 	LUTON_PIN(21),
 	LUTON_PIN(22),
 	LUTON_PIN(23),
 	LUTON_PIN(24),
 	LUTON_PIN(25),
 	LUTON_PIN(26),
 	LUTON_PIN(27),
 	LUTON_PIN(28),
 	LUTON_PIN(29),
 	LUTON_PIN(30),
 	LUTON_PIN(31),
 };
+static const unsigned long luton_gpios[] = {
+	[MSCC_GPIO_OUT_SET] = 0x00,
+	[MSCC_GPIO_OUT_CLR] = 0x04,
+	[MSCC_GPIO_OUT] = 0x08,
+	[MSCC_GPIO_IN] = 0x0c,
+	[MSCC_GPIO_OE] = 0x10,
+	[MSCC_GPIO_INTR] = 0x14,
+	[MSCC_GPIO_INTR_ENA] = 0x18,
+	[MSCC_GPIO_INTR_IDENT] = 0x1c,
+	[MSCC_GPIO_ALT0] = 0x20,
+	[MSCC_GPIO_ALT1] = 0x24,
+};
 static int luton_gpio_probe(struct udevice *dev)
 {
 	struct gpio_dev_priv *uc_priv;
 	uc_priv = dev_get_uclass_priv(dev);
 	uc_priv->bank_name = "luton-gpio";
 	uc_priv->gpio_count = ARRAY_SIZE(luton_pins);
 	return 0;
 }
 static struct driver luton_gpio_driver = {
 	.name	= "luton-gpio",
 	.id	= UCLASS_GPIO,
 	.probe	= luton_gpio_probe,
 	.ops	= &mscc_gpio_ops,
 };
 int luton_pinctrl_probe(struct udevice *dev)
 {
 	int ret;
 	ret = mscc_pinctrl_probe(dev, FUNC_MAX, luton_pins,
-				 ARRAY_SIZE(luton_pins), luton_function_names);
+				 ARRAY_SIZE(luton_pins), luton_function_names,
+				 luton_gpios);
 	if (ret)
 		return ret;
 	ret = device_bind(dev, &luton_gpio_driver, "luton-gpio", NULL,
 			  dev_of_offset(dev), NULL);
 	return 0;
 }
 static const struct udevice_id luton_pinctrl_of_match[] = {
 	{.compatible = "mscc,luton-pinctrl"},
 	{},
 };
 U_BOOT_DRIVER(luton_pinctrl) = {
 	.name = "luton-pinctrl",
 	.id = UCLASS_PINCTRL,
 	.of_match = of_match_ptr(luton_pinctrl_of_match),
 	.probe = luton_pinctrl_probe,
 	.priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
 	.ops = &mscc_pinctrl_ops,
 };

drivers/pinctrl/mscc/pinctrl-ocelot.c

Diff comments View file @ f83ef0d

 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
 /*
  * Microsemi SoCs pinctrl driver
  *
  * Author: <alexandre.belloni@free-electrons.com>
  * Author: <gregory.clement@bootlin.com>
  * License: Dual MIT/GPL
  * Copyright (c) 2017 Microsemi Corporation
  */
 #include <asm/gpio.h>
 #include <asm/system.h>
 #include <common.h>
 #include <config.h>
 #include <dm.h>
 #include <dm/device-internal.h>
 #include <dm/lists.h>
 #include <dm/pinctrl.h>
 #include <dm/root.h>
 #include <errno.h>
 #include <fdtdec.h>
 #include <linux/io.h>
 #include "mscc-common.h"
 enum {
 	FUNC_NONE,
 	FUNC_GPIO,
 	FUNC_IRQ0_IN,
 	FUNC_IRQ0_OUT,
 	FUNC_IRQ1_IN,
 	FUNC_IRQ1_OUT,
 	FUNC_MIIM1,
 	FUNC_PCI_WAKE,
 	FUNC_PTP0,
 	FUNC_PTP1,
 	FUNC_PTP2,
 	FUNC_PTP3,
 	FUNC_PWM,
 	FUNC_RECO_CLK0,
 	FUNC_RECO_CLK1,
 	FUNC_SFP0,
 	FUNC_SFP1,
 	FUNC_SFP2,
 	FUNC_SFP3,
 	FUNC_SFP4,
 	FUNC_SFP5,
 	FUNC_SG0,
 	FUNC_SI,
 	FUNC_TACHO,
 	FUNC_TWI,
 	FUNC_TWI_SCL_M,
 	FUNC_UART,
 	FUNC_UART2,
 	FUNC_MAX
 };
 static char * const ocelot_function_names[] = {
 	[FUNC_NONE]		= "none",
 	[FUNC_GPIO]		= "gpio",
 	[FUNC_IRQ0_IN]		= "irq0_in",
 	[FUNC_IRQ0_OUT]		= "irq0_out",
 	[FUNC_IRQ1_IN]		= "irq1_in",
 	[FUNC_IRQ1_OUT]		= "irq1_out",
 	[FUNC_MIIM1]		= "miim1",
 	[FUNC_PCI_WAKE]		= "pci_wake",
 	[FUNC_PTP0]		= "ptp0",
 	[FUNC_PTP1]		= "ptp1",
 	[FUNC_PTP2]		= "ptp2",
 	[FUNC_PTP3]		= "ptp3",
 	[FUNC_PWM]		= "pwm",
 	[FUNC_RECO_CLK0]	= "reco_clk0",
 	[FUNC_RECO_CLK1]	= "reco_clk1",
 	[FUNC_SFP0]		= "sfp0",
 	[FUNC_SFP1]		= "sfp1",
 	[FUNC_SFP2]		= "sfp2",
 	[FUNC_SFP3]		= "sfp3",
 	[FUNC_SFP4]		= "sfp4",
 	[FUNC_SFP5]		= "sfp5",
 	[FUNC_SG0]		= "sg0",
 	[FUNC_SI]		= "si",
 	[FUNC_TACHO]		= "tacho",
 	[FUNC_TWI]		= "twi",
 	[FUNC_TWI_SCL_M]	= "twi_scl_m",
 	[FUNC_UART]		= "uart",
 	[FUNC_UART2]		= "uart2",
 };
 MSCC_P(0,  SG0,       NONE,      NONE);
 MSCC_P(1,  SG0,       NONE,      NONE);
 MSCC_P(2,  SG0,       NONE,      NONE);
 MSCC_P(3,  SG0,       NONE,      NONE);
 MSCC_P(4,  IRQ0_IN,   IRQ0_OUT,  TWI);
 MSCC_P(5,  IRQ1_IN,   IRQ1_OUT,  PCI_WAKE);
 MSCC_P(6,  UART,      TWI_SCL_M, NONE);
 MSCC_P(7,  UART,      TWI_SCL_M, NONE);
 MSCC_P(8,  SI,        TWI_SCL_M, IRQ0_OUT);
 MSCC_P(9,  SI,        TWI_SCL_M, IRQ1_OUT);
 MSCC_P(10, PTP2,      TWI_SCL_M, SFP0);
 MSCC_P(11, PTP3,      TWI_SCL_M, SFP1);
 MSCC_P(12, UART2,     TWI_SCL_M, SFP2);
 MSCC_P(13, UART2,     TWI_SCL_M, SFP3);
 MSCC_P(14, MIIM1,     TWI_SCL_M, SFP4);
 MSCC_P(15, MIIM1,     TWI_SCL_M, SFP5);
 MSCC_P(16, TWI,       NONE,      SI);
 MSCC_P(17, TWI,       TWI_SCL_M, SI);
 MSCC_P(18, PTP0,      TWI_SCL_M, NONE);
 MSCC_P(19, PTP1,      TWI_SCL_M, NONE);
 MSCC_P(20, RECO_CLK0, TACHO,     NONE);
 MSCC_P(21, RECO_CLK1, PWM,       NONE);
 #define OCELOT_PIN(n) {						\
 	.name = "GPIO_"#n,					\
 	.drv_data = &mscc_pin_##n				\
 }
 static const struct mscc_pin_data ocelot_pins[] = {
 	OCELOT_PIN(0),
 	OCELOT_PIN(1),
 	OCELOT_PIN(2),
 	OCELOT_PIN(3),
 	OCELOT_PIN(4),
 	OCELOT_PIN(5),
 	OCELOT_PIN(6),
 	OCELOT_PIN(7),
 	OCELOT_PIN(8),
 	OCELOT_PIN(9),
 	OCELOT_PIN(10),
 	OCELOT_PIN(11),
 	OCELOT_PIN(12),
 	OCELOT_PIN(13),
 	OCELOT_PIN(14),
 	OCELOT_PIN(15),
 	OCELOT_PIN(16),
 	OCELOT_PIN(17),
 	OCELOT_PIN(18),
 	OCELOT_PIN(19),
 	OCELOT_PIN(20),
 	OCELOT_PIN(21),
 };
+static const unsigned long ocelot_gpios[] = {
+	[MSCC_GPIO_OUT_SET] = 0x00,
+	[MSCC_GPIO_OUT_CLR] = 0x04,
+	[MSCC_GPIO_OUT] = 0x08,
+	[MSCC_GPIO_IN] = 0x0c,
+	[MSCC_GPIO_OE] = 0x10,
+	[MSCC_GPIO_INTR] = 0x14,
+	[MSCC_GPIO_INTR_ENA] = 0x18,
+	[MSCC_GPIO_INTR_IDENT] = 0x1c,
+	[MSCC_GPIO_ALT0] = 0x20,
+	[MSCC_GPIO_ALT1] = 0x24,
+};
 static int ocelot_gpio_probe(struct udevice *dev)
 {
 	struct gpio_dev_priv *uc_priv;
 	uc_priv = dev_get_uclass_priv(dev);
 	uc_priv->bank_name = "ocelot-gpio";
 	uc_priv->gpio_count = ARRAY_SIZE(ocelot_pins);
 	return 0;
 }
 static struct driver ocelot_gpio_driver = {
 	.name	= "ocelot-gpio",
 	.id	= UCLASS_GPIO,
 	.probe	= ocelot_gpio_probe,
 	.ops	= &mscc_gpio_ops,
 };
 int ocelot_pinctrl_probe(struct udevice *dev)
 {
 	int ret;
 	ret = mscc_pinctrl_probe(dev, FUNC_MAX, ocelot_pins,
 				 ARRAY_SIZE(ocelot_pins),
-				 ocelot_function_names);
+				 ocelot_function_names,
+				 ocelot_gpios);
 	if (ret)
 		return ret;
 	ret = device_bind(dev, &ocelot_gpio_driver, "ocelot-gpio", NULL,
 			  dev_of_offset(dev), NULL);
 	return ret;
 }
 static const struct udevice_id ocelot_pinctrl_of_match[] = {
 	{.compatible = "mscc,ocelot-pinctrl"},
 	{},
 };
 U_BOOT_DRIVER(ocelot_pinctrl) = {
 	.name = "ocelot-pinctrl",
 	.id = UCLASS_PINCTRL,
 	.of_match = of_match_ptr(ocelot_pinctrl_of_match),
 	.probe = ocelot_pinctrl_probe,
 	.priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
 	.ops = &mscc_pinctrl_ops,
 };

drivers/spi/Kconfig

Diff comments View file @ f83ef0d

 menuconfig SPI
 	bool "SPI Support"
 if SPI
 config DM_SPI
 	bool "Enable Driver Model for SPI drivers"
 	depends on DM
 	help
 	  Enable driver model for SPI. The SPI slave interface
 	  (spi_setup_slave(), spi_xfer(), etc.) is then implemented by
 	  the SPI uclass. Drivers provide methods to access the SPI
 	  buses that they control. The uclass interface is defined in
 	  include/spi.h. The existing spi_slave structure is attached
 	  as 'parent data' to every slave on each bus. Slaves
 	  typically use driver-private data instead of extending the
 	  spi_slave structure.
 if DM_SPI
 config SPI_MEM
 	bool "SPI memory extension"
 	help
 	  Enable this option if you want to enable the SPI memory extension.
 	  This extension is meant to simplify interaction with SPI memories
 	  by providing an high-level interface to send memory-like commands.
 config ALTERA_SPI
 	bool "Altera SPI driver"
 	help
 	  Enable the Altera SPI driver. This driver can be used to
 	  access the SPI NOR flash on platforms embedding this Altera
 	  IP core. Please find details on the "Embedded Peripherals IP
 	  User Guide" of Altera.
 config ATCSPI200_SPI
 	bool "Andestech ATCSPI200 SPI driver"
 	help
 	  Enable the Andestech ATCSPI200 SPI driver. This driver can be
 	  used to access the SPI flash on AE3XX and AE250 platforms embedding
 	  this Andestech IP core.
 config ATH79_SPI
 	bool "Atheros SPI driver"
 	depends on ARCH_ATH79
 	help
 	  Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was used
 	  to access SPI NOR flash and other SPI peripherals. This driver
 	  uses driver model and requires a device tree binding to operate.
 	  please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
 config ATMEL_SPI
 	bool "Atmel SPI driver"
 	default y if ARCH_AT91
 	help
 	  This enables driver for the Atmel SPI Controller, present on
 	  many AT91 (ARM) chips. This driver can be used to access
 	  the SPI Flash, such as AT25DF321.
 config BCM63XX_HSSPI
 	bool "BCM63XX HSSPI driver"
 	depends on ARCH_BMIPS
 	help
 	  Enable the BCM6328 HSSPI driver. This driver can be used to
 	  access the SPI NOR flash on platforms embedding this Broadcom
 	  SPI core.
 config BCM63XX_SPI
 	bool "BCM6348 SPI driver"
 	depends on ARCH_BMIPS
 	help
 	  Enable the BCM6348/BCM6358 SPI driver. This driver can be used to
 	  access the SPI NOR flash on platforms embedding these Broadcom
 	  SPI cores.
 config BCMSTB_SPI
 	bool "BCMSTB SPI driver"
 	help
 	  Enable the Broadcom set-top box SPI driver. This driver can
 	  be used to access the SPI flash on platforms embedding this
 	  Broadcom SPI core.
 config CADENCE_QSPI
 	bool "Cadence QSPI driver"
 	help
 	  Enable the Cadence Quad-SPI (QSPI) driver. This driver can be
 	  used to access the SPI NOR flash on platforms embedding this
 	  Cadence IP core.
 config DESIGNWARE_SPI
 	bool "Designware SPI driver"
 	help
 	  Enable the Designware SPI driver. This driver can be used to
 	  access the SPI NOR flash on platforms embedding this Designware
 	  IP core.
 config EXYNOS_SPI
 	bool "Samsung Exynos SPI driver"
 	help
 	  Enable the Samsung Exynos SPI driver. This driver can be used to
 	  access the SPI NOR flash on platforms embedding this Samsung
 	  Exynos IP core.
 config FSL_DSPI
 	bool "Freescale DSPI driver"
 	help
 	  Enable the Freescale DSPI driver. This driver can be used to
 	  access the SPI NOR flash and SPI Data flash on platforms embedding
 	  this Freescale DSPI IP core. LS102xA and Colibri VF50/VF61 platforms
 	  use this driver.
 config ICH_SPI
 	bool "Intel ICH SPI driver"
 	help
 	  Enable the Intel ICH SPI driver. This driver can be used to
 	  access the SPI NOR flash on platforms embedding this Intel
 	  ICH IP core.
 config MESON_SPIFC
 	bool "Amlogic Meson SPI Flash Controller driver"
 	depends on ARCH_MESON
 	help
 	  Enable the Amlogic Meson SPI Flash Controller SPIFC) driver.
 	  This driver can be used to access the SPI NOR flash chips on
 	  Amlogic Meson SoCs.
 config MPC8XX_SPI
 	bool "MPC8XX SPI Driver"
 	depends on MPC8xx
 	help
 	  Enable support for SPI on MPC8XX
 config MT7621_SPI
 	bool "MediaTek MT7621 SPI driver"
 	depends on ARCH_MT7620
 	help
 	  Enable the MT7621 SPI driver. This driver can be used to access
 	  the SPI NOR flash on platforms embedding this Ralink / MediaTek
 	  SPI core, like MT7621/7628/7688.
 config MTK_QSPI
 	bool "Mediatek QSPI driver"
 	help
 	  Enable the Mediatek QSPI driver. This driver can be
 	  used to access the SPI NOR flash on platforms embedding this
 	  Mediatek QSPI IP core.
 config MVEBU_A3700_SPI
 	bool "Marvell Armada 3700 SPI driver"
 	select CLK_ARMADA_3720
 	help
 	  Enable the Marvell Armada 3700 SPI driver. This driver can be
 	  used to access the SPI NOR flash on platforms embedding this
 	  Marvell IP core.
 config PIC32_SPI
 	bool "Microchip PIC32 SPI driver"
 	depends on MACH_PIC32
 	help
 	  Enable the Microchip PIC32 SPI driver. This driver can be used
 	  to access the SPI NOR flash, MMC-over-SPI on platforms based on
 	  Microchip PIC32 family devices.
 config PL022_SPI
 	bool "ARM AMBA PL022 SSP controller driver"
 	depends on ARM
 	help
 	  This selects the ARM(R) AMBA(R) PrimeCell PL022 SSP
 	  controller. If you have an embedded system with an AMBA(R)
 	  bus and a PL022 controller, say Y or M here.
 config RENESAS_RPC_SPI
 	bool "Renesas RPC SPI driver"
 	depends on RCAR_GEN3
 	help
 	  Enable the Renesas RPC SPI driver, used to access SPI NOR flash
 	  on Renesas RCar Gen3 SoCs. This uses driver model and requires a
 	  device tree binding to operate.
 config ROCKCHIP_SPI
 	bool "Rockchip SPI driver"
 	help
 	  Enable the Rockchip SPI driver, used to access SPI NOR flash and
 	  other SPI peripherals (such as the Chrome OS EC) on Rockchip SoCs.
 	  This uses driver model and requires a device tree binding to
 	  operate.
 config SANDBOX_SPI
 	bool "Sandbox SPI driver"
 	depends on SANDBOX && DM
 	help
 	  Enable SPI support for sandbox. This is an emulation of a real SPI
 	  bus. Devices can be attached to the bus using the device tree
 	  which specifies the driver to use. As an example, see this device
 	  tree fragment from sandbox.dts. It shows that the SPI bus has a
 	  single flash device on chip select 0 which is emulated by the driver
 	  for "sandbox,spi-flash", which is in drivers/mtd/spi/sandbox.c.
 	  spi@0 {
 		#address-cells = <1>;
 		#size-cells = <0>;
 		reg = <0>;
 		compatible = "sandbox,spi";
 		cs-gpios = <0>, <&gpio_a 0>;
 		flash@0 {
 			reg = <0>;
 			compatible = "spansion,m25p16", "sandbox,spi-flash";
 			spi-max-frequency = <40000000>;
 			sandbox,filename = "spi.bin";
 		};
 	  };
 config STM32_QSPI
 	bool "STM32F7 QSPI driver"
 	depends on STM32F7
 	help
 	  Enable the STM32F7 Quad-SPI (QSPI) driver. This driver can be
 	  used to access the SPI NOR flash chips on platforms embedding
 	  this ST IP core.
 config SUN4I_SPI
 	bool "Allwinner A10 SoCs SPI controller"
 	help
 	  SPI driver for Allwinner sun4i, sun5i and sun7i SoCs
 config TEGRA114_SPI
 	bool "nVidia Tegra114 SPI driver"
 	help
 	  Enable the nVidia Tegra114 SPI driver. This driver can be used to
 	  access the SPI NOR flash on platforms embedding this nVidia Tegra114
 	  IP core.
 	  This controller is different than the older SoCs SPI controller and
 	  also register interface get changed with this controller.
 config TEGRA20_SFLASH
 	bool "nVidia Tegra20 Serial Flash controller driver"
 	help
 	  Enable the nVidia Tegra20 Serial Flash controller driver. This driver
 	  can be used to access the SPI NOR flash on platforms embedding this
 	  nVidia Tegra20 IP core.
 config TEGRA20_SLINK
 	bool "nVidia Tegra20/Tegra30 SLINK driver"
 	help
 	  Enable the nVidia Tegra20/Tegra30 SLINK driver. This driver can
 	  be used to access the SPI NOR flash on platforms embedding this
 	  nVidia Tegra20/Tegra30 IP cores.
 config TEGRA210_QSPI
 	bool "nVidia Tegra210 QSPI driver"
 	help
 	  Enable the Tegra Quad-SPI (QSPI) driver for T210. This driver
 	  be used to access SPI chips on platforms embedding this
 	  NVIDIA Tegra210 IP core.
 config XILINX_SPI
 	bool "Xilinx SPI driver"
 	help
 	  Enable the Xilinx SPI driver from the Xilinx EDK. This SPI
 	  controller support 8 bit SPI transfers only, with or w/o FIFO.
 	  For more info on Xilinx SPI Register Definitions and Overview
 	  see driver file - drivers/spi/xilinx_spi.c
 config ZYNQ_SPI
 	bool "Zynq SPI driver"
 	depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL
 	help
 	  Enable the Zynq SPI driver. This driver can be used to
 	  access the SPI NOR flash on platforms embedding this Zynq
 	  SPI IP core.
 config ZYNQ_QSPI
 	bool "Zynq QSPI driver"
 	depends on ARCH_ZYNQ
 	help
 	  Enable the Zynq Quad-SPI (QSPI) driver. This driver can be
 	  used to access the SPI NOR flash on platforms embedding this
 	  Zynq QSPI IP core. This IP is used to connect the flash in
 	  4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel.
 config ZYNQMP_GQSPI
 	bool "Configure ZynqMP Generic QSPI"
 	depends on ARCH_ZYNQMP || ARCH_VERSAL
 	help
 	  This option is used to enable ZynqMP QSPI controller driver which
 	  is used to communicate with qspi flash devices.
 endif # if DM_SPI
 config SOFT_SPI
 	bool "Soft SPI driver"
 	help
 	 Enable Soft SPI driver. This driver is to use GPIO simulate
 	 the SPI protocol.
+config MSCC_BB_SPI
+	bool "MSCC bitbang SPI driver"
+	depends on SOC_VCOREIII
+	help
+	  Enable MSCC bitbang SPI driver. This driver can be used on
+	  MSCC SOCs.
 config CF_SPI
 	bool "ColdFire SPI driver"
 	help
 	  Enable the ColdFire SPI driver. This driver can be used on
 	  some m68k SoCs.
 config FSL_ESPI
 	bool "Freescale eSPI driver"
 	help
 	  Enable the Freescale eSPI driver. This driver can be used to
 	  access the SPI interface and SPI NOR flash on platforms embedding
 	  this Freescale eSPI IP core.
 config FSL_QSPI
 	bool "Freescale QSPI driver"
 	help
 	  Enable the Freescale Quad-SPI (QSPI) driver. This driver can be
 	  used to access the SPI NOR flash on platforms embedding this
 	  Freescale IP core.
 config DAVINCI_SPI
 	bool "Davinci & Keystone SPI driver"
 	depends on ARCH_DAVINCI || ARCH_KEYSTONE
 	help
 	  Enable the Davinci SPI driver
 config SH_SPI
 	bool "SuperH SPI driver"
 	help
 	  Enable the SuperH SPI controller driver. This driver can be used
 	  on various SuperH SoCs, such as SH7757.
 config SH_QSPI
 	bool "Renesas Quad SPI driver"
 	help
 	  Enable the Renesas Quad SPI controller driver. This driver can be
 	  used on Renesas SoCs.
 config TI_QSPI
 	bool "TI QSPI driver"
 	help
 	  Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms.
 	  This driver support spi flash single, quad and memory reads.
 config KIRKWOOD_SPI
 	bool "Marvell Kirkwood SPI Driver"
 	help
 	  Enable support for SPI on various Marvell SoCs, such as
 	  Kirkwood and Armada 375.
 config LPC32XX_SSP
 	bool "LPC32XX SPI Driver"
 	help
 	  Enable support for SPI on LPC32xx
 config MPC8XXX_SPI
 	bool "MPC8XXX SPI Driver"
 	help
 	  Enable support for SPI on the MPC8XXX PowerPC SoCs.
 config MXC_SPI
 	bool "MXC SPI Driver"
 	help
 	  Enable the MXC SPI controller driver. This driver can be used
 	  on various i.MX SoCs such as i.MX31/35/51/6/7.
 config MXS_SPI
 	bool "MXS SPI Driver"
 	help
 	  Enable the MXS SPI controller driver. This driver can be used
 	  on the i.MX23 and i.MX28 SoCs.
 config OMAP3_SPI
 	bool "McSPI driver for OMAP"
 	help
 	  SPI master controller for OMAP24XX and later Multichannel SPI
 	  (McSPI). This driver be used to access SPI chips on platforms
 	  embedding this OMAP3 McSPI IP core.
 endif # menu "SPI Support"

drivers/spi/Makefile

Diff comments View file @ f83ef0d

 # SPDX-License-Identifier: GPL-2.0+
 #
 # (C) Copyright 2000-2007
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 # There are many options which enable SPI, so make this library available
 ifdef CONFIG_DM_SPI
 obj-y += spi-uclass.o
 obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o
 obj-$(CONFIG_SOFT_SPI) += soft_spi.o
 obj-$(CONFIG_SPI_MEM) += spi-mem.o
 else
 obj-y += spi.o
 obj-$(CONFIG_SOFT_SPI) += soft_spi_legacy.o
 endif
 obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
 obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
 obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
 obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o
 obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o
 obj-$(CONFIG_BCMSTB_SPI) += bcmstb_spi.o
 obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
 obj-$(CONFIG_CF_SPI) += cf_spi.o
 obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
 obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
 obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
 obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
 obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
 obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
 obj-$(CONFIG_ICH_SPI) +=  ich.o
 obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
 obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
 obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
 obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
 obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
 obj-$(CONFIG_MTK_QSPI) += mtk_qspi.o
 obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o
+obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o
 obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
 obj-$(CONFIG_MXC_SPI) += mxc_spi.o
 obj-$(CONFIG_MXS_SPI) += mxs_spi.o
 obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o
 obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
 obj-$(CONFIG_PIC32_SPI) += pic32_spi.o
 obj-$(CONFIG_PL022_SPI) += pl022_spi.o
 obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o
 obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
 obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
 obj-$(CONFIG_SH_SPI) += sh_spi.o
 obj-$(CONFIG_SH_QSPI) += sh_qspi.o
 obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o
 obj-$(CONFIG_SUN4I_SPI) += sun4i_spi.o
 obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
 obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
 obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
 obj-$(CONFIG_TEGRA210_QSPI) += tegra210_qspi.o
 obj-$(CONFIG_TI_QSPI) += ti_qspi.o
 obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
 obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
 obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o
 obj-$(CONFIG_ZYNQMP_GQSPI) += zynqmp_gqspi.o

drivers/spi/mscc_bb_spi.c

Diff comments View file @ f83ef0d

File was created	1	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	2	/*
	3	* Microsemi SoCs spi driver
	4	*
	5	* Copyright (c) 2018 Microsemi Corporation
	6	*/
	7
	8	#include <common.h>
	9	#include <dm.h>
	10	#include <errno.h>
	11	#include <malloc.h>
	12	#include <spi.h>
	13	#include <dm.h>
	14	#include <asm/gpio.h>
	15	#include <asm/io.h>
	16	#include <linux/delay.h>
	17
	18	struct mscc_bb_priv {
	19	void __iomem *regs;
	20	u32 deactivate_delay_us;
	21	bool cs_active; /* State flag as to whether CS is asserted */
	22	int cs_num;
	23	u32 svalue; /* Value to start transfer with */
	24	u32 clk1; /* Clock value start */
	25	u32 clk2; /* Clock value 2nd phase */
	26	};
	27
	28	/* Delay 24 instructions for this particular application */
	29	#define hold_time_delay() mscc_vcoreiii_nop_delay(3)
	30
	31	static int mscc_bb_spi_cs_activate(struct mscc_bb_priv *priv, int mode, int cs)
	32	{
	33	if (!priv->cs_active) {
	34	int cpha = mode & SPI_CPHA;
	35	u32 cs_value;
	36
	37	priv->cs_num = cs;
	38
	39	if (cpha) {
	40	/* Initial clock starts SCK=1 */
	41	priv->clk1 = ICPU_SW_MODE_SW_SPI_SCK;
	42	priv->clk2 = 0;
	43	} else {
	44	/* Initial clock starts SCK=0 */
	45	priv->clk1 = 0;
	46	priv->clk2 = ICPU_SW_MODE_SW_SPI_SCK;
	47	}
	48
	49	/* Enable bitbang, SCK_OE, SDO_OE */
	50	priv->svalue = (ICPU_SW_MODE_SW_PIN_CTRL_MODE \| /* Bitbang */
	51	ICPU_SW_MODE_SW_SPI_SCK_OE \| /* SCK_OE */
	52	ICPU_SW_MODE_SW_SPI_SDO_OE); /* SDO OE */
	53
	54	/* Add CS */
	55	if (cs >= 0) {
	56	cs_value =
	57	ICPU_SW_MODE_SW_SPI_CS_OE(BIT(cs)) \|
	58	ICPU_SW_MODE_SW_SPI_CS(BIT(cs));
	59	} else {
	60	cs_value = 0;
	61	}
	62
	63	priv->svalue \|= cs_value;
	64
	65	/* Enable the CS in HW, Initial clock value */
	66	writel(priv->svalue \| priv->clk2, priv->regs);
	67
	68	priv->cs_active = true;
	69	debug("Activated CS%d\n", priv->cs_num);
	70	}
	71
	72	return 0;
	73	}
	74
	75	static int mscc_bb_spi_cs_deactivate(struct mscc_bb_priv *priv, int deact_delay)
	76	{
	77	if (priv->cs_active) {
	78	/* Keep driving the CLK to its current value while
	79	* actively deselecting CS.
	80	*/
	81	u32 value = readl(priv->regs);
	82
	83	value &= ~ICPU_SW_MODE_SW_SPI_CS_M;
	84	writel(value, priv->regs);
	85	hold_time_delay();
	86
	87	/* Stop driving the clock, but keep CS with nCS == 1 */
	88	value &= ~ICPU_SW_MODE_SW_SPI_SCK_OE;
	89	writel(value, priv->regs);
	90
	91	/* Deselect hold time delay */
	92	if (deact_delay)
	93	udelay(deact_delay);
	94
	95	/* Drop everything */
	96	writel(0, priv->regs);
	97
	98	priv->cs_active = false;
	99	debug("Deactivated CS%d\n", priv->cs_num);
	100	}
	101
	102	return 0;
	103	}
	104
	105	int mscc_bb_spi_claim_bus(struct udevice *dev)
	106	{
	107	return 0;
	108	}
	109
	110	int mscc_bb_spi_release_bus(struct udevice *dev)
	111	{
	112	return 0;
	113	}
	114
	115	int mscc_bb_spi_xfer(struct udevice *dev, unsigned int bitlen,
	116	const void dout, void din, unsigned long flags)
	117	{
	118	struct udevice *bus = dev_get_parent(dev);
	119	struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
	120	struct mscc_bb_priv *priv = dev_get_priv(bus);
	121	u32 i, count;
	122	const u8 *txd = dout;
	123	u8 *rxd = din;
	124
	125	debug("spi_xfer: slave %s:%s cs%d mode %d, dout %p din %p bitlen %u\n",
	126	dev->parent->name, dev->name, plat->cs, plat->mode, dout,
	127	din, bitlen);
	128
	129	if (flags & SPI_XFER_BEGIN)
	130	mscc_bb_spi_cs_activate(priv, plat->mode, plat->cs);
	131
	132	count = bitlen / 8;
	133	for (i = 0; i < count; i++) {
	134	u32 rx = 0, mask = 0x80, value;
	135
	136	while (mask) {
	137	/* Initial condition: CLK is low. */
	138	value = priv->svalue;
	139	if (txd && txd[i] & mask)
	140	value \|= ICPU_SW_MODE_SW_SPI_SDO;
	141
	142	/* Drive data while taking CLK low. The device
	143	* we're accessing will sample on the
	144	* following rising edge and will output data
	145	* on this edge for us to be sampled at the
	146	* end of this loop.
	147	*/
	148	writel(value \| priv->clk1, priv->regs);
	149
	150	/* Wait for t_setup. All devices do have a
	151	* setup-time, so we always insert some delay
	152	* here. Some devices have a very long
	153	* setup-time, which can be adjusted by the
	154	* user through vcoreiii_device->delay.
	155	*/
	156	hold_time_delay();
	157
	158	/* Drive the clock high. */
	159	writel(value \| priv->clk2, priv->regs);
	160
	161	/* Wait for t_hold. See comment about t_setup
	162	* above.
	163	*/
	164	hold_time_delay();
	165
	166	/* We sample as close to the next falling edge
	167	* as possible.
	168	*/
	169	value = readl(priv->regs);
	170	if (value & ICPU_SW_MODE_SW_SPI_SDI)
	171	rx \|= mask;
	172	mask >>= 1;
	173	}
	174	if (rxd) {
	175	debug("Read 0x%02x\n", rx);
	176	rxd[i] = (u8)rx;
	177	}
	178	debug("spi_xfer: byte %d/%d\n", i + 1, count);
	179	}
	180
	181	debug("spi_xfer: done\n");
	182
	183	if (flags & SPI_XFER_END)
	184	mscc_bb_spi_cs_deactivate(priv, priv->deactivate_delay_us);
	185
	186	return 0;
	187	}
	188
	189	int mscc_bb_spi_set_speed(struct udevice *dev, unsigned int speed)
	190	{
	191	/* Accept any speed */
	192	return 0;
	193	}
	194
	195	int mscc_bb_spi_set_mode(struct udevice *dev, unsigned int mode)
	196	{
	197	return 0;
	198	}
	199
	200	static const struct dm_spi_ops mscc_bb_ops = {
	201	.claim_bus = mscc_bb_spi_claim_bus,
	202	.release_bus = mscc_bb_spi_release_bus,
	203	.xfer = mscc_bb_spi_xfer,
	204	.set_speed = mscc_bb_spi_set_speed,
	205	.set_mode = mscc_bb_spi_set_mode,
	206	};
	207
	208	static const struct udevice_id mscc_bb_ids[] = {
	209	{ .compatible = "mscc,luton-bb-spi" },
	210	{ }
	211	};
	212
	213	static int mscc_bb_spi_probe(struct udevice *bus)
	214	{
	215	struct mscc_bb_priv *priv = dev_get_priv(bus);
	216
	217	debug("%s: loaded, priv %p\n", __func__, priv);
	218
	219	priv->regs = (void __iomem *)dev_read_addr(bus);
	220
	221	priv->deactivate_delay_us =
	222	dev_read_u32_default(bus, "spi-deactivate-delay", 0);
	223
	224	priv->cs_active = false;
	225
	226	return 0;
	227	}
	228
	229	U_BOOT_DRIVER(mscc_bb) = {
	230	.name = "mscc_bb",
	231	.id = UCLASS_SPI,
	232	.of_match = mscc_bb_ids,
	233	.ops = &mscc_bb_ops,
	234	.priv_auto_alloc_size = sizeof(struct mscc_bb_priv),
	235	.probe = mscc_bb_spi_probe,
	236	};
	237

include/configs/vcoreiii.h

Diff comments View file @ f83ef0d

 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
 /*
  * Copyright (c) 2018 Microsemi Corporation
  */
 #ifndef __VCOREIII_H
 #define __VCOREIII_H
 #include <linux/sizes.h>
 /* Onboard devices */
 #define CONFIG_SYS_MALLOC_LEN		0x100000
 #define CONFIG_SYS_LOAD_ADDR		0x00100000
 #define CONFIG_SYS_INIT_SP_OFFSET       0x400000
 #define CPU_CLOCK_RATE			500000000 /* Clock for the MIPS core */
 #ifdef CONFIG_SOC_LUTON
 #define CONFIG_SYS_MIPS_TIMER_FREQ	208333333
 #else
 #define CONFIG_SYS_MIPS_TIMER_FREQ	(CPU_CLOCK_RATE / 2)
 #endif
 #define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_MIPS_TIMER_FREQ
+#define CONFIG_BOARD_TYPES
 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
 #define CONFIG_ENV_OFFSET		(1024 * 1024)
 #define CONFIG_ENV_SIZE			(256 * 1024)
 #define CONFIG_ENV_SECT_SIZE		(256 * 1024)
 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
 #define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
 #define CONFIG_ENV_OFFSET_REDUND      (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SPI_MAX_HZ		0 /* This force to read from DT */
 #define CONFIG_ENV_SPI_MODE		0 /* This force to read from DT */
 #endif
 #define CONFIG_SYS_SDRAM_BASE		0x80000000
 #if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || defined(CONFIG_DDRTYPE_MT47H128M8HQ)
 #define CONFIG_SYS_SDRAM_SIZE		(128 * SZ_1M)
 #elif defined(CONFIG_DDRTYPE_MT41J128M16HA) || defined(CONFIG_DDRTYPE_MT41K128M16JT)
 #define CONFIG_SYS_SDRAM_SIZE		(256 * SZ_1M)
 #elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR) || defined(CONFIG_DDRTYPE_MT41K256M16)
 #define CONFIG_SYS_SDRAM_SIZE		(512 * SZ_1M)
 #else
 #error Unknown DDR size - please add!
 #endif
 #define CONFIG_CONS_INDEX		1
 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - SZ_1M)
 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 #define CONFIG_BOARD_EARLY_INIT_R
 #if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT)
 #define VCOREIII_DEFAULT_MTD_ENV		    \
 	"mtdparts="CONFIG_MTDPARTS_DEFAULT"\0"	    \
 	"mtdids="CONFIG_MTDIDS_DEFAULT"\0"
 #else
 #define VCOREIII_DEFAULT_MTD_ENV    /* Go away */
 #endif
 #define CONFIG_SYS_BOOTM_LEN      (16 << 20)      /* Increase max gunzip size */
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	VCOREIII_DEFAULT_MTD_ENV					\
 	"loadaddr=0x81000000\0"						\
 	"spi_image_off=0x00100000\0"					\
 	"console=ttyS0,115200\0"					\
 	"setup=setenv bootargs console=${console} ${mtdparts}"		\
 	"${bootargs_extra}\0"						\
 	"spiboot=run setup; sf probe; sf read ${loadaddr}"		\
 	"${spi_image_off} 0x600000; bootm ${loadaddr}\0"		\
 	"ubootfile=u-boot.bin\0"					\
 	"update=sf probe;mtdparts;dhcp ${loadaddr} ${ubootfile};"	\
 	"sf erase UBoot 0x100000;"					\
 	"sf write ${loadaddr} UBoot  ${filesize}\0"			\
 	"bootcmd=run spiboot\0"						\
 	""
 #endif				/* __VCOREIII_H */

1	# SPDX-License-Identifier: GPL-2.0+	1	# SPDX-License-Identifier: GPL-2.0+
2	#	2	#
3	# Copyright 2000-2008	3	# Copyright 2000-2008
4	# Wolfgang Denk, DENX Software Engineering, wd@denx.de.	4	# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5		5
6	ifndef CONFIG_SPL_BUILD	6	ifndef CONFIG_SPL_BUILD
7	obj-$(CONFIG_DWAPB_GPIO) += dwapb_gpio.o	7	obj-$(CONFIG_DWAPB_GPIO) += dwapb_gpio.o
8	obj-$(CONFIG_AXP_GPIO) += axp_gpio.o	8	obj-$(CONFIG_AXP_GPIO) += axp_gpio.o
9	endif	9	endif
10	obj-$(CONFIG_DM_GPIO) += gpio-uclass.o	10	obj-$(CONFIG_DM_GPIO) += gpio-uclass.o
11		11
12	obj-$(CONFIG_DM_PCA953X) += pca953x_gpio.o	12	obj-$(CONFIG_DM_PCA953X) += pca953x_gpio.o
13	obj-$(CONFIG_DM_74X164) += 74x164_gpio.o	13	obj-$(CONFIG_DM_74X164) += 74x164_gpio.o
14		14
15	obj-$(CONFIG_AT91_GPIO) += at91_gpio.o	15	obj-$(CONFIG_AT91_GPIO) += at91_gpio.o
16	obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o	16	obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o
17	obj-$(CONFIG_BCM6345_GPIO) += bcm6345_gpio.o	17	obj-$(CONFIG_BCM6345_GPIO) += bcm6345_gpio.o
18	obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o	18	obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o
19	obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o	19	obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o
20	obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o	20	obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
21	obj-$(CONFIG_KONA_GPIO) += kona_gpio.o	21	obj-$(CONFIG_KONA_GPIO) += kona_gpio.o
22	obj-$(CONFIG_MARVELL_GPIO) += mvgpio.o	22	obj-$(CONFIG_MARVELL_GPIO) += mvgpio.o
23	obj-$(CONFIG_MARVELL_MFP) += mvmfp.o	23	obj-$(CONFIG_MARVELL_MFP) += mvmfp.o
24	obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o	24	obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o
25	obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o	25	obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o
26	obj-$(CONFIG_PCA953X) += pca953x.o	26	obj-$(CONFIG_PCA953X) += pca953x.o
27	obj-$(CONFIG_PCA9698) += pca9698.o	27	obj-$(CONFIG_PCA9698) += pca9698.o
28	obj-$(CONFIG_ROCKCHIP_GPIO) += rk_gpio.o	28	obj-$(CONFIG_ROCKCHIP_GPIO) += rk_gpio.o
29	obj-$(CONFIG_RCAR_GPIO) += gpio-rcar.o	29	obj-$(CONFIG_RCAR_GPIO) += gpio-rcar.o
30	obj-$(CONFIG_S5P) += s5p_gpio.o	30	obj-$(CONFIG_S5P) += s5p_gpio.o
31	obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o	31	obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o
32	obj-$(CONFIG_SPEAR_GPIO) += spear_gpio.o	32	obj-$(CONFIG_SPEAR_GPIO) += spear_gpio.o
33	obj-$(CONFIG_TEGRA_GPIO) += tegra_gpio.o	33	obj-$(CONFIG_TEGRA_GPIO) += tegra_gpio.o
34	obj-$(CONFIG_TEGRA186_GPIO) += tegra186_gpio.o	34	obj-$(CONFIG_TEGRA186_GPIO) += tegra186_gpio.o
35	obj-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o	35	obj-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
36	obj-$(CONFIG_DM644X_GPIO) += da8xx_gpio.o	36	obj-$(CONFIG_DM644X_GPIO) += da8xx_gpio.o
37	obj-$(CONFIG_ALTERA_PIO) += altera_pio.o	37	obj-$(CONFIG_ALTERA_PIO) += altera_pio.o
38	obj-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o	38	obj-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o
39	obj-$(CONFIG_MPC8XXX_GPIO) += mpc8xxx_gpio.o	39	obj-$(CONFIG_MPC8XXX_GPIO) += mpc8xxx_gpio.o
40	obj-$(CONFIG_SH_GPIO_PFC) += sh_pfc.o	40	obj-$(CONFIG_SH_GPIO_PFC) += sh_pfc.o
41	obj-$(CONFIG_OMAP_GPIO) += omap_gpio.o	41	obj-$(CONFIG_OMAP_GPIO) += omap_gpio.o
42	obj-$(CONFIG_DB8500_GPIO) += db8500_gpio.o	42	obj-$(CONFIG_DB8500_GPIO) += db8500_gpio.o
43	obj-$(CONFIG_BCM2835_GPIO) += bcm2835_gpio.o	43	obj-$(CONFIG_BCM2835_GPIO) += bcm2835_gpio.o
44	obj-$(CONFIG_XILINX_GPIO) += xilinx_gpio.o	44	obj-$(CONFIG_XILINX_GPIO) += xilinx_gpio.o
45	obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o	45	obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o
46	obj-$(CONFIG_TCA642X) += tca642x.o	46	obj-$(CONFIG_TCA642X) += tca642x.o
47	obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o	47	obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o
48	obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o	48	obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o
49	obj-$(CONFIG_STM32F7_GPIO) += stm32f7_gpio.o	49	obj-$(CONFIG_STM32F7_GPIO) += stm32f7_gpio.o
50	obj-$(CONFIG_GPIO_UNIPHIER) += gpio-uniphier.o	50	obj-$(CONFIG_GPIO_UNIPHIER) += gpio-uniphier.o
51	obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o	51	obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o
52	obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o	52	obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o
53	obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o	53	obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o
54	obj-$(CONFIG_HSDK_CREG_GPIO) += hsdk-creg-gpio.o	54	obj-$(CONFIG_HSDK_CREG_GPIO) += hsdk-creg-gpio.o
55	obj-$(CONFIG_IMX_RGPIO2P) += imx_rgpio2p.o	55	obj-$(CONFIG_IMX_RGPIO2P) += imx_rgpio2p.o
56	obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o	56	obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o
57	obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o	57	obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o
58	obj-$(CONFIG_MSM_GPIO) += msm_gpio.o	58	obj-$(CONFIG_MSM_GPIO) += msm_gpio.o
59	obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o	59	obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o
60	obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o	60	obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o
61	obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o	61	obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o
62	obj-$(CONFIG_MSCC_BITBANG_SPI_GPIO) += gpio-mscc-bitbang-spi.o	62	obj-$(CONFIG_MSCC_SGPIO) += mscc_sgpio.o
63		63