Eric Lee / smarc-uboot

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Commit f83ef0dac83110d20389eb71f09285f009f3d198

Authored by Tom Rini
2 parents e964df1e2a 49f0b6bab9
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

Merge tag 'mips-pull-2019-11-16' of git://git.denx.de/u-boot-mips 

- MIPS: mscc: various enhancements for Luton and Ocelot platforms
- MIPS: mscc: added support for Jaguar2 platform
- MIPS: optimised SPL linker script
- MIPS: bcm6368: fix restart flow issues
- MIPS: fixed CONFIG_OF_EMBED warnings for all MIPS boards
- MIPS: mt7688: small fixes and enhancements
- mmc: compile-out write support if disabled

Showing 91 changed files Side-by-side Diff

... ... @@ -523,9 +523,14 @@
523 523 F: arch/mips/dts/luton*
524 524 F: arch/mips/dts/mscc*
525 525 F: arch/mips/dts/ocelot*
  526 +F: arch/mips/dts/jr2*
  527 +F: arch/mips/dts/serval*
526 528 F: board/mscc/
527 529 F: configs/mscc*
  530 +F: drivers/gpio/mscc_sgpio.c
  531 +F: drivers/spi/mscc_bb_spi.c
528 532 F: include/configs/vcoreiii.h
  533 +F: drivers/pinctrl/mscc/
529 534  
530 535 MIPS JZ4780
531 536 M: Ezequiel Garcia <ezequiel@collabora.com>
arch/mips/cpu/u-boot-spl.lds
Diff comments   View file @ f83ef0d
... ... @@ -46,44 +46,76 @@
46 46 __bss_end = .;
47 47 } > .bss_mem
48 48  
49   - .rel.dyn (NOLOAD) : {
50   - *(.rel.dyn)
  49 + /* These mark the ABI of U-Boot for debuggers. */
  50 + .mdebug.abi32 : {
  51 + KEEP(*(.mdebug.abi32))
51 52 }
52   -
53   - .dynsym : {
54   - *(.dynsym)
  53 + .mdebug.abi64 : {
  54 + KEEP(*(.mdebug.abi64))
55 55 }
56 56  
57   - .dynbss : {
58   - *(.dynbss)
59   - }
  57 + /* This is the MIPS specific mdebug section. */
  58 + .mdebug : { *(.mdebug) }
60 59  
61   - .dynstr : {
62   - *(.dynstr)
63   - }
  60 + /* Stabs debugging sections. */
  61 + .stab 0 : { *(.stab) }
  62 + .stabstr 0 : { *(.stabstr) }
  63 + .stab.excl 0 : { *(.stab.excl) }
  64 + .stab.exclstr 0 : { *(.stab.exclstr) }
  65 + .stab.index 0 : { *(.stab.index) }
  66 + .stab.indexstr 0 : { *(.stab.indexstr) }
  67 + .comment 0 : { *(.comment) }
64 68  
65   - .dynamic : {
66   - *(.dynamic)
  69 + /*
  70 + * DWARF debug sections.
  71 + * Symbols in the DWARF debugging sections are relative to
  72 + * the beginning of the section so we begin them at 0.
  73 + */
  74 + /* DWARF 1 */
  75 + .debug 0 : { *(.debug) }
  76 + .line 0 : { *(.line) }
  77 + /* GNU DWARF 1 extensions */
  78 + .debug_srcinfo 0 : { *(.debug_srcinfo) }
  79 + .debug_sfnames 0 : { *(.debug_sfnames) }
  80 + /* DWARF 1.1 and DWARF 2 */
  81 + .debug_aranges 0 : { *(.debug_aranges) }
  82 + .debug_pubnames 0 : { *(.debug_pubnames) }
  83 + /* DWARF 2 */
  84 + .debug_info 0 : {
  85 + *(.debug_info
  86 + .gnu.linkonce.wi.*)
67 87 }
  88 + .debug_abbrev 0 : { *(.debug_abbrev) }
  89 + .debug_line 0 : { *(.debug_line) }
  90 + .debug_frame 0 : { *(.debug_frame) }
  91 + .debug_str 0 : { *(.debug_str) }
  92 + .debug_loc 0 : { *(.debug_loc) }
  93 + .debug_macinfo 0 : { *(.debug_macinfo) }
  94 + .debug_pubtypes 0 : { *(.debug_pubtypes) }
  95 + /* DWARF 3 */
  96 + .debug_ranges 0 : { *(.debug_ranges) }
  97 + /* SGI/MIPS DWARF 2 extensions */
  98 + .debug_weaknames 0 : { *(.debug_weaknames) }
  99 + .debug_funcnames 0 : { *(.debug_funcnames) }
  100 + .debug_typenames 0 : { *(.debug_typenames) }
  101 + .debug_varnames 0 : { *(.debug_varnames) }
  102 + /* GNU DWARF 2 extensions */
  103 + .debug_gnu_pubnames 0 : { *(.debug_gnu_pubnames) }
  104 + .debug_gnu_pubtypes 0 : { *(.debug_gnu_pubtypes) }
  105 + /* DWARF 4 */
  106 + .debug_types 0 : { *(.debug_types) }
  107 + /* DWARF 5 */
  108 + .debug_macro 0 : { *(.debug_macro) }
  109 + .debug_addr 0 : { *(.debug_addr) }
68 110  
69   - .plt : {
70   - *(.plt)
71   - }
72   -
73   - .interp : {
74   - *(.interp)
75   - }
76   -
77   - .gnu : {
78   - *(.gnu*)
79   - }
80   -
81   - .MIPS.stubs : {
82   - *(.MIPS.stubs)
83   - }
84   -
85   - .hash : {
86   - *(.hash)
  111 + /DISCARD/ : {
  112 + /* ABI crap starts here */
  113 + *(.MIPS.abiflags)
  114 + *(.MIPS.options)
  115 + *(.options)
  116 + *(.pdr)
  117 + *(.reginfo)
  118 + *(.eh_frame)
87 119 }
88 120 }
arch/mips/cpu/u-boot.lds
Diff comments   View file @ f83ef0d
... ... @@ -68,40 +68,76 @@
68 68 __bss_end = .;
69 69 }
70 70  
71   - .dynsym _end : {
72   - *(.dynsym)
  71 + /* These mark the ABI of U-Boot for debuggers. */
  72 + .mdebug.abi32 : {
  73 + KEEP(*(.mdebug.abi32))
73 74 }
74   -
75   - .dynbss : {
76   - *(.dynbss)
  75 + .mdebug.abi64 : {
  76 + KEEP(*(.mdebug.abi64))
77 77 }
78 78  
79   - .dynstr : {
80   - *(.dynstr)
81   - }
  79 + /* This is the MIPS specific mdebug section. */
  80 + .mdebug : { *(.mdebug) }
82 81  
83   - .dynamic : {
84   - *(.dynamic)
85   - }
  82 + /* Stabs debugging sections. */
  83 + .stab 0 : { *(.stab) }
  84 + .stabstr 0 : { *(.stabstr) }
  85 + .stab.excl 0 : { *(.stab.excl) }
  86 + .stab.exclstr 0 : { *(.stab.exclstr) }
  87 + .stab.index 0 : { *(.stab.index) }
  88 + .stab.indexstr 0 : { *(.stab.indexstr) }
  89 + .comment 0 : { *(.comment) }
86 90  
87   - .plt : {
88   - *(.plt)
  91 + /*
  92 + * DWARF debug sections.
  93 + * Symbols in the DWARF debugging sections are relative to
  94 + * the beginning of the section so we begin them at 0.
  95 + */
  96 + /* DWARF 1 */
  97 + .debug 0 : { *(.debug) }
  98 + .line 0 : { *(.line) }
  99 + /* GNU DWARF 1 extensions */
  100 + .debug_srcinfo 0 : { *(.debug_srcinfo) }
  101 + .debug_sfnames 0 : { *(.debug_sfnames) }
  102 + /* DWARF 1.1 and DWARF 2 */
  103 + .debug_aranges 0 : { *(.debug_aranges) }
  104 + .debug_pubnames 0 : { *(.debug_pubnames) }
  105 + /* DWARF 2 */
  106 + .debug_info 0 : {
  107 + *(.debug_info
  108 + .gnu.linkonce.wi.*)
89 109 }
  110 + .debug_abbrev 0 : { *(.debug_abbrev) }
  111 + .debug_line 0 : { *(.debug_line) }
  112 + .debug_frame 0 : { *(.debug_frame) }
  113 + .debug_str 0 : { *(.debug_str) }
  114 + .debug_loc 0 : { *(.debug_loc) }
  115 + .debug_macinfo 0 : { *(.debug_macinfo) }
  116 + .debug_pubtypes 0 : { *(.debug_pubtypes) }
  117 + /* DWARF 3 */
  118 + .debug_ranges 0 : { *(.debug_ranges) }
  119 + /* SGI/MIPS DWARF 2 extensions */
  120 + .debug_weaknames 0 : { *(.debug_weaknames) }
  121 + .debug_funcnames 0 : { *(.debug_funcnames) }
  122 + .debug_typenames 0 : { *(.debug_typenames) }
  123 + .debug_varnames 0 : { *(.debug_varnames) }
  124 + /* GNU DWARF 2 extensions */
  125 + .debug_gnu_pubnames 0 : { *(.debug_gnu_pubnames) }
  126 + .debug_gnu_pubtypes 0 : { *(.debug_gnu_pubtypes) }
  127 + /* DWARF 4 */
  128 + .debug_types 0 : { *(.debug_types) }
  129 + /* DWARF 5 */
  130 + .debug_macro 0 : { *(.debug_macro) }
  131 + .debug_addr 0 : { *(.debug_addr) }
90 132  
91   - .interp : {
92   - *(.interp)
93   - }
94   -
95   - .gnu : {
96   - *(.gnu*)
97   - }
98   -
99   - .MIPS.stubs : {
100   - *(.MIPS.stubs)
101   - }
102   -
103   - .hash : {
104   - *(.hash)
  133 + /DISCARD/ : {
  134 + /* ABI crap starts here */
  135 + *(.MIPS.abiflags)
  136 + *(.MIPS.options)
  137 + *(.options)
  138 + *(.pdr)
  139 + *(.reginfo)
  140 + *(.eh_frame)
105 141 }
106 142 }
arch/mips/dts/Makefile
Diff comments   View file @ f83ef0d
... ... @@ -17,6 +17,9 @@
17 17 dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb
18 18 dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
19 19 dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
  20 +dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb
  21 +dtb-$(CONFIG_SOC_OCELOT) += ocelot_pcb120.dtb ocelot_pcb123.dtb
  22 +dtb-$(CONFIG_SOC_JR2) += jr2_pcb110.dtb jr2_pcb111.dtb serval2_pcb112.dtb
20 23  
21 24 targets += $(dtb-y)
22 25  
arch/mips/dts/gardena-smart-gateway-mt7688.dts
Diff comments   View file @ f83ef0d
... ... @@ -34,7 +34,7 @@
34 34 power_green {
35 35 label = "smartgw:power:green";
36 36 gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
37   - default-state = "off";
  37 + default-state = "on";
38 38 };
39 39  
40 40 power_red {
arch/mips/dts/jr2_pcb110.dts
Diff comments   View file @ f83ef0d
  1 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2 +/*
  3 + * Copyright (c) 2018 Microsemi Corporation
  4 + */
  5 +
  6 +/dts-v1/;
  7 +#include "mscc,jr2.dtsi"
  8 +
  9 +/ {
  10 + model = "Jaguar2 Cu8-Sfp16 PCB110 Reference Board";
  11 + compatible = "mscc,jr2-pcb110", "mscc,jr2";
  12 +
  13 + aliases {
  14 + spi0 = &spi0;
  15 + serial0 = &uart0;
  16 + };
  17 +
  18 + chosen {
  19 + stdout-path = "serial0:115200n8";
  20 + };
  21 +
  22 + gpio-leds {
  23 + compatible = "gpio-leds";
  24 +
  25 + status_green {
  26 + label = "pcb110:green:status";
  27 + gpios = <&gpio 12 0>;
  28 + default-state = "on";
  29 + };
  30 +
  31 + status_red {
  32 + label = "pcb110:red:status";
  33 + gpios = <&gpio 13 0>;
  34 + default-state = "off";
  35 + };
  36 + };
  37 +};
  38 +
  39 +&uart0 {
  40 + status = "okay";
  41 +};
  42 +
  43 +&spi0 {
  44 + status = "okay";
  45 + spi-flash@0 {
  46 + compatible = "spi-flash";
  47 + spi-max-frequency = <18000000>; /* input clock */
  48 + reg = <0>; /* CS0 */
  49 + };
  50 +};
  51 +
  52 +&gpio {
  53 + /* SPIO only use DO, CLK, no inputs */
  54 + sgpio1_pins: sgpio1-pins {
  55 + pins = "GPIO_4", "GPIO_5";
  56 + function = "sg1";
  57 + };
  58 +};
  59 +
  60 +&sgpio {
  61 + status = "okay";
  62 + sgpio-ports = <0x00ffffff>;
  63 +};
  64 +
  65 +&sgpio1 {
  66 + status = "okay";
  67 + sgpio-ports = <0x00ff0000>;
  68 +};
  69 +
  70 +&sgpio2 {
  71 + status = "okay";
  72 + sgpio-ports = <0x3f00ffff>;
  73 + gpio-ranges = <&sgpio2 0 0 96>;
  74 +};
arch/mips/dts/jr2_pcb111.dts
Diff comments   View file @ f83ef0d
  1 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2 +/*
  3 + * Copyright (c) 2018 Microsemi Corporation
  4 + */
  5 +
  6 +/dts-v1/;
  7 +#include "mscc,jr2.dtsi"
  8 +
  9 +/ {
  10 + model = "Jaguar2 Cu48 PCB111 Reference Board";
  11 + compatible = "mscc,jr2-pcb111", "mscc,jr2";
  12 +
  13 + aliases {
  14 + spi0 = &spi0;
  15 + serial0 = &uart0;
  16 + };
  17 +
  18 + chosen {
  19 + stdout-path = "serial0:115200n8";
  20 + };
  21 +
  22 + gpio-leds {
  23 + compatible = "gpio-leds";
  24 +
  25 + status_green {
  26 + label = "pcb111:green:status";
  27 + gpios = <&gpio 12 0>;
  28 + default-state = "on";
  29 + };
  30 +
  31 + status_red {
  32 + label = "pcb111:red:status";
  33 + gpios = <&gpio 13 0>;
  34 + default-state = "off";
  35 + };
  36 + };
  37 +};
  38 +
  39 +&uart0 {
  40 + status = "okay";
  41 +};
  42 +
  43 +&spi0 {
  44 + status = "okay";
  45 + spi-flash@0 {
  46 + compatible = "spi-flash";
  47 + spi-max-frequency = <18000000>; /* input clock */
  48 + reg = <0>; /* CS0 */
  49 + };
  50 +};
  51 +
  52 +&gpio {
  53 + /* SPIO only use DO, CLK, no inputs */
  54 + sgpio1_pins: sgpio1-pins {
  55 + pins = "GPIO_4", "GPIO_5";
  56 + function = "sg1";
  57 + };
  58 +};
  59 +
  60 +&sgpio {
  61 + status = "okay";
  62 + sgpio-ports = <0xffffffff>;
  63 +};
  64 +
  65 +&sgpio1 {
  66 + status = "okay";
  67 + sgpio-ports = <0x001effff>;
  68 +};
  69 +
  70 +&sgpio2 {
  71 + status = "okay";
  72 + sgpio-ports = <0xff000000>;
  73 + gpio-ranges = <&sgpio2 0 0 96>;
  74 +};
arch/mips/dts/luton_pcb090.dts
Diff comments   View file @ f83ef0d
  1 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2 +/*
  3 + * Copyright (c) 2018 Microsemi Corporation
  4 + */
  5 +
  6 +/dts-v1/;
  7 +#include "mscc,luton.dtsi"
  8 +
  9 +/ {
  10 + model = "Luton26 PCB090 Reference Board";
  11 + compatible = "mscc,luton-pcb090", "mscc,luton";
  12 +
  13 + aliases {
  14 + serial0 = &uart0;
  15 + spi0 = &spi0;
  16 + };
  17 +
  18 + chosen {
  19 + stdout-path = "serial0:115200n8";
  20 + };
  21 +
  22 + gpio-leds {
  23 + compatible = "gpio-leds";
  24 +
  25 + status_green {
  26 + label = "pcb090:green:status";
  27 + gpios = <&sgpio 64 GPIO_ACTIVE_HIGH>; /* p0.2 */
  28 + default-state = "on";
  29 + };
  30 +
  31 + status_red {
  32 + label = "pcb090:red:status";
  33 + gpios = <&sgpio 65 GPIO_ACTIVE_HIGH>; /* p1.2 */
  34 + default-state = "off";
  35 + };
  36 + };
  37 +};
  38 +
  39 +&sgpio {
  40 + status = "okay";
  41 + gpio-ranges = <&sgpio 0 0 96>;
  42 +};
  43 +
  44 +&uart0 {
  45 + status = "okay";
  46 +};
  47 +
  48 +&spi0 {
  49 + status = "okay";
  50 + spi-flash@0 {
  51 + compatible = "spi-flash";
  52 + spi-max-frequency = <18000000>; /* input clock */
  53 + reg = <0>; /* CS0 */
  54 + spi-cs-high;
  55 + };
  56 +};
arch/mips/dts/luton_pcb091.dts
Diff comments   View file @ f83ef0d
... ... @@ -18,6 +18,33 @@
18 18 chosen {
19 19 stdout-path = "serial0:115200n8";
20 20 };
  21 +
  22 + gpio-leds {
  23 + compatible = "gpio-leds";
  24 +
  25 + top_dimmer {
  26 + label = "pcb091:top:dimmer";
  27 + gpios = <&gpio 29 GPIO_ACTIVE_LOW>;
  28 + default-state = "on";
  29 + };
  30 +
  31 + status_green {
  32 + label = "pcb091:green:status";
  33 + gpios = <&sgpio 26 GPIO_ACTIVE_HIGH>; /* p26.0 */
  34 + default-state = "on";
  35 + };
  36 +
  37 + status_red {
  38 + label = "pcb091:red:status";
  39 + gpios = <&sgpio 58 GPIO_ACTIVE_HIGH>; /* p26.1 */
  40 + default-state = "off";
  41 + };
  42 + };
  43 +};
  44 +
  45 +&sgpio {
  46 + status = "okay";
  47 + mscc,sgpio-ports = <0xFFF000FF>;
21 48 };
22 49  
23 50 &uart0 {
arch/mips/dts/mscc,jr2.dtsi
Diff comments   View file @ f83ef0d
  1 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2 +/*
  3 + * Copyright (c) 2018 Microsemi Corporation
  4 + */
  5 +
  6 +/ {
  7 + #address-cells = <1>;
  8 + #size-cells = <1>;
  9 + compatible = "mscc,jr2";
  10 +
  11 + cpus {
  12 + #address-cells = <1>;
  13 + #size-cells = <0>;
  14 +
  15 + cpu@0 {
  16 + compatible = "mips,mips24KEc";
  17 + device_type = "cpu";
  18 + clocks = <&cpu_clk>;
  19 + reg = <0>;
  20 + };
  21 + };
  22 +
  23 + aliases {
  24 + serial0 = &uart0;
  25 + };
  26 +
  27 + cpuintc: interrupt-controller@0 {
  28 + #address-cells = <0>;
  29 + #interrupt-cells = <1>;
  30 + interrupt-controller;
  31 + compatible = "mti,cpu-interrupt-controller";
  32 + };
  33 +
  34 + cpu_clk: cpu-clock {
  35 + compatible = "fixed-clock";
  36 + #clock-cells = <0>;
  37 + clock-frequency = <500000000>;
  38 + };
  39 +
  40 + ahb_clk: ahb-clk {
  41 + compatible = "fixed-clock";
  42 + #clock-cells = <0>;
  43 + clock-frequency = <250000000>;
  44 + };
  45 +
  46 + ahb {
  47 + compatible = "simple-bus";
  48 + #address-cells = <1>;
  49 + #size-cells = <1>;
  50 + ranges = <0 0x70000000 0x2000000>;
  51 +
  52 + interrupt-parent = <&intc>;
  53 +
  54 + cpu_ctrl: syscon@0 {
  55 + compatible = "mscc,jr2-cpu-syscon", "syscon";
  56 + reg = <0x0 0x2c>;
  57 + };
  58 +
  59 + intc: interrupt-controller@70 {
  60 + compatible = "mscc,jr2-icpu-intr";
  61 + reg = <0x70 0x94>;
  62 + #interrupt-cells = <1>;
  63 + interrupt-controller;
  64 + interrupt-parent = <&cpuintc>;
  65 + interrupts = <2>;
  66 + };
  67 +
  68 + uart0: serial@100000 {
  69 + pinctrl-0 = <&uart_pins>;
  70 + pinctrl-names = "default";
  71 + compatible = "ns16550a";
  72 + reg = <0x100000 0x20>;
  73 + interrupts = <6>;
  74 + clocks = <&ahb_clk>;
  75 + reg-io-width = <4>;
  76 + reg-shift = <2>;
  77 +
  78 + status = "disabled";
  79 + };
  80 +
  81 + uart2: serial@100800 {
  82 + pinctrl-0 = <&uart2_pins>;
  83 + pinctrl-names = "default";
  84 + compatible = "ns16550a";
  85 + reg = <0x100800 0x20>;
  86 + interrupts = <7>;
  87 + clocks = <&ahb_clk>;
  88 + reg-io-width = <4>;
  89 + reg-shift = <2>;
  90 +
  91 + status = "disabled";
  92 + };
  93 +
  94 + spi0: spi-master@101000 {
  95 + #address-cells = <1>;
  96 + #size-cells = <0>;
  97 + compatible = "snps,dw-apb-ssi";
  98 + reg = <0x101000 0x40>;
  99 + num-chipselect = <4>;
  100 + bus-num = <0>;
  101 + reg-io-width = <4>;
  102 + reg-shift = <2>;
  103 + spi-max-frequency = <18000000>; /* input clock */
  104 + clocks = <&ahb_clk>;
  105 +
  106 + status = "disabled";
  107 + };
  108 +
  109 + reset@1010008 {
  110 + compatible = "mscc,jr2-chip-reset";
  111 + reg = <0x1010008 0x4>;
  112 + };
  113 +
  114 + gpio: pinctrl@1070034 {
  115 + compatible = "mscc,jaguar2-pinctrl";
  116 + reg = <0x1010038 0x90>;
  117 + gpio-controller;
  118 + #gpio-cells = <2>;
  119 + gpio-ranges = <&gpio 0 0 64>;
  120 +
  121 + sgpio_pins: sgpio-pins {
  122 + pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
  123 + function = "sg0";
  124 + };
  125 +
  126 + sgpio1_pins: sgpio1-pins {
  127 + pins = "GPIO_4", "GPIO_5", "GPIO_12", "GPIO_13";
  128 + function = "sg1";
  129 + };
  130 +
  131 + sgpio2_pins: sgpio2-pins {
  132 + pins = "GPIO_30", "GPIO_31",
  133 + "GPIO_32", "GPIO_33";
  134 + function = "sg2";
  135 + };
  136 +
  137 + uart_pins: uart-pins {
  138 + pins = "GPIO_10", "GPIO_11";
  139 + function = "uart";
  140 + };
  141 +
  142 + uart2_pins: uart2-pins {
  143 + pins = "GPIO_24", "GPIO_25";
  144 + function = "uart2";
  145 + };
  146 + };
  147 +
  148 + sgpio: gpio@1010150 {
  149 + compatible = "mscc,ocelot-sgpio";
  150 + status = "disabled";
  151 + pinctrl-0 = <&sgpio_pins>;
  152 + pinctrl-names = "default";
  153 + reg = <0x1010150 0x100>;
  154 + gpio-controller;
  155 + #gpio-cells = <2>;
  156 + gpio-ranges = <&sgpio 0 0 64>;
  157 + gpio-bank-name = "sgpio0_";
  158 + sgpio-clock = <0x14>;
  159 + };
  160 +
  161 + sgpio1: gpio@101025c {
  162 + compatible = "mscc,ocelot-sgpio";
  163 + status = "disabled";
  164 + pinctrl-0 = <&sgpio1_pins>;
  165 + pinctrl-names = "default";
  166 + reg = <0x101025c 0x100>;
  167 + gpio-controller;
  168 + #gpio-cells = <2>;
  169 + gpio-ranges = <&sgpio1 0 0 64>;
  170 + gpio-bank-name = "sgpio1_";
  171 + sgpio-clock = <0x14>;
  172 + };
  173 +
  174 + sgpio2: gpio@1010368 {
  175 + compatible = "mscc,ocelot-sgpio";
  176 + status = "disabled";
  177 + pinctrl-0 = <&sgpio2_pins>;
  178 + pinctrl-names = "default";
  179 + reg = <0x1010368 0x100>;
  180 + gpio-controller;
  181 + #gpio-cells = <2>;
  182 + gpio-ranges = <&sgpio2 0 0 64>;
  183 + gpio-bank-name = "sgpio2_";
  184 + sgpio-clock = <0x14>;
  185 + };
  186 + };
  187 +};
arch/mips/dts/mscc,luton.dtsi
Diff comments   View file @ f83ef0d
... ... @@ -25,6 +25,11 @@
25 25 serial0 = &uart0;
26 26 };
27 27  
  28 + sys_clk: sys-clk {
  29 + compatible = "fixed-clock";
  30 + #clock-cells = <0>;
  31 + clock-frequency = <250000000>;
  32 + };
28 33 ahb_clk: ahb-clk {
29 34 compatible = "fixed-clock";
30 35 #clock-cells = <0>;
31 36  
32 37  
33 38  
34 39  
35 40  
... ... @@ -57,28 +62,32 @@
57 62 #gpio-cells = <2>;
58 63 gpio-ranges = <&gpio 0 0 32>;
59 64  
  65 + sgpio_pins: sgpio-pins {
  66 + pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
  67 + function = "sio";
  68 + };
60 69 uart_pins: uart-pins {
61 70 pins = "GPIO_30", "GPIO_31";
62 71 function = "uart";
63 72 };
64   -
65 73 };
66 74  
67   - gpio_spi_bitbang: gpio@10000064 {
68   - compatible = "mscc,spi-bitbang-gpio";
69   - reg = <0x10000064 0x4>;
  75 + sgpio: gpio@70130 {
  76 + compatible = "mscc,luton-sgpio";
  77 + status = "disabled";
  78 + clocks = <&sys_clk>;
  79 + pinctrl-0 = <&sgpio_pins>;
  80 + pinctrl-names = "default";
  81 + reg = <0x0070130 0x100>;
70 82 gpio-controller;
71 83 #gpio-cells = <2>;
72   -
  84 + gpio-ranges = <&sgpio 0 0 64>;
73 85 };
74 86  
75 87 spi0: spi-bitbang {
76   - compatible = "spi-gpio";
  88 + compatible = "mscc,luton-bb-spi";
77 89 status = "okay";
78   - gpio-sck = <&gpio_spi_bitbang 6 0>;
79   - gpio-miso = <&gpio_spi_bitbang 0 0>;
80   - gpio-mosi = <&gpio_spi_bitbang 5 0>;
81   - cs-gpios = <&gpio_spi_bitbang 1 0>;
  90 + reg = <0x10000064 0x4>;
82 91 num-chipselects = <1>;
83 92 #address-cells = <1>;
84 93 #size-cells = <0>;
arch/mips/dts/mscc,ocelot.dtsi
Diff comments   View file @ f83ef0d
... ... @@ -37,6 +37,12 @@
37 37 clock-frequency = <500000000>;
38 38 };
39 39  
  40 + sys_clk: sys-clk {
  41 + compatible = "fixed-clock";
  42 + #clock-cells = <0>;
  43 + clock-frequency = <250000000>;
  44 + };
  45 +
40 46 ahb_clk: ahb-clk {
41 47 compatible = "fixed-clock";
42 48 #clock-cells = <0>;
... ... @@ -118,6 +124,11 @@
118 124 #gpio-cells = <2>;
119 125 gpio-ranges = <&gpio 0 0 22>;
120 126  
  127 + sgpio_pins: sgpio-pins {
  128 + pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
  129 + function = "sg0";
  130 + };
  131 +
121 132 uart_pins: uart-pins {
122 133 pins = "GPIO_6", "GPIO_7";
123 134 function = "uart";
... ... @@ -147,6 +158,18 @@
147 158 pins = "GPIO_17";
148 159 function = "si";
149 160 };
  161 + };
  162 +
  163 + sgpio: gpio@10700f8 {
  164 + compatible = "mscc,ocelot-sgpio";
  165 + status = "disabled";
  166 + clocks = <&sys_clk>;
  167 + pinctrl-0 = <&sgpio_pins>;
  168 + pinctrl-names = "default";
  169 + reg = <0x10700f8 0x100>;
  170 + gpio-controller;
  171 + #gpio-cells = <2>;
  172 + gpio-ranges = <&sgpio 0 0 64>;
150 173 };
151 174 };
152 175 };
arch/mips/dts/ocelot_pcb120.dts
Diff comments   View file @ f83ef0d
... ... @@ -9,5 +9,80 @@
9 9 / {
10 10 model = "Ocelot PCB120 Reference Board";
11 11 compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
  12 +
  13 + chosen {
  14 + stdout-path = "serial0:115200n8";
  15 + };
  16 +
  17 + gpio-leds {
  18 + compatible = "gpio-leds";
  19 +
  20 + poe_green {
  21 + label = "pcb120:green:poe";
  22 + gpios = <&sgpio 44 1>; /* p12.1 */
  23 + default-state = "off";
  24 + };
  25 +
  26 + poe_red {
  27 + label = "pcb120:red:poe";
  28 + gpios = <&sgpio 12 1>; /* p12.0 */
  29 + default-state = "off";
  30 + };
  31 +
  32 + alarm_green {
  33 + label = "pcb120:green:alarm";
  34 + gpios = <&sgpio 45 1>; /* p13.1 */
  35 + default-state = "off";
  36 + };
  37 +
  38 + alarm_red {
  39 + label = "pcb120:red:alarm";
  40 + gpios = <&sgpio 13 1>; /* p13.0 */
  41 + default-state = "off";
  42 + };
  43 +
  44 + dc_a_green {
  45 + label = "pcb120:green:dc_a";
  46 + gpios = <&sgpio 46 1>; /* p14.1 */
  47 + default-state = "off";
  48 + };
  49 +
  50 + dc_a_red {
  51 + label = "pcb120:red:dc_a";
  52 + gpios = <&sgpio 14 1>; /* p14.0 */
  53 + default-state = "off";
  54 + };
  55 +
  56 + dc_b_green {
  57 + label = "pcb120:green:dc_b";
  58 + gpios = <&sgpio 47 1>; /* p15.1 */
  59 + default-state = "off";
  60 + };
  61 +
  62 + dc_b_red {
  63 + label = "pcb120:red:dc_b";
  64 + gpios = <&sgpio 15 1>; /* p15.0 */
  65 + default-state = "off";
  66 + };
  67 +
  68 + status_green {
  69 + label = "pcb120:green:status";
  70 + gpios = <&sgpio 48 1>; /* p16.1 */
  71 + default-state = "on";
  72 + };
  73 +
  74 + status_red {
  75 + label = "pcb120:red:alarm";
  76 + gpios = <&sgpio 16 1>; /* p16.0 */
  77 + default-state = "off";
  78 + };
  79 +
  80 + };
  81 +
  82 +};
  83 +
  84 +&sgpio {
  85 + status = "okay";
  86 + mscc,sgpio-ports = <0x000FFFFF>;
12 87 };
arch/mips/dts/ocelot_pcb123.dts
Diff comments   View file @ f83ef0d
... ... @@ -9,5 +9,30 @@
9 9 / {
10 10 model = "Ocelot PCB123 Reference Board";
11 11 compatible = "mscc,ocelot-pcb123", "mscc,ocelot";
  12 +
  13 + chosen {
  14 + stdout-path = "serial0:115200n8";
  15 + };
  16 +
  17 + gpio-leds {
  18 + compatible = "gpio-leds";
  19 +
  20 + status_green {
  21 + label = "pcb123:green:status";
  22 + gpios = <&sgpio 43 1>; /* p11.1 */
  23 + default-state = "on";
  24 + };
  25 +
  26 + status_red {
  27 + label = "pcb123:red:status";
  28 + gpios = <&sgpio 11 1>; /* p11.0 */
  29 + default-state = "off";
  30 + };
  31 + };
  32 +};
  33 +
  34 +&sgpio {
  35 + status = "okay";
  36 + mscc,sgpio-ports = <0x00FFFFFF>;
12 37 };
arch/mips/dts/serval2_pcb112.dts
Diff comments   View file @ f83ef0d
  1 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2 +/*
  3 + * Copyright (c) 2018 Microsemi Corporation
  4 + */
  5 +
  6 +/dts-v1/;
  7 +#include "mscc,jr2.dtsi"
  8 +
  9 +/ {
  10 + model = "Serval2 NID PCB112 Reference Board";
  11 + compatible = "mscc,serval2-pcb110", "mscc,jr2";
  12 +
  13 + aliases {
  14 + spi0 = &spi0;
  15 + serial0 = &uart0;
  16 + };
  17 +
  18 + chosen {
  19 + stdout-path = "serial0:115200n8";
  20 + };
  21 +
  22 + gpio-leds {
  23 + compatible = "gpio-leds";
  24 +
  25 + status_green {
  26 + label = "pcb110:green:status";
  27 + gpios = <&gpio 12 0>;
  28 + default-state = "on";
  29 + };
  30 +
  31 + status_red {
  32 + label = "pcb110:red:status";
  33 + gpios = <&gpio 13 0>;
  34 + default-state = "off";
  35 + };
  36 + };
  37 +};
  38 +
  39 +&uart0 {
  40 + status = "okay";
  41 +};
  42 +
  43 +&spi0 {
  44 + status = "okay";
  45 + spi-flash@0 {
  46 + compatible = "spi-flash";
  47 + spi-max-frequency = <18000000>; /* input clock */
  48 + reg = <0>; /* CS0 */
  49 + };
  50 +};
  51 +
  52 +&sgpio {
  53 + status = "okay";
  54 + sgpio-ports = <0x0000ffff>;
  55 +};
  56 +
  57 +&sgpio2 {
  58 + status = "okay";
  59 + sgpio-ports = <0x3fe0ffff>;
  60 +};
arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds
View file @ f83ef0d
1   -/* SPDX-License-Identifier: GPL-2.0+ */
2   -
3   -MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
4   - LENGTH = CONFIG_SPL_MAX_SIZE }
5   -MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
6   - LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
7   -
8   -OUTPUT_ARCH(mips)
9   -ENTRY(_start)
10   -SECTIONS
11   -{
12   - .text :
13   - {
14   - __image_copy_start = .;
15   - arch/mips/mach-jz47xx/start.o (.text*)
16   - *(.text*)
17   - } >.sram
18   -
19   - . = ALIGN(4);
20   - .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
21   -
22   - . = ALIGN(4);
23   - .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
24   -
25   - . = ALIGN(4);
26   - __image_copy_end = .;
27   -
28   - .bss : {
29   - . = ALIGN(4);
30   - __bss_start = .;
31   - *(.sbss.*)
32   - *(.bss.*)
33   - *(COMMON)
34   - . = ALIGN(4);
35   - __bss_end = .;
36   - } >.sdram
37   -
38   - /DISCARD/ : {
39   - *(.dynbss)
40   - *(.dynstr)
41   - *(.dynamic)
42   - *(.interp)
43   - *(.hash)
44   - *(.gnu.*)
45   - *(.plt)
46   - *(.got.plt)
47   - *(.rel.plt)
48   - *(.rel.dyn)
49   - }
50   -}
arch/mips/mach-mscc/Kconfig
Diff comments   View file @ f83ef0d
... ... @@ -15,47 +15,36 @@
15 15 config SYS_SOC
16 16 default "mscc"
17 17  
  18 +choice
  19 +
  20 + prompt "SOC Family Variant"
  21 +
18 22 config SOC_OCELOT
19   - bool
  23 + bool "Ocelot SOC Family"
20 24 select SOC_VCOREIII
  25 + select DESIGNWARE_SPI
21 26 help
22 27 This supports MSCC Ocelot family of SOCs.
23 28  
24 29 config SOC_LUTON
25   - bool
  30 + bool "Luton SOC Family"
26 31 select SOC_VCOREIII
  32 + select MSCC_BITBANG_SPI_GPIO
27 33 help
28 34 This supports MSCC Luton family of SOCs.
29 35  
30   -config SYS_CONFIG_NAME
31   - default "vcoreiii"
32   -
33   -choice
34   - prompt "Board select"
35   -
36   -config TARGET_OCELOT_PCB120
37   - bool "MSCC PCB120 Reference Board (aka VSC5635EV)"
38   - select SOC_OCELOT
  36 +config SOC_JR2
  37 + bool "Jaguar2 SOC Family"
  38 + select SOC_VCOREIII
  39 + select DESIGNWARE_SPI
39 40 help
40   - When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
41   - ocelot_pcb120
  41 + This supports MSCC Jaguar2 family of SOCs.
42 42  
43   -config TARGET_OCELOT_PCB123
44   - bool "MSCC PCB123 Reference Board (aka VSC7514EV))"
45   - select SOC_OCELOT
46   - help
47   - When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
48   - ocelot_pcb123
49   -
50   -config TARGET_LUTON_PCB091
51   - bool "MSCC PCB091 Reference Board"
52   - select SOC_LUTON
53   - select MSCC_BITBANG_SPI_GPIO
54   - help
55   - When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
56   - luton_pcb091
57 43 endchoice
58 44  
  45 +config SYS_CONFIG_NAME
  46 + default "vcoreiii"
  47 +
59 48 choice
60 49 prompt "DDR type"
61 50  
... ... @@ -82,6 +71,8 @@
82 71 source "board/mscc/ocelot/Kconfig"
83 72  
84 73 source "board/mscc/luton/Kconfig"
  74 +
  75 +source "board/mscc/jr2/Kconfig"
85 76  
86 77 endmenu
arch/mips/mach-mscc/Makefile
Diff comments   View file @ f83ef0d
... ... @@ -2,6 +2,7 @@
2 2  
3 3 CFLAGS_cpu.o += -finline-limit=64000
4 4  
5   -obj-y += cpu.o dram.o reset.o lowlevel_init.o
6   -obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o
  5 +obj-y += cpu.o dram.o reset.o phy.o lowlevel_init.o
  6 +obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o gpio.o
  7 +obj-$(CONFIG_SOC_OCELOT) += gpio.o
arch/mips/mach-mscc/cpu.c
Diff comments   View file @ f83ef0d
... ... @@ -87,8 +87,15 @@
87 87 ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
88 88 ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
89 89 #else
  90 +#ifdef CONFIG_SOC_OCELOT
90 91 writel(ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
91 92 ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
  93 +#endif
  94 +#ifdef CONFIG_SOC_JR2
  95 + writel(ICPU_SPI_MST_CFG_FAST_READ_ENA +
  96 + ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
  97 + ICPU_SPI_MST_CFG_CLK_DIV(14), BASE_CFG + ICPU_SPI_MST_CFG);
  98 +#endif
92 99 /*
93 100 * Legacy and mainline linux kernel expect that the
94 101 * interruption map was set as it was done by redboot.
arch/mips/mach-mscc/dram.c
Diff comments   View file @ f83ef0d
... ... @@ -19,7 +19,7 @@
19 19  
20 20 ret = hal_vcoreiii_train_bytelane(0);
21 21  
22   -#ifdef CONFIG_SOC_OCELOT
  22 +#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
23 23 if (ret)
24 24 return ret;
25 25 ret = hal_vcoreiii_train_bytelane(1);
arch/mips/mach-mscc/gpio.c
Diff comments   View file @ f83ef0d
  1 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2 +/*
  3 + * Copyright (c) 2018 Microsemi Corporation
  4 + */
  5 +
  6 +#include <common.h>
  7 +#include <asm/io.h>
  8 +
  9 +void mscc_gpio_set_alternate(int gpio, int mode)
  10 +{
  11 + u32 mask = BIT(gpio);
  12 + u32 val0, val1;
  13 +
  14 + val0 = readl(BASE_DEVCPU_GCB + GPIO_ALT(0));
  15 + val1 = readl(BASE_DEVCPU_GCB + GPIO_ALT(1));
  16 +
  17 + if (mode == 1) {
  18 + val0 |= mask;
  19 + val1 &= ~mask;
  20 + } else if (mode == 2) {
  21 + val0 &= ~mask;
  22 + val1 |= mask;
  23 + } else if (mode == 3) {
  24 + val0 |= mask;
  25 + val1 |= mask;
  26 + } else {
  27 + val0 &= ~mask;
  28 + val1 &= ~mask;
  29 + }
  30 +
  31 + writel(val0, BASE_DEVCPU_GCB + GPIO_ALT(0));
  32 + writel(val1, BASE_DEVCPU_GCB + GPIO_ALT(1));
  33 +}
arch/mips/mach-mscc/include/mach/common.h
Diff comments   View file @ f83ef0d
... ... @@ -9,11 +9,18 @@
9 9 #if defined(CONFIG_SOC_OCELOT)
10 10 #include <mach/ocelot/ocelot.h>
11 11 #include <mach/ocelot/ocelot_devcpu_gcb.h>
  12 +#include <mach/ocelot/ocelot_devcpu_gcb_miim_regs.h>
12 13 #include <mach/ocelot/ocelot_icpu_cfg.h>
13 14 #elif defined(CONFIG_SOC_LUTON)
14 15 #include <mach/luton/luton.h>
15 16 #include <mach/luton/luton_devcpu_gcb.h>
  17 +#include <mach/luton/luton_devcpu_gcb_miim_regs.h>
16 18 #include <mach/luton/luton_icpu_cfg.h>
  19 +#elif defined(CONFIG_SOC_JR2)
  20 +#include <mach/jr2/jr2.h>
  21 +#include <mach/jr2/jr2_devcpu_gcb.h>
  22 +#include <mach/jr2/jr2_devcpu_gcb_miim_regs.h>
  23 +#include <mach/jr2/jr2_icpu_cfg.h>
17 24 #else
18 25 #error Unsupported platform
19 26 #endif
... ... @@ -24,6 +31,64 @@
24 31 #define MSCC_FLASH_TO MSCC_MEMCTL1_TO /* Flash base offset */
25 32  
26 33 #define VCOREIII_TIMER_DIVIDER 25 /* Clock tick ~ 0.1 us */
  34 +
  35 +/* Common utility functions */
  36 +
  37 +/*
  38 + * Perform a number of NOP instructions, blocks of 8 instructions.
  39 + * The (inlined) function will not affect cache or processor state.
  40 + */
  41 +static inline void mscc_vcoreiii_nop_delay(int delay)
  42 +{
  43 + while (delay > 0) {
  44 +#define DELAY_8_NOPS() asm volatile("nop; nop; nop; nop; nop; nop; nop; nop;")
  45 + switch (delay) {
  46 + case 8:
  47 + DELAY_8_NOPS();
  48 + /* fallthrough */
  49 + case 7:
  50 + DELAY_8_NOPS();
  51 + /* fallthrough */
  52 + case 6:
  53 + DELAY_8_NOPS();
  54 + /* fallthrough */
  55 + case 5:
  56 + DELAY_8_NOPS();
  57 + /* fallthrough */
  58 + case 4:
  59 + DELAY_8_NOPS();
  60 + /* fallthrough */
  61 + case 3:
  62 + DELAY_8_NOPS();
  63 + /* fallthrough */
  64 + case 2:
  65 + DELAY_8_NOPS();
  66 + /* fallthrough */
  67 + case 1:
  68 + DELAY_8_NOPS();
  69 + }
  70 + delay -= 8;
  71 +#undef DELAY_8_NOPS
  72 + }
  73 +}
  74 +
  75 +int mscc_phy_rd_wr(u8 read,
  76 + u32 miim_controller,
  77 + u8 miim_addr,
  78 + u8 addr,
  79 + u16 *value);
  80 +
  81 +int mscc_phy_rd(u32 miim_controller,
  82 + u8 miim_addr,
  83 + u8 addr,
  84 + u16 *value);
  85 +
  86 +int mscc_phy_wr(u32 miim_controller,
  87 + u8 miim_addr,
  88 + u8 addr,
  89 + u16 value);
  90 +
  91 +void mscc_gpio_set_alternate(int gpio, int mode);
27 92  
28 93 #endif /* __ASM_MACH_COMMON_H */
arch/mips/mach-mscc/include/mach/ddr.h
Diff comments   View file @ f83ef0d
... ... @@ -161,7 +161,7 @@
161 161  
162 162 #endif
163 163  
164   -#ifdef CONFIG_SOC_OCELOT
  164 +#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
165 165 #define MIPS_VCOREIII_MEMORY_16BIT 1
166 166 #endif
167 167  
... ... @@ -239,7 +239,7 @@
239 239 ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(VC3_MPAR_row_addr_cnt - 1) | \
240 240 ICPU_MEMCTRL_CFG_MSB_COL_ADDR(VC3_MPAR_col_addr_cnt - 1)
241 241  
242   -#ifdef CONFIG_SOC_OCELOT
  242 +#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
243 243 #define MSCC_MEMPARM_PERIOD \
244 244 ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(8) | \
245 245 ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(VC3_MPAR_tREFI)
... ... @@ -378,7 +378,7 @@
378 378 PAUSE();
379 379 }
380 380  
381   -#ifdef CONFIG_SOC_OCELOT
  381 +#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
382 382 static u8 training_data[] = { 0xfe, 0x11, 0x33, 0x55, 0x77, 0x99, 0xbb, 0xdd };
383 383  
384 384 static inline void sleep_100ns(u32 val)
... ... @@ -398,6 +398,7 @@
398 398 ;
399 399 }
400 400  
  401 +#if defined(CONFIG_SOC_OCELOT)
401 402 static inline void hal_vcoreiii_ddr_reset_assert(void)
402 403 {
403 404 /* DDR has reset pin on GPIO 19 toggle Low-High to release */
404 405  
... ... @@ -448,7 +449,27 @@
448 449  
449 450 panic("DDR init failed\n");
450 451 }
  452 +#else /* JR2 */
  453 +static inline void hal_vcoreiii_ddr_reset_assert(void)
  454 +{
  455 + /* Ensure the memory controller physical iface is forced reset */
  456 + writel(readl(BASE_CFG + ICPU_MEMPHY_CFG) |
  457 + ICPU_MEMPHY_CFG_PHY_RST, BASE_CFG + ICPU_MEMPHY_CFG);
451 458  
  459 + /* Ensure the memory controller is forced reset */
  460 + writel(readl(BASE_CFG + ICPU_RESET) |
  461 + ICPU_RESET_MEM_RST_FORCE, BASE_CFG + ICPU_RESET);
  462 +}
  463 +
  464 +static inline void hal_vcoreiii_ddr_failed(void)
  465 +{
  466 + writel(0, BASE_CFG + ICPU_RESET);
  467 + writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_CFG + PERF_SOFT_RST);
  468 +
  469 + panic("DDR init failed\n");
  470 +}
  471 +#endif
  472 +
452 473 /*
453 474 * DDR memory sanity checking done, possibly enable ECC.
454 475 *
... ... @@ -738,7 +759,7 @@
738 759 /* Wait for ZCAL to clear */
739 760 while (readl(BASE_CFG + ICPU_MEMPHY_ZCAL) & ICPU_MEMPHY_ZCAL_ZCAL_ENA)
740 761 ;
741   -#ifdef CONFIG_SOC_OCELOT
  762 +#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
742 763 /* Check no ZCAL_ERR */
743 764 if (readl(BASE_CFG + ICPU_MEMPHY_ZCAL_STAT)
744 765 & ICPU_MEMPHY_ZCAL_STAT_ZCAL_ERR)
... ... @@ -752,7 +773,7 @@
752 773 writel(MSCC_MEMPARM_MEMCFG, BASE_CFG + ICPU_MEMCTRL_CFG);
753 774 writel(MSCC_MEMPARM_PERIOD, BASE_CFG + ICPU_MEMCTRL_REF_PERIOD);
754 775  
755   -#ifdef CONFIG_SOC_OCELOT
  776 +#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
756 777 writel(MSCC_MEMPARM_TIMING0, BASE_CFG + ICPU_MEMCTRL_TIMING0);
757 778 #else /* Luton */
758 779 clrbits_le32(BASE_CFG + ICPU_MEMCTRL_TIMING0, ((1 << 20) - 1));
... ... @@ -767,7 +788,7 @@
767 788 writel(MSCC_MEMPARM_MR2, BASE_CFG + ICPU_MEMCTRL_MR2_VAL);
768 789 writel(MSCC_MEMPARM_MR3, BASE_CFG + ICPU_MEMCTRL_MR3_VAL);
769 790  
770   -#ifdef CONFIG_SOC_OCELOT
  791 +#if defined(CONFIG_SOC_OCELOT)
771 792 /* Termination setup - enable ODT */
772 793 writel(ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA |
773 794 /* Assert ODT0 for any write */
... ... @@ -778,6 +799,9 @@
778 799 hal_vcoreiii_ddr_reset_release();
779 800  
780 801 writel(readl(BASE_CFG + ICPU_GPR(7)) + 1, BASE_CFG + ICPU_GPR(7));
  802 +#elif defined(CONFIG_SOC_JR2)
  803 + writel(ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(3),
  804 + BASE_CFG + ICPU_MEMCTRL_TERMRES_CTRL);
781 805 #else /* Luton */
782 806 /* Termination setup - disable ODT */
783 807 writel(0, BASE_CFG + ICPU_MEMCTRL_TERMRES_CTRL);
... ... @@ -796,7 +820,7 @@
796 820  
797 821 /* Settle...? */
798 822 sleep_100ns(10000);
799   -#ifdef CONFIG_SOC_OCELOT
  823 +#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
800 824 /* Establish data contents in DDR RAM for training */
801 825  
802 826 __raw_writel(0xcacafefe, ((void __iomem *)MSCC_DDR_TO));
arch/mips/mach-mscc/include/mach/jr2/jr2.h
Diff comments   View file @ f83ef0d
  1 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2 +/*
  3 + * Microsemi Jaguar2 Switch driver
  4 + *
  5 + * Copyright (c) 2018 Microsemi Corporation
  6 + */
  7 +
  8 +#ifndef _MSCC_JR2_H_
  9 +#define _MSCC_JR2_H_
  10 +
  11 +#include <linux/bitops.h>
  12 +#include <dm.h>
  13 +
  14 +/*
  15 + * Target offset base(s)
  16 + */
  17 +#define MSCC_IO_ORIGIN1_OFFSET 0x70000000
  18 +#define MSCC_IO_ORIGIN1_SIZE 0x00200000
  19 +#define MSCC_IO_ORIGIN2_OFFSET 0x71000000
  20 +#define MSCC_IO_ORIGIN2_SIZE 0x01000000
  21 +#define BASE_CFG ((void __iomem *)0x70000000)
  22 +#define BASE_DEVCPU_GCB ((void __iomem *)0x71010000)
  23 +
  24 +#endif
arch/mips/mach-mscc/include/mach/jr2/jr2_devcpu_gcb.h
Diff comments   View file @ f83ef0d
  1 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2 +/*
  3 + * Copyright (c) 2018 Microsemi Corporation
  4 + */
  5 +
  6 +#ifndef _MSCC_JR2_DEVCPU_GCB_H_
  7 +#define _MSCC_JR2_DEVCPU_GCB_H_
  8 +
  9 +#define PERF_GPR 0x4
  10 +
  11 +#define PERF_SOFT_RST 0x8
  12 +
  13 +#define PERF_SOFT_RST_SOFT_NON_CFG_RST BIT(2)
  14 +#define PERF_SOFT_RST_SOFT_SWC_RST BIT(1)
  15 +#define PERF_SOFT_RST_SOFT_CHIP_RST BIT(0)
  16 +
  17 +#define GPIO_GPIO_ALT(x) (0x78 + 4 * (x))
  18 +#define GPIO_GPIO_ALT1(x) (0x80 + 4 * (x))
  19 +
  20 +#endif
arch/mips/mach-mscc/include/mach/jr2/jr2_devcpu_gcb_miim_regs.h
Diff comments   View file @ f83ef0d
  1 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2 +/*
  3 + * Copyright (c) 2018 Microsemi Corporation
  4 + */
  5 +
  6 +#ifndef _MSCC_JR2_DEVCPU_GCB_MIIM_REGS_H_
  7 +#define _MSCC_JR2_DEVCPU_GCB_MIIM_REGS_H_
  8 +
  9 +#define MIIM_MII_STATUS(gi) (0xc8 + (gi * 36))
  10 +#define MIIM_MII_CMD(gi) (0xd0 + (gi * 36))
  11 +#define MIIM_MII_DATA(gi) (0xd4 + (gi * 36))
  12 +
  13 +#define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0)
  14 +
  15 +#define MSCC_F_MII_CMD_MIIM_CMD_VLD(x) ((x) ? BIT(31) : 0)
  16 +#define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & ((x) << 25))
  17 +#define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & ((x) << 20))
  18 +#define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & ((x) << 4))
  19 +#define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & ((x) << 1))
  20 +#define MSCC_F_MII_CMD_MIIM_CMD_SCAN(x) ((x) ? BIT(0) : 0)
  21 +
  22 +#define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS GENMASK(17, 16)
  23 +#define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) (((x) >> 0) & GENMASK(15, 0))
  24 +
  25 +#endif
arch/mips/mach-mscc/include/mach/jr2/jr2_icpu_cfg.h
Diff comments   View file @ f83ef0d
  1 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2 +/*
  3 + * Copyright (c) 2018 Microsemi Corporation
  4 + */
  5 +
  6 +#ifndef _MSCC_JR2_ICPU_CFG_H_
  7 +#define _MSCC_JR2_ICPU_CFG_H_
  8 +
  9 +#define ICPU_GPR(x) (0x4 * (x))
  10 +#define ICPU_GPR_RSZ 0x4
  11 +
  12 +#define ICPU_RESET 0x20
  13 +
  14 +#define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
  15 +#define ICPU_RESET_CORE_RST_PROTECT BIT(2)
  16 +#define ICPU_RESET_CORE_RST_FORCE BIT(1)
  17 +#define ICPU_RESET_MEM_RST_FORCE BIT(0)
  18 +
  19 +#define ICPU_GENERAL_CTRL 0x24
  20 +
  21 +#define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(15)
  22 +#define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(14)
  23 +#define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(13)
  24 +#define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(12)
  25 +#define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ENA BIT(11)
  26 +#define ICPU_GENERAL_CTRL_IF_PI_SLV_DONEPOL BIT(10)
  27 +#define ICPU_GENERAL_CTRL_IF_PI_MST_ENA BIT(9)
  28 +#define ICPU_GENERAL_CTRL_IF_PI_SLV_ENA BIT(8)
  29 +#define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 6) & GENMASK(7, 6))
  30 +#define ICPU_GENERAL_CTRL_IF_SI_OWNER_M GENMASK(7, 6)
  31 +#define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(7, 6)) >> 4)
  32 +#define ICPU_GENERAL_CTRL_IF_SI1_OWNER(x) (((x) << 4) & GENMASK(5, 4))
  33 +#define ICPU_GENERAL_CTRL_IF_SI1_OWNER_M GENMASK(5, 4)
  34 +#define ICPU_GENERAL_CTRL_IF_SI1_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4)
  35 +#define ICPU_GENERAL_CTRL_SSI_MST_CONTENTION BIT(3)
  36 +#define ICPU_GENERAL_CTRL_CPU_BE_ENA BIT(2)
  37 +#define ICPU_GENERAL_CTRL_CPU_DIS BIT(1)
  38 +#define ICPU_GENERAL_CTRL_BOOT_MODE_ENA BIT(0)
  39 +
  40 +#define ICPU_SPI_MST_CFG 0x3c
  41 +
  42 +#define ICPU_SPI_MST_CFG_A32B_ENA BIT(11)
  43 +#define ICPU_SPI_MST_CFG_FAST_READ_ENA BIT(10)
  44 +#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5))
  45 +#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5)
  46 +#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5)
  47 +#define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
  48 +#define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
  49 +
  50 +#define ICPU_SW_MODE 0x50
  51 +
  52 +#define ICPU_SW_MODE_SW_PIN_CTRL_MODE BIT(13)
  53 +#define ICPU_SW_MODE_SW_SPI_SCK BIT(12)
  54 +#define ICPU_SW_MODE_SW_SPI_SCK_OE BIT(11)
  55 +#define ICPU_SW_MODE_SW_SPI_SDO BIT(10)
  56 +#define ICPU_SW_MODE_SW_SPI_SDO_OE BIT(9)
  57 +#define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5))
  58 +#define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5)
  59 +#define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5)
  60 +#define ICPU_SW_MODE_SW_SPI_CS_OE(x) (((x) << 1) & GENMASK(4, 1))
  61 +#define ICPU_SW_MODE_SW_SPI_CS_OE_M GENMASK(4, 1)
  62 +#define ICPU_SW_MODE_SW_SPI_CS_OE_X(x) (((x) & GENMASK(4, 1)) >> 1)
  63 +#define ICPU_SW_MODE_SW_SPI_SDI BIT(0)
  64 +
  65 +#define ICPU_INTR_ENA 0x88
  66 +
  67 +#define ICPU_DST_INTR_MAP(x) (0x98 + 0x4 * (x))
  68 +#define ICPU_DST_INTR_MAP_RSZ 0x4
  69 +
  70 +#define ICPU_TIMER_TICK_DIV 0x108
  71 +
  72 +#define ICPU_TIMER_VALUE(x) (0x10c + 0x4 * (x))
  73 +#define ICPU_TIMER_VALUE_RSZ 0x4
  74 +
  75 +#define ICPU_TIMER_CTRL(x) (0x124 + 0x4 * (x))
  76 +#define ICPU_TIMER_CTRL_RSZ 0x4
  77 +
  78 +#define ICPU_TIMER_CTRL_MAX_FREQ_ENA BIT(3)
  79 +#define ICPU_TIMER_CTRL_ONE_SHOT_ENA BIT(2)
  80 +#define ICPU_TIMER_CTRL_TIMER_ENA BIT(1)
  81 +#define ICPU_TIMER_CTRL_FORCE_RELOAD BIT(0)
  82 +
  83 +#define ICPU_MEMCTRL_CTRL 0x130
  84 +
  85 +#define ICPU_MEMCTRL_CTRL_PWR_DOWN BIT(3)
  86 +#define ICPU_MEMCTRL_CTRL_MDSET BIT(2)
  87 +#define ICPU_MEMCTRL_CTRL_STALL_REF_ENA BIT(1)
  88 +#define ICPU_MEMCTRL_CTRL_INITIALIZE BIT(0)
  89 +
  90 +#define ICPU_MEMCTRL_CFG 0x134
  91 +
  92 +#define ICPU_MEMCTRL_CFG_DDR_512MBYTE_PLUS BIT(16)
  93 +#define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15)
  94 +#define ICPU_MEMCTRL_CFG_DDR_ECC_COR_ENA BIT(14)
  95 +#define ICPU_MEMCTRL_CFG_DDR_ECC_ENA BIT(13)
  96 +#define ICPU_MEMCTRL_CFG_DDR_WIDTH BIT(12)
  97 +#define ICPU_MEMCTRL_CFG_DDR_MODE BIT(11)
  98 +#define ICPU_MEMCTRL_CFG_BURST_SIZE BIT(10)
  99 +#define ICPU_MEMCTRL_CFG_BURST_LEN BIT(9)
  100 +#define ICPU_MEMCTRL_CFG_BANK_CNT BIT(8)
  101 +#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(x) (((x) << 4) & GENMASK(7, 4))
  102 +#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_M GENMASK(7, 4)
  103 +#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_X(x) (((x) & GENMASK(7, 4)) >> 4)
  104 +#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0))
  105 +#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR_M GENMASK(3, 0)
  106 +
  107 +#define ICPU_MEMCTRL_STAT 0x138
  108 +
  109 +#define ICPU_MEMCTRL_STAT_RDATA_MASKED BIT(5)
  110 +#define ICPU_MEMCTRL_STAT_RDATA_DUMMY BIT(4)
  111 +#define ICPU_MEMCTRL_STAT_RDATA_ECC_ERR BIT(3)
  112 +#define ICPU_MEMCTRL_STAT_RDATA_ECC_COR BIT(2)
  113 +#define ICPU_MEMCTRL_STAT_PWR_DOWN_ACK BIT(1)
  114 +#define ICPU_MEMCTRL_STAT_INIT_DONE BIT(0)
  115 +
  116 +#define ICPU_MEMCTRL_REF_PERIOD 0x13c
  117 +
  118 +#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(x) (((x) << 16) & GENMASK(19, 16))
  119 +#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_M GENMASK(19, 16)
  120 +#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_X(x) (((x) & GENMASK(19, 16)) >> 16)
  121 +#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x) ((x) & GENMASK(15, 0))
  122 +#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD_M GENMASK(15, 0)
  123 +
  124 +#define ICPU_MEMCTRL_ZQCAL 0x140
  125 +
  126 +#define ICPU_MEMCTRL_ZQCAL_ZQCAL_LONG BIT(1)
  127 +#define ICPU_MEMCTRL_ZQCAL_ZQCAL_SHORT BIT(0)
  128 +
  129 +#define ICPU_MEMCTRL_TIMING0 0x144
  130 +
  131 +#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(x) (((x) << 28) & GENMASK(31, 28))
  132 +#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_M GENMASK(31, 28)
  133 +#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28)
  134 +#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY(x) (((x) << 24) & GENMASK(27, 24))
  135 +#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_M GENMASK(27, 24)
  136 +#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24)
  137 +#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY(x) (((x) << 20) & GENMASK(23, 20))
  138 +#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_M GENMASK(23, 20)
  139 +#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_X(x) (((x) & GENMASK(23, 20)) >> 20)
  140 +#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(x) (((x) << 16) & GENMASK(19, 16))
  141 +#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_M GENMASK(19, 16)
  142 +#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16)
  143 +#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(x) (((x) << 12) & GENMASK(15, 12))
  144 +#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_M GENMASK(15, 12)
  145 +#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
  146 +#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(x) (((x) << 8) & GENMASK(11, 8))
  147 +#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_M GENMASK(11, 8)
  148 +#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
  149 +#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(x) (((x) << 4) & GENMASK(7, 4))
  150 +#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_M GENMASK(7, 4)
  151 +#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
  152 +#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0))
  153 +#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY_M GENMASK(3, 0)
  154 +
  155 +#define ICPU_MEMCTRL_TIMING1 0x148
  156 +
  157 +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(x) (((x) << 24) & GENMASK(31, 24))
  158 +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_M GENMASK(31, 24)
  159 +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_X(x) (((x) & GENMASK(31, 24)) >> 24)
  160 +#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(x) (((x) << 16) & GENMASK(23, 16))
  161 +#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_M GENMASK(23, 16)
  162 +#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16)
  163 +#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(x) (((x) << 12) & GENMASK(15, 12))
  164 +#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_M GENMASK(15, 12)
  165 +#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
  166 +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(x) (((x) << 8) & GENMASK(11, 8))
  167 +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_M GENMASK(11, 8)
  168 +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
  169 +#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(x) (((x) << 4) & GENMASK(7, 4))
  170 +#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_M GENMASK(7, 4)
  171 +#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
  172 +#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0))
  173 +#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY_M GENMASK(3, 0)
  174 +
  175 +#define ICPU_MEMCTRL_TIMING2 0x14c
  176 +
  177 +#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(x) (((x) << 28) & GENMASK(31, 28))
  178 +#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_M GENMASK(31, 28)
  179 +#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28)
  180 +#define ICPU_MEMCTRL_TIMING2_MDSET_DLY(x) (((x) << 24) & GENMASK(27, 24))
  181 +#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_M GENMASK(27, 24)
  182 +#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24)
  183 +#define ICPU_MEMCTRL_TIMING2_REF_DLY(x) (((x) << 16) & GENMASK(23, 16))
  184 +#define ICPU_MEMCTRL_TIMING2_REF_DLY_M GENMASK(23, 16)
  185 +#define ICPU_MEMCTRL_TIMING2_REF_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16)
  186 +#define ICPU_MEMCTRL_TIMING2_INIT_DLY(x) ((x) & GENMASK(15, 0))
  187 +#define ICPU_MEMCTRL_TIMING2_INIT_DLY_M GENMASK(15, 0)
  188 +
  189 +#define ICPU_MEMCTRL_TIMING3 0x150
  190 +
  191 +#define ICPU_MEMCTRL_TIMING3_RMW_DLY(x) (((x) << 16) & GENMASK(19, 16))
  192 +#define ICPU_MEMCTRL_TIMING3_RMW_DLY_M GENMASK(19, 16)
  193 +#define ICPU_MEMCTRL_TIMING3_RMW_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16)
  194 +#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY(x) (((x) << 12) & GENMASK(15, 12))
  195 +#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_M GENMASK(15, 12)
  196 +#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
  197 +#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(x) (((x) << 8) & GENMASK(11, 8))
  198 +#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_M GENMASK(11, 8)
  199 +#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
  200 +#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(x) (((x) << 4) & GENMASK(7, 4))
  201 +#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_M GENMASK(7, 4)
  202 +#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
  203 +#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(x) ((x) & GENMASK(3, 0))
  204 +#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY_M GENMASK(3, 0)
  205 +
  206 +#define ICPU_MEMCTRL_TIMING4 0x154
  207 +
  208 +#define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY(x) (((x) << 20) & GENMASK(31, 20))
  209 +#define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY_M GENMASK(31, 20)
  210 +#define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY_X(x) (((x) & GENMASK(31, 20)) >> 20)
  211 +#define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY(x) (((x) << 8) & GENMASK(19, 8))
  212 +#define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY_M GENMASK(19, 8)
  213 +#define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY_X(x) (((x) & GENMASK(19, 8)) >> 8)
  214 +#define ICPU_MEMCTRL_TIMING4_ZQCAL_SHORT_DLY(x) ((x) & GENMASK(7, 0))
  215 +#define ICPU_MEMCTRL_TIMING4_ZQCAL_SHORT_DLY_M GENMASK(7, 0)
  216 +
  217 +#define ICPU_MEMCTRL_MR0_VAL 0x158
  218 +
  219 +#define ICPU_MEMCTRL_MR1_VAL 0x15c
  220 +
  221 +#define ICPU_MEMCTRL_MR2_VAL 0x160
  222 +
  223 +#define ICPU_MEMCTRL_MR3_VAL 0x164
  224 +
  225 +#define ICPU_MEMCTRL_TERMRES_CTRL 0x168
  226 +
  227 +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_EXT BIT(11)
  228 +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA(x) (((x) << 7) & GENMASK(10, 7))
  229 +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_M GENMASK(10, 7)
  230 +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_X(x) (((x) & GENMASK(10, 7)) >> 7)
  231 +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_EXT BIT(6)
  232 +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(x) (((x) << 2) & GENMASK(5, 2))
  233 +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_M GENMASK(5, 2)
  234 +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_X(x) (((x) & GENMASK(5, 2)) >> 2)
  235 +#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_EXT BIT(1)
  236 +#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA BIT(0)
  237 +
  238 +#define ICPU_MEMCTRL_DFT 0x16c
  239 +
  240 +#define ICPU_MEMCTRL_DFT_DDRDFT_LBW BIT(7)
  241 +#define ICPU_MEMCTRL_DFT_DDRDFT_GATE_ENA BIT(6)
  242 +#define ICPU_MEMCTRL_DFT_DDRDFT_TERM_ENA BIT(5)
  243 +#define ICPU_MEMCTRL_DFT_DDRDFT_A10 BIT(4)
  244 +#define ICPU_MEMCTRL_DFT_DDRDFT_STAT BIT(3)
  245 +#define ICPU_MEMCTRL_DFT_DDRDFT_MODE(x) (((x) << 1) & GENMASK(2, 1))
  246 +#define ICPU_MEMCTRL_DFT_DDRDFT_MODE_M GENMASK(2, 1)
  247 +#define ICPU_MEMCTRL_DFT_DDRDFT_MODE_X(x) (((x) & GENMASK(2, 1)) >> 1)
  248 +#define ICPU_MEMCTRL_DFT_DDRDFT_ENA BIT(0)
  249 +
  250 +#define ICPU_MEMCTRL_DQS_DLY(x) (0x170 + 0x4 * (x))
  251 +#define ICPU_MEMCTRL_DQS_DLY_RSZ 0x4
  252 +
  253 +#define ICPU_MEMCTRL_DQS_DLY_TRAIN_DQ_ENA BIT(11)
  254 +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1(x) (((x) << 8) & GENMASK(10, 8))
  255 +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_M GENMASK(10, 8)
  256 +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_X(x) (((x) & GENMASK(10, 8)) >> 8)
  257 +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0(x) (((x) << 5) & GENMASK(7, 5))
  258 +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_M GENMASK(7, 5)
  259 +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_X(x) (((x) & GENMASK(7, 5)) >> 5)
  260 +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY(x) ((x) & GENMASK(4, 0))
  261 +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_M GENMASK(4, 0)
  262 +
  263 +#define ICPU_MEMCTRL_DQS_AUTO (0x178 + 0x4 * (x))
  264 +#define ICPU_MEMCTRL_DQS_AUTO_RSZ 0x4
  265 +
  266 +#define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT(x) (((x) << 6) & GENMASK(7, 6))
  267 +#define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT_M GENMASK(7, 6)
  268 +#define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT_X(x) (((x) & GENMASK(7, 6)) >> 6)
  269 +#define ICPU_MEMCTRL_DQS_AUTO_DQS_OVERFLOW BIT(5)
  270 +#define ICPU_MEMCTRL_DQS_AUTO_DQS_UNDERFLOW BIT(4)
  271 +#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_SRC BIT(3)
  272 +#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_UP BIT(2)
  273 +#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_DOWN BIT(1)
  274 +#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_ENA BIT(0)
  275 +
  276 +#define ICPU_MEMPHY_CFG 0x180
  277 +
  278 +#define ICPU_MEMPHY_CFG_PHY_FLUSH_DIS BIT(10)
  279 +#define ICPU_MEMPHY_CFG_PHY_RD_ADJ_DIS BIT(9)
  280 +#define ICPU_MEMPHY_CFG_PHY_DQS_EXT BIT(8)
  281 +#define ICPU_MEMPHY_CFG_PHY_FIFO_RST BIT(7)
  282 +#define ICPU_MEMPHY_CFG_PHY_DLL_BL_RST BIT(6)
  283 +#define ICPU_MEMPHY_CFG_PHY_DLL_CL_RST BIT(5)
  284 +#define ICPU_MEMPHY_CFG_PHY_ODT_OE BIT(4)
  285 +#define ICPU_MEMPHY_CFG_PHY_CK_OE BIT(3)
  286 +#define ICPU_MEMPHY_CFG_PHY_CL_OE BIT(2)
  287 +#define ICPU_MEMPHY_CFG_PHY_SSTL_ENA BIT(1)
  288 +#define ICPU_MEMPHY_CFG_PHY_RST BIT(0)
  289 +
  290 +#define ICPU_MEMPHY_ZCAL 0x1a8
  291 +
  292 +#define ICPU_MEMPHY_ZCAL_ZCAL_CLK_SEL BIT(9)
  293 +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT(x) (((x) << 5) & GENMASK(8, 5))
  294 +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_M GENMASK(8, 5)
  295 +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_X(x) (((x) & GENMASK(8, 5)) >> 5)
  296 +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG(x) (((x) << 1) & GENMASK(4, 1))
  297 +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_M GENMASK(4, 1)
  298 +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_X(x) (((x) & GENMASK(4, 1)) >> 1)
  299 +#define ICPU_MEMPHY_ZCAL_ZCAL_ENA BIT(0)
  300 +//
  301 +#define ICPU_MEMPHY_ZCAL_STAT 0x1ac
  302 +
  303 +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL(x) (((x) << 12) & GENMASK(31, 12))
  304 +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL_M GENMASK(31, 12)
  305 +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL_X(x) (((x) & GENMASK(31, 12)) >> 12)
  306 +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU(x) (((x) << 8) & GENMASK(9, 8))
  307 +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU_M GENMASK(9, 8)
  308 +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU_X(x) (((x) & GENMASK(9, 8)) >> 8)
  309 +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD(x) (((x) << 6) & GENMASK(7, 6))
  310 +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD_M GENMASK(7, 6)
  311 +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD_X(x) (((x) & GENMASK(7, 6)) >> 6)
  312 +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU(x) (((x) << 4) & GENMASK(5, 4))
  313 +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU_M GENMASK(5, 4)
  314 +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU_X(x) (((x) & GENMASK(5, 4)) >> 4)
  315 +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD(x) (((x) << 2) & GENMASK(3, 2))
  316 +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD_M GENMASK(3, 2)
  317 +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD_X(x) (((x) & GENMASK(3, 2)) >> 2)
  318 +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ERR BIT(1)
  319 +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_DONE BIT(0)
  320 +
  321 +#endif
arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
Diff comments   View file @ f83ef0d
... ... @@ -11,5 +11,9 @@
11 11 #define PERF_SOFT_RST_SOFT_SWC_RST BIT(1)
12 12 #define PERF_SOFT_RST_SOFT_CHIP_RST BIT(0)
13 13  
  14 +#define GPIO_ALT(x) (0x88 + 4 * (x))
  15 +
  16 +#define CHIP_ID (0x08)
  17 +
14 18 #endif
arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h
Diff comments   View file @ f83ef0d
  1 +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
  2 +/*
  3 + * Microsemi Ocelot Switch driver
  4 + *
  5 + * Copyright (c) 2018 Microsemi Corporation
  6 + */
  7 +
  8 +#ifndef _MSCC_LUTON_MIIM_REGS_H_
  9 +#define _MSCC_LUTON_MIIM_REGS_H_
  10 +
  11 +#define MIIM_MII_STATUS(gi) (0xa0 + (gi * 36))
  12 +#define MIIM_MII_CMD(gi) (0xa8 + (gi * 36))
  13 +#define MIIM_MII_DATA(gi) (0xac + (gi * 36))
  14 +
  15 +#define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) (x ? BIT(3) : 0)
  16 +
  17 +#define MSCC_F_MII_CMD_MIIM_CMD_VLD(x) (x ? BIT(31) : 0)
  18 +#define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & (x << 25))
  19 +#define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & (x << 20))
  20 +#define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & (x << 4))
  21 +#define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & (x << 1))
  22 +
  23 +#define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS GENMASK(17, 16)
  24 +#define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) ((x >> 0) & GENMASK(15, 0))
  25 +
  26 +#endif
arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
Diff comments   View file @ f83ef0d
... ... @@ -18,5 +18,7 @@
18 18  
19 19 #define PERF_GPIO_OE 0x44
20 20  
  21 +#define GPIO_ALT(x) (0x54 + 4 * (x))
  22 +
21 23 #endif
arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h
Diff comments   View file @ f83ef0d
  1 +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
  2 +/*
  3 + * Copyright (c) 2018 Microsemi Corporation
  4 + */
  5 +
  6 +#ifndef _MSCC_OCELOT_DEVCPU_GCB_MIIM_REGS_H_
  7 +#define _MSCC_OCELOT_DEVCPU_GCB_MIIM_REGS_H_
  8 +
  9 +#define MIIM_MII_STATUS(gi) (0x9c + (gi * 36))
  10 +#define MIIM_MII_CMD(gi) (0xa4 + (gi * 36))
  11 +#define MIIM_MII_DATA(gi) (0xa8 + (gi * 36))
  12 +
  13 +#define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0)
  14 +
  15 +#define MSCC_F_MII_CMD_MIIM_CMD_VLD(x) ((x) ? BIT(31) : 0)
  16 +#define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & ((x) << 25))
  17 +#define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & ((x) << 20))
  18 +#define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & ((x) << 4))
  19 +#define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & ((x) << 1))
  20 +#define MSCC_F_MII_CMD_MIIM_CMD_SCAN(x) ((x) ? BIT(0) : 0)
  21 +
  22 +#define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS GENMASK(17, 16)
  23 +#define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) (((x) >> 0) & GENMASK(15, 0))
  24 +
  25 +#endif
arch/mips/mach-mscc/phy.c
Diff comments   View file @ f83ef0d
  1 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2 +/*
  3 + * Copyright (c) 2018 Microsemi Corporation
  4 + */
  5 +
  6 +#include <common.h>
  7 +#include <asm/io.h>
  8 +
  9 +int mscc_phy_rd_wr(u8 read,
  10 + u32 miimdev,
  11 + u8 miim_addr,
  12 + u8 addr,
  13 + u16 *value)
  14 +{
  15 + u32 data;
  16 + int i;
  17 +
  18 + /* Command part */
  19 + data = (read ? MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(2) : /* Read */
  20 + MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(1) | /* Write */
  21 + MSCC_F_MII_CMD_MIIM_CMD_WRDATA(*value)); /* value */
  22 +
  23 + /* Addressing part */
  24 + data |=
  25 + MSCC_F_MII_CMD_MIIM_CMD_VLD(1) | /* Valid command */
  26 + MSCC_F_MII_CMD_MIIM_CMD_REGAD(addr) | /* Reg addr */
  27 + MSCC_F_MII_CMD_MIIM_CMD_PHYAD(miim_addr); /* Miim addr */
  28 +
  29 + /* Enqueue MIIM operation to be executed */
  30 + writel(data, BASE_DEVCPU_GCB + MIIM_MII_CMD(miimdev));
  31 +
  32 + /* Wait for MIIM operation to finish */
  33 + i = 0;
  34 + do {
  35 + if (i++ > 100) {
  36 + debug("Miim timeout");
  37 + return -1;
  38 + }
  39 + data = readl(BASE_DEVCPU_GCB + MIIM_MII_STATUS(miimdev));
  40 + debug("Read status miim(%d): 0x%08x\n", miimdev, data);
  41 + } while (data & MSCC_F_MII_STATUS_MIIM_STAT_BUSY(1));
  42 +
  43 + if (read) {
  44 + data = readl(BASE_DEVCPU_GCB + MIIM_MII_DATA(miimdev));
  45 + if (data & MSCC_M_MII_DATA_MIIM_DATA_SUCCESS) {
  46 + debug("Read(%d, %d) returned 0x%08x\n",
  47 + miim_addr, addr, data);
  48 + return -1;
  49 + }
  50 + *value = MSCC_X_MII_DATA_MIIM_DATA_RDDATA(data);
  51 + }
  52 +
  53 + return 0;
  54 +}
  55 +
  56 +int mscc_phy_rd(u32 miimdev,
  57 + u8 miim_addr,
  58 + u8 addr,
  59 + u16 *value)
  60 +{
  61 + if (mscc_phy_rd_wr(1, miimdev, miim_addr, addr, value) == 0)
  62 + return 0;
  63 + debug("Read(%d, %d) returned error\n", miim_addr, addr);
  64 + return -1;
  65 +}
  66 +
  67 +int mscc_phy_wr(u32 miimdev,
  68 + u8 miim_addr,
  69 + u8 addr,
  70 + u16 value)
  71 +{
  72 + return mscc_phy_rd_wr(0, miimdev, miim_addr, addr, &value);
  73 +}
arch/mips/mach-mscc/reset.c
Diff comments   View file @ f83ef0d
... ... @@ -12,6 +12,22 @@
12 12  
13 13 void _machine_restart(void)
14 14 {
  15 +#if defined(CONFIG_SOC_JR2)
  16 + register u32 reg = readl(BASE_CFG + ICPU_GENERAL_CTRL);
  17 + /* Set owner */
  18 + reg &= ~ICPU_GENERAL_CTRL_IF_SI_OWNER_M;
  19 + reg |= ICPU_GENERAL_CTRL_IF_SI_OWNER(1);
  20 + /* Set boot mode */
  21 + reg |= ICPU_GENERAL_CTRL_BOOT_MODE_ENA;
  22 + writel(reg, BASE_CFG + ICPU_GENERAL_CTRL);
  23 + /* Read back in order to make BOOT mode setting active */
  24 + reg = readl(BASE_CFG + ICPU_GENERAL_CTRL);
  25 + /* Reset CPU only - still executing _here_. but from cache */
  26 + writel(readl(BASE_CFG + ICPU_RESET) |
  27 + ICPU_RESET_CORE_RST_CPU_ONLY |
  28 + ICPU_RESET_CORE_RST_FORCE,
  29 + BASE_CFG + ICPU_RESET);
  30 +#else
15 31 register u32 resetbits = PERF_SOFT_RST_SOFT_CHIP_RST;
16 32 (void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST);
17 33  
... ... @@ -24,6 +40,7 @@
24 40  
25 41 /* Do the global reset */
26 42 writel(resetbits, BASE_DEVCPU_GCB + PERF_SOFT_RST);
  43 +#endif
27 44  
28 45 while (1)
29 46 ; /* NOP */
board/mscc/common/Makefile
Diff comments   View file @ f83ef0d
  1 +# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2 +
  3 +obj-$(CONFIG_SOC_JR2) := spi.o
  4 +obj-$(CONFIG_SOC_OCELOT) := spi.o
board/mscc/common/spi.c
Diff comments   View file @ f83ef0d
  1 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2 +/*
  3 + * Copyright (c) 2018 Microsemi Coprporation
  4 + */
  5 +
  6 +#include <common.h>
  7 +#include <asm/io.h>
  8 +#include <spi.h>
  9 +
  10 +void external_cs_manage(struct udevice *dev, bool enable)
  11 +{
  12 + u32 cs = spi_chip_select(dev);
  13 + /* IF_SI0_OWNER, select the owner of the SI interface
  14 + * Encoding: 0: SI Slave
  15 + * 1: SI Boot Master
  16 + * 2: SI Master Controller
  17 + */
  18 + if (!enable) {
  19 + writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE |
  20 + ICPU_SW_MODE_SW_SPI_CS(BIT(cs)),
  21 + BASE_CFG + ICPU_SW_MODE);
  22 + clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
  23 + ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
  24 + ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
  25 + } else {
  26 + writel(0, BASE_CFG + ICPU_SW_MODE);
  27 + clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
  28 + ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
  29 + ICPU_GENERAL_CTRL_IF_SI_OWNER(1));
  30 + }
  31 +}
board/mscc/jr2/Kconfig
Diff comments   View file @ f83ef0d
  1 +# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2 +
  3 +config SYS_VENDOR
  4 + default "mscc"
  5 +
  6 +if SOC_JR2
  7 +
  8 +config SYS_BOARD
  9 + default "jr2"
  10 +
  11 +config SYS_CONFIG_NAME
  12 + default "jr2"
  13 +
  14 +endif
board/mscc/jr2/Makefile
Diff comments   View file @ f83ef0d
  1 +# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2 +
  3 +obj-$(CONFIG_SOC_JR2) := jr2.o
board/mscc/jr2/jr2.c
Diff comments   View file @ f83ef0d
  1 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2 +/*
  3 + * Copyright (c) 2018 Microsemi Corporation
  4 + */
  5 +
  6 +#include <common.h>
  7 +#include <asm/io.h>
  8 +#include <led.h>
  9 +
  10 +enum {
  11 + BOARD_TYPE_PCB110 = 0xAABBCE00,
  12 + BOARD_TYPE_PCB111,
  13 + BOARD_TYPE_PCB112,
  14 +};
  15 +
  16 +int board_early_init_r(void)
  17 +{
  18 + /* Prepare SPI controller to be used in master mode */
  19 + writel(0, BASE_CFG + ICPU_SW_MODE);
  20 + clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
  21 + ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
  22 + ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
  23 +
  24 + /* Address of boot parameters */
  25 + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
  26 +
  27 + /* LED setup */
  28 + if (IS_ENABLED(CONFIG_LED))
  29 + led_default_state();
  30 +
  31 + return 0;
  32 +}
  33 +
  34 +static void vcoreiii_gpio_set_alternate(int gpio, int mode)
  35 +{
  36 + u32 mask;
  37 + u32 val0, val1;
  38 + void __iomem *reg0, *reg1;
  39 +
  40 + if (gpio < 32) {
  41 + mask = BIT(gpio);
  42 + reg0 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT(0);
  43 + reg1 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT(1);
  44 + } else {
  45 + gpio -= 32;
  46 + mask = BIT(gpio);
  47 + reg0 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT1(0);
  48 + reg1 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT1(1);
  49 + }
  50 + val0 = readl(reg0);
  51 + val1 = readl(reg1);
  52 + if (mode == 1) {
  53 + writel(val0 | mask, reg0);
  54 + writel(val1 & ~mask, reg1);
  55 + } else if (mode == 2) {
  56 + writel(val0 & ~mask, reg0);
  57 + writel(val1 | mask, reg1);
  58 + } else if (mode == 3) {
  59 + writel(val0 | mask, reg0);
  60 + writel(val1 | mask, reg1);
  61 + } else {
  62 + writel(val0 & ~mask, reg0);
  63 + writel(val1 & ~mask, reg1);
  64 + }
  65 +}
  66 +
  67 +static void do_board_detect(void)
  68 +{
  69 + int i;
  70 + u16 pval;
  71 +
  72 + /* MIIM 1 + 2 MDC/MDIO */
  73 + for (i = 56; i < 60; i++)
  74 + vcoreiii_gpio_set_alternate(i, 1);
  75 +
  76 + if (mscc_phy_rd(0, 0x10, 0x3, &pval) == 0 &&
  77 + ((pval >> 4) & 0x3F) == 0x3c) {
  78 + gd->board_type = BOARD_TYPE_PCB112; /* Serval2-NID */
  79 + } else if (mscc_phy_rd(1, 0x0, 0x3, &pval) == 0 &&
  80 + ((pval >> 4) & 0x3F) == 0x3c) {
  81 + gd->board_type = BOARD_TYPE_PCB110; /* Jr2-24 */
  82 + } else {
  83 + /* Fall-back */
  84 + gd->board_type = BOARD_TYPE_PCB111; /* Jr2-48 */
  85 + }
  86 +}
  87 +
  88 +#if defined(CONFIG_MULTI_DTB_FIT)
  89 +int board_fit_config_name_match(const char *name)
  90 +{
  91 + if (gd->board_type == BOARD_TYPE_PCB110 &&
  92 + strcmp(name, "jr2_pcb110") == 0)
  93 + return 0;
  94 +
  95 + if (gd->board_type == BOARD_TYPE_PCB111 &&
  96 + strcmp(name, "jr2_pcb111") == 0)
  97 + return 0;
  98 +
  99 + if (gd->board_type == BOARD_TYPE_PCB112 &&
  100 + strcmp(name, "serval2_pcb112") == 0)
  101 + return 0;
  102 +
  103 + return -1;
  104 +}
  105 +#endif
  106 +
  107 +#if defined(CONFIG_DTB_RESELECT)
  108 +int embedded_dtb_select(void)
  109 +{
  110 + do_board_detect();
  111 + fdtdec_setup();
  112 +
  113 + return 0;
  114 +}
  115 +#endif
board/mscc/luton/luton.c
Diff comments   View file @ f83ef0d
... ... @@ -5,16 +5,20 @@
5 5  
6 6 #include <common.h>
7 7 #include <asm/io.h>
  8 +#include <led.h>
8 9  
9   -#define MSCC_GPIO_ALT0 0x88
10   -#define MSCC_GPIO_ALT1 0x8C
11   -
12 10 DECLARE_GLOBAL_DATA_PTR;
13 11  
  12 +enum {
  13 + BOARD_TYPE_PCB090 = 0xAABBCD00,
  14 + BOARD_TYPE_PCB091,
  15 +};
  16 +
14 17 void board_debug_uart_init(void)
15 18 {
16 19 /* too early for the pinctrl driver, so configure the UART pins here */
17   - setbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT0, BIT(30) | BIT(31));
  20 + mscc_gpio_set_alternate(30, 1);
  21 + mscc_gpio_set_alternate(31, 1);
18 22 }
19 23  
20 24 int board_early_init_r(void)
21 25  
... ... @@ -24,6 +28,46 @@
24 28  
25 29 /* Address of boot parameters */
26 30 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
  31 +
  32 + /* LED setup */
  33 + if (IS_ENABLED(CONFIG_LED))
  34 + led_default_state();
  35 +
27 36 return 0;
28 37 }
  38 +
  39 +static void do_board_detect(void)
  40 +{
  41 + u32 chipid = (readl(BASE_DEVCPU_GCB + CHIP_ID) >> 12) & 0xFFFF;
  42 +
  43 + if (chipid == 0x7428 || chipid == 0x7424)
  44 + gd->board_type = BOARD_TYPE_PCB091; // Lu10
  45 + else
  46 + gd->board_type = BOARD_TYPE_PCB090; // Lu26
  47 +}
  48 +
  49 +#if defined(CONFIG_MULTI_DTB_FIT)
  50 +int board_fit_config_name_match(const char *name)
  51 +{
  52 + if (gd->board_type == BOARD_TYPE_PCB090 &&
  53 + strcmp(name, "luton_pcb090") == 0)
  54 + return 0;
  55 +
  56 + if (gd->board_type == BOARD_TYPE_PCB091 &&
  57 + strcmp(name, "luton_pcb091") == 0)
  58 + return 0;
  59 +
  60 + return -1;
  61 +}
  62 +#endif
  63 +
  64 +#if defined(CONFIG_DTB_RESELECT)
  65 +int embedded_dtb_select(void)
  66 +{
  67 + do_board_detect();
  68 + fdtdec_setup();
  69 +
  70 + return 0;
  71 +}
  72 +#endif
board/mscc/ocelot/ocelot.c
Diff comments   View file @ f83ef0d
... ... @@ -9,39 +9,20 @@
9 9 #include <asm/types.h>
10 10 #include <environment.h>
11 11 #include <spi.h>
  12 +#include <led.h>
12 13  
13 14 DECLARE_GLOBAL_DATA_PTR;
14 15  
15   -#define MSCC_GPIO_ALT0 0x54
16   -#define MSCC_GPIO_ALT1 0x58
  16 +enum {
  17 + BOARD_TYPE_PCB120 = 0xAABBCC00,
  18 + BOARD_TYPE_PCB123,
  19 +};
17 20  
18   -void external_cs_manage(struct udevice *dev, bool enable)
19   -{
20   - u32 cs = spi_chip_select(dev);
21   - /* IF_SI0_OWNER, select the owner of the SI interface
22   - * Encoding: 0: SI Slave
23   - * 1: SI Boot Master
24   - * 2: SI Master Controller
25   - */
26   - if (!enable) {
27   - writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE |
28   - ICPU_SW_MODE_SW_SPI_CS(BIT(cs)), BASE_CFG + ICPU_SW_MODE);
29   - clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
30   - ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
31   - ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
32   - } else {
33   - writel(0, BASE_CFG + ICPU_SW_MODE);
34   - clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
35   - ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
36   - ICPU_GENERAL_CTRL_IF_SI_OWNER(1));
37   - }
38   -}
39   -
40 21 void board_debug_uart_init(void)
41 22 {
42 23 /* too early for the pinctrl driver, so configure the UART pins here */
43   - setbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT0, BIT(6) | BIT(7));
44   - clrbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT1, BIT(6) | BIT(7));
  24 + mscc_gpio_set_alternate(6, 1);
  25 + mscc_gpio_set_alternate(7, 1);
45 26 }
46 27  
47 28 int board_early_init_r(void)
48 29  
... ... @@ -54,6 +35,49 @@
54 35  
55 36 /* Address of boot parameters */
56 37 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
  38 +
  39 + /* LED setup */
  40 + if (IS_ENABLED(CONFIG_LED))
  41 + led_default_state();
  42 +
57 43 return 0;
58 44 }
  45 +
  46 +static void do_board_detect(void)
  47 +{
  48 + u16 dummy = 0;
  49 +
  50 + /* Enable MIIM */
  51 + mscc_gpio_set_alternate(14, 1);
  52 + mscc_gpio_set_alternate(15, 1);
  53 + if (mscc_phy_rd(1, 0, 0, &dummy) == 0)
  54 + gd->board_type = BOARD_TYPE_PCB120;
  55 + else
  56 + gd->board_type = BOARD_TYPE_PCB123;
  57 +}
  58 +
  59 +#if defined(CONFIG_MULTI_DTB_FIT)
  60 +int board_fit_config_name_match(const char *name)
  61 +{
  62 + if (gd->board_type == BOARD_TYPE_PCB120 &&
  63 + strcmp(name, "ocelot_pcb120") == 0)
  64 + return 0;
  65 +
  66 + if (gd->board_type == BOARD_TYPE_PCB123 &&
  67 + strcmp(name, "ocelot_pcb123") == 0)
  68 + return 0;
  69 +
  70 + return -1;
  71 +}
  72 +#endif
  73 +
  74 +#if defined(CONFIG_DTB_RESELECT)
  75 +int embedded_dtb_select(void)
  76 +{
  77 + do_board_detect();
  78 + fdtdec_setup();
  79 +
  80 + return 0;
  81 +}
  82 +#endif
configs/bcm968380gerg_ram_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -26,7 +26,6 @@
26 26 # CONFIG_CMD_FLASH is not set
27 27 # CONFIG_CMD_LOADS is not set
28 28 # CONFIG_CMD_MISC is not set
29   -CONFIG_OF_EMBED=y
30 29 CONFIG_DEFAULT_DEVICE_TREE="brcm,bcm968380gerg"
31 30 # CONFIG_NET is not set
32 31 # CONFIG_DM_DEVICE_REMOVE is not set
configs/boston32r2_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -23,7 +23,6 @@
23 23 CONFIG_CMD_EXT4_WRITE=y
24 24 # CONFIG_DOS_PARTITION is not set
25 25 # CONFIG_ISO_PARTITION is not set
26   -CONFIG_OF_EMBED=y
27 26 CONFIG_DEFAULT_DEVICE_TREE="img,boston"
28 27 CONFIG_ENV_IS_IN_FLASH=y
29 28 CONFIG_NET_RANDOM_ETHADDR=y
configs/boston32r2el_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -24,7 +24,6 @@
24 24 CONFIG_CMD_EXT4_WRITE=y
25 25 # CONFIG_DOS_PARTITION is not set
26 26 # CONFIG_ISO_PARTITION is not set
27   -CONFIG_OF_EMBED=y
28 27 CONFIG_DEFAULT_DEVICE_TREE="img,boston"
29 28 CONFIG_ENV_IS_IN_FLASH=y
30 29 CONFIG_NET_RANDOM_ETHADDR=y
configs/boston32r6_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -24,7 +24,6 @@
24 24 CONFIG_CMD_EXT4_WRITE=y
25 25 # CONFIG_DOS_PARTITION is not set
26 26 # CONFIG_ISO_PARTITION is not set
27   -CONFIG_OF_EMBED=y
28 27 CONFIG_DEFAULT_DEVICE_TREE="img,boston"
29 28 CONFIG_ENV_IS_IN_FLASH=y
30 29 CONFIG_NET_RANDOM_ETHADDR=y
configs/boston32r6el_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -25,7 +25,6 @@
25 25 CONFIG_CMD_EXT4_WRITE=y
26 26 # CONFIG_DOS_PARTITION is not set
27 27 # CONFIG_ISO_PARTITION is not set
28   -CONFIG_OF_EMBED=y
29 28 CONFIG_DEFAULT_DEVICE_TREE="img,boston"
30 29 CONFIG_ENV_IS_IN_FLASH=y
31 30 CONFIG_NET_RANDOM_ETHADDR=y
configs/boston64r2_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -24,7 +24,6 @@
24 24 CONFIG_CMD_EXT4_WRITE=y
25 25 # CONFIG_DOS_PARTITION is not set
26 26 # CONFIG_ISO_PARTITION is not set
27   -CONFIG_OF_EMBED=y
28 27 CONFIG_DEFAULT_DEVICE_TREE="img,boston"
29 28 CONFIG_ENV_IS_IN_FLASH=y
30 29 CONFIG_NET_RANDOM_ETHADDR=y
configs/boston64r2el_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -25,7 +25,6 @@
25 25 CONFIG_CMD_EXT4_WRITE=y
26 26 # CONFIG_DOS_PARTITION is not set
27 27 # CONFIG_ISO_PARTITION is not set
28   -CONFIG_OF_EMBED=y
29 28 CONFIG_DEFAULT_DEVICE_TREE="img,boston"
30 29 CONFIG_ENV_IS_IN_FLASH=y
31 30 CONFIG_NET_RANDOM_ETHADDR=y
configs/boston64r6_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -24,7 +24,6 @@
24 24 CONFIG_CMD_EXT4_WRITE=y
25 25 # CONFIG_DOS_PARTITION is not set
26 26 # CONFIG_ISO_PARTITION is not set
27   -CONFIG_OF_EMBED=y
28 27 CONFIG_DEFAULT_DEVICE_TREE="img,boston"
29 28 CONFIG_ENV_IS_IN_FLASH=y
30 29 CONFIG_NET_RANDOM_ETHADDR=y
configs/boston64r6el_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -25,7 +25,6 @@
25 25 CONFIG_CMD_EXT4_WRITE=y
26 26 # CONFIG_DOS_PARTITION is not set
27 27 # CONFIG_ISO_PARTITION is not set
28   -CONFIG_OF_EMBED=y
29 28 CONFIG_DEFAULT_DEVICE_TREE="img,boston"
30 29 CONFIG_ENV_IS_IN_FLASH=y
31 30 CONFIG_NET_RANDOM_ETHADDR=y
configs/ci20_mmc_defconfig
Diff comments   View file @ f83ef0d
1 1 CONFIG_MIPS=y
2   -CONFIG_SPL_LDSCRIPT="arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds"
3 2 CONFIG_SYS_TEXT_BASE=0x80010000
4 3 CONFIG_SPL_GPIO_SUPPORT=y
5 4 CONFIG_SPL_LIBGENERIC_SUPPORT=y
configs/comtrend_ar5315u_ram_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -31,7 +31,6 @@
31 31 CONFIG_CMD_MII=y
32 32 CONFIG_CMD_PING=y
33 33 # CONFIG_CMD_MISC is not set
34   -CONFIG_OF_EMBED=y
35 34 CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5315u"
36 35 CONFIG_NET_RANDOM_ETHADDR=y
37 36 # CONFIG_DM_DEVICE_REMOVE is not set
configs/comtrend_ar5387un_ram_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -31,7 +31,6 @@
31 31 CONFIG_CMD_MII=y
32 32 CONFIG_CMD_PING=y
33 33 # CONFIG_CMD_MISC is not set
34   -CONFIG_OF_EMBED=y
35 34 CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5387un"
36 35 CONFIG_NET_RANDOM_ETHADDR=y
37 36 # CONFIG_DM_DEVICE_REMOVE is not set
configs/comtrend_ct5361_ram_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -28,7 +28,6 @@
28 28 CONFIG_CMD_MII=y
29 29 CONFIG_CMD_PING=y
30 30 # CONFIG_CMD_MISC is not set
31   -CONFIG_OF_EMBED=y
32 31 CONFIG_DEFAULT_DEVICE_TREE="comtrend,ct-5361"
33 32 CONFIG_NET_RANDOM_ETHADDR=y
34 33 # CONFIG_DM_DEVICE_REMOVE is not set
configs/comtrend_vr3032u_ram_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -29,7 +29,6 @@
29 29 CONFIG_CMD_MII=y
30 30 CONFIG_CMD_PING=y
31 31 # CONFIG_CMD_MISC is not set
32   -CONFIG_OF_EMBED=y
33 32 CONFIG_DEFAULT_DEVICE_TREE="comtrend,vr-3032u"
34 33 CONFIG_NET_RANDOM_ETHADDR=y
35 34 # CONFIG_DM_DEVICE_REMOVE is not set
configs/comtrend_wap5813n_ram_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -28,7 +28,6 @@
28 28 CONFIG_CMD_MII=y
29 29 CONFIG_CMD_PING=y
30 30 # CONFIG_CMD_MISC is not set
31   -CONFIG_OF_EMBED=y
32 31 CONFIG_DEFAULT_DEVICE_TREE="comtrend,wap-5813n"
33 32 CONFIG_NET_RANDOM_ETHADDR=y
34 33 # CONFIG_DM_DEVICE_REMOVE is not set
configs/gardena-smart-gateway-mt7688-ram_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -33,8 +33,8 @@
33 33 CONFIG_CMD_TIME=y
34 34 CONFIG_CMD_UUID=y
35 35 CONFIG_CMD_MTDPARTS=y
36   -CONFIG_MTDIDS_DEFAULT="spi-nand0=gd5f,nor0=spi0.0"
37   -CONFIG_MTDPARTS_DEFAULT="spi0.0:640k(uboot),64k(uboot_env0),64k(uboot_env1),64k(factory),-(unused);gd5f:-(nand)"
  36 +CONFIG_MTDIDS_DEFAULT="spi-nand0=spi0.1,nor0=spi0.0"
  37 +CONFIG_MTDPARTS_DEFAULT="spi0.0:640k(uboot),64k(uboot_env0),64k(uboot_env1),64k(factory),-(unused);spi0.1:-(nand)"
38 38 CONFIG_CMD_UBI=y
39 39 CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688"
40 40 CONFIG_ENV_IS_IN_SPI_FLASH=y
configs/gardena-smart-gateway-mt7688_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -36,8 +36,8 @@
36 36 CONFIG_CMD_TIME=y
37 37 CONFIG_CMD_UUID=y
38 38 CONFIG_CMD_MTDPARTS=y
39   -CONFIG_MTDIDS_DEFAULT="spi-nand0=gd5f,nor0=spi0.0"
40   -CONFIG_MTDPARTS_DEFAULT="spi0.0:640k(uboot),64k(uboot_env0),64k(uboot_env1),64k(factory),-(unused);gd5f:-(nand)"
  39 +CONFIG_MTDIDS_DEFAULT="spi-nand0=spi0.1,nor0=spi0.0"
  40 +CONFIG_MTDPARTS_DEFAULT="spi0.0:640k(uboot),64k(uboot_env0),64k(uboot_env1),64k(factory),-(unused);spi0.1:-(nand)"
41 41 CONFIG_CMD_UBI=y
42 42 CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688"
43 43 CONFIG_ENV_IS_IN_SPI_FLASH=y
configs/huawei_hg556a_ram_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -28,7 +28,6 @@
28 28 CONFIG_CMD_MII=y
29 29 CONFIG_CMD_PING=y
30 30 # CONFIG_CMD_MISC is not set
31   -CONFIG_OF_EMBED=y
32 31 CONFIG_DEFAULT_DEVICE_TREE="huawei,hg556a"
33 32 CONFIG_NET_RANDOM_ETHADDR=y
34 33 # CONFIG_DM_DEVICE_REMOVE is not set
configs/imgtec_xilfpga_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -17,7 +17,6 @@
17 17 CONFIG_CMD_PING=y
18 18 CONFIG_CMD_TIME=y
19 19 # CONFIG_ISO_PARTITION is not set
20   -CONFIG_OF_EMBED=y
21 20 CONFIG_DEFAULT_DEVICE_TREE="nexys4ddr"
22 21 CONFIG_NET_RANDOM_ETHADDR=y
23 22 CONFIG_NETCONSOLE=y
configs/malta64_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -18,7 +18,6 @@
18 18 CONFIG_CMD_PING=y
19 19 CONFIG_CMD_DATE=y
20 20 # CONFIG_ISO_PARTITION is not set
21   -CONFIG_OF_EMBED=y
22 21 CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
23 22 CONFIG_ENV_IS_IN_FLASH=y
24 23 CONFIG_MTD_NOR_FLASH=y
configs/malta64el_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -19,7 +19,6 @@
19 19 CONFIG_CMD_PING=y
20 20 CONFIG_CMD_DATE=y
21 21 # CONFIG_ISO_PARTITION is not set
22   -CONFIG_OF_EMBED=y
23 22 CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
24 23 CONFIG_ENV_IS_IN_FLASH=y
25 24 CONFIG_MTD_NOR_FLASH=y
configs/malta_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -17,7 +17,6 @@
17 17 CONFIG_CMD_PING=y
18 18 CONFIG_CMD_DATE=y
19 19 # CONFIG_ISO_PARTITION is not set
20   -CONFIG_OF_EMBED=y
21 20 CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
22 21 CONFIG_ENV_IS_IN_FLASH=y
23 22 CONFIG_MTD_NOR_FLASH=y
configs/maltael_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -18,7 +18,6 @@
18 18 CONFIG_CMD_PING=y
19 19 CONFIG_CMD_DATE=y
20 20 # CONFIG_ISO_PARTITION is not set
21   -CONFIG_OF_EMBED=y
22 21 CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
23 22 CONFIG_ENV_IS_IN_FLASH=y
24 23 CONFIG_MTD_NOR_FLASH=y
configs/mscc_jr2_defconfig
Diff comments   View file @ f83ef0d
  1 +CONFIG_MIPS=y
  2 +CONFIG_SYS_TEXT_BASE=0x40000000
  3 +CONFIG_SYS_MALLOC_F_LEN=0x2000
  4 +CONFIG_ARCH_MSCC=y
  5 +CONFIG_SOC_JR2=y
  6 +CONFIG_SYS_LITTLE_ENDIAN=y
  7 +CONFIG_FIT=y
  8 +CONFIG_BOOTDELAY=3
  9 +CONFIG_USE_BOOTARGS=y
  10 +CONFIG_BOOTARGS="console=ttyS0,115200"
  11 +CONFIG_LOGLEVEL=7
  12 +CONFIG_DISPLAY_CPUINFO=y
  13 +CONFIG_SYS_PROMPT="jr2 # "
  14 +# CONFIG_CMD_BDI is not set
  15 +# CONFIG_CMD_CONSOLE is not set
  16 +# CONFIG_CMD_ELF is not set
  17 +# CONFIG_CMD_EXPORTENV is not set
  18 +# CONFIG_CMD_IMPORTENV is not set
  19 +# CONFIG_CMD_CRC32 is not set
  20 +CONFIG_CMD_MD5SUM=y
  21 +CONFIG_CMD_MEMINFO=y
  22 +CONFIG_CMD_MEMTEST=y
  23 +# CONFIG_CMD_FLASH is not set
  24 +CONFIG_CMD_GPIO=y
  25 +CONFIG_CMD_SF=y
  26 +CONFIG_CMD_SPI=y
  27 +# CONFIG_CMD_NET is not set
  28 +CONFIG_CMD_MTDPARTS=y
  29 +CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
  30 +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:1m(UBoot),256k(Env),256k(Env.bk)"
  31 +# CONFIG_ISO_PARTITION is not set
  32 +CONFIG_DEFAULT_DEVICE_TREE="jr2_pcb110"
  33 +CONFIG_OF_LIST="jr2_pcb110 jr2_pcb111 serval2_pcb112"
  34 +CONFIG_DTB_RESELECT=y
  35 +CONFIG_MULTI_DTB_FIT=y
  36 +CONFIG_ENV_IS_IN_SPI_FLASH=y
  37 +CONFIG_NET_RANDOM_ETHADDR=y
  38 +CONFIG_CLK=y
  39 +CONFIG_DM_GPIO=y
  40 +CONFIG_MSCC_SGPIO=y
  41 +CONFIG_LED=y
  42 +CONFIG_LED_GPIO=y
  43 +CONFIG_DM_SPI_FLASH=y
  44 +CONFIG_SPI_FLASH=y
  45 +CONFIG_SPI_FLASH_BAR=y
  46 +CONFIG_SPI_FLASH_GIGADEVICE=y
  47 +CONFIG_SPI_FLASH_MACRONIX=y
  48 +CONFIG_SPI_FLASH_SPANSION=y
  49 +CONFIG_SPI_FLASH_WINBOND=y
  50 +CONFIG_SPI_FLASH_MTD=y
  51 +CONFIG_DM_ETH=y
  52 +CONFIG_PINCTRL=y
  53 +CONFIG_PINCONF=y
  54 +CONFIG_DM_SERIAL=y
  55 +CONFIG_SYS_NS16550=y
  56 +CONFIG_SPI=y
  57 +CONFIG_DM_SPI=y
  58 +CONFIG_LZMA=y
  59 +CONFIG_XZ=y
configs/mscc_luton_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -5,7 +5,7 @@
5 5 CONFIG_DEBUG_UART_BASE=0x70100000
6 6 CONFIG_DEBUG_UART_CLOCK=208333333
7 7 CONFIG_ARCH_MSCC=y
8   -CONFIG_TARGET_LUTON_PCB091=y
  8 +CONFIG_SOC_LUTON=y
9 9 CONFIG_DDRTYPE_MT47H128M8HQ=y
10 10 CONFIG_SYS_LITTLE_ENDIAN=y
11 11 CONFIG_MIPS_BOOT_FDT=y
... ... @@ -16,7 +16,7 @@
16 16 CONFIG_BOOTARGS="console=ttyS0,115200"
17 17 CONFIG_LOGLEVEL=7
18 18 CONFIG_DISPLAY_CPUINFO=y
19   -CONFIG_SYS_PROMPT="pcb091 # "
  19 +CONFIG_SYS_PROMPT="luton # "
20 20 # CONFIG_CMD_BDI is not set
21 21 # CONFIG_CMD_CONSOLE is not set
22 22 # CONFIG_CMD_ELF is not set
23 23  
24 24  
... ... @@ -34,15 +34,22 @@
34 34 # CONFIG_NET_TFTP_VARS is not set
35 35 # CONFIG_CMD_NFS is not set
36 36 CONFIG_CMD_PING=y
  37 +CONFIG_CMD_TIME=y
37 38 CONFIG_CMD_MTDPARTS=y
38 39 CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
39 40 CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),6m@1m(linux)"
40 41 # CONFIG_ISO_PARTITION is not set
41 42 CONFIG_DEFAULT_DEVICE_TREE="luton_pcb091"
  43 +CONFIG_OF_LIST="luton_pcb090 luton_pcb091"
  44 +CONFIG_DTB_RESELECT=y
  45 +CONFIG_MULTI_DTB_FIT=y
42 46 CONFIG_ENV_IS_IN_SPI_FLASH=y
43 47 CONFIG_NET_RANDOM_ETHADDR=y
44 48 CONFIG_CLK=y
45 49 CONFIG_DM_GPIO=y
  50 +CONFIG_MSCC_SGPIO=y
  51 +CONFIG_LED=y
  52 +CONFIG_LED_GPIO=y
46 53 CONFIG_DM_SPI_FLASH=y
47 54 CONFIG_SPI_FLASH=y
48 55 CONFIG_SPI_FLASH_BAR=y
... ... @@ -60,6 +67,6 @@
60 67 CONFIG_SYS_NS16550=y
61 68 CONFIG_SPI=y
62 69 CONFIG_DM_SPI=y
63   -CONFIG_SOFT_SPI=y
  70 +CONFIG_MSCC_BB_SPI=y
64 71 CONFIG_LZMA=y
configs/mscc_ocelot_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -5,7 +5,6 @@
5 5 CONFIG_DEBUG_UART_BASE=0x70100000
6 6 CONFIG_DEBUG_UART_CLOCK=250000000
7 7 CONFIG_ARCH_MSCC=y
8   -CONFIG_TARGET_OCELOT_PCB123=y
9 8 CONFIG_SYS_LITTLE_ENDIAN=y
10 9 CONFIG_DEBUG_UART=y
11 10 CONFIG_FIT=y
... ... @@ -14,7 +13,7 @@
14 13 CONFIG_BOOTARGS="console=ttyS0,115200"
15 14 CONFIG_LOGLEVEL=7
16 15 CONFIG_DISPLAY_CPUINFO=y
17   -CONFIG_SYS_PROMPT="pcb123 # "
  16 +CONFIG_SYS_PROMPT="ocelot # "
18 17 # CONFIG_CMD_BDI is not set
19 18 # CONFIG_CMD_CONSOLE is not set
20 19 # CONFIG_CMD_ELF is not set
21 20  
... ... @@ -40,12 +39,18 @@
40 39 # CONFIG_CMD_UBIFS is not set
41 40 # CONFIG_ISO_PARTITION is not set
42 41 CONFIG_DEFAULT_DEVICE_TREE="ocelot_pcb123"
  42 +CONFIG_OF_LIST="ocelot_pcb120 ocelot_pcb123"
  43 +CONFIG_DTB_RESELECT=y
  44 +CONFIG_MULTI_DTB_FIT=y
43 45 CONFIG_ENV_IS_IN_SPI_FLASH=y
44 46 CONFIG_NET_RANDOM_ETHADDR=y
45 47 CONFIG_CLK=y
46 48 CONFIG_DM_GPIO=y
47 49 CONFIG_MTD=y
48 50 CONFIG_MTD_SPI_NAND=y
  51 +CONFIG_MSCC_SGPIO=y
  52 +CONFIG_LED=y
  53 +CONFIG_LED_GPIO=y
49 54 CONFIG_DM_SPI_FLASH=y
50 55 CONFIG_SPI_FLASH=y
51 56 CONFIG_SPI_FLASH_BAR=y
... ... @@ -63,6 +68,5 @@
63 68 CONFIG_SYS_NS16550=y
64 69 CONFIG_SPI=y
65 70 CONFIG_DM_SPI=y
66   -CONFIG_DESIGNWARE_SPI=y
67 71 CONFIG_LZMA=y
configs/mscc_ocelot_pcb120_defconfig
View file @ f83ef0d
1   -CONFIG_MIPS=y
2   -CONFIG_SYS_TEXT_BASE=0x40000000
3   -CONFIG_SYS_MALLOC_F_LEN=0x2000
4   -CONFIG_ARCH_MSCC=y
5   -CONFIG_SYS_LITTLE_ENDIAN=y
6   -CONFIG_FIT=y
7   -CONFIG_BOOTDELAY=3
8   -CONFIG_USE_BOOTARGS=y
9   -CONFIG_BOOTARGS="console=ttyS0,115200"
10   -CONFIG_LOGLEVEL=7
11   -CONFIG_DISPLAY_CPUINFO=y
12   -CONFIG_SYS_PROMPT="pcb120 # "
13   -# CONFIG_CMD_BDI is not set
14   -# CONFIG_CMD_CONSOLE is not set
15   -# CONFIG_CMD_ELF is not set
16   -# CONFIG_CMD_EXPORTENV is not set
17   -# CONFIG_CMD_IMPORTENV is not set
18   -# CONFIG_CMD_CRC32 is not set
19   -CONFIG_CMD_MD5SUM=y
20   -CONFIG_CMD_MEMINFO=y
21   -CONFIG_CMD_MEMTEST=y
22   -# CONFIG_CMD_FLASH is not set
23   -CONFIG_CMD_GPIO=y
24   -CONFIG_CMD_MTD=y
25   -CONFIG_CMD_SF=y
26   -CONFIG_CMD_SPI=y
27   -CONFIG_CMD_DHCP=y
28   -# CONFIG_NET_TFTP_VARS is not set
29   -# CONFIG_CMD_NFS is not set
30   -CONFIG_CMD_PING=y
31   -CONFIG_CMD_MTDPARTS=y
32   -CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
33   -CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),15m(linux),15m(linux.bk)"
34   -CONFIG_CMD_UBI=y
35   -# CONFIG_CMD_UBIFS is not set
36   -# CONFIG_ISO_PARTITION is not set
37   -CONFIG_DEFAULT_DEVICE_TREE="ocelot_pcb120"
38   -CONFIG_ENV_IS_IN_SPI_FLASH=y
39   -CONFIG_NET_RANDOM_ETHADDR=y
40   -CONFIG_CLK=y
41   -CONFIG_DM_GPIO=y
42   -CONFIG_MTD=y
43   -CONFIG_MTD_SPI_NAND=y
44   -CONFIG_DM_SPI_FLASH=y
45   -CONFIG_SPI_FLASH=y
46   -CONFIG_SPI_FLASH_BAR=y
47   -CONFIG_SPI_FLASH_GIGADEVICE=y
48   -CONFIG_SPI_FLASH_MACRONIX=y
49   -CONFIG_SPI_FLASH_SPANSION=y
50   -CONFIG_SPI_FLASH_WINBOND=y
51   -CONFIG_SPI_FLASH_MTD=y
52   -CONFIG_DM_ETH=y
53   -CONFIG_PINCTRL=y
54   -CONFIG_PINCONF=y
55   -CONFIG_DM_SERIAL=y
56   -CONFIG_SYS_NS16550=y
57   -CONFIG_SPI=y
58   -CONFIG_DM_SPI=y
59   -CONFIG_DESIGNWARE_SPI=y
60   -CONFIG_LZMA=y
configs/netgear_cg3100d_ram_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -27,7 +27,6 @@
27 27 CONFIG_CMD_SF=y
28 28 CONFIG_CMD_SPI=y
29 29 # CONFIG_CMD_MISC is not set
30   -CONFIG_OF_EMBED=y
31 30 CONFIG_DEFAULT_DEVICE_TREE="netgear,cg3100d"
32 31 # CONFIG_NET is not set
33 32 # CONFIG_DM_DEVICE_REMOVE is not set
configs/netgear_dgnd3700v2_ram_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -30,7 +30,6 @@
30 30 CONFIG_CMD_MII=y
31 31 CONFIG_CMD_PING=y
32 32 # CONFIG_CMD_MISC is not set
33   -CONFIG_OF_EMBED=y
34 33 CONFIG_DEFAULT_DEVICE_TREE="netgear,dgnd3700v2"
35 34 CONFIG_NET_RANDOM_ETHADDR=y
36 35 # CONFIG_DM_DEVICE_REMOVE is not set
configs/pic32mzdask_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -21,7 +21,6 @@
21 21 CONFIG_CMD_EXT4_WRITE=y
22 22 # CONFIG_ISO_PARTITION is not set
23 23 # CONFIG_EFI_PARTITION is not set
24   -CONFIG_OF_EMBED=y
25 24 CONFIG_DEFAULT_DEVICE_TREE="pic32mzda_sk"
26 25 CONFIG_NET_RANDOM_ETHADDR=y
27 26 # CONFIG_BLK is not set
configs/sagem_f@st1704_ram_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -30,7 +30,6 @@
30 30 CONFIG_CMD_MII=y
31 31 CONFIG_CMD_PING=y
32 32 # CONFIG_CMD_MISC is not set
33   -CONFIG_OF_EMBED=y
34 33 CONFIG_DEFAULT_DEVICE_TREE="sagem,f@st1704"
35 34 CONFIG_NET_RANDOM_ETHADDR=y
36 35 # CONFIG_DM_DEVICE_REMOVE is not set
configs/sfr_nb4-ser_ram_defconfig
Diff comments   View file @ f83ef0d
... ... @@ -29,7 +29,6 @@
29 29 CONFIG_CMD_MII=y
30 30 CONFIG_CMD_PING=y
31 31 # CONFIG_CMD_MISC is not set
32   -CONFIG_OF_EMBED=y
33 32 CONFIG_DEFAULT_DEVICE_TREE="sfr,nb4-ser"
34 33 CONFIG_NET_RANDOM_ETHADDR=y
35 34 # CONFIG_DM_DEVICE_REMOVE is not set
doc/device-tree-bindings/gpio/mscc_sgpio.txt
Diff comments   View file @ f83ef0d
  1 +Microsemi Corporation (MSCC) Serial GPIO driver
  2 +
  3 +The MSCC serial GPIO extends the number or GPIO's on the system by
  4 +means of 4 dedicated pins: one input, one output, one clock and one
  5 +strobe pin. By attaching a number of (external) shift registers, the
  6 +effective GPIO count can be extended by up to 128 GPIO's per
  7 +controller.
  8 +
  9 +Required properties:
  10 +- compatible : "mscc,luton-sgpio" or "mscc,ocelot-sgpio"
  11 +- clock: Reference clock used to generate clock divider setting. See
  12 + mscc,sgpio-frequency property.
  13 +- reg : Physical base address and length of the controller's registers.
  14 +- #gpio-cells : Should be two. The first cell is the pin number and the
  15 + second cell is used to specify optional parameters:
  16 + - bit 0 specifies polarity (0 for normal, 1 for inverted)
  17 +- gpio-controller : Marks the device node as a GPIO controller.
  18 +- gpio-ranges: Standard gpio range(s): phandle, gpio base, pinctrl base
  19 + and count.
  20 +
  21 +Optional properties:
  22 +- ngpios: See gpio.txt
  23 +- mscc,sgpio-frequency: The frequency at which the serial bitstream is
  24 + generated and sampled. Default: 12500000 (Hz).
  25 +- mscc,sgpio-ports: A bitmask (32 bits) of which ports are enabled in
  26 + the serialized gpio stream. One 'port' will transport from 1 to 4
  27 + gpio bits. Default: 0xFFFFFFFF.
  28 +
  29 +Typically the pinctrl-0 and pinctrl-names properties will also be
  30 +present to enable the use of the SIO CLK, LD, DI and DO for some
  31 +regular GPIO pins.
  32 +
  33 +Example:
  34 +
  35 +sgpio: gpio@10700f8 {
  36 + compatible = "mscc,ocelot-sgpio";
  37 + pinctrl-0 = <&sgpio_pins>;
  38 + pinctrl-names = "default";
  39 + reg = <0x10700f8 0x100>;
  40 + gpio-controller;
  41 + #gpio-cells = <2>;
  42 + gpio-ranges = <&sgpio 0 0 64>;
  43 + mscc,sgpio-frequency = <12500>;
  44 + mscc,sgpio-ports = <0x000FFFFF>;
  45 +};
drivers/gpio/Kconfig
Diff comments   View file @ f83ef0d
... ... @@ -99,12 +99,16 @@
99 99 help
100 100 Support for the LPC32XX GPIO driver.
101 101  
102   -config MSCC_BITBANG_SPI_GPIO
103   - bool "Microsemi bitbang spi GPIO driver"
  102 +config MSCC_SGPIO
  103 + bool "Microsemi Serial GPIO driver"
104 104 depends on DM_GPIO && SOC_VCOREIII
105 105 help
106   - Support controlling the GPIO used for SPI bitbang by software. Can
107   - be used by the VCoreIII SoCs, but it was mainly useful for Luton.
  106 + Support for the VCoreIII SoC serial GPIO device. By using a
  107 + serial interface, the SIO controller significantly extends
  108 + the number of available GPIOs with a minimum number of
  109 + additional pins on the device. The primary purpose of the
  110 + SIO controller is to connect control signals from SFP
  111 + modules and to act as an LED controller.
108 112  
109 113 config MSM_GPIO
110 114 bool "Qualcomm GPIO driver"
drivers/gpio/Makefile
Diff comments   View file @ f83ef0d
... ... @@ -59,5 +59,5 @@
59 59 obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o
60 60 obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o
61 61 obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o
62   -obj-$(CONFIG_MSCC_BITBANG_SPI_GPIO) += gpio-mscc-bitbang-spi.o
  62 +obj-$(CONFIG_MSCC_SGPIO) += mscc_sgpio.o
drivers/gpio/gpio-mscc-bitbang-spi.c
View file @ f83ef0d
1   -// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2   -/*
3   - * Microsemi SoCs pinctrl driver
4   - *
5   - * Author: <gregory.clement@bootlin.com>
6   - * License: Dual MIT/GPL
7   - * Copyright (c) 2018 Microsemi Corporation
8   - */
9   -
10   -#include <common.h>
11   -#include <asm-generic/gpio.h>
12   -#include <asm/io.h>
13   -#include <dm.h>
14   -#include <errno.h>
15   -
16   -enum {
17   - SDI,
18   - CS0,
19   - CS1,
20   - CS2,
21   - CS3,
22   - SDO,
23   - SCK
24   -};
25   -
26   -static const int pinmap[] = { 0, 5, 6, 7, 8, 10, 12 };
27   -
28   -#define SW_SPI_CSn_OE 0x1E /* bits 1 to 4 */
29   -#define SW_SPI_CS0_OE BIT(1)
30   -#define SW_SPI_SDO_OE BIT(9)
31   -#define SW_SPI_SCK_OE BIT(11)
32   -#define SW_PIN_CTRL_MODE BIT(13)
33   -
34   -struct mscc_bb_spi_gpio {
35   - void __iomem *regs;
36   - u32 cache_val;
37   -};
38   -
39   -static int mscc_bb_spi_gpio_set(struct udevice *dev, unsigned oft, int val)
40   -{
41   - struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
42   -
43   - if (val)
44   - gpio->cache_val |= BIT(pinmap[oft]);
45   - else
46   - gpio->cache_val &= ~BIT(pinmap[oft]);
47   -
48   - writel(gpio->cache_val, gpio->regs);
49   -
50   - return 0;
51   -}
52   -
53   -static int mscc_bb_spi_gpio_direction_output(struct udevice *dev, unsigned oft,
54   - int val)
55   -{
56   - if (oft == 0) {
57   - pr_err("SW_SPI_DSI can't be used as output\n");
58   - return -ENOTSUPP;
59   - }
60   -
61   - mscc_bb_spi_gpio_set(dev, oft, val);
62   -
63   - return 0;
64   -}
65   -
66   -static int mscc_bb_spi_gpio_direction_input(struct udevice *dev, unsigned oft)
67   -{
68   - return 0;
69   -}
70   -
71   -static int mscc_bb_spi_gpio_get(struct udevice *dev, unsigned int oft)
72   -{
73   - struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
74   - u32 val = readl(gpio->regs);
75   -
76   - return !!(val & BIT(pinmap[oft]));
77   -}
78   -
79   -static const struct dm_gpio_ops mscc_bb_spi_gpio_ops = {
80   - .direction_output = mscc_bb_spi_gpio_direction_output,
81   - .direction_input = mscc_bb_spi_gpio_direction_input,
82   - .set_value = mscc_bb_spi_gpio_set,
83   - .get_value = mscc_bb_spi_gpio_get,
84   -};
85   -
86   -static int mscc_bb_spi_gpio_probe(struct udevice *dev)
87   -{
88   - struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
89   - struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
90   -
91   - gpio->regs = dev_remap_addr(dev);
92   - if (!gpio->regs)
93   - return -EINVAL;
94   -
95   - uc_priv->bank_name = dev->name;
96   - uc_priv->gpio_count = ARRAY_SIZE(pinmap);
97   - /*
98   - * Enable software mode to control the SPI pin, enables the
99   - * output mode for most of the pin and initialize the cache
100   - * value in the same time
101   - */
102   -
103   - gpio->cache_val = SW_PIN_CTRL_MODE | SW_SPI_SCK_OE | SW_SPI_SDO_OE |
104   - SW_SPI_CS0_OE;
105   - writel(gpio->cache_val, gpio->regs);
106   -
107   - return 0;
108   -}
109   -
110   -static const struct udevice_id mscc_bb_spi_gpio_ids[] = {
111   - {.compatible = "mscc,spi-bitbang-gpio"},
112   - {}
113   -};
114   -
115   -U_BOOT_DRIVER(gpio_mscc_bb_spi) = {
116   - .name = "gpio-mscc-spi-bitbang",
117   - .id = UCLASS_GPIO,
118   - .ops = &mscc_bb_spi_gpio_ops,
119   - .probe = mscc_bb_spi_gpio_probe,
120   - .of_match = of_match_ptr(mscc_bb_spi_gpio_ids),
121   - .priv_auto_alloc_size = sizeof(struct mscc_bb_spi_gpio),
122   -};
drivers/gpio/mscc_sgpio.c
Diff comments   View file @ f83ef0d
  1 +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2 +/*
  3 + * Microsemi SoCs serial gpio driver
  4 + *
  5 + * Author: <lars.povlsen@microchip.com>
  6 + *
  7 + * Copyright (c) 2018 Microsemi Corporation
  8 + */
  9 +
  10 +#include <common.h>
  11 +#include <dm.h>
  12 +#include <asm/gpio.h>
  13 +#include <asm/io.h>
  14 +#include <errno.h>
  15 +#include <clk.h>
  16 +
  17 +#define MSCC_SGPIOS_PER_BANK 32
  18 +#define MSCC_SGPIO_BANK_DEPTH 4
  19 +
  20 +enum {
  21 + REG_INPUT_DATA,
  22 + REG_PORT_CONFIG,
  23 + REG_PORT_ENABLE,
  24 + REG_SIO_CONFIG,
  25 + REG_SIO_CLOCK,
  26 + MAXREG
  27 +};
  28 +
  29 +struct mscc_sgpio_bf {
  30 + u8 beg;
  31 + u8 end;
  32 +};
  33 +
  34 +struct mscc_sgpio_props {
  35 + u8 regoff[MAXREG];
  36 + struct mscc_sgpio_bf auto_repeat;
  37 + struct mscc_sgpio_bf port_width;
  38 + struct mscc_sgpio_bf clk_freq;
  39 + struct mscc_sgpio_bf bit_source;
  40 +};
  41 +
  42 +#define __M(bf) GENMASK((bf).end, (bf).beg)
  43 +#define __F(bf, x) (__M(bf) & ((x) << (bf).beg))
  44 +#define __X(bf, x) (((x) >> (bf).beg) & GENMASK(((bf).end - (bf).beg), 0))
  45 +
  46 +#define MSCC_M_CFG_SIO_AUTO_REPEAT(p) BIT(p->props->auto_repeat.beg)
  47 +#define MSCC_F_CFG_SIO_PORT_WIDTH(p, x) __F(p->props->port_width, x)
  48 +#define MSCC_M_CFG_SIO_PORT_WIDTH(p) __M(p->props->port_width)
  49 +#define MSCC_F_CLOCK_SIO_CLK_FREQ(p, x) __F(p->props->clk_freq, x)
  50 +#define MSCC_M_CLOCK_SIO_CLK_FREQ(p) __M(p->props->clk_freq)
  51 +#define MSCC_F_PORT_CFG_BIT_SOURCE(p, x) __F(p->props->bit_source, x)
  52 +#define MSCC_X_PORT_CFG_BIT_SOURCE(p, x) __X(p->props->bit_source, x)
  53 +
  54 +const struct mscc_sgpio_props props_luton = {
  55 + .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b },
  56 + .auto_repeat = { 5, 5 },
  57 + .port_width = { 2, 3 },
  58 + .clk_freq = { 0, 11 },
  59 + .bit_source = { 0, 11 },
  60 +};
  61 +
  62 +const struct mscc_sgpio_props props_ocelot = {
  63 + .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 },
  64 + .auto_repeat = { 10, 10 },
  65 + .port_width = { 7, 8 },
  66 + .clk_freq = { 8, 19 },
  67 + .bit_source = { 12, 23 },
  68 +};
  69 +
  70 +struct mscc_sgpio_priv {
  71 + u32 bitcount;
  72 + u32 ports;
  73 + u32 clock;
  74 + u32 mode[MSCC_SGPIOS_PER_BANK];
  75 + u32 __iomem *regs;
  76 + const struct mscc_sgpio_props *props;
  77 +};
  78 +
  79 +static inline u32 sgpio_readl(struct mscc_sgpio_priv *priv, u32 rno, u32 off)
  80 +{
  81 + u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
  82 +
  83 + return readl(reg);
  84 +}
  85 +
  86 +static inline void sgpio_writel(struct mscc_sgpio_priv *priv,
  87 + u32 val, u32 rno, u32 off)
  88 +{
  89 + u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
  90 +
  91 + writel(val, reg);
  92 +}
  93 +
  94 +static void sgpio_clrsetbits(struct mscc_sgpio_priv *priv,
  95 + u32 rno, u32 off, u32 clear, u32 set)
  96 +{
  97 + u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
  98 +
  99 + clrsetbits_le32(reg, clear, set);
  100 +}
  101 +
  102 +static int mscc_sgpio_direction_input(struct udevice *dev, unsigned int gpio)
  103 +{
  104 + struct mscc_sgpio_priv *priv = dev_get_priv(dev);
  105 +
  106 + u32 port = gpio % MSCC_SGPIOS_PER_BANK;
  107 + u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
  108 +
  109 + priv->mode[port] |= BIT(bit);
  110 +
  111 + return 0;
  112 +}
  113 +
  114 +static int mscc_sgpio_direction_output(struct udevice *dev,
  115 + unsigned int gpio, int value)
  116 +{
  117 + struct mscc_sgpio_priv *priv = dev_get_priv(dev);
  118 + u32 port = gpio % MSCC_SGPIOS_PER_BANK;
  119 + u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
  120 + u32 mask = 3 << (3 * bit);
  121 +
  122 + debug("set: port %d, bit %d, mask 0x%08x, value %d\n",
  123 + port, bit, mask, value);
  124 +
  125 + value = (value & 3) << (3 * bit);
  126 + sgpio_clrsetbits(priv, REG_PORT_CONFIG, port,
  127 + MSCC_F_PORT_CFG_BIT_SOURCE(priv, mask),
  128 + MSCC_F_PORT_CFG_BIT_SOURCE(priv, value));
  129 + clrbits_le32(&priv->mode[port], BIT(bit));
  130 +
  131 + return 0;
  132 +}
  133 +
  134 +static int mscc_sgpio_get_function(struct udevice *dev, unsigned int gpio)
  135 +{
  136 + struct mscc_sgpio_priv *priv = dev_get_priv(dev);
  137 + u32 port = gpio % MSCC_SGPIOS_PER_BANK;
  138 + u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
  139 + u32 val = priv->mode[port] & BIT(bit);
  140 +
  141 + if (val)
  142 + return GPIOF_INPUT;
  143 + else
  144 + return GPIOF_OUTPUT;
  145 +}
  146 +
  147 +static int mscc_sgpio_set_value(struct udevice *dev,
  148 + unsigned int gpio, int value)
  149 +{
  150 + return mscc_sgpio_direction_output(dev, gpio, value);
  151 +}
  152 +
  153 +static int mscc_sgpio_get_value(struct udevice *dev, unsigned int gpio)
  154 +{
  155 + struct mscc_sgpio_priv *priv = dev_get_priv(dev);
  156 + u32 port = gpio % MSCC_SGPIOS_PER_BANK;
  157 + u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
  158 + int ret;
  159 +
  160 + if (mscc_sgpio_get_function(dev, gpio) == GPIOF_INPUT) {
  161 + ret = !!(sgpio_readl(priv, REG_INPUT_DATA, bit) & BIT(port));
  162 + } else {
  163 + u32 portval = sgpio_readl(priv, REG_PORT_CONFIG, port);
  164 +
  165 + ret = MSCC_X_PORT_CFG_BIT_SOURCE(priv, portval);
  166 + ret = !!(ret & (3 << (3 * bit)));
  167 + }
  168 +
  169 + debug("get: gpio %d, port %d, bit %d, value %d\n",
  170 + gpio, port, bit, ret);
  171 + return ret;
  172 +}
  173 +
  174 +static int mscc_sgpio_get_count(struct udevice *dev)
  175 +{
  176 + struct ofnode_phandle_args args;
  177 + int count = 0, i = 0, ret;
  178 +
  179 + ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3, i, &args);
  180 + while (ret != -ENOENT) {
  181 + count += args.args[2];
  182 + ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
  183 + ++i, &args);
  184 + }
  185 + return count;
  186 +}
  187 +
  188 +static int mscc_sgpio_probe(struct udevice *dev)
  189 +{
  190 + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  191 + struct mscc_sgpio_priv *priv = dev_get_priv(dev);
  192 + int err, div_clock = 0, port;
  193 + u32 val;
  194 + struct clk clk;
  195 +
  196 + err = clk_get_by_index(dev, 0, &clk);
  197 + if (!err) {
  198 + err = clk_get_rate(&clk);
  199 + if (IS_ERR_VALUE(err)) {
  200 + dev_err(dev, "Invalid clk rate\n");
  201 + return -EINVAL;
  202 + }
  203 + div_clock = err;
  204 + } else {
  205 + dev_err(dev, "Failed to get clock\n");
  206 + return err;
  207 + }
  208 +
  209 + priv->props = (const struct mscc_sgpio_props *)dev_get_driver_data(dev);
  210 + priv->ports = dev_read_u32_default(dev, "mscc,sgpio-ports", 0xFFFFFFFF);
  211 + priv->clock = dev_read_u32_default(dev, "mscc,sgpio-frequency",
  212 + 12500000);
  213 + if (priv->clock <= 0 || priv->clock > div_clock) {
  214 + dev_err(dev, "Invalid frequency %d\n", priv->clock);
  215 + return -EINVAL;
  216 + }
  217 +
  218 + uc_priv->gpio_count = mscc_sgpio_get_count(dev);
  219 + uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios",
  220 + uc_priv->gpio_count);
  221 + if (uc_priv->gpio_count < 1 || uc_priv->gpio_count >
  222 + (4 * MSCC_SGPIOS_PER_BANK)) {
  223 + dev_err(dev, "Invalid gpio count %d\n", uc_priv->gpio_count);
  224 + return -EINVAL;
  225 + }
  226 + priv->bitcount = DIV_ROUND_UP(uc_priv->gpio_count,
  227 + MSCC_SGPIOS_PER_BANK);
  228 + debug("probe: gpios = %d, bit-count = %d\n",
  229 + uc_priv->gpio_count, priv->bitcount);
  230 +
  231 + priv->regs = (u32 __iomem *)dev_read_addr(dev);
  232 + uc_priv->bank_name = "sgpio";
  233 +
  234 + sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0,
  235 + MSCC_M_CFG_SIO_PORT_WIDTH(priv),
  236 + MSCC_F_CFG_SIO_PORT_WIDTH(priv, priv->bitcount - 1) |
  237 + MSCC_M_CFG_SIO_AUTO_REPEAT(priv));
  238 + val = div_clock / priv->clock;
  239 + debug("probe: div-clock = %d KHz, freq = %d KHz, div = %d\n",
  240 + div_clock / 1000, priv->clock / 1000, val);
  241 + sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0,
  242 + MSCC_M_CLOCK_SIO_CLK_FREQ(priv),
  243 + MSCC_F_CLOCK_SIO_CLK_FREQ(priv, val));
  244 +
  245 + for (port = 0; port < 32; port++)
  246 + sgpio_writel(priv, 0, REG_PORT_CONFIG, port);
  247 + sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0);
  248 +
  249 + debug("probe: sgpio regs = %p\n", priv->regs);
  250 +
  251 + return 0;
  252 +}
  253 +
  254 +static const struct dm_gpio_ops mscc_sgpio_ops = {
  255 + .direction_input = mscc_sgpio_direction_input,
  256 + .direction_output = mscc_sgpio_direction_output,
  257 + .get_function = mscc_sgpio_get_function,
  258 + .get_value = mscc_sgpio_get_value,
  259 + .set_value = mscc_sgpio_set_value,
  260 +};
  261 +
  262 +static const struct udevice_id mscc_sgpio_ids[] = {
  263 + { .compatible = "mscc,luton-sgpio", .data = (ulong)&props_luton },
  264 + { .compatible = "mscc,ocelot-sgpio", .data = (ulong)&props_ocelot },
  265 + { }
  266 +};
  267 +
  268 +U_BOOT_DRIVER(gpio_mscc_sgpio) = {
  269 + .name = "mscc-sgpio",
  270 + .id = UCLASS_GPIO,
  271 + .of_match = mscc_sgpio_ids,
  272 + .ops = &mscc_sgpio_ops,
  273 + .probe = mscc_sgpio_probe,
  274 + .priv_auto_alloc_size = sizeof(struct mscc_sgpio_priv),
  275 +};
drivers/mmc/jz_mmc.c
Diff comments   View file @ f83ef0d
... ... @@ -134,6 +134,60 @@
134 134 return 24000000;
135 135 }
136 136  
  137 +#if CONFIG_IS_ENABLED(MMC_WRITE)
  138 +static inline void jz_mmc_write_data(struct jz_mmc_priv *priv, struct mmc_data *data)
  139 +{
  140 + int sz = DIV_ROUND_UP(data->blocks * data->blocksize, 4);
  141 + const void *buf = data->src;
  142 +
  143 + while (sz--) {
  144 + u32 val = get_unaligned_le32(buf);
  145 +
  146 + wait_for_bit_le32(priv->regs + MSC_IREG,
  147 + MSC_IREG_TXFIFO_WR_REQ,
  148 + true, 10000, false);
  149 + writel(val, priv->regs + MSC_TXFIFO);
  150 + buf += 4;
  151 + }
  152 +}
  153 +#else
  154 +static void jz_mmc_write_data(struct jz_mmc_priv *priv, struct mmc_data *data)
  155 +{}
  156 +#endif
  157 +
  158 +static inline int jz_mmc_read_data(struct jz_mmc_priv *priv, struct mmc_data *data)
  159 +{
  160 + int sz = data->blocks * data->blocksize;
  161 + void *buf = data->dest;
  162 + u32 stat, val;
  163 +
  164 + do {
  165 + stat = readl(priv->regs + MSC_STAT);
  166 +
  167 + if (stat & MSC_STAT_TIME_OUT_READ)
  168 + return -ETIMEDOUT;
  169 + if (stat & MSC_STAT_CRC_READ_ERROR)
  170 + return -EINVAL;
  171 + if (stat & MSC_STAT_DATA_FIFO_EMPTY) {
  172 + udelay(10);
  173 + continue;
  174 + }
  175 + do {
  176 + val = readl(priv->regs + MSC_RXFIFO);
  177 + if (sz == 1)
  178 + *(u8 *)buf = (u8)val;
  179 + else if (sz == 2)
  180 + put_unaligned_le16(val, buf);
  181 + else if (sz >= 4)
  182 + put_unaligned_le32(val, buf);
  183 + buf += 4;
  184 + sz -= 4;
  185 + stat = readl(priv->regs + MSC_STAT);
  186 + } while (!(stat & MSC_STAT_DATA_FIFO_EMPTY));
  187 + } while (!(stat & MSC_STAT_DATA_TRAN_DONE));
  188 + return 0;
  189 +}
  190 +
137 191 static int jz_mmc_send_cmd(struct mmc *mmc, struct jz_mmc_priv *priv,
138 192 struct mmc_cmd *cmd, struct mmc_data *data)
139 193 {
140 194  
... ... @@ -249,51 +303,14 @@
249 303 cmd->response[0] |= readw(priv->regs + MSC_RES) & 0xff;
250 304 }
251 305 }
252   -
253   - if (data && (data->flags & MMC_DATA_WRITE)) {
254   - /* write the data */
255   - int sz = DIV_ROUND_UP(data->blocks * data->blocksize, 4);
256   - const void *buf = data->src;
257   -
258   - while (sz--) {
259   - u32 val = get_unaligned_le32(buf);
260   -
261   - wait_for_bit_le32(priv->regs + MSC_IREG,
262   - MSC_IREG_TXFIFO_WR_REQ,
263   - true, 10000, false);
264   - writel(val, priv->regs + MSC_TXFIFO);
265   - buf += 4;
  306 + if (data) {
  307 + if (data->flags & MMC_DATA_WRITE)
  308 + jz_mmc_write_data(priv, data);
  309 + else if (data->flags & MMC_DATA_READ) {
  310 + ret = jz_mmc_read_data(priv, data);
  311 + if (ret)
  312 + return ret;
266 313 }
267   - } else if (data && (data->flags & MMC_DATA_READ)) {
268   - /* read the data */
269   - int sz = data->blocks * data->blocksize;
270   - void *buf = data->dest;
271   -
272   - do {
273   - stat = readl(priv->regs + MSC_STAT);
274   -
275   - if (stat & MSC_STAT_TIME_OUT_READ)
276   - return -ETIMEDOUT;
277   - if (stat & MSC_STAT_CRC_READ_ERROR)
278   - return -EINVAL;
279   - if (stat & MSC_STAT_DATA_FIFO_EMPTY) {
280   - udelay(10);
281   - continue;
282   - }
283   - do {
284   - u32 val = readl(priv->regs + MSC_RXFIFO);
285   -
286   - if (sz == 1)
287   - *(u8 *)buf = (u8)val;
288   - else if (sz == 2)
289   - put_unaligned_le16(val, buf);
290   - else if (sz >= 4)
291   - put_unaligned_le32(val, buf);
292   - buf += 4;
293   - sz -= 4;
294   - stat = readl(priv->regs + MSC_STAT);
295   - } while (!(stat & MSC_STAT_DATA_FIFO_EMPTY));
296   - } while (!(stat & MSC_STAT_DATA_TRAN_DONE));
297 314 }
298 315  
299 316 return 0;
drivers/mmc/mmc_write.c
Diff comments   View file @ f83ef0d
... ... @@ -65,13 +65,13 @@
65 65 return err;
66 66 }
67 67  
68   -#ifdef CONFIG_BLK
  68 +#if CONFIG_IS_ENABLED(BLK)
69 69 ulong mmc_berase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt)
70 70 #else
71 71 ulong mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt)
72 72 #endif
73 73 {
74   -#ifdef CONFIG_BLK
  74 +#if CONFIG_IS_ENABLED(BLK)
75 75 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
76 76 #endif
77 77 int dev_num = block_dev->devnum;
... ... @@ -183,7 +183,7 @@
183 183 return blkcnt;
184 184 }
185 185  
186   -#ifdef CONFIG_BLK
  186 +#if CONFIG_IS_ENABLED(BLK)
187 187 ulong mmc_bwrite(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
188 188 const void *src)
189 189 #else
... ... @@ -191,7 +191,7 @@
191 191 const void *src)
192 192 #endif
193 193 {
194   -#ifdef CONFIG_BLK
  194 +#if CONFIG_IS_ENABLED(BLK)
195 195 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
196 196 #endif
197 197 int dev_num = block_dev->devnum;
drivers/net/bcm6368-eth.c
Diff comments   View file @ f83ef0d
... ... @@ -309,6 +309,43 @@
309 309 struct bcm6368_eth_priv *priv = dev_get_priv(dev);
310 310 uint8_t i;
311 311  
  312 + /* disable all ports */
  313 + for (i = 0; i < priv->num_ports; i++) {
  314 + setbits_8(priv->base + ETH_PORTOV_REG(i),
  315 + ETH_PORTOV_ENABLE_MASK);
  316 + setbits_8(priv->base + ETH_PTCTRL_REG(i),
  317 + ETH_PTCTRL_RXDIS_MASK | ETH_PTCTRL_TXDIS_MASK);
  318 + priv->sw_port_link[i] = 0;
  319 + }
  320 +
  321 + /* enable external ports */
  322 + for (i = ETH_RGMII_PORT0; i < priv->num_ports; i++) {
  323 + u8 rgmii_ctrl = ETH_RGMII_CTRL_GMII_CLK_EN;
  324 +
  325 + if (!priv->used_ports[i].used)
  326 + continue;
  327 +
  328 + if (priv->rgmii_override)
  329 + rgmii_ctrl |= ETH_RGMII_CTRL_MII_OVERRIDE_EN;
  330 + if (priv->rgmii_timing)
  331 + rgmii_ctrl |= ETH_RGMII_CTRL_TIMING_SEL_EN;
  332 +
  333 + setbits_8(priv->base + ETH_RGMII_CTRL_REG(i), rgmii_ctrl);
  334 + }
  335 +
  336 + /* reset mib */
  337 + setbits_8(priv->base + ETH_GMCR_REG, ETH_GMCR_RST_MIB_MASK);
  338 + mdelay(1);
  339 + clrbits_8(priv->base + ETH_GMCR_REG, ETH_GMCR_RST_MIB_MASK);
  340 + mdelay(1);
  341 +
  342 + /* force CPU port state */
  343 + setbits_8(priv->base + ETH_IMPOV_REG,
  344 + ETH_IMPOV_FORCE_MASK | ETH_IMPOV_LINKUP_MASK);
  345 +
  346 + /* enable switch forward engine */
  347 + setbits_8(priv->base + ETH_SWMODE_REG, ETH_SWMODE_FWD_EN_MASK);
  348 +
312 349 /* prepare rx dma buffers */
313 350 for (i = 0; i < ETH_RX_DESC; i++) {
314 351 int ret = dma_prepare_rcv_buf(&priv->rx_dma, net_rx_packets[i],
315 352  
... ... @@ -368,7 +405,32 @@
368 405 static void bcm6368_eth_stop(struct udevice *dev)
369 406 {
370 407 struct bcm6368_eth_priv *priv = dev_get_priv(dev);
  408 + uint8_t i;
371 409  
  410 + /* disable all ports */
  411 + for (i = 0; i < priv->num_ports; i++) {
  412 + setbits_8(priv->base + ETH_PORTOV_REG(i),
  413 + ETH_PORTOV_ENABLE_MASK);
  414 + setbits_8(priv->base + ETH_PTCTRL_REG(i),
  415 + ETH_PTCTRL_RXDIS_MASK | ETH_PTCTRL_TXDIS_MASK);
  416 + }
  417 +
  418 + /* disable external ports */
  419 + for (i = ETH_RGMII_PORT0; i < priv->num_ports; i++) {
  420 + if (!priv->used_ports[i].used)
  421 + continue;
  422 +
  423 + clrbits_8(priv->base + ETH_RGMII_CTRL_REG(i),
  424 + ETH_RGMII_CTRL_GMII_CLK_EN);
  425 + }
  426 +
  427 + /* disable CPU port */
  428 + clrbits_8(priv->base + ETH_IMPOV_REG,
  429 + ETH_IMPOV_FORCE_MASK | ETH_IMPOV_LINKUP_MASK);
  430 +
  431 + /* disable switch forward engine */
  432 + clrbits_8(priv->base + ETH_SWMODE_REG, ETH_SWMODE_FWD_EN_MASK);
  433 +
372 434 /* disable dma rx channel */
373 435 dma_disable(&priv->rx_dma);
374 436  
... ... @@ -444,7 +506,6 @@
444 506 struct eth_pdata *pdata = dev_get_platdata(dev);
445 507 struct bcm6368_eth_priv *priv = dev_get_priv(dev);
446 508 int num_ports, ret, i;
447   - uint32_t val;
448 509 ofnode node;
449 510  
450 511 /* get base address */
... ... @@ -560,52 +621,6 @@
560 621 ret = bcm6368_mdio_init(dev->name, priv);
561 622 if (ret)
562 623 return ret;
563   -
564   - /* disable all ports */
565   - for (i = 0; i < priv->num_ports; i++) {
566   - writeb_be(ETH_PORTOV_ENABLE_MASK,
567   - priv->base + ETH_PORTOV_REG(i));
568   - writeb_be(ETH_PTCTRL_RXDIS_MASK |
569   - ETH_PTCTRL_TXDIS_MASK,
570   - priv->base + ETH_PTCTRL_REG(i));
571   -
572   - priv->sw_port_link[i] = 0;
573   - }
574   -
575   - /* enable external ports */
576   - for (i = ETH_RGMII_PORT0; i < priv->num_ports; i++) {
577   - u8 rgmii_ctrl;
578   -
579   - if (!priv->used_ports[i].used)
580   - continue;
581   -
582   - rgmii_ctrl = readb_be(priv->base + ETH_RGMII_CTRL_REG(i));
583   - rgmii_ctrl |= ETH_RGMII_CTRL_GMII_CLK_EN;
584   - if (priv->rgmii_override)
585   - rgmii_ctrl |= ETH_RGMII_CTRL_MII_OVERRIDE_EN;
586   - if (priv->rgmii_timing)
587   - rgmii_ctrl |= ETH_RGMII_CTRL_TIMING_SEL_EN;
588   - writeb_be(rgmii_ctrl, priv->base + ETH_RGMII_CTRL_REG(i));
589   - }
590   -
591   - /* reset mib */
592   - val = readb_be(priv->base + ETH_GMCR_REG);
593   - val |= ETH_GMCR_RST_MIB_MASK;
594   - writeb_be(val, priv->base + ETH_GMCR_REG);
595   - mdelay(1);
596   - val &= ~ETH_GMCR_RST_MIB_MASK;
597   - writeb_be(val, priv->base + ETH_GMCR_REG);
598   - mdelay(1);
599   -
600   - /* force CPU port state */
601   - val = readb_be(priv->base + ETH_IMPOV_REG);
602   - val |= ETH_IMPOV_FORCE_MASK | ETH_IMPOV_LINKUP_MASK;
603   - writeb_be(val, priv->base + ETH_IMPOV_REG);
604   -
605   - /* enable switch forward engine */
606   - val = readb_be(priv->base + ETH_SWMODE_REG);
607   - val |= ETH_SWMODE_FWD_EN_MASK;
608   - writeb_be(val, priv->base + ETH_SWMODE_REG);
609 624  
610 625 /* enable jumbo on all ports */
611 626 writel_be(0x1ff, priv->base + ETH_JMBCTL_PORT_REG);
drivers/pinctrl/mscc/Kconfig
Diff comments   View file @ f83ef0d
... ... @@ -20,4 +20,13 @@
20 20 help
21 21 Support pin multiplexing and pin configuration control on
22 22 Microsemi luton SoCs.
  23 +
  24 +config PINCTRL_MSCC_JR2
  25 + depends on SOC_JR2 && PINCTRL_FULL && OF_CONTROL
  26 + select PINCTRL_MSCC
  27 + default y
  28 + bool "Microsemi jr2 family pin control driver"
  29 + help
  30 + Support pin multiplexing and pin configuration control on
  31 + Microsemi jr2 SoCs.
drivers/pinctrl/mscc/Makefile
Diff comments   View file @ f83ef0d
... ... @@ -3,4 +3,5 @@
3 3 obj-y += mscc-common.o
4 4 obj-$(CONFIG_PINCTRL_MSCC_OCELOT) += pinctrl-ocelot.o
5 5 obj-$(CONFIG_PINCTRL_MSCC_LUTON) += pinctrl-luton.o
  6 +obj-$(CONFIG_PINCTRL_MSCC_JR2) += pinctrl-jr2.o
drivers/pinctrl/mscc/mscc-common.c
Diff comments   View file @ f83ef0d
... ... @@ -22,17 +22,38 @@
22 22 #include <linux/io.h>
23 23 #include "mscc-common.h"
24 24  
25   -#define MSCC_GPIO_OUT_SET 0x0
26   -#define MSCC_GPIO_OUT_CLR 0x4
27   -#define MSCC_GPIO_OUT 0x8
28   -#define MSCC_GPIO_IN 0xc
29   -#define MSCC_GPIO_OE 0x10
30   -#define MSCC_GPIO_INTR 0x14
31   -#define MSCC_GPIO_INTR_ENA 0x18
32   -#define MSCC_GPIO_INTR_IDENT 0x1c
33   -#define MSCC_GPIO_ALT0 0x20
34   -#define MSCC_GPIO_ALT1 0x24
  25 +static void mscc_writel(unsigned int offset, void *addr)
  26 +{
  27 + if (offset < 32)
  28 + writel(BIT(offset), addr);
  29 + else
  30 + writel(BIT(offset % 32), addr + 4);
  31 +}
35 32  
  33 +static unsigned int mscc_readl(unsigned int offset, void *addr)
  34 +{
  35 + if (offset < 32)
  36 + return readl(addr);
  37 + else
  38 + return readl(addr + 4);
  39 +}
  40 +
  41 +static void mscc_setbits(unsigned int offset, void *addr)
  42 +{
  43 + if (offset < 32)
  44 + writel(readl(addr) | BIT(offset), addr);
  45 + else
  46 + writel(readl(addr + 4) | BIT(offset % 32), addr + 4);
  47 +}
  48 +
  49 +static void mscc_clrbits(unsigned int offset, void *addr)
  50 +{
  51 + if (offset < 32)
  52 + writel(readl(addr) & ~BIT(offset), addr);
  53 + else
  54 + writel(readl(addr + 4) & ~BIT(offset % 32), addr + 4);
  55 +}
  56 +
36 57 static int mscc_get_functions_count(struct udevice *dev)
37 58 {
38 59 struct mscc_pinctrl *info = dev_get_priv(dev);
... ... @@ -67,7 +88,7 @@
67 88 {
68 89 struct mscc_pinctrl *info = dev_get_priv(dev);
69 90 struct mscc_pin_caps *pin = info->mscc_pins[pin_selector].drv_data;
70   - int f;
  91 + int f, offset, regoff;
71 92  
72 93 f = mscc_pin_function_idx(pin_selector, selector, info->mscc_pins);
73 94 if (f < 0)
74 95  
75 96  
76 97  
77 98  
... ... @@ -79,15 +100,22 @@
79 100 * This is racy because both registers can't be updated at the same time
80 101 * but it doesn't matter much for now.
81 102 */
  103 + offset = pin->pin;
  104 + regoff = info->mscc_gpios[MSCC_GPIO_ALT0];
  105 + if (offset >= 32) {
  106 + offset = offset % 32;
  107 + regoff = info->mscc_gpios[MSCC_GPIO_ALT1];
  108 + }
  109 +
82 110 if (f & BIT(0))
83   - setbits_le32(info->regs + MSCC_GPIO_ALT0, BIT(pin->pin));
  111 + mscc_setbits(offset, info->regs + regoff);
84 112 else
85   - clrbits_le32(info->regs + MSCC_GPIO_ALT0, BIT(pin->pin));
  113 + mscc_clrbits(offset, info->regs + regoff);
86 114  
87 115 if (f & BIT(1))
88   - setbits_le32(info->regs + MSCC_GPIO_ALT1, BIT(pin->pin - 1));
  116 + mscc_setbits(offset, info->regs + regoff + 4);
89 117 else
90   - clrbits_le32(info->regs + MSCC_GPIO_ALT1, BIT(pin->pin - 1));
  118 + mscc_clrbits(offset, info->regs + regoff + 4);
91 119  
92 120 return 0;
93 121 }
... ... @@ -120,8 +148,8 @@
120 148 }
121 149  
122 150 info->func[f].ngroups = npins;
123   - info->func[f].groups = devm_kzalloc(dev, npins *
124   - sizeof(char *), GFP_KERNEL);
  151 + info->func[f].groups = devm_kzalloc(dev, npins * sizeof(char *),
  152 + GFP_KERNEL);
125 153 if (!info->func[f].groups)
126 154 return -ENOMEM;
127 155  
128 156  
... ... @@ -150,9 +178,15 @@
150 178 struct mscc_pinctrl *info = dev_get_priv(dev->parent);
151 179 unsigned int val;
152 180  
153   - val = readl(info->regs + MSCC_GPIO_IN);
  181 + if (mscc_readl(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]) &
  182 + BIT(offset % 32))
  183 + val = mscc_readl(offset,
  184 + info->regs + info->mscc_gpios[MSCC_GPIO_OUT]);
  185 + else
  186 + val = mscc_readl(offset,
  187 + info->regs + info->mscc_gpios[MSCC_GPIO_IN]);
154 188  
155   - return !!(val & BIT(offset));
  189 + return !!(val & BIT(offset % 32));
156 190 }
157 191  
158 192 static int mscc_gpio_set(struct udevice *dev, unsigned int offset, int value)
159 193  
... ... @@ -160,9 +194,11 @@
160 194 struct mscc_pinctrl *info = dev_get_priv(dev->parent);
161 195  
162 196 if (value)
163   - writel(BIT(offset), info->regs + MSCC_GPIO_OUT_SET);
  197 + mscc_writel(offset,
  198 + info->regs + info->mscc_gpios[MSCC_GPIO_OUT_SET]);
164 199 else
165   - writel(BIT(offset), info->regs + MSCC_GPIO_OUT_CLR);
  200 + mscc_writel(offset,
  201 + info->regs + info->mscc_gpios[MSCC_GPIO_OUT_CLR]);
166 202  
167 203 return 0;
168 204 }
169 205  
170 206  
... ... @@ -172,16 +208,16 @@
172 208 struct mscc_pinctrl *info = dev_get_priv(dev->parent);
173 209 unsigned int val;
174 210  
175   - val = readl(info->regs + MSCC_GPIO_OE);
  211 + val = mscc_readl(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]);
176 212  
177   - return (val & BIT(offset)) ? GPIOF_OUTPUT : GPIOF_INPUT;
  213 + return (val & BIT(offset % 32)) ? GPIOF_OUTPUT : GPIOF_INPUT;
178 214 }
179 215  
180 216 static int mscc_gpio_direction_input(struct udevice *dev, unsigned int offset)
181 217 {
182 218 struct mscc_pinctrl *info = dev_get_priv(dev->parent);
183 219  
184   - clrbits_le32(info->regs + MSCC_GPIO_OE, BIT(offset));
  220 + mscc_clrbits(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]);
185 221  
186 222 return 0;
187 223 }
... ... @@ -191,7 +227,7 @@
191 227 {
192 228 struct mscc_pinctrl *info = dev_get_priv(dev->parent);
193 229  
194   - setbits_le32(info->regs + MSCC_GPIO_OE, BIT(offset));
  230 + mscc_setbits(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]);
195 231  
196 232 return mscc_gpio_set(dev, offset, value);
197 233 }
... ... @@ -215,7 +251,8 @@
215 251  
216 252 int mscc_pinctrl_probe(struct udevice *dev, int num_func,
217 253 const struct mscc_pin_data *mscc_pins, int num_pins,
218   - char *const *function_names)
  254 + char * const *function_names,
  255 + const unsigned long *mscc_gpios)
219 256 {
220 257 struct mscc_pinctrl *priv = dev_get_priv(dev);
221 258 int ret;
... ... @@ -230,6 +267,7 @@
230 267 priv->mscc_pins = mscc_pins;
231 268 priv->num_pins = num_pins;
232 269 priv->function_names = function_names;
  270 + priv->mscc_gpios = mscc_gpios;
233 271 ret = mscc_pinctrl_register(dev, priv);
234 272  
235 273 return ret;
drivers/pinctrl/mscc/mscc-common.h
Diff comments   View file @ f83ef0d
... ... @@ -9,6 +9,19 @@
9 9  
10 10 #define MSCC_FUNC_PER_PIN 4
11 11  
  12 +enum mscc_regs_gpio {
  13 + MSCC_GPIO_OUT_SET,
  14 + MSCC_GPIO_OUT_CLR,
  15 + MSCC_GPIO_OUT,
  16 + MSCC_GPIO_IN,
  17 + MSCC_GPIO_OE,
  18 + MSCC_GPIO_INTR,
  19 + MSCC_GPIO_INTR_ENA,
  20 + MSCC_GPIO_INTR_IDENT,
  21 + MSCC_GPIO_ALT0,
  22 + MSCC_GPIO_ALT1,
  23 +};
  24 +
12 25 struct mscc_pin_caps {
13 26 unsigned int pin;
14 27 unsigned char functions[MSCC_FUNC_PER_PIN];
15 28  
... ... @@ -41,11 +54,13 @@
41 54 const struct mscc_pin_data *mscc_pins;
42 55 int num_pins;
43 56 char * const *function_names;
  57 + const unsigned long *mscc_gpios;
44 58 };
45 59  
46 60 int mscc_pinctrl_probe(struct udevice *dev, int num_func,
47 61 const struct mscc_pin_data *mscc_pins, int num_pins,
48   - char * const *function_names);
  62 + char * const *function_names,
  63 + const unsigned long *mscc_gpios);
49 64 const struct pinctrl_ops mscc_pinctrl_ops;
50 65  
51 66 const struct dm_gpio_ops mscc_gpio_ops;
drivers/pinctrl/mscc/pinctrl-jr2.c
Diff comments   View file @ f83ef0d
  1 +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2 +/*
  3 + * Microsemi SoCs pinctrl driver
  4 + *
  5 + * Author: <horatiu.vultur@microchip.com>
  6 + * Copyright (c) 2018 Microsemi Corporation
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <config.h>
  11 +#include <dm.h>
  12 +#include <dm/device-internal.h>
  13 +#include <dm/lists.h>
  14 +#include <dm/pinctrl.h>
  15 +#include <dm/root.h>
  16 +#include <errno.h>
  17 +#include <fdtdec.h>
  18 +#include <linux/io.h>
  19 +#include <asm/gpio.h>
  20 +#include <asm/system.h>
  21 +#include "mscc-common.h"
  22 +
  23 +enum {
  24 + FUNC_NONE,
  25 + FUNC_GPIO,
  26 + FUNC_IRQ0_IN,
  27 + FUNC_IRQ0_OUT,
  28 + FUNC_IRQ1_IN,
  29 + FUNC_IRQ1_OUT,
  30 + FUNC_MIIM1,
  31 + FUNC_MIIM2,
  32 + FUNC_PCI_WAKE,
  33 + FUNC_PTP0,
  34 + FUNC_PTP1,
  35 + FUNC_PTP2,
  36 + FUNC_PTP3,
  37 + FUNC_PWM,
  38 + FUNC_RECO_CLK0,
  39 + FUNC_RECO_CLK1,
  40 + FUNC_SFP0,
  41 + FUNC_SFP1,
  42 + FUNC_SFP2,
  43 + FUNC_SFP3,
  44 + FUNC_SFP4,
  45 + FUNC_SFP5,
  46 + FUNC_SFP6,
  47 + FUNC_SFP7,
  48 + FUNC_SFP8,
  49 + FUNC_SFP9,
  50 + FUNC_SFP10,
  51 + FUNC_SFP11,
  52 + FUNC_SFP12,
  53 + FUNC_SFP13,
  54 + FUNC_SFP14,
  55 + FUNC_SFP15,
  56 + FUNC_SG0,
  57 + FUNC_SG1,
  58 + FUNC_SG2,
  59 + FUNC_SI,
  60 + FUNC_TACHO,
  61 + FUNC_TWI,
  62 + FUNC_TWI2,
  63 + FUNC_TWI_SCL_M,
  64 + FUNC_UART,
  65 + FUNC_UART2,
  66 + FUNC_MAX
  67 +};
  68 +
  69 +static char * const jr2_function_names[] = {
  70 + [FUNC_NONE] = "none",
  71 + [FUNC_GPIO] = "gpio",
  72 + [FUNC_IRQ0_IN] = "irq0_in",
  73 + [FUNC_IRQ0_OUT] = "irq0_out",
  74 + [FUNC_IRQ1_IN] = "irq1_in",
  75 + [FUNC_IRQ1_OUT] = "irq1_out",
  76 + [FUNC_MIIM1] = "miim1",
  77 + [FUNC_MIIM2] = "miim2",
  78 + [FUNC_PCI_WAKE] = "pci_wake",
  79 + [FUNC_PTP0] = "ptp0",
  80 + [FUNC_PTP1] = "ptp1",
  81 + [FUNC_PTP2] = "ptp2",
  82 + [FUNC_PTP3] = "ptp3",
  83 + [FUNC_PWM] = "pwm",
  84 + [FUNC_RECO_CLK0] = "reco_clk0",
  85 + [FUNC_RECO_CLK1] = "reco_clk1",
  86 + [FUNC_SFP0] = "sfp0",
  87 + [FUNC_SFP1] = "sfp1",
  88 + [FUNC_SFP2] = "sfp2",
  89 + [FUNC_SFP3] = "sfp3",
  90 + [FUNC_SFP4] = "sfp4",
  91 + [FUNC_SFP5] = "sfp5",
  92 + [FUNC_SFP6] = "sfp6",
  93 + [FUNC_SFP7] = "sfp7",
  94 + [FUNC_SFP8] = "sfp8",
  95 + [FUNC_SFP9] = "sfp9",
  96 + [FUNC_SFP10] = "sfp10",
  97 + [FUNC_SFP11] = "sfp11",
  98 + [FUNC_SFP12] = "sfp12",
  99 + [FUNC_SFP13] = "sfp13",
  100 + [FUNC_SFP14] = "sfp14",
  101 + [FUNC_SFP15] = "sfp15",
  102 + [FUNC_SG0] = "sg0",
  103 + [FUNC_SG1] = "sg1",
  104 + [FUNC_SG2] = "sg2",
  105 + [FUNC_SI] = "si",
  106 + [FUNC_TACHO] = "tacho",
  107 + [FUNC_TWI] = "twi",
  108 + [FUNC_TWI2] = "twi2",
  109 + [FUNC_TWI_SCL_M] = "twi_scl_m",
  110 + [FUNC_UART] = "uart",
  111 + [FUNC_UART2] = "uart2",
  112 +};
  113 +
  114 +#define JR2_P(p, f0, f1) \
  115 +static struct mscc_pin_caps jr2_pin_##p = { \
  116 + .pin = p, \
  117 + .functions = { \
  118 + FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \
  119 + }, \
  120 +}
  121 +
  122 +JR2_P(0, SG0, NONE);
  123 +JR2_P(1, SG0, NONE);
  124 +JR2_P(2, SG0, NONE);
  125 +JR2_P(3, SG0, NONE);
  126 +JR2_P(4, SG1, NONE);
  127 +JR2_P(5, SG1, NONE);
  128 +JR2_P(6, IRQ0_IN, IRQ0_OUT);
  129 +JR2_P(7, IRQ1_IN, IRQ1_OUT);
  130 +JR2_P(8, PTP0, NONE);
  131 +JR2_P(9, PTP1, NONE);
  132 +JR2_P(10, UART, NONE);
  133 +JR2_P(11, UART, NONE);
  134 +JR2_P(12, SG1, NONE);
  135 +JR2_P(13, SG1, NONE);
  136 +JR2_P(14, TWI, TWI_SCL_M);
  137 +JR2_P(15, TWI, NONE);
  138 +JR2_P(16, SI, TWI_SCL_M);
  139 +JR2_P(17, SI, TWI_SCL_M);
  140 +JR2_P(18, SI, TWI_SCL_M);
  141 +JR2_P(19, PCI_WAKE, NONE);
  142 +JR2_P(20, IRQ0_OUT, TWI_SCL_M);
  143 +JR2_P(21, IRQ1_OUT, TWI_SCL_M);
  144 +JR2_P(22, TACHO, NONE);
  145 +JR2_P(23, PWM, NONE);
  146 +JR2_P(24, UART2, NONE);
  147 +JR2_P(25, UART2, SI);
  148 +JR2_P(26, PTP2, SI);
  149 +JR2_P(27, PTP3, SI);
  150 +JR2_P(28, TWI2, SI);
  151 +JR2_P(29, TWI, SI);
  152 +JR2_P(30, SG2, SI);
  153 +JR2_P(31, SG2, SI);
  154 +JR2_P(32, SG2, SI);
  155 +JR2_P(33, SG2, SI);
  156 +JR2_P(34, NONE, TWI_SCL_M);
  157 +JR2_P(35, NONE, TWI_SCL_M);
  158 +JR2_P(36, NONE, TWI_SCL_M);
  159 +JR2_P(37, NONE, TWI_SCL_M);
  160 +JR2_P(38, NONE, TWI_SCL_M);
  161 +JR2_P(39, NONE, TWI_SCL_M);
  162 +JR2_P(40, NONE, TWI_SCL_M);
  163 +JR2_P(41, NONE, TWI_SCL_M);
  164 +JR2_P(42, NONE, TWI_SCL_M);
  165 +JR2_P(43, NONE, TWI_SCL_M);
  166 +JR2_P(44, NONE, SFP8);
  167 +JR2_P(45, NONE, SFP9);
  168 +JR2_P(46, NONE, SFP10);
  169 +JR2_P(47, NONE, SFP11);
  170 +JR2_P(48, SFP0, NONE);
  171 +JR2_P(49, SFP1, SI);
  172 +JR2_P(50, SFP2, SI);
  173 +JR2_P(51, SFP3, SI);
  174 +JR2_P(52, SFP4, NONE);
  175 +JR2_P(53, SFP5, NONE);
  176 +JR2_P(54, SFP6, NONE);
  177 +JR2_P(55, SFP7, NONE);
  178 +JR2_P(56, MIIM1, SFP12);
  179 +JR2_P(57, MIIM1, SFP13);
  180 +JR2_P(58, MIIM2, SFP14);
  181 +JR2_P(59, MIIM2, SFP15);
  182 +JR2_P(60, NONE, NONE);
  183 +JR2_P(61, NONE, NONE);
  184 +JR2_P(62, NONE, NONE);
  185 +JR2_P(63, NONE, NONE);
  186 +
  187 +#define JR2_PIN(n) { \
  188 + .name = "GPIO_"#n, \
  189 + .drv_data = &jr2_pin_##n \
  190 +}
  191 +
  192 +static const struct mscc_pin_data jr2_pins[] = {
  193 + JR2_PIN(0),
  194 + JR2_PIN(1),
  195 + JR2_PIN(2),
  196 + JR2_PIN(3),
  197 + JR2_PIN(4),
  198 + JR2_PIN(5),
  199 + JR2_PIN(6),
  200 + JR2_PIN(7),
  201 + JR2_PIN(8),
  202 + JR2_PIN(9),
  203 + JR2_PIN(10),
  204 + JR2_PIN(11),
  205 + JR2_PIN(12),
  206 + JR2_PIN(13),
  207 + JR2_PIN(14),
  208 + JR2_PIN(15),
  209 + JR2_PIN(16),
  210 + JR2_PIN(17),
  211 + JR2_PIN(18),
  212 + JR2_PIN(19),
  213 + JR2_PIN(20),
  214 + JR2_PIN(21),
  215 + JR2_PIN(22),
  216 + JR2_PIN(23),
  217 + JR2_PIN(24),
  218 + JR2_PIN(25),
  219 + JR2_PIN(26),
  220 + JR2_PIN(27),
  221 + JR2_PIN(28),
  222 + JR2_PIN(29),
  223 + JR2_PIN(30),
  224 + JR2_PIN(31),
  225 + JR2_PIN(32),
  226 + JR2_PIN(33),
  227 + JR2_PIN(34),
  228 + JR2_PIN(35),
  229 + JR2_PIN(36),
  230 + JR2_PIN(37),
  231 + JR2_PIN(38),
  232 + JR2_PIN(39),
  233 + JR2_PIN(40),
  234 + JR2_PIN(41),
  235 + JR2_PIN(42),
  236 + JR2_PIN(43),
  237 + JR2_PIN(44),
  238 + JR2_PIN(45),
  239 + JR2_PIN(46),
  240 + JR2_PIN(47),
  241 + JR2_PIN(48),
  242 + JR2_PIN(49),
  243 + JR2_PIN(50),
  244 + JR2_PIN(51),
  245 + JR2_PIN(52),
  246 + JR2_PIN(53),
  247 + JR2_PIN(54),
  248 + JR2_PIN(55),
  249 + JR2_PIN(56),
  250 + JR2_PIN(57),
  251 + JR2_PIN(58),
  252 + JR2_PIN(59),
  253 + JR2_PIN(60),
  254 + JR2_PIN(61),
  255 + JR2_PIN(62),
  256 + JR2_PIN(63),
  257 +};
  258 +
  259 +static const unsigned long jr2_gpios[] = {
  260 + [MSCC_GPIO_OUT_SET] = 0x00,
  261 + [MSCC_GPIO_OUT_CLR] = 0x08,
  262 + [MSCC_GPIO_OUT] = 0x10,
  263 + [MSCC_GPIO_IN] = 0x18,
  264 + [MSCC_GPIO_OE] = 0x20,
  265 + [MSCC_GPIO_INTR] = 0x28,
  266 + [MSCC_GPIO_INTR_ENA] = 0x30,
  267 + [MSCC_GPIO_INTR_IDENT] = 0x38,
  268 + [MSCC_GPIO_ALT0] = 0x40,
  269 + [MSCC_GPIO_ALT1] = 0x48,
  270 +};
  271 +
  272 +static int jr2_gpio_probe(struct udevice *dev)
  273 +{
  274 + struct gpio_dev_priv *uc_priv;
  275 +
  276 + uc_priv = dev_get_uclass_priv(dev);
  277 + uc_priv->bank_name = "jr2-gpio";
  278 + uc_priv->gpio_count = ARRAY_SIZE(jr2_pins);
  279 +
  280 + return 0;
  281 +}
  282 +
  283 +static struct driver jr2_gpio_driver = {
  284 + .name = "jr2-gpio",
  285 + .id = UCLASS_GPIO,
  286 + .probe = jr2_gpio_probe,
  287 + .ops = &mscc_gpio_ops,
  288 +};
  289 +
  290 +static int jr2_pinctrl_probe(struct udevice *dev)
  291 +{
  292 + int ret;
  293 +
  294 + ret = mscc_pinctrl_probe(dev, FUNC_MAX, jr2_pins,
  295 + ARRAY_SIZE(jr2_pins),
  296 + jr2_function_names,
  297 + jr2_gpios);
  298 +
  299 + if (ret)
  300 + return ret;
  301 +
  302 + ret = device_bind(dev, &jr2_gpio_driver, "jr2-gpio", NULL,
  303 + dev_of_offset(dev), NULL);
  304 +
  305 + if (ret)
  306 + return ret;
  307 +
  308 + return 0;
  309 +}
  310 +
  311 +static const struct udevice_id jr2_pinctrl_of_match[] = {
  312 + { .compatible = "mscc,jaguar2-pinctrl" },
  313 + {},
  314 +};
  315 +
  316 +U_BOOT_DRIVER(jr2_pinctrl) = {
  317 + .name = "jr2-pinctrl",
  318 + .id = UCLASS_PINCTRL,
  319 + .of_match = of_match_ptr(jr2_pinctrl_of_match),
  320 + .probe = jr2_pinctrl_probe,
  321 + .priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
  322 + .ops = &mscc_pinctrl_ops,
  323 +};
drivers/pinctrl/mscc/pinctrl-luton.c
Diff comments   View file @ f83ef0d
... ... @@ -123,6 +123,19 @@
123 123 LUTON_PIN(31),
124 124 };
125 125  
  126 +static const unsigned long luton_gpios[] = {
  127 + [MSCC_GPIO_OUT_SET] = 0x00,
  128 + [MSCC_GPIO_OUT_CLR] = 0x04,
  129 + [MSCC_GPIO_OUT] = 0x08,
  130 + [MSCC_GPIO_IN] = 0x0c,
  131 + [MSCC_GPIO_OE] = 0x10,
  132 + [MSCC_GPIO_INTR] = 0x14,
  133 + [MSCC_GPIO_INTR_ENA] = 0x18,
  134 + [MSCC_GPIO_INTR_IDENT] = 0x1c,
  135 + [MSCC_GPIO_ALT0] = 0x20,
  136 + [MSCC_GPIO_ALT1] = 0x24,
  137 +};
  138 +
126 139 static int luton_gpio_probe(struct udevice *dev)
127 140 {
128 141 struct gpio_dev_priv *uc_priv;
... ... @@ -146,7 +159,8 @@
146 159 int ret;
147 160  
148 161 ret = mscc_pinctrl_probe(dev, FUNC_MAX, luton_pins,
149   - ARRAY_SIZE(luton_pins), luton_function_names);
  162 + ARRAY_SIZE(luton_pins), luton_function_names,
  163 + luton_gpios);
150 164  
151 165 if (ret)
152 166 return ret;
drivers/pinctrl/mscc/pinctrl-ocelot.c
Diff comments   View file @ f83ef0d
... ... @@ -138,6 +138,19 @@
138 138 OCELOT_PIN(21),
139 139 };
140 140  
  141 +static const unsigned long ocelot_gpios[] = {
  142 + [MSCC_GPIO_OUT_SET] = 0x00,
  143 + [MSCC_GPIO_OUT_CLR] = 0x04,
  144 + [MSCC_GPIO_OUT] = 0x08,
  145 + [MSCC_GPIO_IN] = 0x0c,
  146 + [MSCC_GPIO_OE] = 0x10,
  147 + [MSCC_GPIO_INTR] = 0x14,
  148 + [MSCC_GPIO_INTR_ENA] = 0x18,
  149 + [MSCC_GPIO_INTR_IDENT] = 0x1c,
  150 + [MSCC_GPIO_ALT0] = 0x20,
  151 + [MSCC_GPIO_ALT1] = 0x24,
  152 +};
  153 +
141 154 static int ocelot_gpio_probe(struct udevice *dev)
142 155 {
143 156 struct gpio_dev_priv *uc_priv;
... ... @@ -162,7 +175,8 @@
162 175  
163 176 ret = mscc_pinctrl_probe(dev, FUNC_MAX, ocelot_pins,
164 177 ARRAY_SIZE(ocelot_pins),
165   - ocelot_function_names);
  178 + ocelot_function_names,
  179 + ocelot_gpios);
166 180  
167 181 if (ret)
168 182 return ret;
... ... @@ -294,6 +294,13 @@
294 294 Enable Soft SPI driver. This driver is to use GPIO simulate
295 295 the SPI protocol.
296 296  
  297 +config MSCC_BB_SPI
  298 + bool "MSCC bitbang SPI driver"
  299 + depends on SOC_VCOREIII
  300 + help
  301 + Enable MSCC bitbang SPI driver. This driver can be used on
  302 + MSCC SOCs.
  303 +
297 304 config CF_SPI
298 305 bool "ColdFire SPI driver"
299 306 help
drivers/spi/Makefile
Diff comments   View file @ f83ef0d
... ... @@ -36,6 +36,7 @@
36 36 obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
37 37 obj-$(CONFIG_MTK_QSPI) += mtk_qspi.o
38 38 obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o
  39 +obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o
39 40 obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
40 41 obj-$(CONFIG_MXC_SPI) += mxc_spi.o
41 42 obj-$(CONFIG_MXS_SPI) += mxs_spi.o
drivers/spi/mscc_bb_spi.c
Diff comments   View file @ f83ef0d
  1 +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2 +/*
  3 + * Microsemi SoCs spi driver
  4 + *
  5 + * Copyright (c) 2018 Microsemi Corporation
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <dm.h>
  10 +#include <errno.h>
  11 +#include <malloc.h>
  12 +#include <spi.h>
  13 +#include <dm.h>
  14 +#include <asm/gpio.h>
  15 +#include <asm/io.h>
  16 +#include <linux/delay.h>
  17 +
  18 +struct mscc_bb_priv {
  19 + void __iomem *regs;
  20 + u32 deactivate_delay_us;
  21 + bool cs_active; /* State flag as to whether CS is asserted */
  22 + int cs_num;
  23 + u32 svalue; /* Value to start transfer with */
  24 + u32 clk1; /* Clock value start */
  25 + u32 clk2; /* Clock value 2nd phase */
  26 +};
  27 +
  28 +/* Delay 24 instructions for this particular application */
  29 +#define hold_time_delay() mscc_vcoreiii_nop_delay(3)
  30 +
  31 +static int mscc_bb_spi_cs_activate(struct mscc_bb_priv *priv, int mode, int cs)
  32 +{
  33 + if (!priv->cs_active) {
  34 + int cpha = mode & SPI_CPHA;
  35 + u32 cs_value;
  36 +
  37 + priv->cs_num = cs;
  38 +
  39 + if (cpha) {
  40 + /* Initial clock starts SCK=1 */
  41 + priv->clk1 = ICPU_SW_MODE_SW_SPI_SCK;
  42 + priv->clk2 = 0;
  43 + } else {
  44 + /* Initial clock starts SCK=0 */
  45 + priv->clk1 = 0;
  46 + priv->clk2 = ICPU_SW_MODE_SW_SPI_SCK;
  47 + }
  48 +
  49 + /* Enable bitbang, SCK_OE, SDO_OE */
  50 + priv->svalue = (ICPU_SW_MODE_SW_PIN_CTRL_MODE | /* Bitbang */
  51 + ICPU_SW_MODE_SW_SPI_SCK_OE | /* SCK_OE */
  52 + ICPU_SW_MODE_SW_SPI_SDO_OE); /* SDO OE */
  53 +
  54 + /* Add CS */
  55 + if (cs >= 0) {
  56 + cs_value =
  57 + ICPU_SW_MODE_SW_SPI_CS_OE(BIT(cs)) |
  58 + ICPU_SW_MODE_SW_SPI_CS(BIT(cs));
  59 + } else {
  60 + cs_value = 0;
  61 + }
  62 +
  63 + priv->svalue |= cs_value;
  64 +
  65 + /* Enable the CS in HW, Initial clock value */
  66 + writel(priv->svalue | priv->clk2, priv->regs);
  67 +
  68 + priv->cs_active = true;
  69 + debug("Activated CS%d\n", priv->cs_num);
  70 + }
  71 +
  72 + return 0;
  73 +}
  74 +
  75 +static int mscc_bb_spi_cs_deactivate(struct mscc_bb_priv *priv, int deact_delay)
  76 +{
  77 + if (priv->cs_active) {
  78 + /* Keep driving the CLK to its current value while
  79 + * actively deselecting CS.
  80 + */
  81 + u32 value = readl(priv->regs);
  82 +
  83 + value &= ~ICPU_SW_MODE_SW_SPI_CS_M;
  84 + writel(value, priv->regs);
  85 + hold_time_delay();
  86 +
  87 + /* Stop driving the clock, but keep CS with nCS == 1 */
  88 + value &= ~ICPU_SW_MODE_SW_SPI_SCK_OE;
  89 + writel(value, priv->regs);
  90 +
  91 + /* Deselect hold time delay */
  92 + if (deact_delay)
  93 + udelay(deact_delay);
  94 +
  95 + /* Drop everything */
  96 + writel(0, priv->regs);
  97 +
  98 + priv->cs_active = false;
  99 + debug("Deactivated CS%d\n", priv->cs_num);
  100 + }
  101 +
  102 + return 0;
  103 +}
  104 +
  105 +int mscc_bb_spi_claim_bus(struct udevice *dev)
  106 +{
  107 + return 0;
  108 +}
  109 +
  110 +int mscc_bb_spi_release_bus(struct udevice *dev)
  111 +{
  112 + return 0;
  113 +}
  114 +
  115 +int mscc_bb_spi_xfer(struct udevice *dev, unsigned int bitlen,
  116 + const void *dout, void *din, unsigned long flags)
  117 +{
  118 + struct udevice *bus = dev_get_parent(dev);
  119 + struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
  120 + struct mscc_bb_priv *priv = dev_get_priv(bus);
  121 + u32 i, count;
  122 + const u8 *txd = dout;
  123 + u8 *rxd = din;
  124 +
  125 + debug("spi_xfer: slave %s:%s cs%d mode %d, dout %p din %p bitlen %u\n",
  126 + dev->parent->name, dev->name, plat->cs, plat->mode, dout,
  127 + din, bitlen);
  128 +
  129 + if (flags & SPI_XFER_BEGIN)
  130 + mscc_bb_spi_cs_activate(priv, plat->mode, plat->cs);
  131 +
  132 + count = bitlen / 8;
  133 + for (i = 0; i < count; i++) {
  134 + u32 rx = 0, mask = 0x80, value;
  135 +
  136 + while (mask) {
  137 + /* Initial condition: CLK is low. */
  138 + value = priv->svalue;
  139 + if (txd && txd[i] & mask)
  140 + value |= ICPU_SW_MODE_SW_SPI_SDO;
  141 +
  142 + /* Drive data while taking CLK low. The device
  143 + * we're accessing will sample on the
  144 + * following rising edge and will output data
  145 + * on this edge for us to be sampled at the
  146 + * end of this loop.
  147 + */
  148 + writel(value | priv->clk1, priv->regs);
  149 +
  150 + /* Wait for t_setup. All devices do have a
  151 + * setup-time, so we always insert some delay
  152 + * here. Some devices have a very long
  153 + * setup-time, which can be adjusted by the
  154 + * user through vcoreiii_device->delay.
  155 + */
  156 + hold_time_delay();
  157 +
  158 + /* Drive the clock high. */
  159 + writel(value | priv->clk2, priv->regs);
  160 +
  161 + /* Wait for t_hold. See comment about t_setup
  162 + * above.
  163 + */
  164 + hold_time_delay();
  165 +
  166 + /* We sample as close to the next falling edge
  167 + * as possible.
  168 + */
  169 + value = readl(priv->regs);
  170 + if (value & ICPU_SW_MODE_SW_SPI_SDI)
  171 + rx |= mask;
  172 + mask >>= 1;
  173 + }
  174 + if (rxd) {
  175 + debug("Read 0x%02x\n", rx);
  176 + rxd[i] = (u8)rx;
  177 + }
  178 + debug("spi_xfer: byte %d/%d\n", i + 1, count);
  179 + }
  180 +
  181 + debug("spi_xfer: done\n");
  182 +
  183 + if (flags & SPI_XFER_END)
  184 + mscc_bb_spi_cs_deactivate(priv, priv->deactivate_delay_us);
  185 +
  186 + return 0;
  187 +}
  188 +
  189 +int mscc_bb_spi_set_speed(struct udevice *dev, unsigned int speed)
  190 +{
  191 + /* Accept any speed */
  192 + return 0;
  193 +}
  194 +
  195 +int mscc_bb_spi_set_mode(struct udevice *dev, unsigned int mode)
  196 +{
  197 + return 0;
  198 +}
  199 +
  200 +static const struct dm_spi_ops mscc_bb_ops = {
  201 + .claim_bus = mscc_bb_spi_claim_bus,
  202 + .release_bus = mscc_bb_spi_release_bus,
  203 + .xfer = mscc_bb_spi_xfer,
  204 + .set_speed = mscc_bb_spi_set_speed,
  205 + .set_mode = mscc_bb_spi_set_mode,
  206 +};
  207 +
  208 +static const struct udevice_id mscc_bb_ids[] = {
  209 + { .compatible = "mscc,luton-bb-spi" },
  210 + { }
  211 +};
  212 +
  213 +static int mscc_bb_spi_probe(struct udevice *bus)
  214 +{
  215 + struct mscc_bb_priv *priv = dev_get_priv(bus);
  216 +
  217 + debug("%s: loaded, priv %p\n", __func__, priv);
  218 +
  219 + priv->regs = (void __iomem *)dev_read_addr(bus);
  220 +
  221 + priv->deactivate_delay_us =
  222 + dev_read_u32_default(bus, "spi-deactivate-delay", 0);
  223 +
  224 + priv->cs_active = false;
  225 +
  226 + return 0;
  227 +}
  228 +
  229 +U_BOOT_DRIVER(mscc_bb) = {
  230 + .name = "mscc_bb",
  231 + .id = UCLASS_SPI,
  232 + .of_match = mscc_bb_ids,
  233 + .ops = &mscc_bb_ops,
  234 + .priv_auto_alloc_size = sizeof(struct mscc_bb_priv),
  235 + .probe = mscc_bb_spi_probe,
  236 +};
include/configs/vcoreiii.h
Diff comments   View file @ f83ef0d
... ... @@ -22,6 +22,8 @@
22 22 #endif
23 23 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ
24 24  
  25 +#define CONFIG_BOARD_TYPES
  26 +
25 27 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
26 28 #define CONFIG_ENV_OFFSET (1024 * 1024)
27 29 #define CONFIG_ENV_SIZE (256 * 1024)