Eric Lee / smarc-uboot | Embedian Git Server

Commit f901a83b70a586cef89682843e2d16d6c7b2288a

Authored by Wolfgang Denk 2005-08-06 07:42:58 +0800

Exists in master and in 54 other branches

Add support for ep8248 board

Patch by Yuli Barcohen, 12 Dec 2004

Minor code cleanup.

Showing 13 changed files with 1468 additions and 706 deletions Inline Diff

CHANGELOG
MAINTAINERS
MAKEALL
Makefile
board/amcc/bamboo/bamboo.c
board/amcc/bamboo/bamboo.h
board/ep8248/Makefile
board/ep8248/config.mk
board/ep8248/ep8248.c
board/ep8248/u-boot.lds
cpu/ppc4xx/start.S
doc/README.mpc83xxads
include/configs/ep8248.h

CHANGELOG

Diff comments View file @ f901a83

 ======================================================================
 Changes for U-Boot 1.1.3:
 ======================================================================
+* Add support for ep8248 board
+  Patch by Yuli Barcohen, 12 Dec 2004
+  Minor code cleanup.
 * Fix baudrate setting for KGDB on MPC8260
   Patch by HoJin, 11 Dec 2004
 * Fix 'mii help' text formatting
   Patch by Cory Tusar, 10 Dec 2004
 * Fix return code of NFS command
   Patch by Hiroshi Ito, 11 Dec 2004
 * Fix typo
 * Fix compiler warnings in cpu/ppc4xx/usbdev.c
   Patch by Steven Blakeslee, 04 Aug 2005
 * Add support for AMCC Bamboo PPC440EP eval board
   Patch by Stefan Roese, 04 Aug 2005
 * Patch by Jon Loeliger
   Fix style issues primarily in 85xx and 83xx boards.
     - C++ comments
     - Trailing white space
     - Indentation not by TAB
     - Excessive amount of empty lines
     - Trailing empty lines
 * Patch by Ron Alder, 11 Jul 2005
     Add Xianghua Xiao and Lunsheng Wang's support for the
     GDA MPC8540 EVAL board.
 * Patch by Eran Liberty
   Add support for the Freescale MPC8349ADS board.
 * Patch by Jon Loeliger, 25 Jul 2005
   Move the TSEC driver out of cpu/mpc85xx as it will be shared
   by the upcoming mpc83xx family as well.
 * Patch by Jon Loeliger, 05 May 2005
   Implemented support for MPC8548CDS board.
   Added DDR II support based on SPD values for MPC85xx boards.
   This roll-up patch also includes bugfies for the previously
   published patches:
     DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
 * Patch by Jon Loeliger, 10 Feb 2005
   Add config option CONFIG_HAS_FEC calling out 8540 FEC features.
 * Patch by Jon Loeliger, Kumar Gala, 08 Feb 2005
   For MPC85xxCDS:
     Adds Relaxed Timing TRLX bit to FLASH ORx regs to allow
     for faster flash parts.
     Add documentation for BR/OR for FLASH.
 * Patch by Jon Loeliger 08 Feb 2005
   Determine L2 Cache size dynamically on 85XX boards.
 * Patch by Jon Loeliger, Kumar Gala 08 Feb 2005
   - Convert the CPM2 based functionality to use new CONFIG_CPM2
     option rather than a myriad of CONFIG_MPC8560-like variants.
     Applies to MPC85xx and MPC8260 boards, includes stxgp3 and sbc8560.
     Eliminates the CONFIG_MPC8560 option entirely.  Distributes the
     new CONFIG_CPM2 option to each 8260 board.
 * Add support for MicroSys PM856 board
   Patch by Josef Wagner, 03 Aug 2005
 * Minor fixes to PM854 board
   Patch by Josef Wagner, 03 Aug 2005
 * Adjust configuration of XENIAX board
   (chip select and GPIO required for USB operation)
 * Fix typos in cpu/85xx/start.S which caused DataTLB exception to be
   routed to the Watchdog handler
   Patch by Eugene Surovegin, 18 Jun 2005
 * (re)enabled scsi commands do_scsi() and do_scsiboot()
   Patch by Denis Peter, 06 Dec 2004
 * Fix endianess problem in TFTP / NFS default filenames
   Patch by Hiroshi Ito, 06 Dec 2004
 * Ignore broadcast status bit in received frames in 8260 FCC ethernet
   loopback test code
   Patch by Murray Jensen, 18 Jul 2005
 * Fix typo in mkconfig script (used == instead of =)
   Patch by Murray Jensen, 18 Jul 2005
 * Cleanup build problems on 64 bit build hosts
 * Update MAINTAINERS file
 * Patch by Stefan Roese, 01 Aug 2005:
   - Major cleanup for AMCC eval boards Walnut, Bubinga, Ebony, Ocotea
     (former IBM eval board). Please see "doc/README.AMCC-eval-boards-cleanup"
     for details.
   - Sycamore (PPC405GPr) eval board added (Walnut port is extended
     to run on both 405GP and 405GPr eval boards).
 * Patch by Steven Blakeslee, 27 Jul 2005:
   - Add support for AMCC PPC440EP/GR.
   - Add support for AMCC Yosemite PPC440EP eval board.
   - Add support for AMCC Yellowstone PPC440GR eval board.
 * Minor fixes for PPChameleon Board:
   - fix alignment of NAND size
   - make code do what the comment says
 * Implement h/w sector protection status synchronization at boot.
   The code is provided for, and was tested on, the Yukon/Alaska
   and PM520 boards only.
   A bug in flash_real_protect() for the Yukon board was fixed by
   adding a function that tells if two banks are on one flash chip.
 * Fix sysmon POST problem: check I2C error codes
   This fixes a problem of displaying bogus voltages when the voltages
   are so low that the I2C devices start failing while the rest of the
   system keeps running.
 * Patch by Cedric Vincent, 6 Jul 2005:
   Fix CFG_CMD_SETGETDCR handling in "common/cmd_dcr.c"
 * Patch by Jon Loeliger, 20 Jul 2005:
   Add missing PCI IO port definitions.
 * Add CompactFlash support for HMI1001 board.
 * Adjust printed board ID for LWMON board.
 * Fix low-level OHCI transfers for ARM920t and MPC5xxx
 * Add new argument format for flash commands to allow for usage like
   "erase $(addr) +$(filesize)", i. e. a size argument can be used and
   U-Boot will automaticially find the end of the corresponding sector.
 * Patch by Stefan Roese, 5 Jul 2005:
   Update uc100 board PHY setup
 * Patch by Stefan Roese, 1 Jul 2005:
   Fix PHY address for CATcenter board (now correct!)
 * Patch by Stefan Roese, 30 Jun 2005:
   Fix PHY addresses for PPChameleon and CATcenter boards
   Change MAINTAINER for most esd boards
 * Patch by Detlev Zundel, 30 Jun 2005:
   Fix LCD logo for lwmon board which got lost in the merge of 8xx and PXA LCD code
 * Fix baudrate calculation problem on MPC5200 systems
 * Add EEPROM and RTC support for HMI1001 board
 * Patch by Detlev Zundel, 20 Jun 2005:
   Fix initialization of low active GPIO pins on inka4x0 board
 * Enable redundant environment, disable HW flash protection of
   HMI1001 board
 * Patch by Travis Sawyer, 10 Jun 2005:
   Initialize allocated dev and private hw structures
   after their respective allocation in 440gx_enet.c
 * Patch by Steven Scholz, 10 Jun 2005:
   Fix byteorder problems with second argument of "bootm" with
   standalone images;
 * Add support for HMI1001 board
 * Disable "date" and "sntp" commands on TQM866M
 * Fix watchdog reset problems on LWMON board
 * Patch by Juergen Selent, 17 May 2005:
   Add support for Funkwerk VoVPN gateway module.
 * Cleanup debug code for MPC8220 FEC driver
 * Extend burst mode RAM test program to take a loop count
   (0 = infinite)
 * Use CONFIG_DRIVER_KS8695ETH to enable KS8695 ethernet driver on
   those boards that use it.
 * Patches by Greg Ungerer, 19 May 2005:
   - add support for the KS8695P (ARM 922 based) CPU
   - add support for the OpenGear CM4008, CM4116 and CM4148 boards
 * Patch by Steven Scholz, 19 May 2005:
   Add support for CONFIG_SERIAL_TAG on ARM boards
 * Add PCI support for Sorcery board.
   Code cleanup (especially Sorcery / Alaska / Yukon serial driver).
 * Fix compile problems caused by new burst mode SDRAM test;
   make port pins to trigger logic analyzer configurable
 * Fix timer handling on MPC85xx systems
 * Fix debug code in omap5912osk flash driver
 * Add support for MPC8247 based "IDS8247" board.
 * Add support for 2 x TSEC interfaces on the TQM8540 board.
 * On LWMON we must use the watchdog to reset the board as the CPU
   genereated HRESET pulse is too short to reset the external
   circuitry.
 * Add test tool to exercise SDRAM accesses in burst mode
   (as standalone program, MPC8xx/PowerPC only)
 * Increase CFG_MONITOR_LEN for Rattler board to match actual code
   size.
 * Major upate of JFFS2 code; now in sync with snapshot of MTD CVS of
   March 13, 2005); new configuration option CONFIG_JFFS2_LZO_LZARI
   added to support LZO and LZARI compression modes (undefined by
   default).
 * Fix problem with symbolic links in JFFS2 code.
 * Use linker ASSERT statement to prevent undetected overlapping of
   sections on PPChameleon board; other boards might use this, too.
 * Patch by Stefan Roese, 03 May 2005:
   Update for P3G4
   Fix problems in cmd_universe.c
 * Patch by Matthias Fuchs, 03 May 2005:
   Added missing variable declaration in cmd_nand.c
   Modified CFG_PCI_PTM1MS in configs/PLU405.h to map 128MB ram
 * Fix INKA4x0: use CS1 as gpio_wkup_6 output
 * Fix bug in the SDRAM initialization code for canmb, IceCube and
   PM520 boards.
   Fix PHY address for canmb board.
 * Cleanup serial console baudrate calculation on AT91RM9200;
   get rid of obsolete CFG_AT91C_BRGR_DIVISOR definition
 * Patch by Matthias Fuchs, 18 Apr 2005:
   Make PCI target address spaces on PMC405 and CPCI405 boards
   configurable via environment variables
 * Auto-size RAM on canmb board.
 * Add support for canmb board
 * Patch by Stefan Roese, 13 Apr 2005:
   Update for esd apc405
 * Fixes for TQM8560 board:
   - fix clock rates
   - remove debug messages
   - fix flash sector protection
 * Patch by Steven Scholz, 07 Apr 2005:
   Add i2c_reg_write() and i2c_reg_write() for at91rm9200 I2C
 * Patches by Steven Scholz, 07 Apr 2005:
   Fix compiler warning in altera.c
   Fix warning in cpu/arm920t/at91rm9200/i2c.c
 * Patch by Ladislav Michl, 06 Apr 2005:
   Fix voiceblue configuration.
 * Patch by Stefan Roese, 06 Apr 2005:
   Updates for OCOTEA board:
   - Changed U-Boot size from 512kByte to 256kByte
   - Fixed flash driver to support boot from soldered user flash
   - Added README for switch from PIBS firmware to U-Boot
 * Patch by Travis Sawyer, 05 Apr 2005:
   - Change timer frequency for ppc 440 from 10 ms to 1 ms.
     Problem found by Andrew Wozniak.
 * Patch by Steven Scholz, 06 Apr 2005:
   - creating SoC subdir for Atmel AT91RM9200 cpu/arm920t/at91rm9200
   - moving code out of cpu/at91rm9200 into cpu/arm920t/at91rm9200
 * Patches by Robert Whaley, 29 Nov 2004:
   - update the pxa-regs.h file for PXA27x chips
   - add PXA27x based ADSVIX board
   - add support for MMC on PXA27x processors
 * Patch by Andrew E. Mileski, 28 Nov 2004:
   Fix PPC4xx SPD SDRAM detection bug
 * Patch by Hiroshi Ito, 26 Nov 2004:
   Fix logic of "test -z" and "test -n" commands
 * Patch by Ladislav Michl, 05 Apr 2005:
   Add support for VoiceBlue board.
 * Patch by Ladislav Michl, 05 Apr 2005:
   Fix netboot_common() prototypes.
 * Patch by Steven Scholz, 05 Apr 2005:
   Use i.MX watchdog timer for reset_cpu()
 * Patch by Steven Scholz, 05 Apr 2005:
   Move reset_cpu() out of cpu/arm920t/start.S into the SoC specific
   subdirectories cpu/arm920t/imx/ and cpu/arm920t/s3c24x0/
   (now in interupts.c)
 * Add support for MPC8220 based "sorcery" board.
 * Add support for TQM8560 board.
 * Add FEC support for TQM8540 board.
   Interfaces are named as follows: "ENET1" - TSEC2, "ENET2" - FEC
 * Patch by Martin Krause, 04 Apr 2005:
   Update default configuration for CMC_PU2 board.
 * Patch by Steven Scholz, 04 Apr 2005:
   - remove all references to CONFIG_INIT_CRITICAL for ARM based boards
   - introduce two new configuration options instead:
     CONFIG_SKIP_LOWLEVEL_INIT and CONFIG_SKIP_RELOCATE_UBOOT
 * Patch by Steven Scholz, 04 Apr 2005:
   Make sure that MDIO clock does not exceed 2.5 MHz on AT91
 * Fix timer code for ARM systems: make sure that udelay() does not
   reset timers so it's save to use udelay() in timeout code.
 * Patch by Mathias Küster, 23 Nov 2004:
   add udelay support for the mcf5282 cpu
 * Patch by Tolunay Orkun, 16 November 2004:
   fix incorrect onboard Xilinx CPLD base address
 * Patch by Jerry Van Baren, 08 Nov 2004:
   - Add low-boot option for MPC8260ADS board (if lowboot is selected,
     the jumper for the HRCW source should select flash. If lowboot is
     not selected, the jumper for the HRCW source should select the
     BCSR.
   - change default load base address to 0x00400000
 * Patch by Yuli Barcohen, 08 Nov 2004:
   Add support for Analogue & Micro Rattler boards.
   Tested on Rattler8248.
 * Patch by Andre Renaud, 08 Nov 2004:
   Fix watchdog support in common/lcd.c
 * Patch by Marc Leeman, 05 Nov 2003:
   Enable all 4 PCMBRW buffers for the MPC8245 processor since the CPU
   bug only affects the XPC8245 processors
 * Patches by Josef Wagner, 29 Oct 2004:
   - Add support for MicroSys CPU87 board
   - Add support for MicroSys PM854 board
 * Patch by Jian Zhang, 02 Nov 2004:
   Add 16-bit NAND support
 * Patch by Scott McNutt, 01 Nov 2004:
   Add missing NIOS/NIOS2 support for "iminfo" command
 * Patch by Detlev Zundel, 29 Oct 2004:
   Add missing NIOS/NIOS2 support for "mkimage" tool.
 * Patch by David Adair, 27 Oct 2004:
   Add missing 440GX SDRAM Controller reset
 * Patch by Steven Scholz, 25 Oct 2004:
   Declare reset_cpu() in include/common.h instead locally
 * Patch by Yusdi Santoso, 22 Oct 2004:
   - Add support for HIDDEN_DRAGON board
   - fix endianess problem in driver/rtl1839.c
 * Patch by Allen Curtis, 21 Oct 2004:
   support multiple serial ports
 * Patch by Richard Klingler, 03 Apr 2005:
   Add call to eth_halt() in net/net.c when called functions fail
   after eth_init() has been called.
 * Patch by Sam Song, 3 April 2005:
   - Update README.Netconsole
   - Update README
 * Prepare for SoC rework of ARM code:
   - rename CONFIG_BOOTBINFUNC into  CONFIG_INIT_CRITICAL
   - rename memsetup into lowlevel_init (function name and source files)
   Patch by Steven Scholz, 03 Apr 2005:
   - create SoC specific directories include/asm-arm/arch-imx and
     include/asm-arm/arch-s3c24x0
 * Fix problems with SNTP support;
   enable SNTP support in some boards.
 * Patches by Martin Krause, 01 Apr 2005:
   - Fix flash erase timeout on CMC_PU2
   - Add automatic HW detection for CMC_PU2 and CMC_BASIC
 * Patch by Steven Scholz, 13 March 2005:
   fix cache enabling for AT91RM9200
 * Patch by Masami Komiya, 30 Mar 2005:
   add SNTP support and expand time server and time offset fields of
   DHCP support. See doc/README.SNTP
 * Patch by Steven Scholz, 13 Dec 2004:
   Fix bug in at91rm920 ethernet driver
 * Patch by Steven Scholz, 13 Dec 2004:
   Remove duplicated code by merging memsetup.S files for
   at91rm9200 boards into one cpu/at91rm9200/lowlevel.S
 * Patch by Detlev Zundel, 31 Mar 2005:
   Cleanup duplicate definition of overwrite_console()
 * Update TQM5200 configuration;
   prepare for Rev. 200 starter kit boards
 * Patch by Scott McNutt, 21 Oct 2004:
   Add support for Nios-II EPCS Controller core.
 * Patch by Scott McNutt, 20 Oct 2004:
   Nios-II cleanups:
   - Add sysid command (Nios-II only).
   - Locate default exception trampoline at proper offset.
   - Implement I/O routines (readb, writeb, etc)
   - Implement do_bootm_linux
 * Patches by Martin Krause, 22 Mar 2005:
   - use TQM5200_auto as MAKEALL target for TQM5200 systems
   - add support for SM501 graphics controller
   - add support for graphic console on TQM5200
   - add support for TQM5200 Rev 200
   - cleanup, fix typo in include/configs/TQM5200.h
 * Patch by Manfred Baral, 17 Mar 2005:
   Fix typo
 * Fix RTC configuration for PPChameleon board
 * Cleanup, fix typo in include/configs/TQM5200.h
 * Patch by Stefan Roese, 16 Mar 2005:
   Update for esd auto_update and hh405 board
 * Adapt for U-Boot image size (new features enabled) on TQM5200
 * Update code for TQM8540 board (and 85xx in general):
   - Change the name of the Ethernet driver: MOTO ENET -> ENET
   - Reformat boot messages
   - Enable redundant environment
   - Replace the -O2 optimization flag with -mno-string
 * Patch by David Brownell, 10 Mar 2005:
   Restore copyright statements in OHCI drivers.
 * Add support for TQM8540 board
 * Patch by Detlev Zundel, 14 Mar 2005:
   NC650: changed NAND flash addressing to using UPMB
 * Patch by Stefan Roese, 14 Mar 2005:
   Update for esd voh405 fpga image
 * INKA4x0: Allow initialization of LCD backlight dimming from
   "brightness" environment variable.
 * Add port initialization for digital I/O on INKA4x0
 * Patch by Stefan Roese, 01 Mar 2005:
   Update for esd boards dp405 and hub405
 * Fix get_partition_info() parameter error in all other calls
   (common/cmd_ide.c, common/cmd_reiser.c, common/cmd_scsi.c).
 * Enable USB and IDE support for INKA4x0 board
 * Patch by Andrew Dyer, 28 Feb 2005:
   fix ext2load passing an incorrect pointer to get_partition_info()
   resulting in load failure for devices other than 0
 * Add support for SRAM and 2 x Quad UARTs on INKA4x0 board
 * Cleanup USB and partition defines
 * Add support for ext2 filesystems and image timestamps to TQM5200 board
 * Add reset code for Coral-P on INKA4x0 board
 * Patch by Martin Krause, 28 Jun 2004:
   Update for TRAB board.
 * Fix some missing "volatile"s in MPC5xxx FEC driver
 * Fix cirrus voltage detection (for CPC45)
 * Fix byteorder problem in usbboot and scsiboot commands.
 * Patch by Cajus Hahn, 04 Feb 2005:
   - don't insist on leading '/' for filename in ext2load
   - set default partition to useful value (1) in ext2load
 * Patch by Andrew Dyer, 08 Jan 2005:
   fix wrong return codes in ext2 code
 * Removed '--no-warn-mismatch' option from Makefile. This option
   makes 'ld' to overlook binary objects compatibility.
 * Moved $(PLATFORM_LIBS) from the library group (--start-group ...
   --end-group) outside of the group. This will make 'ld' to do
   _multiple_ search in the library group when resolving symbol
   references and do only a _single_ seach in libgcc.a after the group
   search.
 * Fix stability problems on CPC45 board again.
 * Make image detection for diskboot / usbboot / scsiboot more robust
   (also check header checksum)
 * Update CPC45 board configuration.
 * Add USB and PCI support for INKA4x0 board
 * Fix IDE stability problems on CPC45 board (needs 2 x EIEIO).
 * Code cleanup
 * Patch by Robin Getz, 13 Oct 2004:
   Add standalone application to change SMC91C111 MAC addresses,
   see examples/README.smc91111_eeprom
 * Patch by Xiaogeng (Shawn) Jin, 12 Oct 2004:
   Fix Flash support for ARM Integrator CP.
 * Patch by Richard Woodruff, 10 Jan 2005:
   Update support for OMAP2420 (ARM11) and H4 board:
   o clean up and add new types to H4 memory probe code.
   o fix to work with internal boot.
   o added PRCM config III operation.
   o fix marginal flash timings.
   o add revison ATAG usage.
   o enable voltage scaling at power chip.
   o fix compile error for i2c.
 * Fix network problem (error when receiving multiple ARP packets)
 * Patch by Daniel Poirot, 12 Oct 2004:
   Add support for Wind River sbc405 board
 * Patch by Rainer Brestan, 12 Oct 2004:
   Make examples/Makefile more robust
 * Patch by Sam Song, 11 October 2004:
   - Add RESET/PREBOOT/AUTOBOOT support for RPXlite_DW board
   - Adjust CPU:BUS frequency ratio 1:1 when core frequency
     less than 50MHz
 * Patch by Sam Song, 10 Oct 2004:
   Fix a parameter error in run_command() in main.c
 * Patch by Richard Woodruff, 01 Oct 2004:
   add support for the TI OMAP2420 processor and its H4 reference
   board
 * Patch by Christian Pellegrin, 24 Sep 2004:
   Added support for NE2000 compatible (DP8390, DP83902) NICs.
 * Patch by Leif Lindholm, 23 Sep 2004:
   add support for the AMD db1550 board
 * Patch by Travis Sawyer, 15 Sep 2004:
   Add CONFIG_SERIAL_MULTI support for ppc4xx,
   update README.serial_multi
 * Patches by David Snowdon, 07 Sep 2004:
   - add u-boot.hex target in the top level Makefile
   - add support for the UNSW/NICTA PLEB 2 board (pleb2)
   - use -mtune=xscale and -march=armv5 options for PXA
 * Patch by Florian Schlote, 08 Sep 2004:
   Add support for SenTec-COBRA5272-board (Coldfire).
 * Patch by Gleb Natapov, 07 Sep 2004:
   mpc824x: set PCI latency timer to a sane value
   (is 0 after reset).
 * Patch by Kurt Stremerch, 03 Sep 2004:
   Add bitstream configuration option for fpga command (Xilinx only).
 * Patch by Kurt Stremerch, 03 Sep 2004:
   Add Xilinx Spartan2E family FPGA support
 * Patch by Jeff Angielski, 02 Sep 2004:
   Add Added support for H2 revision of the EP8260 board.
   Fixed formatting for some of the EP8260 related source files.
 * Patch by Jon Loeliger, 02 Sep 2004:
   Reset monitor size back to 256 so environment can be written
   to flash on MPC85xx ADS and CDS releases.
 * Patch by Paolo Broggini, 02 Sep 2004:
   Make BSS clearing on ARM systems more robust
 * Patch by Yue Hu and Joe, 01 Sep 2004:
   - add PCI support for ixp425;
   - add EEPRO100 suppor tfor ixdp425 board.
 * Fix problem with protected sector detection in driver/cfi_flash.c
 ======================================================================
 Changes for U-Boot 1.1.2:
 ======================================================================
 * Code cleanup, mostly for GCC-3.3.x
 * Cleanup confusing use of CONFIG_ETH*ADDR - ust his only to
   pre-define a MAC address; use CONFIG_HAS_ETH* to enable support for
   additional ethernet addresses.
 * Cleanup drivers/i82365.c - avoid duplication of code
 * Fix bogus "cannot span across banks" flash error message
 * Code cleanup
 * Add support for CompactFlash for the CPC45 Board.
 * Fix problems with CMC_PU2 flash driver.
 * Cleanup:
   - avoid trigraph warning in fs/ext2/ext2fs.c
   - rename UC100 -> uc100
 * Add support for UC100 board
 * Patch by Stefan Roese, 16 Dez 2004:
   - ext2fs support added
   - Tundra universe support added
   - Coldfire MCF5249 support added (no preloader needed!)
   - MCF5249 board TASREG added
   - PPC boards added: APC405, CPCI405DT, CPCI750, G2000, HH405,
     VOM405, WUH405
   - some esd boards updated
   - memory commands "mdc" and "mwc" added for cyclic read/write
     (CONFIG_MX_CYCLIC, see README for further description)
 * Add support for INKA4X0 board
 * Patch by Steven Scholz, 12 Dec 2004:
   Fix typo in AT91 memory setup.
 * Patch by Martin Krause, 27 Oct 2004:
   - add support for "STK52xx" board (including PS/2 multiplexer)
   - add hardware detection for TQM5200
 * Clean up CMC PU2 flash driver
 * Update MAINTAINERS file
 * Fix bug in MPC823 LCD driver
 * Fix udelay() on AT91RM9200 for delays < 1 ms.
 * Enable long help on CMC PU2 board;
   fix reset issue;
   increase CPU speed from 179 to 207 MHz.
 * Fix smc91111 ethernet driver for Xaeniax board (need to handle
   unaligned tail part specially).
 * Update for AT91RM9200DK and CMC_PU2 boards:
   - Enable booting directly from flash
   - fix CMC_PU2 flash driver
 * Fix mkimage usage message
 * Map SRAM on NC650 board
 * Work around for Ethernet problems on Xaeniax board
 * Patch by TsiChung Liew, 23 Sep 2004:
   - add support for MPC8220 CPU
   - Add support for Alaska and Yukon boards
 * Fix configuration for ERIC board (needs more room)
 * Adjust MIPS compiler options at run-time depending on tools version
   ("-march=4kc -mtune=4kc -Wa,-mips_allow_branch_to_undefined" for new,
   "-mcpu=4kc" for old tools)
 * Add passing of the command line and memory size information to  the
   kernel on xaeniax board.
 * Enable NAND flash support for NC650 board.
 * Patch by Thomas Lange 07 Oct 2004:
   Updated README for DBAu1x00 boards to match current status
 * Patch by Philippe Robin, 28 Sept 2004:
   Fix Flash support for Versatile.
 * Patch by Roger Blofeld, 16 Sep 2004:
   Fix timeout for DHCP command retry
 * Patch by Pantelis Antoniou, 14 Sep 2004:
   Fix early serial hang when CONFIG_SERIAL_MULTI is defined.
 * Patch by Pantelis Antoniou, 14 Sep 2004:
   Kick watchdog when bz-decompressing
 * Fix CFG_HZ problems on AT91RM9200 systems
   [Remember: CFG_HZ should be 1000 on ALL systems!]
 * Patch by Gridish Shlomi, 30 Aug 2004:
   - Add support to revA version of PQ27 and PQ27E.
   - Reverted MPC8260ADS baudrate back to original 115200
 * Patch by Hojin, 17 Sep 2004:
   Fix typo in cfi_flash.c
 * Patch by Mark Jonas, 09 September 2004:
   mtest's data line test (with CFG_ALT_MEMTEST set) returned a wrong
   error message
 * Patch by Mark Jonas, 31 August 2004:
   Added option CFG_XLB_PIPELINING to enable XLB pipelining. This
   improves FTP performance for MPC5200 systems. Enabled for IceCube
   by default.
 * Patch by Michael Bendzick, 30 Aug 2004:
   - Improve platform.S code for omap1510inn that detects whether code
     is running from SDRAM or not. Patch allows SDRAM to be configured
     if code is running out of SRAM at 0x20000000.
 * Patch by Frederick Klatt, 30 Aug 2004:
   Add support for the Wind River SBC8540/SBC8560 boards
 * Configure SX1 board to use drivers/cfi_flash.c
 * Patches by Michael Bendzick, 30 Aug 2004:
   - Configure omap1510inn board to use drivers/cfi_flash.c
   - Make drivers/cfi_flash.c protect environment and redundant
     environment.
 * Patch by Steven Scholz, 23 Jun 2004:
   - Add script (tools/img2brec.sh) to programm U-Boot into
     (Synch)Flash using the Bootstrap Mode of the MC9328MX1/L
 * Patches by Scott McNutt, 24 Aug 2004:
   - Add support for Altera Nios-II processors.
   - Add support for Psyent PCI-5441 board.
   - Add support for Psyent PK1C20 board.
 * Patches by Jon Loeliger, 24 Aug 2004:
   - Add support for the MPC8541 and MPC8555 CDS boards
   - Cleanup eth?addr handling: make dependent on CONFIG_ETH?ADDR
   - Convert MPC85xxADS to use common CFI flash driver
   - Fix PCI window on MPC85xx; remove unneeded PCI initialization
     from board_early_init_f()
   - Provide SW workaround for PCI initialization on 85xx CDS
 * Patches by George G. Davis, 24 Aug 2004:
   - Enable ramdisk/initrd tagged param support for omap1610h2_config
   - Remove static network setup defaults from mx1ads_config
   - update ARM boards to use constants from mach-types.h
 * Patch by Gary Jennejohn, 04 Oct 2004:
   - fix I2C on at91rm9200
   - add support for Ricoh RS5C372A RTC
 * Patch by Gary Jennejohn, 01 Oct 2004:
   - add support for CMC PU2 board
   - add support for I2C on at91rm9200
 * Patch by Gary Jennejohn, 28 Sep 2004:
   fix baudrate handling on at91rm9200
 * Patch by Yuli Barcohen, 22 Aug 2004:
   - remove ZPC.1900 board-specific flash driver;
     switch the port to generic CFI driver;
   - port clean-up
 * Patch by Hinko Kocevar, 21 Aug 2004:
   Add calc_fbsize() function used with VIDEOLFB_TAG on TRAB
 * Clean up tools/bmp_logo.c to not add trailing white space
 * Patch by Hinko Kocevar, 21 Aug 2004:
   - Group common framebuffer functions in common/lcd.c
   - Group common framebuffer macros and #defines in include/lcd.h
   - Provide calc_fbsize() for video ATAG
 * Patch by Sam Song, 21 August 2004:
   - Fix a typo in README
   - Align "(RO)" output for "flinfo" after "protect on"
   - Add RESET support for RPXlite_DW board; adjust CPU:BUS frequency
     ratio 1:1 when core frequency less than 50MHz
 * Patches by Hinko Kocevar, 21 Aug 2004:
   - fix some "use of label at end of compound statement" warnings
   - Define type of LCD panel on lubbock board if CONFIG_LCD is used
 * Patch by Steven Scholz, 16 Aug 2004:
   - Introducing the concept of SoCs "./cpu/$(CPU)/$(SOC)"
   - creating subdirs for SoCs ./cpu/arm920t/imx and ./cpu/arm920t/s3c24x0
   - moving SoC specific code out of cpu/arm920t/ into cpu/arm920t/$(SOC)/
   - moving drivers/s3c24x0_i2c.c and drivers/serial_imx.c out of drivers/
     into cpu/arm920t/$(SOC)/
 * Patches by Sean Chang, 09 Aug 2004:
   - Added support for both 8 and 16 bit mode access to System ACE CF
     through MPU.
   - Fixed missing System ACE CF device during get FAT partition info
     in fat_register_device function.
   - Enabled System ACE CF support on ML300.
 * Patch by Sean Chang, 09 Aug 2004:
   Synch defines for saveenv and do_saveenv functions so they get
   compiled under the same statement.
 * Patch by Sean Chang, 09 Aug 2004:
   - Added I2C support for ML300.
   - Added support for ML300 to read out its environment information
     stored on the EEPROM.
   - Added support to use board specific parameters as part of
     U-Boot's environment information.
   - Updated MLD files to support configuration for new features
     above.
 * Patches by Travis Sawyer, 05 Aug 2004:
   - Remove incorrect bridge settings for eth group 6
   - Add call to setup bridge in ppc_440x_eth_initialize
   - Fix ppc_440x_eth_init to reset the phy only if its the
     first time through, otherwise, just check the phy for the
     autonegotiated speed/duplex.  This allows the use of netconsole
   - only print the speed/duplex the first time the phy is reset.
 * Patch by Shlomo Kut, 29 Mar 2004:
   Add support for MKS Instruments "Quantum" board
 * Fix build problem with Cogent boards;
   avoid using <asm/byteorder.h> when using the host compiler
 * Patch by Ganapathi C, 04 Aug 2004:
   Fix NFS timeout issue
 * Patch by Yuli Barcohen, 19 Jul 2004:
   - Fix host tools building in Cygwin environment
   - Fix header files search order for host tools
 * Patch by Tom Armistead, 19 Jul 2004:
   Fix kgdb.S support for 74xx_75x cpu
 * Patch by Jon Loeliger, 15 Jul 2004:
   Fix MPC85xx I2C driver
 * Fix problems with CDROM drive as slave device on Lite5200 IDE bus.
 * Patch by Stephen Williams, 15 July 2004
   Set the PCI class code for JSE board as part of PCI interface setup
 * Patch by Michael Bendzick, 15 Jul 2004:
   Fix problem with writes with odd sizes in drivers/cfi_flash.c when
   CFG_FLASH_USE_BUFFER_WRITE is set
 * Patch by Yuli Barcohen, 13 Jul 2004:
   Allow clock setting on MPC866/MPC885 series chips according to
   environment variable `cpuclk'
 * Patch by Yuli Barcohen, 20 Apr 2004:
   Remove unnecessary redefine of CPM_DATAONLY_SIZE for MPC826x
 * Patch by Vincent Dubey, 24 Sep 2004:
   Add support for xaeniax board
 * Add comment about non-GPL character of standalone applications to
   COPYING file
 * Fix FEC ethernet problem on NSCU board.
 * Patch by Gary Jennejohn, 09 Sep 2004:
   allow to use USART1 as console port on at91rm9200dk boards
 * Patch by Stefan Roese, 16 Sep 2004:
   Update AR405 board.
 * Fix SysClk handling for PPChameleon and CATcenter boards
 * Patch by Detlev Zundel, 08 Sep 2004:
   Update etags build target
 * Improve NetConsole support: add support for broadcast destination
   address and buffered input.
 * Cleanup compiler warnings for GCC 3.3.x and later
 * Fix problem in cmd_jffs2.c introduced by CFG_JFFS_SINGLE_PART patch
 * Add support for IDS "NC650" board
 * Add automatic update support for LWMON board
 * Clear Block Lock-Bits when erasing flash on LWMON board.
 * Fix return code of "fatload" command
 * Enable MSDOS/VFAT filesystem support for LWMON board
 * Patch by Martin Krause, 03 Aug 2004:
   change timing for SM501 graphics controller on TQM5200 module
 * Patch by Mark Jonas, 13 July 2004:
   - Total5200 LCD now run in little endian mode. Endianess conversion
     is done in hardware.
   - Removed last reference to "console" environment variable.
 * Patches by Lars Munch, 12 Jul 2004:
   - move at45.c to board/at91rm9200dk/ since this is at91rm9200dk
     board specific
   - split out the LXT971A PHY from ns_9750_eth.h
   - split the dm9161 phy part out of at91rm9200_ether.c
 * Patch by Andreas Engel, 12 Jul 2004:
   Replaced hardcoded PL011 clock frequency with config variable.
   Fixed wrong CONFIG_CMD_DFL doc.
 * Patch by Thomas Viehweger, 09 Jun 2004:
   make it possible to remove chpart when there is only one partition
 * Add support for console over UDP (compatible to Ingo Molnar's
   netconsole patch under Linux)
 * Patch by Jon Loeliger, 16 Jul 2004:
   - support larger DDR memories up to 2G on the PC8540/8560ADS and
     STXGP3 boards
   - Made MPC8540/8560ADS be 33Mhz PCI by default.
   - Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
     and CONFIG_L2_INIT_RAM options.
   - Refactor Local Bus initialization out of SDRAM setup.
   - Re-implement new version of LBC11/DDR11 errata workarounds.
   - Moved board specific PCI init parts out of CPU directory.
   - Added TLB entry for PCI-1 IO Memory
   - Updated README.mpc85xxads
 * Patch by Sascha Hauer, 28 Jun:
   - add generic support for Motorola i.MX architecture
   - add support for mx1ads, mx1fs2 and scb9328 boards
 * Patches by Marc Leeman, 23 Jul 2004:
   - Add define for the PCI/Memory Buffer Configuration Register
   - corrected comments in cpu/mpc824x/cpu_init.c
 * Add support for multiple serial interfaces
   (for example to allow modem dial-in / dial-out)
 * Patch by Stefan Roese, 15 Jul 2004:
   cpu/ppc4xx/sdram.c rewritten now using get_ram_size()
 * Fix NSCU config; add ethernet wakeup code.
 * Add link for preloader for Motorola Coldfire to README.m68k
 * Patch by Michael Bendzick, 12 Jul 2004:
   fix output formatting in drivers/cfi_flash.c
 * Patch by Mark Jonas, 02 Jul 2004:
   Fix lowboot (again) on MPC5xxx
 * Patch by Curt Brune, 07 Jul 2004:
   relocate exception vectors on arm720t if needed
 * Patch by George G. Davis, 06 Jul 2004:
   - update mach-types.h to latest arm.linux.org.uk master list
   - Set correct OMAP1610 bi_arch_number for build target
 * Patch by Curt Brune, 06 Jul 2004:
   evb4510: add support for timer interrupt; cleanup
 * Patch by Dan Poirot, 06 Jul 2004:
   Fix sbc8260 environment variables
 * Cleanup redundand "console" environment variable
 * Patch by Mark Jonas, 05 Jul 2004:
   add support for the Total5100's and Total5200's LCD screen
 * Patches by Dan Eisenhut, 01 Jul 2004:
   - README fixes.
   - Move doc2000.h include to prevent compiler warning on some boards
 * Patch by Mark Jonas, 01 Jul 2004:
   Added support for Total5100 and Total5200 (Rev.1 and Rev.2)
   MGT5100 and MPC5200 based Freescale platforms.
 * Patch by Philippe Robin, 01 Jul 2004:
   Add initialization for Integrator and versatile board files.
 * Patch by Hinko Kocevar, 01 Jun 2004:
   Fix VFD FB allocation, add LCD FB allocation on ARM
 * Patch by Martin Krause, 30 Jun 2004:
   Add support for TQM5200 board
 * Patch by Martin Krause, 29 Jun 2004:
   Add loopw command: infinite write loop on address range
 * Patches by Yasushi Shoji, 29 Jun 2004:
   - add empty include/asm-microblaze/processor.h
   - add to CREDITS and MAINTAINERS
   - add gd initialization
   - add MicroBlaze and SUZAKU board to MAKEALL script
   - add reset support for SUZAKU
   - add flush_cache() for MicroBlaze
   - add CFG_FLASH_SIZE to include/configs/suzaku.h since we have fixed
     size flash memory on SUZAKU
 * Patch by Prakash Kumar, 27 Jun 2004:
   Add support for the PXA250 based Intrinsyc Cerf board.
 * Patch by Yasushi Shoji, 27 Jun 2004:
   fix comment in include/common.h
 * Rename SBC8560 into sbc8560 for consistency
 * Patch by Daniel Poirot, 24 Jun 2004:
   Add support for Wind River's sbc8240 board
 * Patches by Yasushi Shoji, 26 Jun 2004:
   - drivers/serial_xuartlite.c: fix "return 0" in void function
   - add microblaze support to mkimage tool
 * Patch by Fred Klatt, 25 Jun 2004:
   Add support for WindRiver's sbc8560 board
 * Patch by Nicolas Lacressonniere, 24 Jun 2004
   Small Bugs fixes for "at91rm9200dk" board:
   - Timing modifications for SPI DataFlash access
   - Fix NAND flash detection bug
 * Patch by Nicolas Lacressonniere, 24 Jun 2004:
   Add Support for Flash AT49BV6416 for AT91RM9200DK board
 * Patch by Jon Loeliger, 17 June 2004:
   Completion of the 8540ADS/8560ADS updates:
   Fix some PCI and Rapid I/O memory maps,
   Initialize both TSEC 1 and 2,
   Initialize SDRAM
   Update MAINTAINER for 85xx boards and README.mpc85xxads
 * Patch by Yuli Barcohen, 16 Jun 2004:
   Remove obsolete AdderII port which was superseded by unified
   AdderII/Adder87x port
 * Patch by Ladislav Michl, 16 Jun 2004:
   Fix gcc-3.3.3 warnings for smc91111.c
 * Patch by Stefan Roese, 02 Jul 2004:
   - Fix bug in 405 ethernet driver; allocated data not cleared!
   - Fix problem in 405 i2c driver; don't try to print without console!
 * Patch by Paul Ruhland, 11 Jun 2004:
   Remove debug code from 'board/lpd7a40x/flash.c'
 * Patch by Andrea Marson, 11 Jun 2004:
   Update for PPChameleon board:
   - support for SysClk @ 25MHz
   - support for Silicon Motion SM712 VGA controller
   - some clean ups
 * Patches by Richard Woodruff, 10 Jun 2004:
   - fix problems with examples/stubs.c for GCC >= 3.4
   - fix problems with gd initialization
 * Patch by Curt Brune, 17 May 2004:
   - Add support for Samsung S3C4510B CPU (ARM7tdmi based SoC)
   - Add support for ESPD-Inc. EVB4510 Board
 * Patch by Marc Leeman, 11 May 2004:
   Fix for MPC8245 - reading PPC Memory from another device with the
   PPC as PCI target device corrupts data due to interenal hardware
   buffering.
 * Fix "cls" command when used with splash screen
 * Increase NFS download timeout (now 1 min - 10 sec is to short for a
   slow download of a big image)
 * Add "cls" function to MPC823 LCD driver so we can reinitialize the
   display even after showing a bitmap
 * Patch by Josef Wagner, 04 Jun 2004:
   - DDR Ram support for PM520 (MPC5200)
   - support for different flash types (PM520)
   - USB / IDE / CF-Card / DiskOnChip support for PM520
   - 8 bit boot rom support for PM520/CE520
   - Add auto SDRAM module detection for MicroSys CPC45 board (MPC8245)
   - I2C and RTC support for CPC45
   - support of new flash type (28F160C3T) for CPC45
 * Fix flash parameters passed to Linux for PPChameleon board
 * Remove eth_init() from lib_arm/board.c; it's done in net.net.c.
 * Patch by Paul Ruhland, 10 Jun 2004:
   fix support for Logic SDK-LH7A404 board and clean up the
   LH7A404 register macros.
 * Patch by Matthew McClintock, 10 Jun 2004:
   Modify code to select correct serial clock on Sandpoint8245
 * Patch by Robert Schwebel, 10 Jun 2004:
   Add support for Intel K3 strata flash.
 * Patch by Thomas Brand, 10 Jun 2004:
   Fix "loads" command on DK1S10 board
 * Patch by Yuli Barcohen, 09 Jun 2004:
   Add support for 8MB flash SIMM and JFFS2 file system on
   Motorola FADS board and its derivatives (MPC86xADS, MPC885ADS).
 * Patch by Yuli Barcohen, 09 Jun 2004:
   Add support for Analogue&Micro Adder87x and the older AdderII board.
 * Patch by Ming-Len Wu, 09 Jun 2004:
   Add suppport for MC9328 (Dargonball) CPU and Motorola MX1ADS board
 * Patch by Sam Song, 09 Jun 2004:
   - Add support for RPXlite_DW board
   - Update FLASH driver for 4*AM29DL323DB90VI
   - Add option configuration of CFG_ENV_IS_IN_NVRAM on RPXlite_DW board
 * Patch by Mark Jonas, 08 June 2004:
   - Make MPC5200 boards evaluate the SVR to print processor name and
     version in checkcpu() (cpu/mpc5xxx/cpu.c).
 * Patch by Kai-Uwe Bloem, 06 May 2004:
   Fix endianess problem in cramfs code
 * Patch by Tom Armistead, 04 Jun 2004:
   Add support for MAX6900 RTC
 * Patches by Ladislav Michl, 03 Jun 2004:
   - fix cfi_flash.c on LE systems
   - let 'make mrproper' delete u-boot.img as well
   - turn printf into debug in cfi_flash.c
 * Patch by Kurt Stremerch, 28 May 2004:
   Add support for Exys XSEngine board
 * Patch by Martin Krause, 27 May 2004:
   Fix a MPC5xxx I2C timing issue in i2c_probe().
 * Patch by Leif Lindholm, 27 May 2004:
   Fix board_init_f() for dbau1x00 board.
 * Patch by Imre Deak, 26 May 2004:
   On OMAP1610 platforms check if booting from RAM(CS0) or flash(CS3).
   Set flash base accordingly, and decide whether to do or skip board
   specific setup steps.
 * Patch by Josef Baumgartner, 26 May 2004:
   Add missing define in include/asm-m68k/global_data.h
 * Patch by Josef Baumgartner, 25 May 2004:
   Add missing functions get_ticks() and get_tbclk() in lib_m68k/time.c
 * Patch by Paul Ruhland, 24 May 2004:
   fix SDRAM initialization for LPD7A400 board.
 * Patch by Jian Zhang, 20 May 2004:
   add support for environment in NAND flash
 * Patch by Yuli Barcohen, 20 May 2004:
   Add support for Interphase iSPAN boards.
 * Patches by Paul Ruhland, 17 May 2004:
   - Add I/O functions to the smc91111 ethernet driver to support the
     Logic LPD7A40x boards.
   - Add support for the Logic Zoom LH7A40x based SDK board(s),
     specifically the LPD7A400.
 * Patches by Robert Schwebel, 15 May 2004:
   - call MAC address reading code also for SMSC91C111;
   - make SMSC91C111 timeout configurable, remove duplicate code
   - fix get_timer() for PXA
   - update doc/README.JFFS2
   - use "bootfile" env variable also for jffs2
 * Patch by Tolunay Orkun, 14 May 2004:
   Add support for Cogent CSB472 board (8MB Flash Rev)
 * Patch by Thomas Viehweger, 14 May 2004:
   - flash.h: more flash types added
   - immap_8260.h: some bits added (useful for RMII)
   - cmd_coninfo.c: typo corrected, printf -> puts
   - reduced size by replacing spaces with tab
 * Patch by Robert Schwebel, 13 May 2004:
   Add 'imgextract' command: extract one part of a multi file image.
 * Patches by Jon Loeliger, 11 May 2004:
   Dynamically handle REV1 and REV2 MPC85xx parts.
     (Jon Loeliger, 10-May-2004).
   New consistent memory map and Local Access Window across MPC85xx line.
   New CCSRBAR at 0xE000_0000 now.
   Add RAPID I/O memory map.
   New memory map in README.MPC85xxads
     (Kumar Gala, 10-May-2004)
   Better board and CPU identification on MPC85xx boards at boot.
     (Jon Loeliger, 10-May-2004)
   SDRAM clock control fixes on MPC8540ADS & MPC8560 boards.
   Some configuration options for MPC8540ADS & MPC8560ADS cleaned up.
     (Jim Robertson, 10-May-2004)
   Rewrite of the MPC85xx Three Speed Ethernet Controller (TSEC) driver.
   Supports multiple PHYs.
     (Andy Fleming, 10-May-2004)
   Some README.MPC85xxads updates.
     (Kumar Gala, 10-May-2004)
   Copyright updates for "Freescale"
     (Andy Fleming, 10-May-2004)
 * Patch by Stephen Williams, 11 May 2004:
   Add flash support for ST M29W040B
   Reduce JSE specific flash.c to remove dead code.
 * Patch by Markus Pietrek, 04 May 2004:
   Fix clear_bss code for ARM systems (all except s3c44b0 which
   doesn't clear BSS at all?)
 * Fix "ping" problem on INC-IP board. Strange problem:
   Sometimes the store word instruction hangs while writing to one of
   the Switch registers, but only if the next instruction is 16-byte
   aligned. Moving the instruction into a separate function somehow
   makes the problem go away.
 * Patch by Rishi Bhattacharya, 08 May 2004:
   Add support for TI OMAP5912 OSK Board
 * Patch by Sam Song May, 07 May 2004:
   Fix typo of UPM table for rmu board
 * Patch by Pantelis Antoniou, 05 May 2004:
   - Intracom board update.
   - Add Codec POST.
 * Add support for the second Ethernet interface for the 'PPChameleon'
   board.
 * Patch by Dave Peverley, 30 Apr 2004:
   Add support for OMAP730 Perseus2 Development board
 * Patch by Alan J. Luse, 29 Apr 2004:
   Fix flash chip-select (OR0) option register setting on FADS boards.
 * Patch by Alan J. Luse, 29 Apr 2004:
   Report MII network speed and duplex setting properly when
   auto-negotiate is not enabled.
 * Patch by Jarrett Redd, 29 Apr 2004:
   Fix hang on reset on Ocotea board due to flash in wrong mode.
 * Patch by Dave Peverley, 29 Apr 2004:
   add MAC address detection to smc91111 driver
 * Patch by David Müller, 28 Apr 2004:
   fix typo in lib_arm/board.c
 * Patch by Tolunay Orkun, 20 Apr 2004:
   - README update: add CONFIG_CSB272 and csb272_config
   - add descriptions for some MII/PHY options, CONFIG_I2CFAST, and
     i2cfast environment variable
 * Patch by Yuli Barcohen, 19 Apr 2004:
   - Rename DUET_ADS to MPC885ADS
   - Rename CONFIG_DUET to CONFIG_MPC885_FAMILY
   - Rename CONFIG_866_et_al to CONFIG_MPC866_FAMILY
   - Clean up FADS family port to use the new defines
 * Fix PCI support on CPC45 board
 * Patch by Scott McNutt, 25 Apr 2004:
   Add Nios GDB/JTAG Console support:
   - Add stubs to support gdb via JTAG.
   - Add support for console over JTAG.
   - Minor cleanup.
 * Add support for CATcenter board (based on PPChameleon ME module)
 * Patch by Klaus Heydeck, 12 May 2004:
   Using external watchdog for KUP4 boards in mpc8xx/cpu.c;
   load_sernum_ethaddr() for KUP4 boards in lib_ppc/board.c;
   various changes to KUP4 board specific files
 * Fix minor network problem on MPC5200: need some delay between
   resetting the PHY and sending the first packet. Implemented in a
   "natural" way by invoking the PHY reset and initialization code
   only once after power on vs. each time the interface is brought up.
 * Add some limited support for low-speed devices to SL811 USB controller
   (at least "usb reset" now passes successfully and "usb info" displays
   correct information)
 * Change init sequence for multiple network interfaces: initialize
   on-chip interfaces before external cards.
 * Fix memory leak in the NAND-specific JFFS2 code
 * Fix SL811 USB controller when attached to a USB hub
 * Fix config option spelling in PM520 config file
 * Fix PHY discovery problem in cpu/mpc8xx/fec.c (introduced by
   patches by Pantelis Antoniou, 30 Mar 2004)
 * Fix minor NAND JFFS2 related issue
 * Fixes for SL811 USB controller:
   - implement workaround for broken memory stick
   - improve error handling
 * Increase packet send timeout to 1 ms in cpu/mpc8xx/scc.c to better
   cope with congested networks.
 ======================================================================
 Changes for U-Boot 1.1.1:
 ======================================================================
 * Patch by Travis Sawyer, 23 Apr 2004:
   Fix VSC/CIS 8201 phy descrambler interoperability timing due to
   errata from Vitesse Semiconductor.
 * Patch by Philippe Robin, 22 Apr 2004:
   Fix ethernet configuration for "versatile" board
 * Patch by Kshitij Gupta, 21 Apr 2004:
   Remove busy loop and use MPU timer fr usleep() on OMAP1510/1610 boards
 * Patch by Steven Scholz, 24 Feb 2004:
   Fix a bug in AT91RM9200 ethernet driver:
   The MII interface is now initialized before accessing the PHY.
 * Patch by John Kerl, 19 Apr 2004:
   Use U-boot's miiphy.h for PHY register names, rather than
   introducing a new header file.
 * Update pci_ids.h from linux-2.4.26
 * Patch by Masami Komiya, 19 Apr 2004:
   Fix problem cause by VLAN function on little endian architecture
   without VLAN environment
 * Clean up the TQM8xx_YYMHz configurations; allow to use the same
   binary image for all clock frequencies. Implement run-time
   optimization of flash access timing based on the actual bus
   frequency.
 * Modify KUP4X board configuration to use SL811 driver for USB memory
   sticks (including FAT / VFAT filesystem support)
 * Add SL811 Host Controller Interface driver for USB
 * Add CFG_I2C_EEPROM_ADDR_OVERFLOW desription to README
 * Patch by Pantelis Antoniou, 19 Apr 2004:
   Allow to use shell style syntax (i. e. ${var} ) with standard parser.
   Minor patches for Intracom boards.
 * Patch by Christian Pell, 19 Apr 2004:
   cleanup support for CF/IDE on PCMCIA for PXA25X
 * Temporarily disabled John Kerl's extended MII command code because
   "miivals.h" is missing
 * Patches by Mark Jonas, 13 Apr 2004:
   - Remove CS0 chip select timing setting from cpu/mpc5xxx/start.S
   - Add sync instructions to IceCube SDRAM init code
   - Move SDRAM chip constants into seperate include files
   - Unify DDR and SDR initialization code
   - Unify all IceCube (Lite5xxx) target names
 * Patch by John Kerl, 16 Apr 2004:
   Enable ranges in mii command, e.g. mii read 0-1f 0 or
   mii read 4-7 18-1a.  Also add mii dump subcommand for
   pretty-printing standard regs 0-5.
 * Patch by  Stephen Williams, 16 April 2004:
   fix typo in JSE.h; update MAINTAINERS
 * Patch by Matthew S. McClintock, 14 Apr 2004:
   fix initdram function for utx8245 board
 * Patch by Markus Pietrek, 14 Apr 2004:
   use ATAG_INITRD2 instead of deprecated ATAG_INITRD tag
 * Patch by Reinhard Meyer, 18 Apr 2004:
   provide the IDE Reset Function for EMK 5200 boards
 * Patch by Masami Komiya, 12 Apr 2004:
   fix pci_hose_write_config_{byte,word}_via_dword problems
 * Patch by Sangmoon Kim, 12 Apr 2004:
   Update max RAM size for debris board
 * Patch by Travis Sawyer, 08 Apr 2004:
   Add TLB entry for second DIMM slot on ocotea
 * Patch by Masami Komiya, 08 Apr 2004:
   add RTL8169 network driver
 * Patch by Dan Malek, 07 Apr 2004:
   - Add support for RPC/STx GP3, Motorola 8560 board
   - Update 85xx TSEC driver so it searches MII for first available PHY
     and uses that one.
   - Add functions to support console MII commands.
 * Patch by Tolunay Orkun, 07 Apr 2004:
   Move initialization of bi_iic_fast[]
   from board_init_f() to board_init_r()
 * Patch by Yasushi Shoji, 07 Apr 2004:
   Cleanup microblaze port
 * Patch by Sangmoon Kim, 07 Apr 2004:
   Add auto SDRAM module detection for Debris board
 * Patch by Rune Torgersen, 06 Apr 2004:
   - Fix some PCI problems on the MPC8266ADS board
   - Fix the location of some PCI entries in the immap structure
 * Patch by Yasushi Shoji, 07 Apr 2004:
   - add support for microblaze processors
   - add support for AtmarkTechno "suzaku" board
 * Configure PPChameleon board to use redundand environment in flash
 * Configure PPChameleon board to use JFFS2 NAND support.
 * Added support for JFFS2 filesystem (read-only) on top of NAND flash
 * Patch by Rune Torgersen, 16 Apr 2004:
   LBA48 fixes
 * Patches by Pantelis Antoniou, 16 Apr 2004:
   - add support for a new version of an Intracom board and fix
     various other things on others.
   - add verify support to the crc32 command (define
     CONFIG_CRC32_VERIFY to enable it)
   - fix FEC driver for MPC8xx systems:
     1. fix compilation problems for boards that use dynamic
        allocation of DPRAM
     2. shut down FEC after network transfers
   - HUSH parser fixes:
     1. A new test command was added. This is a simplified version of
        the one in the bourne shell.
     2. A new exit command was added which terminates the current
        executing script.
     3. Fixed handing of $? (exit code of last executed command)
   - Fix some compile problems;
     add "once" functionality for the netretry variable
 * Patch by George G. Davis, 02 Apr 2004:
   add support for Intel Assabet board
 * Patch by Stephen Williams, 01 Apr 2004:
   Add support for Picture Elements JSE board
 * Patch by Christian Pell, 01 Apr 2004:
   Add CompactFlash support for PXA systems.
 * Patches by Pantelis Antoniou, 30 Mar 2004:
   - add auto-complete support to the U-Boot CLI
   - add support for NETTA and NETPHONE boards; fix NETVIA board
   - add support for the Epson 156x series of graphical displays
     (These displays are serial and not suitable for using a normal
     framebuffer console on them)
   - add infrastructure needed in order to POST any DSPs in a board
   - improve and fix various things in the MPC8xx FEC driver:
     1. The new 87x and 88x series of processors have two FECs,
        and the new driver supports them both.
     2. Another change in the 87x/88x series is support for
        the RMII (Reduced MII) interface. However numerous
        changes are needed to make it work since the PHYs
        are connected to the same lines. That means that
        you have to address them correctly over the MII
        interface.
     3. We now correctly match the MII/RMII interface
        configuration to what the PHY reports.
   - Fix problem when readingthe MII status register. Due to the
     internal design of many PHYs you have to read the register
     twice. The problem is more apparent in 10Mbit mode.
   - add new mode ".jffs2s" for reading from a NAND device: it just
     skips over bad blocks.
   - add networking support for VLANs (802.1q), and CDP (Cisco
     Discovery Protocol)
   - some minor patches / cleanup
 * Patch by Yuli Barcohen, 28 Mar 2004:
   - Add support for MPC8272 family including MPC8247/8248/8271/8272
   - Add support for MPC8272ADS evaluation board (another flavour of MPC8260ADS)
   - Change configuration method for MPC8260ADS family
 * add startup code to clear the BSS of standalone applications
 * Fix if / elif handling bug in HUSH shell
 ======================================================================
 Changes for U-Boot 1.1.0:
 ======================================================================
 * Patch by Mark Jonas: Remove config.tmp files only when
   unconfiguring the board
 * Adapt RMU board for bigger flash memory
 * Patch by Klaus Heydeck, 13 Mar 2003:
   Add support for KUP4X Board
 * Patch by Pavel Bartusek, 21 Mar 2004
   Add Reiserfs support
 * Patch by Hinko Kocevar, 20 Mar 2004
   - Add auto-release for SMSC LAN91c111 driver
   - Add save/restore of PTR and PNR regs as suggested in datasheet
 * Patch by Stephen Williams, 19 March 2004
   Increase speed of sector reads from SystemACE,
   shorten poll timeout and remove a useless reset
 * Patch by Tolunay Orkun, 19 Mar 2004:
   Make GigE PHY 1000Mbps Speed/Duplex detection conditional
   (CONFIG_PHY_GIGE)
 * Patch by Brad Kemp, 18 Mar 2004:
   prevent machine checks during a PCI scan
 * Patch by Pierre Aubert, 18 Mar 2004:
   Fix string cleaning in IDE identification
 * Patch by Pierre Aubert, 18 Mar 2004:
   - Unify video mode handling for Chips & Technologies 69000 Video
     chip and Silicon Motion SMI 712/710/810 Video chip
   - Add selection of the video output (CRT or LCD) via 'videoout'
     environment variable for the Silicon Motion
   - README update
 * Patch by Pierre Aubert, 18 Mar 2004:
   include/common.h typo fix
 * Patches by Tolunay Orkun, 17 Mar 2004:
   - Add support for bd->bi_iic_fast[] initialization via environment
     variable "i2cfast" (CONFIG_I2CFAST)
   - Add "i2cfast" u-boot environment variable support for csb272
 * Patch by Carl Riechers, 17 Mar 2004:
   Ignore '\0' characters in console input for use with telnet and
   telco pads.
 * Patch by Leon Kukovec, 17 Mar 2004:
   typo fix for strswab prototype #ifdef
 * Patches by Thomas Viehweger, 16 Mar 2004:
   - show PCI clock frequency on MPC8260 systems
   - add FCC_PSMR_RMII flag for HiP7 processors
   - in do_jffs2_fsload(), take load address from load_addr if not set
     explicit, update load_addr otherwise
   - replaced printf by putc/puts when no formatting is needed
     (smaller code size, faster execution)
 * Patch by Phillippe Robin, 16 Mar 2004:
   avoid dereferencing NULL pointer in lib_arm/armlinux.c
 * Patch by Stephen Williams, 15 Mar 2004:
   Fix CONFIG_SERIAL_SOFTWARE_FIFO documentation
 * Patch by Tolunay Orkun, 15 Mar 2004:
   Initialize bi_opbfreq to real OPB frequency via get_OPB_freq()
 * Patch by Travis Sawyer, 15 Mar 2004:
   Update CREDITS & MAINTAINERS files for PPC440GX & Ocotea port
 * Add start-up delay to make sure power has stabilized before
   attempting to switch on USB on SX1 board.
 * Patch by Josef Wagner, 18 Mar 2004:
   - Add support for MicroSys XM250 board (PXA255)
   - Add support for MicroSys PM828 board (MPC8280)
   - Add support for 32 MB Flash on PM825/826
   - new SDRAM refresh rate for PM825/PM826
   - added support for MicroSys PM520 (MPC5200)
   - replaced Query by Identify command in CPU86/flash.c
     to support 28F160F3B
 * Fix wrap around problem with udelay() on ARM920T
 * Add support for Macronix flash on TRAB board
 * Patch by Pierre Aubert, 15 Mar 2004:
   Fix buffer overflow in IDE identification
 * Fix power-off of LCD for out-of-band temperatures on LWMON board
 * Remove redundand #define in IceCube.h
 * Patch by Steven Scholz, 27 Feb 2004:
   - Adding get_ticks() and get_tbclk() for AT91RM9200
   - Many white space fixes in cpu/at91rm9200/interrupts.c
 * Patches by Steven Scholz, 20 Feb 2004:
   some cleanup in AT91RM9200 related code
 * Patches by Travis Sawyer, 12 Mar 2004:
   - Fix Gigabit Ethernet support for 440GX
   - Add Gigabit Ethernet Support to MII PHY utilities
 * Patch by Brad Kemp, 12 Mar 2004:
   Fixes for drivers/cfi_flash.c:
   - Better support for x8/x16 implementations
   - Added failure for AMD chips attempting to use CFG_FLASH_USE_BUFFER_WRITE
   - Added defines for AMD command and address constants
 * Patch by Leon Kukovec, 12 Mar 2004:
   Fix get_dentfromdir() to correctly handle deleted dentries
 * Patch by George G. Davis, 11 Mar 2004:
   Remove hard coded network settings in TI OMAP1610 H2
   default board config
 * Patch by George G. Davis, 11 Mar 2004:
   add support for ADS GraphicsClient+ board.
 * Patch by Pierre Aubert, 11 Mar 2004:
   - add bitmap command and splash screen support in cfb console
   - add [optional] origin in the bitmap display command
 * Patch by Travis Sawyer, 11 Mar 2004:
   Fix ocotea board early init interrupt setup.
 * Patch by Thomas Viehweger, 11 Mar 2004:
   Remove redundand code; add  PCI-specific bits to include/mpc8260.h
 * Patch by Stephan Linz, 09 Mar 2004
   - Add support for the SSV ADNP/ESC1 (Nios Softcore)
 * Patch by George G. Davis, 9 Mar 2004:
   fix recent build failure for SA1100 target
 * Patch by Travis Sawyer, 09 Mar 2004:
   Support native interrupt mode for the IBM440GX.
   Previously it was running in 440GP compatibility mode.
 * Patch by Philippe Robin, 09 Mar 2004:
   Added ARM Integrator AP, CP and Versatile PB926EJ-S Reference
   Platform support.
 * Patch by Masami Komiya, 08 Mar 2004:
   Don't overwrite server IP address or boot file name
   when the boot server does not return values
 * Patch by Tolunay Orkun, 5 Mar 2004:
   Removed compile time restriction on CFG_I2C_SPEED for DS1338 RTC
 * Patch by Tolunay Orkun, 5 Mar 2004:
   Fix early board initialization for Cogent CSB272 board
 * Patch by Ed Okerson, 3 Mar 2004:
   fix CFI flash writes for little endian systems
 * Patch by Reinhard Meyer, 01 Mar 2004:
   generalize USB and IDE support for MPC5200 with according
   changes to IceCube.h and TOP5200.h
   add Am29LV256 256 MBit FLASH support for TOP5200 boards
   add info about USB and IDE to README
 * Patch by Yuli Barcohen, 4 Mar 2004:
   Fix problems with GCC 3.3.x which changed handling of global
   variables explicitly initialized to zero (now in .bss instead of
   .data as before).
 * Patch by Leon Kukovec, 02 Mar 2004:
   add strswab() to fix IDE LBA capacity, firmware and model numbers
   on little endian machines
 * Patch by Masami Komiya, 02 Mar 2004:
   - Remove get_ticks() from NFS code
   - Add verification of RPC transaction ID
 * Patch by Pierre Aubert, 02 Mar 2004:
   cleanup for IDE and USB drivers for MPC5200
 * Patch by Travis Sawyer, 01 Mar 2004:
   Ocotea:
   - Add IBM PPC440GX Ref Platform support (Ocotea)
     Original code by Paul Reynolds <PaulReynolds@lhsolutions.com>
     Adapted to U-Boot and 440GX port
   440gx_enet.c:
   - Add gracious handling of all Ethernet Pin Selections for 440GX
   - Add RGMII selection for Cicada CIS8201 Gigabit PHY
   ppc440.h:
   - Add needed bit definitions
   - Fix formatting
 * Patch by Carl Riechers, 1 Mar 2004:
   Add PPC440GX prbdv0 divider to fix memory clock calculation.
 * Patch by Stephan Linz, 27 Feb 2004
   - avoid problems for targets without NFS download support
 * Patch by Rune Torgersen, 27 Feb 2004:
   - Added LBA48 support (CONFIG_LBA48 & CFG_64BIT_LBA)
   - Added support for 64bit printing in vsprintf (CFG_64BIT_VSPRINTF)
   - Added support for 64bit strtoul (CFG_64BIT_STRTOUL)
 * Patch by Masami Komiya, 27 Feb 2004:
   Fix rarpboot: add autoload by NFS
 * Patch by Dan Eisenhut, 26 Feb 2004:
   fix flash_write return value in saveenv
 * Patch by Stephan Linz, 11 Dec 2003
   expand config.mk to avoid trigraph warnings on NIOS
 * Rename "BMS2003" board into "HMI10"
 * SX1 patches: use "serial#" for USB serial #; use redundand environment
   storage; auto-set console on USB port (using preboot command)
 * Add support for SX1 mobile phone; add support for USB-based console
   (enable with "setenv stdout usbtty; setenv stdin usbtty")
 * Fix LOWBOOT configuration for MPC5200 with DDR memory
 * Fix SDRAM timings for LITE5200 / IceCube board
 * Handle Auti-MDIX / connection status for INCA-IP
 * Fix USB problems when attempting to read 0 bytes
 * Patch by Travis Sawyer, 26 Feb 2004:
   Fix broken compile for XPEDITE1K target.
 * Patch by Stephan Linz, 26 Feb 2004:
   Bug fix for NFS code on NIOS targets
 * Patch by Stephen Williams, 26 Feb 2004:
   Break up SystemACE reads of large block counts
 * Patch by Pierre Aubert, 26 Feb 2004
   add IDE support for MPC5200
 * Patch by Masami Komiya, 26 Feb 2004:
   add autoload via NFS
 * Patch by Stephen Williams
   Use of CONFIG_SERIAL_SOFTWARE_FIFO in board.c consistent with uses
   elsewhere in the source.
 * Patch by Steven Scholz, 25 Feb 2004:
   - Timeouts in FPGA code should be based on CFG_HZ
   - Minor cleanup in code for Altera FPGA ACEX1K
 * Patch by Steven Scholz, 25 Feb 2004:
   Changed "Directory Hierarchy" section in README
 * Patch by Masami Komiya, 25 Feb 2004:
   Reduce copy count in nfs_read_reply() of NFS code
 * Patch by Markus Pietrek, 24 Feb 2004:
   NS9750 DevBoard added
 * Patch by Pierre Aubert, 24 Feb 2004
   add USB support for MPC5200
 * Patch by Steven Scholz, 24 Feb 2004:
   - fix MII commands to use values from last command
 * Patch by Torsten Demke, 24 Feb 2004:
   Add support for the eXalion platform (SPSW-8240, F-30, F-300)
 * Patch by Rahul Shanbhag, 19 Feb 2004:
   Fixes for for OMAP1610 board:
   - shift some IRQ specific code to platform.S file
   - remove duplicatewatchdog reset code from start.S
 * Make Auto-MDIX Support configurable on INCA-IP board
 * Fix license for mkimage tool
 * Patch by Masami Komiya, 24 Feb 2004:
   Update NetBootFileXferSize in NFS code
 * Patch by Scott McNutt, 24 Feb 2004:
   fix packet length in NFS code
 * Patch by Masami Komiy, 22 Feb 2004:
   Add support for NFS for file download
 * Patch by Andrea Scian, 17 Feb 2004:
   Add support for S3C44B0 processor and DAVE B2 board
 * Patch by Steven Scholz, 20 Feb 2004:
   - Add support for MII commands on AT91RM9200 boards
   - some cleanup in AT91RM9200 ethernet code
 * Patch by Peter Ryser, 20 Feb 2004:
   Add support for the Xilinx ML300 platform
 * Patch by Stephan Linz, 17 Feb 2004:
   Fix watchdog support for NIOS
 * Patch by Josh Fryman, 16 Feb 2004:
   Fix byte-swapping for cfi_flash.c for different bus widths
 * Patch by Jon Diekema, 14 Jeb 2004:
   Remove duplicate "FPGA Support" notes from the README file
 * Patches by Reinhard Meyer, 14 Feb 2004:
   - update board/emk tree; use common flash driver
   - Corrected tested bits in machine check exception in cpu/mpc5xxx/traps.c
     [adapted for other PPC CPUs -- wd]
   - Added support for the M48T08 on the EVAL5200 board in rtc/mk48t59.c
 * Patch by Jon Diekema, 13 Feb 2004:
   Call show_boot_progress() whenever POST "FAILED" is printed.
 * Patch by Nishant Kamat, 13 Feb 2004:
   Add support for TI OMAP1610 H2 Board
   Fixes for cpu/arm926ejs/interrupt.c
 	(based on Richard Woodruff's patch for arm925, 16 Oct 03)
   Fix for a timer bug in OMAP1610 Innovator
   Add support for CS0 (ROM)/CS3 (Flash) boot in OMAP1610 Innovator and H2
 * Patches by Stephan Linz, 12 Feb 2004:
   - add support for NIOS timer with variable period preload counter value
   - prepare POST framework support for NIOS targets
 * Patch by Denis Peter, 11 Feb 2004:
   add POST support for the MIP405 board
 * Patch by Laurent Mohin, 10 Feb 2004:
   Fix buffer overflow in common/usb.c
 * Patch by Tolunay Orkun, 10 Feb 2004:
   Add support for Cogent CSB272 board
 * Patch by Thomas Elste, 10 Feb 2004:
   Add support for NET+50 CPU and ModNET50 board
 * Patch by Sam Song, 10 Feb 2004:
   Fix typos in cfi_flash.c
 * Patch by Leon Kukovec, 10 Feb 2004
   Fixed long dir entry slot id calculation in get_vfatname
 * Patch by Robin Gilks, 10 Feb 2004:
   add "itest" command (operators: -eq, -ne, -lt, -gt, -le, -ge, ==,
   !=, <>, <, >, <=, >=)
 * Fix problem with side effects in macros in include/usb.h
 * Patch by David Benson, 13 Nov 2003:
   bug 841358 - fix TFTP download size limit
 * Fixing bug 850768:
   improper flush_cache() in load_serial()
 * Fixing bug 834943:
   MPC8540 - missing volatile declarations
 * Patch by Stephen Williams, 09 Feb 2004:
   Add support for Xilinx SystemACE chip:
   - New files common/cmd_ace.c and include/systemace.h
   - Hook systemace support into cmd_fat and the partition manager
 * Patch by Travis Sawyer, 09 Feb 2004:
   Add bi_opbfreq & bi_iic_fast to 440GX bd_info as needed for Linux
 * Patch by Travis Sawyer, 09 Feb 2004:
   o 440GX:
     - Fix PCI Indirect access for type 1 config cycles with ppc440.
     - Add phymode for 440 enet
     - fix pci pre init
   o XPedite1K:
     - Change board_pre_init to board_early_init_f
     - Add user flash to bus controller setup
     - Fix pci pre init
     - Fix is_pci_host to check GPIO for monarch bit
     - Force xpedite1k to pci conventional mode (via #define option)
 * Patch by Brad Kemp, 4 Feb 2004:
   - handle the machine check that is generated during the PCI scans
     on 82xx processors.
   - define the registers used in the IMMR by the PCI subsystem.
 * Patch by Pierre Aubert, 03 Feb 2004:
   cpu/mpc5xxx/start.S: copy MBAR into SPR311
 * Patch by Jeff Angielski, 03 Feb 2004:
   Fix copy & paste error in cpu/mpc8260/pci.c
 * Patch by Reinhard Meyer, 24 Jan 2004:
   Fix typo in cpu/mpc5xxx/pci_mpc5200.c
 * Add Auto-MDIX support for INCA-IP
 * Some code cleanup
 * Patch by Josef Baumgartner, 10 Feb 2004:
   Fixes for Coldfire port
 * Patch by Brad Kemp, 11 Feb 2004:
   Fix CFI flash driver problems
 * Make sure to use a bus clock divider of 2 only when running TQM8xxM
   modules at CPU clock frequencies above 66 MHz.
 * Optimize flash programming speed for LWMON (by another 100% :-)
 * Patch by Jian Zhang, 3 Feb 2004:
   - Changed the incorrect FAT12BUFSIZE
   - data_begin in fsdata can be negative. Changed it to be short.
 * Patches by Stephan Linz, 30 Jan 2004:
   1: - board/altera/common/flash.c:flash_erase():
        o allow interrupts befor get_timer() call
        o check-up each erased sector and avoid unexpected timeouts
      - board/altera/dk1c20/dk1s10.c:board_early_init_f():
        o enclose sevenseg_set() in cpp condition
      - remove the ASMI configuration for DK1S10_standard_32 (never present)
      - fix some typed in mistakes in the NIOS documentation
   2: - split DK1C20 configuration into several header files:
        o two new files for each NIOS CPU description
        o U-Boot related part is remaining in DK1C20.h
   3: - split DK1S10 configuration into several header files:
        o two new files for each NIOS CPU description
        o U-Boot related part is remaining in DK1S10.h
   4: - Add support for the Microtronix Linux Development Kit
        NIOS CPU configuration at the Altera Nios Development Kit,
        Stratix Edition (DK-1S10)
   5: - Add documentation for the Altera Nios Development Kit,
        Stratix Edition (DK-1S10)
   6: - Add support for the Nios Serial Peripharel Interface (SPI)
        (master only)
   7: - Add support for the common U-Boot SPI framework at
        RTC driver DS1306
 * Patch by Rahul Shanbhag, 28 Jan 2004:
   Fix flash protection/locking handling for OMAP1610 innovator board.
 * Patch by Rolf Peukert, 28 Jan 2004:
   fix flash write problems on CSB226 board (write with 32 bit bus width)
 * Patches by Mark Jonas, 16 Jan 2004:
   - fix rounding error when calculating baudrates for MPC5200 PSCs
   - make sure CFG_RAMBOOT and CFG_LOWBOOT are not enabled at the same
     time which is not supported
 * Patch by Yuli Barcohen, 26 Jan 2004:
   Allow bzip2 compression for small memory footprint boards
 * Patch by Brad Kemp, 21 Jan 2004:
   Add support for CFI flash driver for both the Intel and the AMD
   command sets.
 * Patch by Travis Sawyer, 20 Jan 2004:
   Fix pci bridge auto enumeration of sibling p2p bridges.
 * Patch by Tolunay Orkun, 12 Jan 2004:
   Add some delays as needed for Intel LXT971A PHY support
 * Patches by Stephan Linz, 09 Jan 2004:
   - avoid warning: unused variable `piop' in board/altera/common/sevenseg.c
   - make DK1C20 board configuration related to ASMI conform to
     documentation
 * Patch by Anders Larsen, 09 Jan 2004:
   ARM memory layout fixes: the abort-stack is now set up in the
   correct RAM area, and the BSS is zeroed out as it should be.
   Furthermore, the magic variables 'armboot_end' and 'armboot_end_data'
   of the linker scripts are replaced by '__bss_start' and '_end',
   resp., which is a further step to eliminate unnecessary differences
   between the implementation of the CPU architectures.
 * Patch by liang a lei, 9 Jan 2004:
   Fix Intel 28F128J3 ID in include/flash.h
 * Patch by Masami Komiya, 09 Jan 2004:
   add support for TB0229 board (NEC VR4131 MIPS processor)
 * Patch by Leon Kukovec, 12 Dec 2003:
   changed extern __inline__ into static __inline__ in
   include/linux/byteorder/swab.h
 * Patch by Travis Sawyer, 30 Dec 2003:
   Add support for IBM PPC440GX. Multiple EMAC Ethernet devices,
   select MDI port based on enabled EMAC device.
   Add support for XES Inc <http://www.xes-inc.com> XPedite1000 440GX
   base PrPMC board.
 * Patch by Wolter Kamphuis, 15 Dec 2003:
   made CONFIG_SILENT_CONSOLE usable on all architectures
 * Disable date command on TQM866M - there is no RTC on MPC866
 * Fix variable CPU clock for MPC859/866 systems for low CPU clocks
 * Implement adaptive SDRAM timing configuration based on actual CPU
   clock frequency for INCA-IP; fix problem with board hanging when
   switching from 150MHz to 100MHz
 * Add PCMCIA CS support for BMS2003 board
 * Add variable CPU clock for MPC859/866 systems (so far only TQM866M):
   see doc/README.MPC866 for details;
   implement workaround for "SIU4" and "SIU9" silicon bugs on MPC866;
   calculate CPU clock frequency from PLL register values.
 * Add support for 128 MB RAM on TQM8xxL/M modules
 * Fix PS/2 keyboard problem caused by statically initialized variable
   pointing to a location in flash
 * Fix INCA-IP clock calculation: 400/3 = 133.3 MHz, not 130.
 * The PS/2 mux on the BMS2003 board needs 450 ms after power on
   before we can access it; add delay in case we are faster (with no
   CF card inserted)
 * Cleanup of some init functions
 * Make sure SCC Ethernet is always stopped by the time we boot Linux
   to avoid Linux crashes by early packets coming in.
 * Accelerate flash accesses on LWMON board by using buffered writes
 * Fix typo in Makefile;
   fix problem with PARTNUM detection
 * Patch by Reinhard Meyer, 09 Jan 2004:
   - add RTC support for MPC5200 based boards (requires RTC_XTAL)
 * Add support for IDE LED on BMS2003 board
   (exclusive with status LED!)
 * Add support for PS/2 keyboard (used with PS/2 multiplexor on
   BMS2003 board)
 * Patches by Reinhard Meyer, 4 Jan 2004 + 7 Jan 2004:
   Add common files for "emk" boards
 * Add a common get_ram_size() function and modify the the
   board-specific files to invoke that common implementation.
 ======================================================================
 Changes for U-Boot 1.0.1:
 ======================================================================
 * Set default clock for INCA-IP to 150 MHz
 * Make BMS2003 use a separate config file to avoid #ifdef mess;
   add I2C support; add support for DS1337 RTC
 * Add CompactFlash support  for BMS2003 board
 * Add support for status LED on BMS2003 board
 * Patch by Scott McNutt, 02 Jan 2004:
   Add support for the Nios Active Serial Memory Interface (ASMI)
   on Cyclone devices
 * Patch by Andrea Marson, 16 Dec 2003:
   Add support for the PPChameleon ME and HI modules
 * Patch by Yuli Barcohen, 22 Dec 2003:
   Add support for Motorola DUET ADS board (MPC87x/88x)
 * Patch by Robert Schwebel, 15 Dec 2003:
   add support for cramfs (uses JFFS2 command interface)
 * Patches by Stephan Linz, 11 Dec 2003:
   - more documentation for NIOS port
   - new struct nios_pio_t, struct nios_spi_t
   - Reconfiguration for NIOS Development Kit DK1C20:
     o move board related code from board/dk1c20
       to board/altera/dk1c20
     o create a new common source path board/altera/common
       and move generic flash access stuff into it
     o change/expand configuration file DK1C20.h
   - Add support for NIOS Development Kit DK1S10
   - Add status LED support for NIOS systems
   - Add dual 7-segment LED support for Altera NIOS DevKits
 * Patch by Ronen Shitrit, 10 Dec 2003:
   Add support for the Marvell DB64360 / DB64460 development boards
 * Patch by Detlev Zundel, 10 Dec 2003:
   fix dependency problem in examples/Makefile
 * Patch by Denis Peter, 8 Dec 2003
   - add support for the PATI board (MPC555)
   - add SPI support for the MPC5xx
 * Patch by Anders Larsen, 08 Dec 2003:
   add configuration options CONFIG_SERIAL_TAG and CONFIG_REVISION_TAG
   to pass ATAG_SERIAL and ATAG_REVISION, resp., to the ARM target;
   cleanup some redundand #defines
 * Patch by André Schwarz, 8 Dec 2003:
   fixes for Davicom DM9102A Ethernet Chip (#define CONFIG_TULIP_FIX_DAVICOM):
   - TX and RX deskriptors must be quad-word aligned
   - does not work with only one TX deskriptor
   - standard reset method does not work
 * Patch by Masami Komiya, 08 Dec 2003:
   add RTL8139 ethernet driver
 * Patches by Ed Okerson, 07 Dec 2003:
   - fix ethernet for the AU1x00 processors in little-endian mode.
   - extend memsetup.S for the AU1x00 processors in BE and LE modes
 * Minor code cleanup (coding style)
 * Patch by Reinhard Meyer, 30 Dec 2003:
   - cpu/mpc5xxx/fec.c: added CONFIG_PHY_ADDR, added CONFIG_PHY_TYPE,
   - added CONFIG_PHY_ADDR to include/configs/IceCube.h,
   - turned debug print of PHY registers into a function (called in two places)
   - added support for EMK MPC5200 based modules
 * Fix MPC8xx PLPRCR_MFD_SHIFT typo
 * Add support for TQM866M modules
 * Fixes for TQM855M with 4 MB flash (Am29DL163 = _no_ mirror bit flash)
 * Fix a few compiler warnings
 * Patch by Reinhard Meyer, 28 Dec 2003:
   Add initial support for TOP5200 board
 * Make CPU clock on ICA-IP board controllable by a "cpuclk"
   environment variable which can set to "100", "133", or "150". The
   CPU clock will be configured accordingly upon next reboot. Other
   values are ignored. In case of an invalid or undefined "cpuclk"
   value, the compile-time default CPU clock speed will be used.
 * Enable Quad-UART on BMS2003 board (initialize the PCMCIA memory
   window that is used to access the UART registers by the Linux driver)
 * Patch by Reinhard Meyer, 20 Dec 2003:
   Fix clock calculation for the MPC5200 for higher clock frequencies
   (above 2**32 / 10 = 429.5 MHz).
 * Fix CONFIG_PLL_PCI_TO_MEM_MULTIPLIER divider error in SP8240 configuration
 * Fix IceCube CLKIN configuration (it's 33.000000MHz)
 * Add new configuration for IceCube board with DDR memory
 * Update TRAB memory configurations
 * Add JFFS2 support for INCA-IP board
 * Patch by Bill Hargen, 09 Dec 2003:
   - BUBINGA405EP: changed flash driver to protect top sector containing
     first instruction.
   - BUBINGA405EP: configured "eeprom" command to access boot config EEPROM.
   - BUBINGA405EP: fixed PLL init (init chip selects before FPGA/NVRAM access).
   - 405EP: fixed SPD-based SDRAM init (only use banks 0 and 1).
   - 405EP: added/fixed support for "reginfo" command.
   - 4xx: removed spurious MII error messages on "mii info" command.
 * Patch by Bernhard Kuhn, 28 Nov 2003:
   add support for Coldfire CPU
   add support for Motorola M5272C3 and M5282EVB boards
 * Patch by Pierre Aubert, 24 Nov 2003:
   - add a return value for the fpga command
   - add ide_preinit() function called in ide_init if CONFIG_IDE_PREINIT
     is defined. If ide_preinit fails, ide_init is aborted.
   - fix an endianess problem in fat.h
 * Patch by Wolter Kamphuis, 05 Dec 2003:
   Add support for SNMC's QS850/QS823/QS860T boards
 * Patch by Yuli Barcohen, 3 Dec 2003:
   "revive" U-Boot support for old Motorola MPC860ADS board
 * Patch by Cam(ilo?), 03 Dec 2003:
   make examples build even with broken Montavista objcopy
 * Patch by Pavel Bartusek, 27 Nov 2003:
   fix conversion problem with "bootretry" evironment variable
 * Patch by Andre Schwarz, 24 Nov 2003:
   add support for mvblue (mvBlueLYNX and mvBlueBOX) boards
 * Patch by Pavel Bartusek, 21 Nov 2003:
   set ZMII bridge speed on 440
 * Patch by Anders Larsen, 17 Nov 2003:
   Fix mismatched #ifdef / #endif in include/asm-arm/arch-pxa/hardware.h
 * Patches by David Müller, 14 Nov 2003:
   - board/mpl/common/common_util.c
     * implement support for BZIP2 compressed images
     * various cleanups (printf -> puts, ...)
   - board/mpl/common/flash.c
     * report correct errors to upper layers
     * check the erase fail and VPP low bits in status reg
   - board/mpl/vcma9/cmd_vcma9.c
   - board/mpl/vcma9/flash.c
     * various cleanups (printf -> puts, ...)
   - common/cmd_usb.c
     * fix typo in comment
   - cpu/arm920t/usb_ohci.c
     * support for S3C2410 is missing in #if line
   - drivers/cs8900.c
     * reinit some registers in case of error (cable missing, ...)
   - fs/fat/fat.c
     * support for USB/MMC devices is missing in #if line
   - include/configs/MIP405.h
   - include/configs/PIP405.h
     * enable BZIP2 support
     * enlarge malloc space to 1MiB because of BZIP2 support
   - include/configs/VCMA9.h
     * enable BZIP2 support
     * enlarge malloc space to 1MiB because of BZIP2 support
     * enable USB support
   - lib_arm/armlinux.c
     * change calling convention of ARM Linux kernel as
       described on http://www.arm.linux.org.uk/developer/booting.php
 * Patch by Thomas Lange, 14 Nov 2003:
   Split dbau1x00 into dbau1000, dbau1100 and dbau1500 configs to
   support all these AMD boards.
 * Patch by Thomas Lange, 14 Nov 2003:
   Workaround for mips au1x00 physical memory accesses (the au1x00
   uses a 36 bit bus internally and cannot access physical memory
   directly. Use the uncached SDRAM address instead of the physical
   one.)
 * Patch by Xue Ligong (Joe), 13 Nov 2003:
   add Realtek 8019 ethernet driver
 * Patch by Yuli Barcohen, 13 Nov 2003:
   MPC826xADS/PQ2FADS  cleanup
 * Patch by Anders Larsen, 12 Nov 2003:
   Update README to mark the PORTIO commands non-standard
 * Patch by Nicolas Lacressonnière, 12 Nov 2003:
   update for for Atmel AT91RM9200DK development kit:
   - support for environment variables in DataFlash
   - Atmel DataFlash AT45DB1282 support
 * Patch by Jeff Carr, 11 Nov 2003:
   add support for new version of 8270 processors
 * Patches by George G. Davis, 05 Nov 2003:
   - only pass the ARM linux initrd tag to the kernel when an initrd
     is actually present
   - update omap1510inn configuration file
 * Patches by Stephan Linz, 3 Nov 2003:
   - more endianess fixes for LAN91C111 driver
   - CFG_HZ configuration patch for NIOS Cyclone board
 * Patch by Stephan Linz, 28 Oct 2003:
   fix PHY_INT_REG vs. PHY_MASK_REG bug in drivers/smc91111.c
 * Patch by Steven Scholz, 20 Oct 2003:
   - make "mii info <addr>" show infor for PHY at "addr" only
   - Endian fix for miiphy_info()
 * Patch by Gleb Natapov, 19 Sep 2003:
   Move most of the timer interrupt related PPC code to ppc_lib/interrupts.c
 * Patch by Anders Larsen, 17 Sep 2003:
   Bring ARM memory layout in sync with the documentation:
   stack and malloc-heap are now located _below_ the U-Boot code
 * Accelerate booting on TRAB board: read and check  autoupdate  image
   headers first instead of always reading the whole images.
 * Fix type in MPC5XXX code (pointed out by Victor Wren)
 * Enabled password check on RMU board
 * Fix configuration problem with IceCube in LOWBOOT configuration:
   envrionment got embedded, corrupting the image layout.
 * Fix NEC display names (it's 6440 [for 640x480], not 6640).
 * Added BMS2003 board
   add support for NEC NL6448BC33-54. 10.4", 640x480 TFT display
 * Fix flash driver for TRAB board (must use Unlock Bypass Reset
   command to exit Unlock Bypass Mode); adjust timings for flash, SRAM
   and CPLD
 * Use "-fPIC" instead of "-mrelocatable" to prevent problems with
   recent tools
 * Add checksum verification to 'imls' command
 * Add bd_info fields needed for 4xx Linux I2C driver
 * Patch by Martin Krause, 4 Nov. 2003:
   Fix error in cmd_vfd.c (TRAB board: "vfd /1" shows now only one Bitmap)
 * Print used network interface when CONFIG_NET_MULTI is set
 * Patch by Bernhard Kuhn, 28 Oct 2003:
   Add low boot support for MPC5200
 * Fix problem with dual PCMCIA support (NSCU)
 * Fix MPC5200 I2C initialization function
 ======================================================================
 Changes for U-Boot 1.0.0:
 ======================================================================
 * Fix parameter passing to standalone images with bootm command
 * Patch by Kyle Harris, 30 Oct 2003:
   Fix build errors for ixdp425 board
 * Patch by David M. Horn, 29 Oct 2003:
   Fixes to build under CYGWIN
 * Get IceCube MGT5100 working (again)
 * Fix problems in memory test on some boards (which was not
   non-destructive as intended)
 * Patch by Gary Jennejohn, 28 Oct 2003:
   Change fs/fat/fat.c to put I/O buffers in BSS instead on the stack
   to prevent stack overflow on ARM systems
 * Patch by Stephan Linz, 28 Oct 2003:
   fix init sequence error for NIOS port
 * Allow lowercase spelling for IceCube_5200; support MPC5200LITE name
 * Add CONFIG_VERSION_VARIABLE to TRAB configuration
 * Patch by Xiao Xianghua, 23 Oct 2003:
   small patch for mpc85xx
 * Fix small problem in MPC5200 I2C driver
 * Fix FCC3 support on ATC board
 * Correct header printing for multi-image files in do_bootm()
 * Make CONFIG_SILENT_CONSOLE work with CONFIG_AUTOBOOT_KEYED
 * Fix PCI problems on PPChameleon board
 * Patch by Steven Scholz, 18 Oct 2003:
   Fix AT91RM9200 ethernet driver
 * Patch by Nye Liu, 17 Oct 2003:
   Fix typo in include/mpc8xx.h
 * Patch by Richard Woodruff, 16 Oct 03:
   Fixes for cpu/arm925/interrupt.c
   - Initialize timestamp & lastdec vars.
   - fix timestamp overflows.
   - fix lastdec overflow.
   - smarter normalization to allow udelay() below 1ms to work.
 * Patch by Scott McNutt, 16 Oct
   add networking support for the Altera Nios Development Kit,
   Cyclone Edition (DK-1C20)
 * Patch by Jon Diekema, 14 Oct 2003:
   add hint about doc/README.silent to README file
 * Add CompactFlash support for NSCU
 * Fix PCI problems on PPChameleonEVB
 * TRAB auto-update: Base decision if we have to strip the image
   header on image type as encoded in the header
   (include image type patch by Martin Krause, 17 Oct 2003)
 * Patches by Xianghua Xiao, 15 Oct 2003:
   - Added Motorola CPU 8540/8560 support (cpu/85xx)
   - Added Motorola MPC8540ADS board support (board/mpc8540ads)
   - Added Motorola MPC8560ADS board support (board/mpc8560ads)
 * Fix flash timings on TRAB board
 * Make sure HUSH is initialized for running auto-update scripts
 * Make 5200 reset command _really_ reset the board, without running
   any other code after it
 * Fix errors with flash erase when range spans  across banks
   that are mapped in reverse order
 * Fix flash mapping and display on P3G4 board
 * Patch by Kyle Harris, 15 Jul 2003:
   - add support for Intel IXP425 CPU
   - add support for IXDP425 eval board
 * Added config option CONFIG_SILENT_CONSOLE.  See doc/README.silent
   for more information
 * Patch by Steven Scholz, 10 Oct 2003
   - Add support for Altera FPGA ACEX1K
 * Patches by Thomas Lange, 09 Oct 2003:
   - fix cmd_ide.c for non ppc boards (read/write functions did not
     add ATA base address)
   - fix for shannon board
   - #ifdef CONFIG_IDE_8xx_DIRECT some otherwise unused code
   - Endian swap ATA identity for all big endian CPUs, not just PPC
   - MIPS only: New option CONFIG_MEMSIZE_IN_BYTES for passing memsize
     args to linux
   - add support for dbau1x00 board (MIPS32)
 * Patch by Sangmoon Kim, 07 Oct 2003:
   add support for debris board
 * Patch by Martin Krause, 09 Oct 2003:
   Fixes for TRAB board
   - /board/trab/rs485.c: correct baudrate
   - /board/trab/cmd_trab.c: bug fix for problem with timer overflow in
     udelay(); fix some timing problems with adc controller
   - /board/trab/trab_fkt.c: add new commands: gain, eeprom and power;
     modify commands: touch and buzzer
 * Disable CONFIG_SUPPORT_VFAT when used with CONFIG_AUTO_UPDATE
   (quick & dirty workaround for rogue pointer problem in get_vfatname());
   Use direct function calls for auto_update instead of hush commands
 * Patch by Scott McNutt, 04 Oct 2003:
   - add support for Altera Nios-32 CPU
   - add support for Nios Cyclone Development Kit (DK-1C20)
 * Patch by Steven Scholz, 29 Sep 2003:
   - A second parameter for bootm overwrites the load address for
     "Standalone Application" images.
   - bootm sets environment variable "filesize" to the resulting
     (uncompressed) data length for "Standalone Application" images
     when autostart is set to "no". Now you can do something like
 	if bootm $fpgadata $some_free_ram ; then
 		fpga load 0 $some_free_ram $filesize
 	fi
 * Patch by Denis Peter, 25 Sept 2003:
   add support for the MIP405 Rev. C board
 * Patch by Yuli Barcohen, 25 Sep 2003:
   add support for Zephyr Engineering ZPC.1900 board
 * Patch by Anders Larsen, 23 Sep 2003:
   add CMD_PORTIO to CFG_CMD_NONSTD (commands in question are only
   implemented for the x86 architecture)
 * Patch by Sangmoon Kim, 23 Sep 2003:
   fix pll_pci_to_mem_multiplier table for MPC8245
 * Patch by Anders Larsen, 22 Sep 2003:
   enable timed autoboot on PXA
 * Patch by David Müller, 22 Sep 2003:
   - add $(CFLAGS) to "-print-libgcc-filename" so compiler driver
     returns correct libgcc file path
   - "latency" reduction of busy-loop waiting to improve "U-Boot" boot
     time on s3c24x0 systems
 * Patch by Jon Diekema, 19 Sep 2003:
   - Add CFG_FAULT_ECHO_LINK_DOWN option to echo the inverted Ethernet
     link state to the fault LED.
   - In NetLoop, make the Fault LED reflect the link status.  The link
     status gets updated on entry, and on timeouts.
 * Patch by Anders Larsen, 18 Sep 2003:
   allow mkimage to build and run on Cygwin-hosted systems
 * Patch by Frank Müller, 18 Sep 2003:
   use bi_intfreq instead of bi_busfreq to compute fec_mii_speed in
   cpu/mpc8xx/fec.c
 * Patch by Pantelis Antoniou, 16 Sep 2003:
   add tool to compute fileds in the PLPRCR register for MPC86x
 * Use IH_TYPE_FILESYSTEM for TRAB "disk" images.
 * Fix build problems under FreeBSD
 * Add generic filesystem image type
 * Make fatload set filesize environment variable
 * enable basic / medium / high-end configurations for PPChameleonEVB
   board; fix NAND code
 * enable TFTP client code to specify to the server the desired
   timeout value (see RFC-2349)
 * Improve SDRAM setup for TRAB board
 * Suppress all output with splashscreen configured only if "splashimage"
   is set
 * Fix problems with I2C support for mpc5200
 * Adapt TRAB configuration and auto_update to new memory layout
 * Add configuration for wtk board
 * Add support for the Sharp LQ065T9DR51U LCD display
 * Patch by Rune Torgersen, 17 Sep 2003:
   - Fixes for MPC8266 default config
   - Allow eth_loopback_test() on 8260 to use a subset of the FCC's
 * Patches by Jon Diekema, 17 Sep 2003:
   - update README (SHOW_BOOT_PROGRESS values for cmd_nand.c and
     env_common.c)
   - sbc8260 tweaks
   - adjust "help" output
 * Patches by Anders Larsen, 17 Sep 2003:
   - fix spelling errors
   - set GD_FLG_DEVINIT flag only after device function pointers
     are valid
   - Allow CFG_ALT_MEMTEST on systems where address zero isn't
     writeable
   - enable 3.rd UART (ST-UART) on PXA(XScale) CPUs
   - trigger watchdog while waiting in serial driver
 * Add auto-update code for TRAB board using USB memory sticks,
   support new configuration with more memory
 * disable MPC5200 bus pipelining as workaround for bus contention
 * Modify XLB arbiter priorities on MPC5200 so all devices use same
   priority; configure critical interrupts to be handled like external
   interrupts
 * Make IPB clock on MGT5100/MPC5200 configurable in board config file;
   go back to 66 MHz for stability
 * Patches by Jon Diekema, 15 Sep 2003:
   - add description for missing CFG_CMD_* entries in the README file
   - sacsng tweaks
 * Patch by Gleb Natapov, 14 Sep 2003:
   enable watchdog support for all MPC824x boards that have a watchdog
 * On MPC5200, restrict FEC to a maximum of 10 Mbps to work around the
   "Non-octet Aligned Frame" errors we see at 100 Mbps
 * Patch by Sharad Gupta, 14 Sep 2003:
   fix SPR numbers for upper BAT register ([ID]BAT[4-7][UL])
 * Patch by llandre, 11 Sep 2003:
   update configuration for PPChameleonEVB board
 * Patch by David Müller, 13 Sep 2003:
   various changes to VCMA9 board specific files
 * Add I2C support for MGT5100 / MPC5200
 * Patch by Rune Torgersen, 11 Sep 2003:
   Changed default memory option on MPC8266ADS to NOT be Page Based
   Interleave, since this doesn't work very well with the standard
   16MB DIMM
 * Patch by George G. Davis, 12 Sep 2003:
   fix Makefile settings for sk98 driver
 * Patch by Stefan Roese, 12 Sep 2003:
   - new boards added: DP405, HUB405, PLU405, VOH405
   - some esd boards updated
   - cpu/ppc4xx/sdram.c: disable memory controller before setting
     first values
   - cpu/ppc4xx/405_pci.c: set vendor id on PPC405EP systems
 * Patch by Martin Krause, 11 Sep 2003:
   add burn-in tests for TRAB board
 * Enable instruction cache on MPC5200 board
 * Patch by Denis Peter, 11 Sep 2003:
   - fix USB data pointer assignment for bulk only transfer.
   - prevent to display erased directories in FAT filesystem.
 * Change output format for NAND flash - make it look like for other
   memory, too
 ======================================================================
 Changes for U-Boot 0.4.8:
 ======================================================================
 * Add I2C and RTC support for RMU board
 * Patches by Denis Peter, 9 Sep 2003:
   add FAT support for IDE, SCSI and USB
 * Patches by Gleb Natapov, 2 Sep 2003:
   - cleanup of POST code for unsupported architectures
   - MPC824x locks way0 of data cache for use as initial RAM;
     this patch unlocks it after relocation to RAM and invalidates
     the locked entries.
 * Patch by Gleb Natapov, 30 Aug 2003:
   new I2C driver for mpc107 bridge. Now works from flash.
 * Patch by Dave Ellis, 11 Aug 2003:
   - JFFS2: fix typo in common/cmd_jffs2.c
   - JFFS2: fix CFG_JFFS2_SORT_FRAGMENTS option
   - JFFS2: remove node version 0 warning
   - JFFS2: accept JFFS2 PADDING nodes
   - SXNI855T: add AM29LV800 support
   - SXNI855T: move environment from EEPROM to flash
   - SXNI855T: boot from JFFS2 in NOR or NAND flash
 * Patch by Bill Hargen, 11 Aug 2003:
   fixes for I2C on MPC8240
   - fix i2c_write routine
   - fix iprobe command
   - eliminates use of global variables, plus dead code, cleanup.
 * Add support for USB Mass Storage Devices (BBB)
   (tested with USB memory sticks only)
 * Avoid flicker on TRAB's VFD
 * Add support for SK98xx driver
 * Add PCI support for SL8245 board
 * Support IceCube board configurations with 1 x AMD AM29LV065 (8 MB)
   or 1 x AM29LV652 (two LV065 in one chip = 16 MB);
   Run IPB at 133 Mhz; adjust the MII clock frequency accordingly
 * Set BRG_CLK on PM825/826 to 64MHz (VCO_OUT / 4, instead of 16  MHz)
   to allow for more accurate baudrate settings
   (error now 0.7% at 115 kbps, instead of 3.5% before)
 * Patch by Andreas Mohr, 4 Sep 2003:
   Fix a lot of spelling errors
 * Add support for PPChameleon Eval Board
 * Add support for P3G4 board
 * Fix problem with MGT5100 FEC driver: add "early" MAC address
   initialization
 * Patch by Yuli Barcohen, 7 Aug 2003:
   check BCSR to detect if the board is configured in PCI mode
 ======================================================================
 Changes for U-Boot 0.4.7:
 ======================================================================
 * Patch by Raghu Krishnaprasad, 7 Aug 2003:
   add support for Adder II MPC852T module
 * Patch by George G. Davis, 19 Aug 2003:
   fix TI Innovator/OMAP1510 pin configs
 * Patches by Kshitij, 18 Aug 2003
   - add support for arm926ejs cpu core
   - add support for TI OMAP 1610 Innovator Board
 * Patch by Yuli Barcohen, 14 Aug 2003:
   add support for bzip2 uncompression
 * Add GCC library to examples/Makefile so GCC utility functions will
   be resolved, too
 * Add I2C and RTC support for RMU board using software I2C driver
   (because of better response to iprobe command); fix problem with
   "reset" command
 * Patch by Matthias Fuchs, 28 Aug 2003:
   Added CONFIG_BOOTP_DNS2 and CONFIG_BOOTP_SEND_HOSTNAME to
   CONFIG_BOOTP_MAKS (see README).
 * Fix ICU862 environment problem
 * Fix RAM size detection for RMU board
 * Implement "reset" for MGT5100/MPC5200 systems
 ======================================================================
 Changes for U-Boot 0.4.6:
 ======================================================================
 * Make Ethernet autonegotiation on INCA-IP work for all clock rates;
   allow selection of clock frequency as "make" target
 * Implement memory autosizing code for IceCube boards
 * Configure network port on INCA-IP for autonegotiation
 * Fix overflow problem in network timeout code
 * Patch by Richard Woodruff, 8 Aug 2003:
   Allow crc32 to be used at address 0x000 (crc32_no_comp, too).
 ======================================================================
 Changes for U-Boot 0.4.5:
 ======================================================================
 * Update for TQM board defaults:
   disable clocks_in_mhz, enable boot count limit
 * Removed tools/gdb from "make all" target.  Added make target "gdbtools"
   in toplevel directory instead.  Removed astest.c from tools/gdb because
   it is no longer relevant.
 * Fix PCI support for MPC5200 / IceCube Board
 * Map ISP1362 USB OTG controller for NSCU board
 * Patch by Brad Parker, 02 Aug 2003:
   fix sc520_cdp problems
 * Implement Boot Cycle Detection (Req. 2.3 of OSDL CGL Reqirements)
 * Allow erase command to cross flash bank boundaries
 * Patch by Scott McNutt, 21 Jul 2003:
   Add support for LynuxWorks Kernel Downloadable Images (KDIs).
   Both LynxOS and BlueCat linux KDIs are supported.
 * Patch by Richard Woodruff, 25 Jul 2003:
   use more reliable reset for OMAP/925T
 * Patch by Nye Liu, 25 Jul 2003:
   fix typo in mpc8xx.h
 * Patch by Richard Woodruff, 24 Jul 2003:
   Fixes for cmd_nand.c:
   - Fixed null dereferece which could result in incorrect ECC values.
   - Added support for devices with no Ready/Busy signal hooked up.
   - Added OMAP1510 read/write protect handling.
   - Fixed nand.h's ECCPOS. A conflict existed with POS5 and badblock
     for non-JFFS2.
   - Switched default ECC to be JFFS2.
 * Allow crc32 to be used at address 0x000
 * Provide consistent interface to standalone applications to access
   the 'global_data' structure
   Provide a doc/README.standalone more useful to users/developers.
 * Make IceCube MGT5100 FEC driver work
 * Implement new mechanism to export U-Boot's functions to standalone
   applications: instead of using (PPC-specific) system calls we now
   use a jump table; please see doc/README.standalone for details
 * Patch by Dave Westwood, 24 Jul 2003:
   added support for Unity OS (a proprietary OS)
 * Patch by Detlev Zundel, 23 Jul 2003:
   add "imls" command to print flash table of contents
 * Fix cold boot detection for log buffer reset
 * Return error for invalid length specifiers with "cp.X" etc.
 * Fix startup problem on MIPS
 * Allow for CONFIG_SPLASH_SCREEN even when no explicit
   bitmap support is configured
 * Patch by Bill Hargen, 18 Jul 2003:
   - fix endinaness problem in cpu/mpc824x/drivers/i2c/i2c1.c
 * Patch by Denis Peter, 18 Jul 2003:
   - fix memory configuration for MIP405T
   - fix printout of baudrate for "loadb <loadaddr> <baudrate>"
 * Cleanup of TQM82xx configurations; use "official" board types
   to make selection easier.
 * Patch by Martin Krause, 17 Jul 2003:
   add delay to get I2C working with "imm" command and s3c24x0_i2c.c
 * Patch by Richard Woodruff, 17 July 03:
   - Fixed bug in OMAP1510 baud rate divisor settings.
 * Patch by Nye Liu, 16 July 2003:
   MPC860FADS fixes:
   - add MPC86xADS support (uses MPC86xADS.h)
   - add 866P/T core support (also MPC859T/MPC859DSL/MPC852T)
     o PLPRCR changes
     o BRG changes (EXTAL/XTAL restricted to 10MHz)
     o don't trust gclk() software measurement by default, depend on
       CONFIG_8xx_GCLK_FREQ
   - add DRAM SIMM not installed detection
   - use more "correct" SDRAM initialization sequence
   - allow different SDRAM sizes (8xxADS has 8M)
   - default DER is 0
   - remove unused MAMR defines from FADS860T.h (all done in fads.c)
   - rename MAMR/MBMR defines to be more consistent. Should eventually
     be merged into MxMR to better reflect the PowerQUICC datasheet.
 * Patch by Yuli Barcohen, 16 Jul 2003:
   support new Motorola PQ2FADS-ZU evaluation board which replaced
   MPC8260ADS and MPC8266ADS
 ======================================================================
 Changes for U-Boot 0.4.4:
 ======================================================================
 * Add support for IceCube board (with MGT5100 and MPC5200 CPUs)
 * Add support for MGT5100 and MPC5200 processors
 * Patch by Lutz Dennig, 15 Jul 2003:
   update for R360MPI board
 ======================================================================
 Changes for U-Boot 0.4.3:
 ======================================================================
 * Patches by Kshitij, 04 Jul 2003
   - added support for arm925t cpu core
   - added support for TI OMAP 1510 Innovator Board
 * Patches by Martin Krause, 14 Jul 2003:
   - add I2C support for s3c2400 systems (trab board)
   - (re-) add "ping" to command table
 * Fix handling of "slow" POST routines
 * Patches by Yuli Barcohen, 13 Jul 2003:
   - Correct flash and JFFS2 support for MPC8260ADS
   - fix PVR values and clock generation for PowerQUICC II family
     (8270/8275/8280)
 * Patch by Bernhard Kuhn, 08 Jul 2003:
   - add support for M68K targets
 * Patch by Ken Chou, 3 Jul:
   - Fix PCI config table for A3000
   - Fix iobase for natsemi.c
     (PCI_BASE_ADDRESS_0 is the IO base register for DP83815)
 * Allow to enable "slow" POST routines by key press on power-on
 * Fix temperature dependend switching of LCD backlight on LWMON
 * Tweak output format for LWMON
 * Patch by Stefan Roese, 11 Jul 2003:
   - Fix bug in CONFIG_VERSION_VARIABLE.
   - AR405 config updated.
   - OCRTC/ORSG: bsp command added.
   - ASH405 bsp update.
 ======================================================================
 Changes for U-Boot 0.4.2:
 ======================================================================
 * Add support for NSCU board
 * Add support for TQM823M, TQM850M, TQM855M and TQM860M modules
 * Add support for Am29LV160ML, Am29LV320ML, and Am29LV640ML
   mirror bit flash on TQM8xxM modules
 * Patch by Kenneth Johansson, 30 Jun 2003:
   get rid of MK_CMD_ENTRY macro; update doc/README.command
 * Patch by Seb James, 30 Jun 2003:
   Improve documentation of I2C configuration in README
 * Fix problems with previous log buffer "fixes"
 * Fix minor help text issues
 * "log append" did not append a newline
 ======================================================================
 Changes for U-Boot 0.4.1:
 ======================================================================
 * Fix some missing commands, cleanup header files
   (autoscript, bmp, bsp, fat, mmc, nand, portio, ...)
 * Rewrite command lookup and help command (fix problems with bubble
   sort when sorting command name list). Minor cleanup here and there.
 * Merge from "stable branch", tag LABEL_2003_06_28_1800-stable:
   - Allow to call sysmon function interactively
   - PIC on LWMON board needs delay after power-on
   - Add missing RSR definitions for MPC8xx
   - Improve log buffer handling: guarantee clean reset after power-on
   - Add support for EXBITGEN board (aka "genie")
   - Add support for SL8245 board
 * Code cleanup:
   - remove trailing white space, trailing empty lines, C++ comments, etc.
   - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)
 * Patches by Kenneth Johansson, 25 Jun 2003:
   - major rework of command structure
     (work done mostly by Michal Cendrowski and Joakim Kristiansen)
 ======================================================================
 Changes for U-Boot 0.4.0:
 ======================================================================
 * Patches by Robert Schwebel, 26 Jun 2003:
   - csb226 configuration updated
   - credits for logodl port updated
   - innokom configuration updated
   - logodl tree update, still with coding style inconsistencies
   - added OCM for ppc405 warning to README
 * Patch by Pantelis Antoniou, 25 Jun 2003:
   update NetVia with V2 board support
 * Header file cleanup for ARM
 * Patch by Murray Jensen, 24 Jun 2003:
   - make sure to use only U-boot provided header files
   - fix problems with ".rodata.str1.4" section as used by GCC-3.x
 * Patch by Stefan Roese, 24 Jun 2003:
   - Update esd ASH405 board files.
   - Update esd DASA_SIM config file.
   - Add ping command to some esd boards.
 * Patch by Yuli Barcohen, 23 Jun 2003:
   Update for MPC8260ADS board
 * Patch by Murray Jensen, 23 Jun 2003:
   - cleanup of GCC 3.x compiler warnings
 * Patch by Rune Torgersen, 4 Jun 2003:
   add large memory support for MPC8266ADS board
 * Patch by Richard Woodruff, 19 June 03:
   - Enabled standard u-boot device abstraction for ARM
   - Enabled console device for ARM
   - Initilized bi_baudrate for ARM
 * Patch by Bill Hargen, 23 Apr 2003:
   fix byte order for 824x I2C addresses (write op)
 * Patch by Murray Jensen, 20 Jun 2003:
   - hymod update
   - cleanup (especially for gcc-3.x compilers)
 * Patch by Tom Guilliams, 20 Jun 2003:
   added CONFIG_750FX support for IBM 750FX processors
 * Patch by Devin Crumb, 02 Apr 2003:
   Fix clock divider rounding problem in drivers/serial.c
 * Patch by Richard Woodruff, 19 June 03:
   - Fixed smc91c111 driver to sync with the u-boot environment
     (driver/smc91c111.c).
   - Added eth_init error return check in NetLoop (net/net.c).
 * Patch by Ken Chou, 19 June 2003:
   Added support for A3000 SBC board (Artis Microsystems Inc.)
 * Patches by Murray Jensen, 17 Jun 2003:
   - Hymod board database mods: add "who" field and new xilinx chip types
   - provide new "init_cmd_timeout()" function so code external to
     "common/main.c" can use the "reset_cmd_timeout()" function before
     entering the main loop
   - add DTT support for adm1021 (new file dtt/adm1021.c; config
     slightly different. see include/configs/hymod.h for an example
     (requires CONFIG_DTT_ADM1021, CONFIG_DTT_SENSORS, and
     CFG_DTT_ADM1021 defined)
   - add new "eeprom_probe()" function which has similar args and
     behaves in a similar way to "eeprom_read()" etc.
   - add 8260 FCC ethernet loopback code (new "eth_loopback_test()"
     function which is enabled by defining CONFIG_ETHER_LOOPBACK_TEST)
   - gdbtools copyright update
   - ensure that set_msr() executes the "sync" and "isync" instructions
     after the "mtmsr" instruction in cpu/mpc8260/interrupts.c
   - 8260 I/O ports fix: Open Drain should be set last when configuring
   - add SIU IRQ defines for 8260
   - allow LDSCRIPT override and OBJCFLAGS initialization: change to
     config.mk to allow board configurations to override the GNU
     linker script, selected via the LDSCRIPT, make variable, and to
     give an initial value to the OBJCFLAGS make variable
   - 8260 i2c enhancement:
     o correctly extends the timeout depending on the size of all
       queued messages for both transmit and receive
     o will not continue with receive if transmit times out
     o ensures that the error callback is done for all queued tx
       and rx messages
     o correctly detects both tx and rx timeouts, only delivers one to
       the callback, and does not overwrite an earlier error
     o logic in i2c_probe now correct
   - add "vprintf()" function so that "panic()" function can be
     technically correct
   - many Hymod board changes
 * Patches by Robert Schwebel, 14 Jun 2003:
   - add support for Logotronic DL datalogger board
   - cleanup serial line after kermit binary download
   - add debugX macro (debug level support)
   - update mach-types.h to latest arm.linux.org.uk master list.
 * Patches by David Müller, 12 Jun 2003:
   - rewrite of the S3C24X0 register definitions stuff
   - "driver" for the built-in S3C24X0 RTC
 * Patches by Yuli Barcohen, 12 Jun 2003:
   - Add MII support and Ethernet PHY initialization for MPC8260ADS board
   - Fix incorrect SIUMCR initialisation caused by wrong Hard Reset
     configuration word supplied by FPGA on some MPC8260ADS boards
 * Patch by Pantelis Antoniou, 10 Jun 2003:
   Unify status LED interface
 * Add support for DS12887 RTC; add RTC support for ATC board
 * Patch by Nicolas Lacressonniere, 11 Jun 2003:
   Modifications for Atmel AT91RM9200DK ARM920T based development kit
   - Add Atmel DataFlash support for reading and writing.
   - Add possibility to boot a Linux from DataFlash with BOOTM command.
   - Add Flash detection on Atmel AT91RM9200DK
     (between Atmel AT49BV1614 and AT49BV1614A flashes)
   - Replace old Ethernet PHY layer functions
   - Change link address
 * Patch by Frank Smith, 9 Jun 2003:
   use CRIT_EXCEPTION for machine check on 4xx
 * Patch by Detlev Zundel, 13 Jun 2003:
   added implementation of the "carinfo" command in cmd_immap.c
 * Fix CONFIG_NET_MULTI support in include/net.h
 * Patches by Kyle Harris, 13 Mar 2003:
   - Add FAT partition support
   - Add command support for FAT
   - Add command support for MMC
   ----
   - Add Intel PXA support for video
   - Add Intel PXA support for MMC
   ----
   - Enable MMC and FAT for lubbock board
   - Other misc changes for lubbock board
 * Patch by Robert Schwebel, April 02, 2003:
   fix for SMSC91111 driver
 * Patch by Vladimir Gurevich, 04 Jun 2003:
   make ppc405 ethernet driver compatible with CONFIG_NET_MULTI option
 * Patch by Stefan Roese, 05 Jun 2003:
   - PPC4xx: Fix bug for initial stack in data cache as pointed out by
     Thomas Schaefer (tschaefer@giga-stream.de). Now inital stack in
     data cache can be used even if the chip select is in use.
   - CFG_RX_ETH_BUFFER added to set the ethernet receive buffer count
     (see README for further description).
   - Changed config files of CONFIG_EEPRO100 boards to use the
     CFG_RX_ETH_BUFFER define.
 * Add support for RMU board
 * Add support for TQM862L at 100/50 MHz
 * Patch by Pantelis Antoniou, 02 Jun 2003:
   major reconstruction of networking code;
   add "ping" support (outgoing only!)
 * Patch by Denis Peter, 04 June 2003:
   add support for the MIP405T board
 * Patches by Udi Finkelstein, 2 June 2003:
   - Added support for custom keyboards, initialized by defining a
     board-specific drv_keyboard_init as well as defining CONFIG_KEYBOARD .
   - Added support for the RBC823 board.
   - cpu/mpc8xx/lcd.c now automatically calculates the
     Horizontal Pixel Count field.
 * Fix alignment problem in BOOTP (dhcp_leasetime option)
   [pointed out by Nicolas Lacressonnière, 2 Jun 2003]
 * Patch by Mark Rakes, 14 May 2003:
   add support for Intel e1000 gig cards.
 * Patch by Nye Liu, 3 Jun 2003:
   fix critical typo in MAMR definition (include/mpc8xx.h)
 * Fix requirement to align U-Boot image on 16 kB boundaries on PPC.
 * Patch by Klaus Heydeck, 2 Jun 2003
   Minor changes for KUP4K configuration
 * Patch by Marc Singer, 29 May 2003:
   Fixed rarp boot method for IA32 and other little-endian CPUs.
 * Patch by Marc Singer, 28 May 2003:
   Added port I/O commands.
 * Patch by Matthew McClintock, 28 May 2003
   - cpu/mpc824x/start.S: fix relocation code when booting from RAM
   - minor patches for utx8245
 * Patch by Daniel Engström, 28 May 2003:
   x86 update
 * Patch by Dave Ellis, 9 May 2003 + 27 May 2003:
   add nand flash support to SXNI855T configuration
   fix/extend nand flash support:
   - fix 'nand erase' command so does not erase bad blocks
   - fix 'nand write' command so does not write to bad blocks
   - fix nand_probe() so handles no flash detected properly
   - add doc/README.nand
   - add .jffs2 and .oob options to nand read/write
   - add 'nand bad' command to list bad blocks
   - add 'clean' option to 'nand erase' to write JFFS2 clean markers
   - make NAND read/write faster
 * Patch by Rune Torgersen, 23 May 2003:
   Update for MPC8266ADS board
 * Get (mostly) rid of CFG_MONITOR_LEN definition; compute real length
   instead CFG_MONITOR_LEN is now only used to determine  _at_compile_
   _time_  (!) if the environment is embedded within the U-Boot image,
   or in a separate flash sector.
 * Cleanup CFG_DER #defines in config files (wd maintained only)
 * Fix data abort exception handling for arm920t CPU
 * Fix alignment problems with flash driver for TRAB board
 * Patch by Donald White, 21 May 2003:
   fix calculation of base address in pci_hose_config_device()
 * Fix bug in command line parsing: "cmd1;cmd2" is supposed to always
   execute "cmd2", even if "cmd1" fails. Note that this is different
   to "run var1 var2" where the contents of "var2" will NOT be
   executed when a command in "var1" fails.
 * Add zero-copy ramdisk support (requires corresponding kernel support!)
 * Patch by Kyle Harris, 20 May 2003:
   In preparation for an ixp port, rename cpu/xscale and arch-xscale
   into cpu/pxa and arch-pxa.
 * Patch by Stefan Roese, 23 May 2003:
   - IBM PPC405EP port added.
   - CONFIG_UART1_CONSOLE added. If defined internal UART1 (and not
     UART0) is used as default U-Boot console. PPC4xx only!
   - esd ASH405 board added (PPC405EP based).
   - BUBINGA405EP board added (PPC405EP based - IBM Eval Board).
   - esd CPCI405AB board added.
   - esd PMC405 board added.
   - Update of some esd boards.
 * Patch by Denis Peter, 19 Mai 2003:
   add support for the MIP405-3 board
 * Patch by Dave Ellis, 22 May 2003:
   Fix problem with only partially cleared .bss segment
 * Patch by Rune Torgersen, 12 May 2003:
   get PCI to work on a MPC8266ADS board; incorporate change to
   cpu/mpc8260/pci.c to enable overrides of PCI memory parameters
 * Patch by Nye Liu, 1 May 2003:
   minor patches for the FADS8xx
 * Patch by Thomas Schäfer, 28 Apr 2003:
   Fix SPD handling for 256 ECC DIMM on Walnut
 * Add support for arbitrary bitmaps for TRAB's  VFD command;
   allow to pass boot bitmap addresses in environment variables;
   allow for zero boot delay
 * Patch by Christian Geißinger, 19 May 2002:
   On TRAB: wait until the dummy byte has been completely sent
 * Patch by David Updegraff, 22 Apr 2003:
   update for CrayL1 board
 * Patch by Pantelis Antoniou, 21 Apr 2003:
   add boot support for ARTOS (a proprietary OS)
 * Patch by Steven Scholz, 11 Apr 2003:
   Add support for RTC DS1338
 * Patch by Rod Boyce, 24 Jan 2003:
   Fix counting of extended partitions in diskboot command
 * Patch by Christophe Lindheimer, 20 May 2003:
   allow the use of CFG_LOADS when CFG_NO_FLASH is set
 * Fix SDRAM timing on Purple board
 * Add support for CompactFlash on ATC board
   (includes support for Intel 82365 and compatible PC Card controllers,
   and Yenta-compatible PCI-to-CardBus controllers)
 * Patch by Mathijs Haarman, 08 May 2003:
   Add lan91c96 driver (tested on Lubbock and custom PXA250 board only)
 * Fix problem with usage of "true" (undefined in current versions of bfd.h)
 * Add support for Promess ATC board
 * Patch by Keith Outwater, 28 Apr 2003:
   - Miscellaneous corrections and additions to GEN860T board specific code.
   - Added GEN860_SC variant to GEN860T.
   - Miscellaneous corrections to GEN860T documentation.
   - Correct duplicate entry in U-Boot CREDITS file.
   - Add GEN860T_SC entry in MAINTAINERS file.
   - Update CREDITS file with GEN860T_SC info.
 * Update Smiths Aerospace addresses in MAINTAINERS file
 * Fix error handling in hush's version of "run" command
 * LWMON extensions:
   - Splashscreen support
   - modem support
   - sysmon support
   - temperature dependend enabling of LCD
 * Allow booting from old "PPCBoot" disk partitions
 * Add support for TQM8255 Board / MPC8255 CPU
 ======================================================================
 Changes for U-Boot 0.3.1:
 ======================================================================
 * Make sure Block Lock Bits get cleared in R360MPI flash driver
 * MPC823 LCD driver: Fill color map backwards, to allow for steady
   display when Linux takes over
 * Patch by Erwin Rol, 27 Feb 2003:
   Add support for RTEMS (this time for real).
 * Add support for "bmp info" and "bmp display" commands to load
   bitmap images; this can be used (for example in a "preboot"
   command) to display a splash screen very quickly after poweron.
 * Add support for 133 MHz clock on INCA-IP board
 * Patch by Lutz Dennig, 10 Apr 2003:
   Update for R360MPI board
 * Add new meaning to "autostart" environment variable:
   If set to "no", a standalone image passed to the
   "bootm" command will be copied to the load address
   (and eventually uncompressed), but NOT be started.
   This can be used to load and uncompress arbitrary
   data.
 * Patch by Stefan Roese, 10 Apr 2003:
   Changed DHCP client to use IP address from server option field #54
   from the OFFER packet in the server option field #54 in the REQUEST
   packet. This fixes a problem using a Windows 2000 DHCP server,
   where the DHCP-server is not the TFTP-server.
 * Set max brightness for MN11236 displays on TRAB board
 * Add support for TQM862L modules
 ======================================================================
 Changes for U-Boot 0.3.0:
 ======================================================================
 * Patch by Arun Dharankar, 4 Apr 2003:
   Add IDMA example code (tested on 8260 only)
 * Add support for Purple Board (MIPS64 5Kc)
 * Add support for MIPS64 5Kc CPUs
 * Fix missing setting of "loadaddr" and "bootfile" on ARM and MIPS
 * Patch by Denis Peter, 04 Apr 2003:
   - update MIP405-4 board
 * Patch by Stefan Roese, 4 Apr 2003:
   - U-Boot version environment variable "ver" added
     (CONFIG_VERSION_VARIABLE).
   - Changed PPC405GPr version from A to B.
   - Changed CPCI405 to use CTS instead of DSR on PPC405 UART1.
 * Patches by Denis Peter, 03 April 2003:
   - fix PCI IRQs on MPL boards
   - fix two more un-relocated pointer problems
 * Fix behaviour of "run" command:
   - print error message iv variable does not exist
   - terminate processing of arguments in case of error
 * Patches by Peter Figuli, 10 Mar 2003
   - Add support for BTUART on PXA platform
   - Add support for WEP EP250 (PXA) board
 * Fix flash problems on INCA-IP; add tool to allow bruning images  to
   flash using a BDI2000
 * Implement fix for I2C Edge Conditions problem for all boards that
   use the bit-banging driver (common/soft_i2c.c)
 * Patch by Martin Winistoerfer, 23 Mar 2003
   - Add port to MPC555/556 microcontrollers
   - Add support for cmi customer board with
     Intel 28F128J3A, 28F320J3A or 28F640J3A flash.
 * Patch by Rick Bronson, 28 Mar 2003:
   - fix common/cmd_nand.c
 * Patch by Arun Dharankar, 24 Mar 2003:
   - add threads / scheduler example code
 * Add patches by Robert Schwebel, 31 Mar 2003:
   - add ctrl-c support for kermit download
   - align bdinfo output on ARM
   - csb226 board: bring in sync with innokom/memsetup.S
   - csb226 board: fix MDREFR handling
   - misc doc fixes / extensions
   - innokom board: cleanup, MDREFR fix in memsetup.S, config update
   - add BOOT_PROGRESS to armlinux.c
 * Add CPU ID, version, and clock speed for INCA-IP
 * Patches by Dave Ellis, 18 Mar 2003 for SXNI855T board:
   - fix SRAM and SDRAM memory sizing
   - add status LED support
   - add MAC address for second (SCC1) ethernet port
 * Update default environment for TQM8260 board
 * Patch by Rick Bronson, 16 Mar 2003:
   - Add NAND flash support for reading, writing, and erasing NAND
     flash (certain forms of which are called SmartMedia).
   - Add support for Atmel AT91RM9200DK ARM920T based development kit.
 * Patches by Robert Schwebel, 19 Mar 2003:
   - use arm-linux-gcc as default compiler for ARM
   - fix i2c fixup code
   - fix missing baudrate setting
   - added $loadaddr / CFG_LOAD_ADDR support to loadb
   - moved "ignoring trailing characters" _before_ u-boot wants to
     print out diagnostics messages; removes bogus characters at the
     end of transmission
 * Patch by John Zhan, 18 Mar 2003:
   Add support for SinoVee Microsystems SC8xx boards
 * Patch by Rolf Offermanns, 21 Mar 2003:
   ported the dnp1110 related changes from the current armboot cvs to
   current u-boot cvs. smc91111 does not work. problem marked in
   smc91111.c, grep for "FIXME".
 * Patch by Brian Auld, 25 Mar 2003:
   Add support for STM flash chips on ebony board
 * Add PCI support for MPC8250 Boards (PM825 module)
 * Patch by Stefan Roese, 25 Mar 2003:
   - PCI405 update.
 * Patch by Stefan Roese, 20 Mar 2003:
   - CPCI4052 update (support for revision 3).
   - Set edge conditioning circuitry on PPC405GPr for compatibility
     to existing PPC405GP designs.
   - Clip udiv to 5 bits on PPC405 (serial.c).
 * Extend INCAIP board support:
   - add automatic RAM size detection
   - add "bdinfo" command
   - pass flash address and size to Linux kernel
   - switch to 150 MHz clock
 * Avoid flicker on the TRAB's VFD by synchronizing the enable with
   the HSYNC/VSYNC. Requires new CPLD code (Version 101 for Rev. 100
   boards, version 153 for Rev. 200 boards).
 * Patch by Vladimir Gurevich, 12 Mar 2003:
   Fix relocation problem of statically initialized string pointers
   in common/cmd_pci.c
 * Patch by Kai-Uwe Blöm, 12 Mar 2003:
   Cleanup & bug fixes for JFFS2 code:
   - the memory mangement was broken. It caused havoc on malloc by
     writing beyond the block boundaries.
   - the length calculation for files was wrong, sometimes resulting
     in short file reads.
   - data copying now optionally takes fragment version numbers into
     account, to avoid copying from older data.
   See doc/README.JFFS2 for details.
 * Patch by Josef Wagner, 12 Mar 2003:
   - 16/32 MB and 50/80 MHz support with auto-detection for IP860
   - ETH05 and BEDBUG support for CU824
   - added support for MicroSys CPC45
   - new BOOTROM/FLASH0 and DOC base for PM826
 * Patch by Robert Schwebel, 12 Mar 2003:
   Fix the chpart command on innokom board
 * Name cleanup:
   mv include/asm-i386/ppcboot-i386.h include/asm-i386/u-boot-i386.h
   s/PPCBoot/U-Boot/ in some files
   s/pImage/uImage/  in some files
 * Patch by Detlev Zundel, 15 Jan 2003:
   Fix '' command line quoting
 * Patch by The LEOX team, 19 Jan 2003:
   - add support for the ELPT860 board
   - add support for Dallas ds164x RTC
 * Patches by David Müller, 31 Jan 2003:
   - minimal setup for CardBus bridges
   - add EEPROM read/write support in the CS8900 driver
   - add support for the builtin I2C controller in the Samsung s3c24x0 chips
   - add support for MPL's VCMA9 (Samsung s3c2410 based) board
 * Patch by Steven Scholz, 04 Feb 2003:
   add support for RTC DS1307
 * Patch by Reinhard Meyer, 5 Feb 2003:
   fix PLPRCR/SCCR init sequence on 8xx to allow for
   changes of EBDF by software
 * Patch by Vladimir Gurevich, 07 Feb 2003:
   "API-compatibility patch" for 4xx I2C driver
 * TRAB fixes / extensions:
   - Restore VFD brightness as saved in environment
   - add support for Fujitsu flashes
   - make sure both buzzers are turned off (drive low level)
 * Patches by Robert Schwebel, 06 Mar 2003:
   - fix bug in BOOTP code (must use NetCopyIP)
   - update of CSB226 port
   - clear BSS segment on XScale
   - added support for i2c_init_board() function
   - update to the Innokom plattform
 * Extend support for redundand environments for configurations where
   environment size < sector size
 * Patch by Rune Torgersen, 13 Feb 2003:
   Add support for Motorola MPC8266ADS board
 * Patch by Kyle Harris, 19 Feb 2003:
   patches for the Intel lubbock board:
   memsetup.S - general cleanup (based on Robert's csb226 code)
   flash.c - overhaul, actually works now
   lubbock.c - fix init funcs to return proper value
 * Patch by Kenneth Johansson, 26 Feb 2003:
   - Fixed off by one in RFTA calculation.
   - No need to abort when LDF is lower than we can program it's only
     minimum timing so clamp it to what we can do.
   - Takes function pointer to function for reading the spd_nvram. Usefull
     for faking data or hardcode a module without the nvram.
   - fix other user for above change
   - fix some comments.
 * Patches by Brian Waite, 26 Feb 2003:
   - fix port for evb64260 board
   - fix PCI for evb64260 board
   - fix PCI scan
 * Patch by Reinhard Meyer, 1 Mar 2003:
   Add support for EMK TOP860 Module
 * Patch by Yuli Barcohen, 02 Mar 2003:
   Add SPD EEPROM support for MPC8260ADS board
 * Patch by Robert Schwebel, 21 Jan 2003:
   - Add support for Innokom board
   - Don't complain if "install" fails
   - README cleanup (remove duplicated lines)
   - Update PXA header files
 * Add documentation for existing POST code (doc/README.POST)
 * Patch by Laudney Ren, 15 Jan 2003:
   Fix handling of redundand environment in "tools/envcrc.c"
 * Patch by Detlev Zundel, 28 Feb 2003:
   Add bedbug support for 824x systems
 * Add support for 16 MB flash configuration of TRAB board
 * Patch by Erwin Rol, 27 Feb 2003:
   Add support for RTEMS
 * Add image information to README
 * Patch by Stefan Roese, 18 Feb 2003:
   CPCIISER4 configuration updated.
 * Patch by Stefan Roese, 17 Feb 2003:
   Fixed bug in ext. serial clock setup on PPC405 (since PPC440 port).
 * Patch by Stefan Roese, 13 Feb 2003:
   Add "pcidelay" environment variable (in ms, enabled via
   CONFIG_PCI_BOOTDELAY).
   PCI spec 2.2 defines, that a pci target has 2^25 pci clocks after
   RST# to respond to configuration cycles (33MHz -> 1s).
 * Fix dual PCMCIA slot support (when running with just one
   slot populated)
 * Add VFD type detection to trab board
 * extend drivers/cs8900.c driver to synchronize  ethaddr  environment
   variable with value in the EEPROM
 * Patch by Stefan Roese, 10 Feb 2003:
   Add support for 4MB and 128MB onboard SDRAM (cpu/ppc4xx/sdram.c)
 * Add support for MIPS32 4Kc CPUs
 * Add support for INCA-IP Board
 ======================================================================
 Changes for U-Boot 0.2.2:
 ======================================================================
 * Add dual ethernet support on PM826
 * Add support for LXT971 PHY on PM826
 * Patch by Tord Andersson, 16 Jan 2003:
   Fix flash sector count for TQM8xxL
 * Fix I2C EEPROM problem on ICU862 board (would only write the first
   16 bytes out of each 32 byte block)
 ======================================================================
 Changes for U-Boot 0.2.1:
 ======================================================================
 * Add support for V37 board
   (patch by Jón Benediktsson, 11 Dec 2002)
 * Update baudrate in bd_info when it gets changed
 * Add watchdog trigger points while waiting for serial port
   (so far only 8xx -- needed on LWMON with 100ms watchdog)
 * Improve command line tool to access the U-Boot's environment
   (figuration of the utility, using a config file)
 * Add single quote support for (old) command line parser
 * Switch LWMON board default config from FRAM to EEPROM;
   in POST, EEPROM shows up on 8 addresses
 ======================================================================
 Changes for U-Boot 0.2.0:
 ======================================================================
 * Use 1-byte-read instead of -write for iprobe() function
   Add i2c commands to PM826 config
 * extend I2C POST code: check for list on known addresses
 * Improve log buffer code; use "loglevel" to decide which messages
   to log on the console, too (like in Linux); get rid of "logstart"
 * Add command line tool to access the U-Boot's environment
   (board-specific for TRAB now, to be fixed later)
 * Patch by Hans-Joerg Frieden, 06 Dec 2002
   Fix misc problems with AmigaOne support
 * Patch by Chris Hallinan, 3 Dec 2002:
   minor cleanup to the MPC8245 EPIC driver
 * Patch by Pierre Aubert , 28 Nov 2002
   Add support for external (SIU) interrupts on MPC8xx
 * Patch by Pierre Aubert , 28 Nov 2002
   Fix nested syscalls bug in standalone applications
 * Patch by David Müller, 27 Nov 2002:
   fix output of "pciinfo" command for CardBus bridge devices.
 * Fix bug in TQM8260 board detection - boards got stuck when board ID
   was not readable
 * Add LED indication for IDE activity on KUP4K board
 * Fix startup problems with VFD display on TRAB
 * Patch by Pierre Aubert, 20 Nov 2002
   Add driver for Epson SED13806 graphic controller.
   Add support for BMP logos in cfb_console driver.
 * Added support for both PCMCIA slots (at the same time!) on MPC8xx
 * Patch by Rod Boyce, 21 Nov 2002:
   fix PCMCIA on MBX8xx board
 * Patch by Pierre Aubert , 21 Nov 2002
   Add CFG_CPM_POST_WORD_ADDR to make the offset of the
   bootmode word in DPRAM configurable
 * Patch by Daniel Engström, 18 Nov 2002:
   Fixes for x86 port (mostly strings issues)
 * Patch by Ken Chou, 18 Nov 2002:
   Fix for natsemi NIC cards (DP83815)
 * Patch by Pierre Aubert, 19 Nov 2002:
   fix a bug for the MII configuration, and some warnings
 * Patch by Thomas Frieden, 13 Nov 2002:
   Add code for AmigaOne board
   (preliminary merge to U-Boot, still WIP)
 * Patch by Jon Diekema, 12 Nov 2002:
   - Adding URL for IEEE OUI lookup
   - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED
     being defined.
   - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and
     root-on-nfs macros are designed to switch how the default boot
     method gets defined.
 * Patch by Daniel Engström, 13 Nov 2002:
   Add support for i386 architecture and AMD SC520 board
 * Patch by Pierre Aubert, 12 Nov 2002:
   Add support for DOS filesystem and booting from DOS floppy disk
 * Patch by Jim Sandoz, 07 Nov 2002:
   Increase number of network RX buffers (PKTBUFSRX in
   "include/net.h") for EEPRO100 based boards (especially SP8240)
   which showed "Receiver is not ready" errors when U-Boot was
   processing the receive buffers slower than the network controller
   was filling them.
 * Patch by Andreas Oberritter, 09 Nov 2002:
   Change behaviour of NetLoop(): return -1 for errors, filesize
   otherwise; return code 0 is valid an means no file loaded - in this
   case the environment still gets updated!
 * Patches by Jon Diekema, 9 Nov 2002:
   - improve ADC/DAC clocking on the SACSng board to align
     the failing edges of LRCLK and SCLK
   - sbc8260 configuration tweaks
   - add status LED support for 82xx systems
   - wire sspi/sspo commands into command handler; improved error
     handlering
   - add timestamp support and alternate memory test to the
     SACSng configuration
 * Patch by Vince Husovsky, 7 Nov 2002:
   Add "-n" to linker options to get rid of "Not enough room for
   program headers" problem
 * Patch by David Müller, 05 Nov 2002
   Rename CONFIG_PLL_INPUT_FREQ to CONFIG_SYS_CLK_FREQ
   so we can use an already existing name
 * Patch by Pierre Aubert, 05 Nov 2002
   Hardware relatied improvments in FDC boot code
 * Patch by Holger Schurig, 5 Nov 2002:
   Make the PXA really change it's frequency
 * Patch by Pierre Aubert, 05 Nov 2002
   Add support for slave serial Spartan 2 FPGAs
 * Fix uninitialized memory (MAC  address)  in  8xx  SCC/FEC  ethernet
   drivers
 * Add support for log buffer which can be passed to Linux kernel's
   syslog mechanism; used especially for POST results.
 * Patch by Klaus Heydeck, 31 Oct 2002:
   Add initial support for kup4k board
 * Patch by Robert Schwebel, 04 Nov 2002:
   - use watchdog to reset PXA250 systems
   - added progress callbacks to (some of the) ARM code
   - update for Cogent CSB226 board
 * Add support for FPS860 board
 * Patch by Guillaume Alexandre,, 04 Nov 2002:
   Improve PCI access on 32-bits Compact PCI bus
 * Fix mdelay() on TRAB - this was still the debugging version with
   seconds instead of ms.
 * Patch by Robert Schwebel, 1 Nov 2002:
   XScale related cleanup (affects all ARM boards)
 * Cleanup of names and README.
 ======================================================================
 Notes for U-Boot 0.1.0:
 ======================================================================
 This is the initial version of "Das U-Boot", the Universal Boot Loader.
 It is based on version 2.0.0 (the "Halloween Release") of PPCBoot.
 For information about the history of the project please see the
 PPCBoot project page at http://sourceforge.net/projects/ppcboot
 ======================================================================

MAINTAINERS

Diff comments View file @ f901a83

 #########################################################################
 #									#
 # Regular Maintainers for U-Boot board support:				#
 #									#
 # For any board without permanent maintainer, please contact		#
 #	Wolfgang Denk <wd@denx.de>					#
 # and Cc: the <U-Boot-Users@lists.sourceforge.net> mailing lists.	#
 #									#
 # Note: lists sorted by Maintainer Name					#
 #########################################################################
 #########################################################################
 # PowerPC Systems:							#
 #									#
 # Maintainer Name, Email Address					#
 #	Board			CPU					#
 #########################################################################
 Greg Allen <gallen@arlut.utexas.edu>
 	UTX8245			MPC8245
 Pantelis Antoniou <panto@intracom.gr>
 	NETVIA			MPC8xx
 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
 	CPCI750			PPC750FX/GX
 Yuli Barcohen <yuli@arabellasw.com>
 	Adder			MPC87x/MPC852T
+	ep8248			MPC8248
 	ISPAN			MPC8260
 	MPC8260ADS		MPC826x/MPC827x/MPC8280
 	Rattler			MPC8248
 	ZPC1900			MPC8265
 Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
 	sacsng			MPC8260
 Rick Bronson <rick@efn.org>
 	AT91RM9200DK		at91rm9200
 Oliver Brown <obrown@adventnetworks.com>
 	gw8260			MPC8260
 Conn Clark <clark@esteem.com>
 	ESTEEM192E		MPC8xx
 Kári Davíðsson <kd@flaga.is>
 	FLAGADM			MPC823
 Torsten Demke <torsten.demke@fci.com>
 	eXalion			MPC824x
 Wolfgang Denk <wd@denx.de>
 	IceCube_5100		MGT5100
 	IceCube_5200		MPC5200
 	AMX860			MPC860
 	ETX094			MPC850
 	FPS850L			MPC850
 	FPS860L			MPC860
 	ICU862			MPC862
 	IP860			MPC860
 	IVML24			MPC860
 	IVML24_128		MPC860
 	IVML24_256		MPC860
 	IVMS8			MPC860
 	IVMS8_128		MPC860
 	IVMS8_256		MPC860
 	LANTEC			MPC850
 	LWMON			MPC823
 	NC650			MPC852
 	R360MPI			MPC823
 	RMU			MPC850
 	RRvision		MPC823
 	SM850			MPC850
 	SPD823TS		MPC823
 	TQM823L			MPC823
 	TQM823L_LCD		MPC823
 	TQM850L			MPC850
 	TQM855L			MPC855
 	TQM860L			MPC860
 	TQM860L_FEC		MPC860
 	c2mon			MPC855
 	hermes			MPC860
 	lwmon			MPC823
 	pcu_e			MPC855
 	CU824			MPC8240
 	Sandpoint8240		MPC8240
 	SL8245			MPC8245
 	ATC			MPC8250
 	PM825			MPC8250
 	TQM8255			MPC8255
 	CPU86			MPC8260
 	PM826			MPC8260
 	TQM8260			MPC8260
 	P3G4			MPC7410
 	PCIPPC2			MPC750
 	PCIPPC6			MPC750
 	EXBITGEN		PPC405GP
 Jon Diekema <jon.diekema@smiths-aerospace.com>
 	sbc8260			MPC8260
 Dave Ellis <DGE@sixnetio.com>
 	SXNI855T		MPC8xx
 Thomas Frieden <ThomasF@hyperion-entertainment.com>
 	AmigaOneG3SE		MPC7xx
 Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 	ADCIOP			IOP480 (PPC401)
 	APC405			PPC405GP
 	AR405			PPC405GP
 	ASH405			PPC405EP
 	CANBT			PPC405CR
 	CPCI405			PPC405GP
 	CPCI4052		PPC405GP
 	CPCI405AB		PPC405GP
 	CPCI405DT		PPC405GP
 	CPCI440			PPC440GP
 	CPCIISER4		PPC405GP
 	DASA_SIM		IOP480 (PPC401)
 	DP405			PPC405EP
 	DU405			PPC405GP
 	G2000			PPC405EP
 	HH405			PPC405EP
 	HUB405			PPC405EP
 	OCRTC			PPC405GP
 	ORSG			PPC405GP
 	PCI405			PPC405GP
 	PLU405			PPC405EP
 	PMC405			PPC405GP
 	VOH405			PPC405EP
 	VOM405			PPC405EP
 	WUH405			PPC405EP
 Frank Gottschling <fgottschling@eltec.de>
 	MHPC			MPC8xx
 	BAB7xx			MPC740/MPC750
 Wolfgang Grandegger <wg@denx.de>
 	CCM			MPC855
 	PN62			MPC8240
 	IPHASE4539		MPC8260
 	SCM			MPC8260
 Howard Gray <mvsensor@matrix-vision.de>
 	MVS1			MPC823
 Klaus Heydeck <heydeck@kieback-peter.de>
 	KUP4K			MPC855
 	KUP4X			MPC859
 Murray Jensen <Murray.Jensen@cmst.csiro.au>
 	cogent_mpc8xx		MPC8xx
 	cogent_mpc8260		MPC8260
 	hymod			MPC8260
 Brad Kemp <Brad.Kemp@seranoa.com>
 	ppmc8260		MPC8260
 Sangmoon Kim <dogoil@etinsys.com>
 	debris			MPC8245
 Thomas Lange <thomas@corelatus.se>
 	GTH			MPC860
 The LEOX team <team@leox.org>
 	ELPT860			MPC860T
 Nye Liu <nyet@zumanetworks.com>
 	ZUMA			MPC7xx_74xx
 Jon Loeliger <jdl@freescale.com>
 	MPC8540ADS		MPC8540
 	MPC8560ADS		MPC8560
 	MPC8541CDS		MPC8541
 	MPC8555CDS		MPC8555
 Dan Malek <dan@embeddededge.com>
 	STxGP3			MPC85xx
 Eran Man <eran@nbase.co.il>
 	EVB64260_750CX		MPC750CX
 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
 	PPChameleonEVB	PPC405EP
 Reinhard Meyer <r.meyer@emk-elektronik.de>
 	TOP860			MPC860T
 	TOP5200			MPC5200
 Tolunay Orkun <torkun@nextio.com>
 	csb272			PPC405GP
 	csb472			PPC405GP
 Keith Outwater <Keith_Outwater@mvis.com>
 	GEN860T			MPC860T
 	GEN860T_SC		MPC860T
 Frank Panno <fpanno@delphintech.com>
 	ep8260			MPC8260
 Peter Pearse <peter.pearse@arm.com>
 	Integrator/AP		CM 926EJ-S, CM7x0T, CM9x0T
 	Integrator/CP		CM 926EJ-S  CM920T, CM940T, CM922T-XA10
 	Versatile/AB		ARM926EJ-S
 	Versatile/PB		ARM926EJ-S
 Denis Peter <d.peter@mpl.ch>
 	MIP405			PPC4xx
 	PIP405			PPC4xx
 Daniel Poirot <dan.poirot@windriver.com>
 	sbc8240			MPC8240
 	sbc405			PPC405GP
 Stefan Roese <sr@denx.de>
 	bamboo			PPC440EP
 	bunbinga		PPC405EP
 	ebony			PPC440GP
 	ocotea			PPC440GX
 	sycamore		PPC405GPr
 	walnut			PPC405GP
 	yellowstone		PPC440GR
 	yosemite		PPC440EP
 Yusdi Santoso <yusdi_santoso@adaptec.com>
 	HIDDEN_DRAGON	MPC8241/MPC8245
 Travis Sawyer (travis.sawyer@sandburst.com>
 	XPEDITE1K		PPC440GX
 Peter De Schrijver <p2@mind.be>
 	ML2			PPC4xx
 Erik Theisen <etheisen@mindspring.com>
 	W7OLMC			PPC4xx
 	W7OLMG			PPC4xx
 Jim Thompson <jim@musenki.com>
 	MUSENKI			MPC8245/8241
 	Sandpoint8245		MPC8245
 Rune Torgersen <runet@innovsys.com>
 	MPC8266ADS		MPC8266
 Josef Wagner <Wagner@Microsys.de>
 	CPC45			MPC8245
 	PM520			MPC5200
 Stephen Williams <steve@icarus.com>
 	JSE			PPC405GPr
 John Zhan <zhanz@sinovee.com>
 	svm_sc8xx		MPC8xx
 -------------------------------------------------------------------------
 Unknown / orphaned boards:
 	ADS860			MPC8xx
 	FADS823			MPC8xx
 	FADS850SAR		MPC8xx
 	FADS860T		MPC8xx
 	GENIETV			MPC8xx
 	IAD210			MPC8xx
 	MBX			MPC8xx
 	MBX860T			MPC8xx
 	NX823			MPC8xx
 	RPXClassic		MPC8xx
 	RPXlite			MPC8xx
 	CRAYL1			PPC4xx
 	ERIC			PPC4xx
 	MOUSSE			MPC824x
 	RPXsuper		MPC8260
 	rsdproto		MPC8260
 	EVB64260		MPC7xx_74xx
 #########################################################################
 # ARM Systems:								#
 #									#
 # Maintainer Name, Email Address					#
 #	Board			CPU					#
 #########################################################################
 Rishi Bhattacharya <rishi@ti.com>
 	omap5912osk		ARM926EJS
 George G. Davis <gdavis@mvista.com>
 	assabet			SA1100
 	gcplus			SA1100
 Thomas Elste <info@elste.org>
 	modnet50		ARM720T (NET+50)
 Peter Figuli <peposh@etc.sk>
 	wepep250		xscale
 Marius Gröger <mag@sysgo.de>
 	impa7			ARM720T (EP7211)
 	ep7312			ARM720T (EP7312)
 Kshitij Gupta <kshitij@ti.com>
 	omap1510inn		ARM925T
 	omap1610inn		ARM926EJS
 Kyle Harris <kharris@nexus-tech.net>
 	lubbock			xscale
 	cradle			xscale
 	ixdp425			xscale
 Gary Jennejohn <gj@denx.de>
 	smdk2400		ARM920T
 	trab			ARM920T
 Nishant Kamat <nskamat@ti.com>
 	omap1610h2		ARM926EJS
 Prakash Kumar <prakash@embedx.com>
 	cerf250			xscale
 David Müller <d.mueller@elsoft.ch>
 	smdk2410		ARM920T
 	VCMA9			ARM920T
 Rolf Offermanns <rof@sysgo.de>
 	shannon			SA1100
 Dave Peverley <dpeverley@mpc-data.co.uk>
 	omap730p2		ARM926EJS
 Robert Schwebel <r.schwebel@pengutronix.de>
 	csb226			xscale
 	innokom			xscale
 Andrea Scian <andrea.scian@dave-tech.it>
 	B2			ARM7TDMI (S3C44B0X)
 Greg Ungerer <greg.ungerer@opengear.com>
 	cm4008			ks8695p
 	cm4116			ks8695p
 	cm4148			ks8695p
 Richard Woodruff <r-woodruff2@ti.com>
 	omap2420h4		ARM1136EJS
 Alex Züpke <azu@sysgo.de>
 	lart			SA1100
 	dnp1110			SA1110
 #########################################################################
 # x86 Systems:								#
 #									#
 # Maintainer Name, Email Address					#
 #	Board			CPU					#
 #########################################################################
 Daniel Engström <daniel@omicron.se>
 	sc520_cdp		x86
 #########################################################################
 # MIPS Systems:								#
 #									#
 # Maintainer Name, Email Address					#
 #	Board			CPU					#
 #########################################################################
 Wolfgang Denk <wd@denx.de>
 	incaip			MIPS32 4Kc
 	purple			MIPS64 5Kc
 Thomas Lange <thomas@corelatus.se>
 	dbau1x00		MIPS32 Au1000
 #########################################################################
 # Nios-32 Systems:							#
 #									#
 # Maintainer Name, Email Address					#
 #	Board			CPU					#
 #########################################################################
 Stephan Linz <linz@li-pro.net>
 	DK1S10			Nios-32
 	ADNPESC1		Nios-32
 Scott McNutt <smcnutt@psyent.com>
 	DK1C20			Nios-32
 #########################################################################
 # Nios-II Systems:							#
 #									#
 # Maintainer Name, Email Address					#
 #	Board			CPU					#
 #########################################################################
 Scott McNutt <smcnutt@psyent.com>
 	PCI5441			Nios-II
 	PK1C20			Nios-II
 #########################################################################
 # MicroBlaze Systems:							#
 #									#
 # Maintainer Name, Email Address					#
 #	Board			CPU					#
 #########################################################################
 Yasushi Shoji <yashi@atmark-techno.com>
 	SUZAKU			MicroBlaze
 #########################################################################
 # Coldfire Systems:							#
 #									#
 # Maintainer Name, Email Address					#
 #	Board			CPU					#
 #########################################################################
 Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 	TASREG			MCF5249
 #########################################################################
 # End of MAINTAINERS list						#
 #########################################################################

MAKEALL

Diff comments View file @ f901a83

1	#!/bin/sh	1	#!/bin/sh
2		2
3	: ${JOBS:=}	3	: ${JOBS:=}
4		4
5	if [ "${CROSS_COMPILE}" ] ; then	5	if [ "${CROSS_COMPILE}" ] ; then
6	MAKE="make CROSS_COMPILE=${CROSS_COMPILE}"	6	MAKE="make CROSS_COMPILE=${CROSS_COMPILE}"
7	else	7	else
8	MAKE=make	8	MAKE=make
9	fi	9	fi
10		10
11	[ -d LOG ] \|\| mkdir LOG \|\| exit 1	11	[ -d LOG ] \|\| mkdir LOG \|\| exit 1
12		12
13	LIST=""	13	LIST=""
14		14
15	#########################################################################	15	#########################################################################
16	## MPC5xx Systems	16	## MPC5xx Systems
17	#########################################################################	17	#########################################################################
18		18
19	LIST_5xx=" \	19	LIST_5xx=" \
20	cmi_mpc5xx \	20	cmi_mpc5xx \
21	"	21	"
22		22
23	#########################################################################	23	#########################################################################
24	## MPC5xxx Systems	24	## MPC5xxx Systems
25	#########################################################################	25	#########################################################################
26		26
27	LIST_5xxx=" \	27	LIST_5xxx=" \
28	icecube_5100 icecube_5200 EVAL5200 PM520 \	28	icecube_5100 icecube_5200 EVAL5200 PM520 \
29	Total5100 Total5200 Total5200_Rev2 TQM5200_auto \	29	Total5100 Total5200 Total5200_Rev2 TQM5200_auto \
30	"	30	"
31		31
32	#########################################################################	32	#########################################################################
33	## MPC8xx Systems	33	## MPC8xx Systems
34	#########################################################################	34	#########################################################################
35		35
36	LIST_8xx=" \	36	LIST_8xx=" \
37	Adder87x GENIETV MBX860T R360MPI \	37	Adder87x GENIETV MBX860T R360MPI \
38	AdderII GTH MHPC RBC823 \	38	AdderII GTH MHPC RBC823 \
39	ADS860 hermes MPC86xADS rmu \	39	ADS860 hermes MPC86xADS rmu \
40	AMX860 IAD210 MPC885ADS RPXClassic \	40	AMX860 IAD210 MPC885ADS RPXClassic \
41	c2mon ICU862_100MHz MVS1 RPXlite \	41	c2mon ICU862_100MHz MVS1 RPXlite \
42	CCM IP860 NETPHONE RPXlite_DW \	42	CCM IP860 NETPHONE RPXlite_DW \
43	cogent_mpc8xx IVML24 NETTA RRvision \	43	cogent_mpc8xx IVML24 NETTA RRvision \
44	ELPT860 IVML24_128 NETTA2 SM850 \	44	ELPT860 IVML24_128 NETTA2 SM850 \
45	ESTEEM192E IVML24_256 NETTA_ISDN SPD823TS \	45	ESTEEM192E IVML24_256 NETTA_ISDN SPD823TS \
46	ETX094 IVMS8 NETVIA svm_sc8xx \	46	ETX094 IVMS8 NETVIA svm_sc8xx \
47	FADS823 IVMS8_128 NETVIA_V2 SXNI855T \	47	FADS823 IVMS8_128 NETVIA_V2 SXNI855T \
48	FADS850SAR IVMS8_256 NX823 TOP860 \	48	FADS850SAR IVMS8_256 NX823 TOP860 \
49	FADS860T KUP4K pcu_e TQM823L \	49	FADS860T KUP4K pcu_e TQM823L \
50	FLAGADM KUP4X QS823 TQM823L_LCD \	50	FLAGADM KUP4X QS823 TQM823L_LCD \
51	FPS850L LANTEC QS850 TQM850L \	51	FPS850L LANTEC QS850 TQM850L \
52	GEN860T lwmon QS860T TQM855L \	52	GEN860T lwmon QS860T TQM855L \
53	GEN860T_SC MBX quantum TQM860L \	53	GEN860T_SC MBX quantum TQM860L \
54	uc100 \	54	uc100 \
55	v37 \	55	v37 \
56	"	56	"
57		57
58	#########################################################################	58	#########################################################################
59	## PPC4xx Systems	59	## PPC4xx Systems
60	#########################################################################	60	#########################################################################
61		61
62	LIST_4xx=" \	62	LIST_4xx=" \
63	ADCIOP AR405 ASH405 bubinga \	63	ADCIOP AR405 ASH405 bubinga \
64	CANBT CPCI405 CPCI4052 CPCI405AB \	64	CANBT CPCI405 CPCI4052 CPCI405AB \
65	CPCI440 CPCIISER4 CRAYL1 csb272 \	65	CPCI440 CPCIISER4 CRAYL1 csb272 \
66	csb472 DASA_SIM DP405 DU405 \	66	csb472 DASA_SIM DP405 DU405 \
67	ebony ERIC EXBITGEN HUB405 \	67	ebony ERIC EXBITGEN HUB405 \
68	JSE MIP405 MIP405T ML2 \	68	JSE MIP405 MIP405T ML2 \
69	ml300 ocotea OCRTC ORSG \	69	ml300 ocotea OCRTC ORSG \
70	PCI405 PIP405 PLU405 PMC405 \	70	PCI405 PIP405 PLU405 PMC405 \
71	PPChameleonEVB VOH405 W7OLMC W7OLMG \	71	PPChameleonEVB VOH405 W7OLMC W7OLMG \
72	walnut WUH405 XPEDITE1K yellowstone \	72	walnut WUH405 XPEDITE1K yellowstone \
73	yosemite \	73	yosemite \
74	"	74	"
75		75
76	#########################################################################	76	#########################################################################
77	## MPC8220 Systems	77	## MPC8220 Systems
78	#########################################################################	78	#########################################################################
79		79
80	LIST_8220=" \	80	LIST_8220=" \
81	Alaska8220 Yukon8220 \	81	Alaska8220 Yukon8220 \
82	"	82	"
83		83
84	#########################################################################	84	#########################################################################
85	## MPC824x Systems	85	## MPC824x Systems
86	#########################################################################	86	#########################################################################
87		87
88	LIST_824x=" \	88	LIST_824x=" \
89	A3000 BMW CPC45 CU824 \	89	A3000 BMW CPC45 CU824 \
90	debris eXalion HIDDEN_DRAGON MOUSSE \	90	debris eXalion HIDDEN_DRAGON MOUSSE \
91	MUSENKI MVBLUE OXC PN62 \	91	MUSENKI MVBLUE OXC PN62 \
92	Sandpoint8240 Sandpoint8245 SL8245 utx8245 \	92	Sandpoint8240 Sandpoint8245 SL8245 utx8245 \
93	sbc8240 \	93	sbc8240 \
94	"	94	"
95		95
96	#########################################################################	96	#########################################################################
97	## MPC8260 Systems (includes 8250, 8255 etc.)	97	## MPC8260 Systems (includes 8250, 8255 etc.)
98	#########################################################################	98	#########################################################################
99		99
100	LIST_8260=" \	100	LIST_8260=" \
101	atc cogent_mpc8260 CPU86 CPU87 \	101	atc cogent_mpc8260 CPU86 CPU87 \
102	ep8260 gw8260 hymod IPHASE4539 \	102	ep8248 ep8260 gw8260 hymod \
103	ISPAN MPC8260ADS MPC8266ADS MPC8272ADS \	103	IPHASE4539 ISPAN MPC8260ADS MPC8266ADS \
104	PM826 PM828 ppmc8260 Rattler8248 \	104	MPC8272ADS PM826 PM828 ppmc8260 \
105	RPXsuper rsdproto sacsng sbc8260 \	105	Rattler8248 RPXsuper rsdproto sacsng \
106	SCM TQM8260_AC TQM8260_AD TQM8260_AE \	106	sbc8260 SCM TQM8260_AC TQM8260_AD \
107	ZPC1900 \	107	TQM8260_AE ZPC1900 \
108	"	108	"
109		109
110	#########################################################################	110	#########################################################################
111	## MPC83xx Systems (includes 8349, etc.)	111	## MPC83xx Systems (includes 8349, etc.)
112	#########################################################################	112	#########################################################################
113		113
114	LIST_83xx=" \	114	LIST_83xx=" \
115	MPC8349ADS \	115	MPC8349ADS \
116	"	116	"
117		117
118		118
119	#########################################################################	119	#########################################################################
120	## MPC85xx Systems (includes 8540, 8560 etc.)	120	## MPC85xx Systems (includes 8540, 8560 etc.)
121	#########################################################################	121	#########################################################################
122		122
123	LIST_85xx=" \	123	LIST_85xx=" \
124	MPC8540ADS MPC8540EVAL MPC8541CDS MPC8548CDS \	124	MPC8540ADS MPC8540EVAL MPC8541CDS MPC8548CDS \
125	MPC8555CDS MPC8560ADS PM854 PM856 \	125	MPC8555CDS MPC8560ADS PM854 PM856 \
126	sbc8540 sbc8560 stxgp3 TQM8540 \	126	sbc8540 sbc8560 stxgp3 TQM8540 \
127	"	127	"
128		128
129	#########################################################################	129	#########################################################################
130	## 74xx/7xx Systems	130	## 74xx/7xx Systems
131	#########################################################################	131	#########################################################################
132		132
133	LIST_74xx=" \	133	LIST_74xx=" \
134	DB64360 DB64460 EVB64260 P3G4 \	134	DB64360 DB64460 EVB64260 P3G4 \
135	PCIPPC2 PCIPPC6 ZUMA \	135	PCIPPC2 PCIPPC6 ZUMA \
136	"	136	"
137		137
138	LIST_7xx=" \	138	LIST_7xx=" \
139	BAB7xx CPCI750 ELPPC \	139	BAB7xx CPCI750 ELPPC \
140	"	140	"
141		141
142	LIST_ppc="${LIST_5xx} ${LIST_5xxx} \	142	LIST_ppc="${LIST_5xx} ${LIST_5xxx} \
143	${LIST_8xx} \	143	${LIST_8xx} \
144	${LIST_8220} ${LIST_824x} ${LIST_8260} \	144	${LIST_8220} ${LIST_824x} ${LIST_8260} \
145	${LIST_83xx} \	145	${LIST_83xx} \
146	${LIST_85xx} \	146	${LIST_85xx} \
147	${LIST_4xx} \	147	${LIST_4xx} \
148	${LIST_74xx} ${LIST_7xx}"	148	${LIST_74xx} ${LIST_7xx}"
149		149
150	#########################################################################	150	#########################################################################
151	## StrongARM Systems	151	## StrongARM Systems
152	#########################################################################	152	#########################################################################
153		153
154	LIST_SA="assabet dnp1110 gcplus lart shannon"	154	LIST_SA="assabet dnp1110 gcplus lart shannon"
155		155
156	#########################################################################	156	#########################################################################
157	## ARM7 Systems	157	## ARM7 Systems
158	#########################################################################	158	#########################################################################
159		159
160	LIST_ARM7="B2 ep7312 evb4510 impa7 modnet50"	160	LIST_ARM7="B2 ep7312 evb4510 impa7 modnet50"
161		161
162	#########################################################################	162	#########################################################################
163	## ARM9 Systems	163	## ARM9 Systems
164	#########################################################################	164	#########################################################################
165		165
166	LIST_ARM9=" \	166	LIST_ARM9=" \
167	at91rm9200dk cmc_pu2 integratorcp integratorap \	167	at91rm9200dk cmc_pu2 integratorcp integratorap \
168	lpd7a400 mx1ads mx1fs2 omap1510inn \	168	lpd7a400 mx1ads mx1fs2 omap1510inn \
169	omap1610h2 omap1610inn omap730p2 scb9328 \	169	omap1610h2 omap1610inn omap730p2 scb9328 \
170	smdk2400 smdk2410 trab VCMA9 \	170	smdk2400 smdk2410 trab VCMA9 \
171	versatile voiceblue \	171	versatile voiceblue \
172	"	172	"
173		173
174	#########################################################################	174	#########################################################################
175	## ARM11 Systems	175	## ARM11 Systems
176	#########################################################################	176	#########################################################################
177	LIST_ARM11="omap2420h4"	177	LIST_ARM11="omap2420h4"
178		178
179	#########################################################################	179	#########################################################################
180	## Xscale Systems	180	## Xscale Systems
181	#########################################################################	181	#########################################################################
182		182
183	LIST_pxa=" \	183	LIST_pxa=" \
184	adsvix cerf250 cradle csb226 \	184	adsvix cerf250 cradle csb226 \
185	innokom lubbock wepep250 xaeniax \	185	innokom lubbock wepep250 xaeniax \
186	xm250 xsengine \	186	xm250 xsengine \
187	"	187	"
188		188
189	LIST_ixp="ixdp425"	189	LIST_ixp="ixdp425"
190		190
191		191
192	LIST_arm=" \	192	LIST_arm=" \
193	${LIST_SA} \	193	${LIST_SA} \
194	${LIST_ARM7} ${LIST_ARM9} ${LIST_ARM11} \	194	${LIST_ARM7} ${LIST_ARM9} ${LIST_ARM11} \
195	${LIST_pxa} ${LIST_ixp} \	195	${LIST_pxa} ${LIST_ixp} \
196	"	196	"
197		197
198	#########################################################################	198	#########################################################################
199	## MIPS Systems	199	## MIPS Systems
200	#########################################################################	200	#########################################################################
201		201
202	LIST_mips4kc="incaip"	202	LIST_mips4kc="incaip"
203		203
204	LIST_mips5kc="purple"	204	LIST_mips5kc="purple"
205		205
206	LIST_au1xx0="dbau1000 dbau1100 dbau1500 dbau1550 dbau1550_el"	206	LIST_au1xx0="dbau1000 dbau1100 dbau1500 dbau1550 dbau1550_el"
207		207
208	LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1xx0}"	208	LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1xx0}"
209		209
210	#########################################################################	210	#########################################################################
211	## i386 Systems	211	## i386 Systems
212	#########################################################################	212	#########################################################################
213		213
214	LIST_I486="sc520_cdp sc520_spunk sc520_spunk_rel"	214	LIST_I486="sc520_cdp sc520_spunk sc520_spunk_rel"
215		215
216	LIST_x86="${LIST_I486}"	216	LIST_x86="${LIST_I486}"
217		217
218	#########################################################################	218	#########################################################################
219	## NIOS Systems	219	## NIOS Systems
220	#########################################################################	220	#########################################################################
221		221
222	LIST_nios=" \	222	LIST_nios=" \
223	ADNPESC1 ADNPESC1_base_32 \	223	ADNPESC1 ADNPESC1_base_32 \
224	ADNPESC1_DNPEVA2_base_32 \	224	ADNPESC1_DNPEVA2_base_32 \
225	DK1C20 DK1C20_standard_32 \	225	DK1C20 DK1C20_standard_32 \
226	DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20 \	226	DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20 \
227	"	227	"
228		228
229	#########################################################################	229	#########################################################################
230	## Nios-II Systems	230	## Nios-II Systems
231	#########################################################################	231	#########################################################################
232		232
233	LIST_nios2="PCI5441 PK1C20"	233	LIST_nios2="PCI5441 PK1C20"
234		234
235	#########################################################################	235	#########################################################################
236	## MicroBlaze Systems	236	## MicroBlaze Systems
237	#########################################################################	237	#########################################################################
238		238
239	LIST_microblaze="suzaku"	239	LIST_microblaze="suzaku"
240		240
241	#-----------------------------------------------------------------------	241	#-----------------------------------------------------------------------
242		242
243	#----- for now, just run PPC by default -----	243	#----- for now, just run PPC by default -----
244	[ $# = 0 ] && set $LIST_ppc	244	[ $# = 0 ] && set $LIST_ppc
245		245
246	#-----------------------------------------------------------------------	246	#-----------------------------------------------------------------------
247		247
248	build_target() {	248	build_target() {
249	target=$1	249	target=$1
250		250
251	${MAKE} distclean >/dev/null	251	${MAKE} distclean >/dev/null
252	${MAKE} ${target}_config	252	${MAKE} ${target}_config
253	${MAKE} ${JOBS} all 2>&1 >LOG/$target.MAKELOG \| tee LOG/$target.ERR	253	${MAKE} ${JOBS} all 2>&1 >LOG/$target.MAKELOG \| tee LOG/$target.ERR
254	${CROSS_COMPILE:-ppc_8xx-}size u-boot \| tee -a LOG/$target.MAKELOG	254	${CROSS_COMPILE:-ppc_8xx-}size u-boot \| tee -a LOG/$target.MAKELOG
255	}	255	}
256		256
257	#-----------------------------------------------------------------------	257	#-----------------------------------------------------------------------
258		258
259		259
260	for arg in $@	260	for arg in $@
261	do	261	do
262	case "$arg" in	262	case "$arg" in
263	ppc\|5xx\|5xxx\|8xx\|8220\|824x\|8260\|83xx\|85xx\|4xx\|7xx\|74xx\| \	263	ppc\|5xx\|5xxx\|8xx\|8220\|824x\|8260\|83xx\|85xx\|4xx\|7xx\|74xx\| \
264	arm\|SA\|ARM7\|ARM9\|ARM11\|pxa\|ixp\| \	264	arm\|SA\|ARM7\|ARM9\|ARM11\|pxa\|ixp\| \
265	microblaze\| \	265	microblaze\| \
266	mips\| \	266	mips\| \
267	nios\|nios2\| \	267	nios\|nios2\| \
268	x86\|I486)	268	x86\|I486)
269	for target in `eval echo '$LIST_'${arg}`	269	for target in `eval echo '$LIST_'${arg}`
270	do	270	do
271	build_target ${target}	271	build_target ${target}
272	done	272	done
273	;;	273	;;
274	*) build_target ${arg}	274	*) build_target ${arg}
275	;;	275	;;
276	esac	276	esac
277	done	277	done
278		278

Makefile

Diff comments View file @ f901a83

 #
 # (C) Copyright 2000-2005
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
 # project.
 #
 # This program is free software; you can redistribute it and/or
 # modify it under the terms of the GNU General Public License as
 # published by the Free Software Foundation; either version 2 of
 # the License, or (at your option) any later version.
 #
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
 #
 # You should have received a copy of the GNU General Public License
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
 HOSTARCH := $(shell uname -m | \
 	sed -e s/i.86/i386/ \
 	    -e s/sun4u/sparc64/ \
 	    -e s/arm.*/arm/ \
 	    -e s/sa110/arm/ \
 	    -e s/powerpc/ppc/ \
 	    -e s/macppc/ppc/)
 HOSTOS := $(shell uname -s | tr A-Z a-z | \
 	    sed -e 's/\(cygwin\).*/cygwin/')
 export	HOSTARCH
 # Deal with colliding definitions from tcsh etc.
 VENDOR=
 #########################################################################
 TOPDIR	:= $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi)
 export	TOPDIR
 ifeq (include/config.mk,$(wildcard include/config.mk))
 # load ARCH, BOARD, and CPU configuration
 include include/config.mk
 export	ARCH CPU BOARD VENDOR SOC
 # load other configuration
 include $(TOPDIR)/config.mk
 ifndef CROSS_COMPILE
 ifeq ($(HOSTARCH),ppc)
 CROSS_COMPILE =
 else
 ifeq ($(ARCH),ppc)
 CROSS_COMPILE = powerpc-linux-
 endif
 ifeq ($(ARCH),arm)
 CROSS_COMPILE = arm-linux-
 endif
 ifeq ($(ARCH),i386)
 ifeq ($(HOSTARCH),i386)
 CROSS_COMPILE =
 else
 CROSS_COMPILE = i386-linux-
 endif
 endif
 ifeq ($(ARCH),mips)
 CROSS_COMPILE = mips_4KC-
 endif
 ifeq ($(ARCH),nios)
 CROSS_COMPILE = nios-elf-
 endif
 ifeq ($(ARCH),nios2)
 CROSS_COMPILE = nios2-elf-
 endif
 ifeq ($(ARCH),m68k)
 CROSS_COMPILE = m68k-elf-
 endif
 ifeq ($(ARCH),microblaze)
 CROSS_COMPILE = mb-
 endif
 endif
 endif
 export	CROSS_COMPILE
 #########################################################################
 # U-Boot objects....order is important (i.e. start must be first)
 OBJS  = cpu/$(CPU)/start.o
 ifeq ($(CPU),i386)
 OBJS += cpu/$(CPU)/start16.o
 OBJS += cpu/$(CPU)/reset.o
 endif
 ifeq ($(CPU),ppc4xx)
 OBJS += cpu/$(CPU)/resetvec.o
 endif
 ifeq ($(CPU),mpc83xx)
 OBJS += cpu/$(CPU)/resetvec.o
 endif
 ifeq ($(CPU),mpc85xx)
 OBJS += cpu/$(CPU)/resetvec.o
 endif
 LIBS  = lib_generic/libgeneric.a
 LIBS += board/$(BOARDDIR)/lib$(BOARD).a
 LIBS += cpu/$(CPU)/lib$(CPU).a
 ifdef SOC
 LIBS += cpu/$(CPU)/$(SOC)/lib$(SOC).a
 endif
 LIBS += lib_$(ARCH)/lib$(ARCH).a
 LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a \
 	fs/reiserfs/libreiserfs.a fs/ext2/libext2fs.a
 LIBS += net/libnet.a
 LIBS += disk/libdisk.a
 LIBS += rtc/librtc.a
 LIBS += dtt/libdtt.a
 LIBS += drivers/libdrivers.a
 LIBS += drivers/sk98lin/libsk98lin.a
 LIBS += post/libpost.a post/cpu/libcpu.a
 LIBS += common/libcommon.a
 .PHONY : $(LIBS)
 # Add GCC lib
 PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
 # The "tools" are needed early, so put this first
 # Don't include stuff already done in $(LIBS)
 SUBDIRS	= tools \
 	  examples \
 	  post \
 	  post/cpu
 .PHONY : $(SUBDIRS)
 #########################################################################
 #########################################################################
 ALL = u-boot.srec u-boot.bin System.map
 all:		$(ALL)
 u-boot.hex:	u-boot
 		$(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@
 u-boot.srec:	u-boot
 		$(OBJCOPY) ${OBJCFLAGS} -O srec $< $@
 u-boot.bin:	u-boot
 		$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
 u-boot.img:	u-boot.bin
 		./tools/mkimage -A $(ARCH) -T firmware -C none \
 		-a $(TEXT_BASE) -e 0 \
 		-n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' include/version.h | \
 			sed -e 's/"[	 ]*$$/ for $(BOARD) board"/') \
 		-d $< $@
 u-boot.dis:	u-boot
 		$(OBJDUMP) -d $< > $@
 u-boot:		depend $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT)
 		UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed  -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
 		$(LD) $(LDFLAGS) $$UNDEF_SYM $(OBJS) \
 			--start-group $(LIBS) --end-group $(PLATFORM_LIBS) \
 			-Map u-boot.map -o u-boot
 $(LIBS):
 		$(MAKE) -C `dirname $@`
 $(SUBDIRS):
 		$(MAKE) -C $@ all
 gdbtools:
 		$(MAKE) -C tools/gdb || exit 1
 depend dep:
 		@for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir .depend ; done
 tags:
 		ctags -w `find $(SUBDIRS) include \
 				lib_generic board/$(BOARDDIR) cpu/$(CPU) lib_$(ARCH) \
 				fs/cramfs fs/fat fs/fdos fs/jffs2 \
 				net disk rtc dtt drivers drivers/sk98lin common \
 			\( -name CVS -prune \) -o \( -name '*.[ch]' -print \)`
 etags:
 		etags -a `find $(SUBDIRS) include \
 				lib_generic board/$(BOARDDIR) cpu/$(CPU) lib_$(ARCH) \
 				fs/cramfs fs/fat fs/fdos fs/jffs2 \
 				net disk rtc dtt drivers drivers/sk98lin common \
 			\( -name CVS -prune \) -o \( -name '*.[ch]' -print \)`
 System.map:	u-boot
 		@$(NM) $< | \
 		grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
 		sort > System.map
 #########################################################################
 else
 all install u-boot u-boot.srec depend dep:
 	@echo "System not configured - see README" >&2
 	@ exit 1
 endif
 #########################################################################
 unconfig:
 	@rm -f include/config.h include/config.mk board/*/config.tmp
 #========================================================================
 # PowerPC
 #========================================================================
 #########################################################################
 ## MPC5xx Systems
 #########################################################################
 canmb_config:	unconfig
 	@./mkconfig -a canmb ppc mpc5xxx canmb
 cmi_mpc5xx_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc5xx cmi
 PATI_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc5xx pati mpl
 #########################################################################
 ## MPC5xxx Systems
 #########################################################################
 hmi1001_config:         unconfig
 	@./mkconfig hmi1001 ppc mpc5xxx hmi1001
 Lite5200_config				\
 Lite5200_LOWBOOT_config			\
 Lite5200_LOWBOOT08_config		\
 icecube_5200_config			\
 icecube_5200_LOWBOOT_config		\
 icecube_5200_LOWBOOT08_config		\
 icecube_5200_DDR_config 		\
 icecube_5200_DDR_LOWBOOT_config 	\
 icecube_5200_DDR_LOWBOOT08_config	\
 icecube_5100_config:			unconfig
 	@ >include/config.h
 	@[ -z "$(findstring LOWBOOT_,$@)" ] || \
 		{ if [ "$(findstring DDR,$@)" ] ; \
 			then echo "TEXT_BASE = 0xFF800000" >board/icecube/config.tmp ; \
 			else echo "TEXT_BASE = 0xFF000000" >board/icecube/config.tmp ; \
 		  fi ; \
 		  echo "... with LOWBOOT configuration" ; \
 		}
 	@[ -z "$(findstring LOWBOOT08,$@)" ] || \
 		{ echo "TEXT_BASE = 0xFF800000" >board/icecube/config.tmp ; \
 		  echo "... with 8 MB flash only" ; \
 		  echo "... with LOWBOOT configuration" ; \
 		}
 	@[ -z "$(findstring DDR,$@)" ] || \
 		{ echo "#define CONFIG_MPC5200_DDR"	>>include/config.h ; \
 		  echo "... DDR memory revision" ; \
 		}
 	@[ -z "$(findstring 5200,$@)" ] || \
 		{ echo "#define CONFIG_MPC5200"		>>include/config.h ; \
 		  echo "... with MPC5200 processor" ; \
 		}
 	@[ -z "$(findstring 5100,$@)" ] || \
 		{ echo "#define CONFIG_MGT5100"		>>include/config.h ; \
 		  echo "... with MGT5100 processor" ; \
 		}
 	@./mkconfig -a IceCube ppc mpc5xxx icecube
 inka4x0_config:		unconfig
 	@./mkconfig inka4x0 ppc mpc5xxx inka4x0
 PM520_config \
 PM520_DDR_config \
 PM520_ROMBOOT_config \
 PM520_ROMBOOT_DDR_config:	unconfig
 	@ >include/config.h
 	@[ -z "$(findstring DDR,$@)" ] || \
 		{ echo "#define CONFIG_MPC5200_DDR"	>>include/config.h ; \
 		  echo "... DDR memory revision" ; \
 		}
 	@[ -z "$(findstring ROMBOOT,$@)" ] || \
 		{ echo "#define CONFIG_BOOT_ROM" >>include/config.h ; \
 		  echo "... booting from 8-bit flash" ; \
 		}
 	@./mkconfig -a PM520 ppc mpc5xxx pm520
 MINI5200_config	\
 EVAL5200_config	\
 TOP5200_config:	unconfig
 	@ echo "#define CONFIG_$(@:_config=) 1"	>include/config.h
 	@./mkconfig -a TOP5200 ppc mpc5xxx top5200 emk
 Total5100_config		\
 Total5200_config		\
 Total5200_lowboot_config	\
 Total5200_Rev2_config		\
 Total5200_Rev2_lowboot_config:	unconfig
 	@ >include/config.h
 	@[ -z "$(findstring 5100,$@)" ] || \
 		{ echo "#define CONFIG_MGT5100"		>>include/config.h ; \
 		  echo "... with MGT5100 processor" ; \
 		}
 	@[ -z "$(findstring 5200,$@)" ] || \
 		{ echo "#define CONFIG_MPC5200"		>>include/config.h ; \
 		  echo "... with MPC5200 processor" ; \
 		}
 	@[ -n "$(findstring Rev,$@)" ] || \
 		{ echo "#define CONFIG_TOTAL5200_REV 1"	>>include/config.h ; \
 		  echo "... revision 1 board" ; \
 		}
 	@[ -z "$(findstring Rev2_,$@)" ] || \
 		{ echo "#define CONFIG_TOTAL5200_REV 2"	>>include/config.h ; \
 		  echo "... revision 2 board" ; \
 		}
 	@[ -z "$(findstring lowboot_,$@)" ] || \
 		{ echo "TEXT_BASE = 0xFE000000" >board/total5200/config.tmp ; \
 		  echo "... with lowboot configuration" ; \
 		}
 	@./mkconfig -a Total5200 ppc mpc5xxx total5200
 TQM5200_auto_config		\
 TQM5200_AA_config	\
 TQM5200_AB_config	\
 TQM5200_AC_config	\
 MiniFAP_config:	unconfig
 	@ >include/config.h
 	@[ -z "$(findstring MiniFAP,$@)" ] || \
 		{ echo "#define CONFIG_MINIFAP"	>>include/config.h ; \
 		  echo "#define CONFIG_TQM5200_AC"	>>include/config.h ; \
 		  echo "... TQM5200_AC on MiniFAP" ; \
 		}
 	@[ -z "$(findstring AA,$@)" ] || \
 		{ echo "#define CONFIG_TQM5200_AA"	>>include/config.h ; \
 		  echo "... with 4 MB Flash, 16 MB SDRAM, 32 kB EEPROM" ; \
 		}
 	@[ -z "$(findstring AB,$@)" ] || \
 		{ echo "#define CONFIG_TQM5200_AB"	>>include/config.h ; \
 		  echo "... with 64 MB Flash, 64 MB SDRAM, 32 kB EEPROM, 512 kB SRAM" ; \
 		  echo "... with Graphics Controller"; \
 		}
 	@[ -z "$(findstring AC,$@)" ] || \
 		{ echo "#define CONFIG_TQM5200_AC"	>>include/config.h ; \
 		  echo "... with 4 MB Flash, 128 MB SDRAM" ; \
 		  echo "... with Graphics Controller"; \
 		}
 	@[ -z "$(findstring auto,$@)" ] || \
 		{ echo "#define CONFIG_CS_AUTOCONF"	>>include/config.h ; \
 		  echo "... with automatic CS configuration" ; \
 		}
 	@./mkconfig -a TQM5200 ppc mpc5xxx tqm5200
 #########################################################################
 ## MPC8xx Systems
 #########################################################################
 Adder_config    \
 Adder87x_config \
 AdderII_config  \
 	:		unconfig
 	$(if $(findstring AdderII,$@), \
 	@echo "#define CONFIG_MPC852T" > include/config.h)
 	@./mkconfig -a Adder ppc mpc8xx adder
 ADS860_config     \
 FADS823_config    \
 FADS850SAR_config \
 MPC86xADS_config  \
 MPC885ADS_config  \
 FADS860T_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx fads
 AMX860_config	:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx amx860 westel
 c2mon_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx c2mon
 CCM_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx CCM siemens
 cogent_mpc8xx_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx cogent
 ELPT860_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx elpt860 LEOX
 ESTEEM192E_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx esteem192e
 ETX094_config	:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx etx094
 FLAGADM_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx flagadm
 xtract_GEN860T = $(subst _SC,,$(subst _config,,$1))
 GEN860T_SC_config	\
 GEN860T_config: unconfig
 	@ >include/config.h
 	@[ -z "$(findstring _SC,$@)" ] || \
 		{ echo "#define CONFIG_SC" >>include/config.h ; \
 		  echo "With reduced H/W feature set (SC)..." ; \
 		}
 	@./mkconfig -a $(call xtract_GEN860T,$@) ppc mpc8xx gen860t
 GENIETV_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx genietv
 GTH_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx gth
 hermes_config	:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx hermes
 HMI10_config	:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx tqm8xx
 IAD210_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx IAD210 siemens
 xtract_ICU862 = $(subst _100MHz,,$(subst _config,,$1))
 ICU862_100MHz_config	\
 ICU862_config: unconfig
 	@ >include/config.h
 	@[ -z "$(findstring _100MHz,$@)" ] || \
 		{ echo "#define CONFIG_100MHz"	>>include/config.h ; \
 		  echo "... with 100MHz system clock" ; \
 		}
 	@./mkconfig -a $(call xtract_ICU862,$@) ppc mpc8xx icu862
 IP860_config	:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx ip860
 IVML24_256_config \
 IVML24_128_config \
 IVML24_config:	unconfig
 	@ >include/config.h
 	@[ -z "$(findstring IVML24_config,$@)" ] || \
 		 { echo "#define CONFIG_IVML24_16M"	>>include/config.h ; \
 		 }
 	@[ -z "$(findstring IVML24_128_config,$@)" ] || \
 		 { echo "#define CONFIG_IVML24_32M"	>>include/config.h ; \
 		 }
 	@[ -z "$(findstring IVML24_256_config,$@)" ] || \
 		 { echo "#define CONFIG_IVML24_64M"	>>include/config.h ; \
 		 }
 	@./mkconfig -a IVML24 ppc mpc8xx ivm
 IVMS8_256_config \
 IVMS8_128_config \
 IVMS8_config:	unconfig
 	@ >include/config.h
 	@[ -z "$(findstring IVMS8_config,$@)" ] || \
 		 { echo "#define CONFIG_IVMS8_16M"	>>include/config.h ; \
 		 }
 	@[ -z "$(findstring IVMS8_128_config,$@)" ] || \
 		 { echo "#define CONFIG_IVMS8_32M"	>>include/config.h ; \
 		 }
 	@[ -z "$(findstring IVMS8_256_config,$@)" ] || \
 		 { echo "#define CONFIG_IVMS8_64M"	>>include/config.h ; \
 		 }
 	@./mkconfig -a IVMS8 ppc mpc8xx ivm
 KUP4K_config	:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx kup4k kup
 KUP4X_config    :       unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx kup4x kup
 LANTEC_config	:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx lantec
 lwmon_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx lwmon
 MBX_config	\
 MBX860T_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx mbx8xx
 MHPC_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx mhpc eltec
 MVS1_config :		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx mvs1
 xtract_NETVIA = $(subst _V2,,$(subst _config,,$1))
 NETVIA_V2_config \
 NETVIA_config:		unconfig
 	@ >include/config.h
 	@[ -z "$(findstring NETVIA_config,$@)" ] || \
 		 { echo "#define CONFIG_NETVIA_VERSION 1" >>include/config.h ; \
 		  echo "... Version 1" ; \
 		 }
 	@[ -z "$(findstring NETVIA_V2_config,$@)" ] || \
 		 { echo "#define CONFIG_NETVIA_VERSION 2" >>include/config.h ; \
 		  echo "... Version 2" ; \
 		 }
 	@./mkconfig -a $(call xtract_NETVIA,$@) ppc mpc8xx netvia
 xtract_NETPHONE = $(subst _V2,,$(subst _config,,$1))
 NETPHONE_V2_config \
 NETPHONE_config:	unconfig
 	@ >include/config.h
 	@[ -z "$(findstring NETPHONE_config,$@)" ] || \
 		 { echo "#define CONFIG_NETPHONE_VERSION 1" >>include/config.h ; \
 		 }
 	@[ -z "$(findstring NETPHONE_V2_config,$@)" ] || \
 		 { echo "#define CONFIG_NETPHONE_VERSION 2" >>include/config.h ; \
 		 }
 	@./mkconfig -a $(call xtract_NETPHONE,$@) ppc mpc8xx netphone
 xtract_NETTA = $(subst _SWAPHOOK,,$(subst _6412,,$(subst _ISDN,,$(subst _config,,$1))))
 NETTA_ISDN_6412_SWAPHOOK_config \
 NETTA_ISDN_SWAPHOOK_config \
 NETTA_6412_SWAPHOOK_config \
 NETTA_SWAPHOOK_config \
 NETTA_ISDN_6412_config \
 NETTA_ISDN_config \
 NETTA_6412_config \
 NETTA_config:		unconfig
 	@ >include/config.h
 	@[ -z "$(findstring ISDN_,$@)" ] || \
 		 { echo "#define CONFIG_NETTA_ISDN 1" >>include/config.h ; \
 		 }
 	@[ -n "$(findstring ISDN_,$@)" ] || \
 		 { echo "#undef CONFIG_NETTA_ISDN" >>include/config.h ; \
 		 }
 	@[ -z "$(findstring 6412_,$@)" ] || \
 		 { echo "#define CONFIG_NETTA_6412 1" >>include/config.h ; \
 		 }
 	@[ -n "$(findstring 6412_,$@)" ] || \
 		 { echo "#undef CONFIG_NETTA_6412" >>include/config.h ; \
 		 }
 	@[ -z "$(findstring SWAPHOOK_,$@)" ] || \
 		 { echo "#define CONFIG_NETTA_SWAPHOOK 1" >>include/config.h ; \
 		 }
 	@[ -n "$(findstring SWAPHOOK_,$@)" ] || \
 		 { echo "#undef CONFIG_NETTA_SWAPHOOK" >>include/config.h ; \
 		 }
 	@./mkconfig -a $(call xtract_NETTA,$@) ppc mpc8xx netta
 xtract_NETTA2 = $(subst _V2,,$(subst _config,,$1))
 NETTA2_V2_config \
 NETTA2_config:		unconfig
 	@ >include/config.h
 	@[ -z "$(findstring NETTA2_config,$@)" ] || \
 		 { echo "#define CONFIG_NETTA2_VERSION 1" >>include/config.h ; \
 		 }
 	@[ -z "$(findstring NETTA2_V2_config,$@)" ] || \
 		 { echo "#define CONFIG_NETTA2_VERSION 2" >>include/config.h ; \
 		 }
 	@./mkconfig -a $(call xtract_NETTA2,$@) ppc mpc8xx netta2
 NC650_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx nc650
 NX823_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx nx823
 pcu_e_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx pcu_e siemens
 QS850_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx qs850 snmc
 QS823_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx qs850 snmc
 QS860T_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx qs860t snmc
 quantum_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx quantum
 R360MPI_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx r360mpi
 RBC823_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx rbc823
 RPXClassic_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx RPXClassic
 RPXlite_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx RPXlite
 RPXlite_DW_64_config  		\
 RPXlite_DW_LCD_config 		\
 RPXlite_DW_64_LCD_config 	\
 RPXlite_DW_NVRAM_config		\
 RPXlite_DW_NVRAM_64_config      \
 RPXlite_DW_NVRAM_LCD_config	\
 RPXlite_DW_NVRAM_64_LCD_config  \
 RPXlite_DW_config:         unconfig
 	@ >include/config.h
 	@[ -z "$(findstring _64,$@)" ] || \
 		{ echo "#define RPXlite_64MHz"		>>include/config.h ; \
 		  echo "... with 64MHz system clock ..."; \
 		}
 	@[ -z "$(findstring _LCD,$@)" ] || \
 		{ echo "#define CONFIG_LCD"          	>>include/config.h ; \
 		  echo "#define CONFIG_NEC_NL6448BC20"	>>include/config.h ; \
 		  echo "... with LCD display ..."; \
 		}
 	@[ -z "$(findstring _NVRAM,$@)" ] || \
 		{ echo "#define  CFG_ENV_IS_IN_NVRAM" 	>>include/config.h ; \
 		  echo "... with ENV in NVRAM ..."; \
 		}
 	@./mkconfig -a RPXlite_DW ppc mpc8xx RPXlite_dw
 rmu_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx rmu
 RRvision_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx RRvision
 RRvision_LCD_config:	unconfig
 	@echo "#define CONFIG_LCD" >include/config.h
 	@echo "#define CONFIG_SHARP_LQ104V7DS01" >>include/config.h
 	@./mkconfig -a RRvision ppc mpc8xx RRvision
 SM850_config	:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx tqm8xx
 SPD823TS_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx spd8xx
 svm_sc8xx_config:	unconfig
 	@ >include/config.h
 	@./mkconfig $(@:_config=) ppc mpc8xx svm_sc8xx
 SXNI855T_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx sixnet
 # EMK MPC8xx based modules
 TOP860_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx top860 emk
 # Play some tricks for configuration selection
 # Only 855 and 860 boards may come with FEC
 # and only 823 boards may have LCD support
 xtract_8xx = $(subst _LCD,,$(subst _config,,$1))
 FPS850L_config		\
 FPS860L_config		\
 NSCU_config		\
 TQM823L_config		\
 TQM823L_LCD_config	\
 TQM850L_config		\
 TQM855L_config		\
 TQM860L_config		\
 TQM862L_config		\
 TQM823M_config		\
 TQM850M_config		\
 TQM855M_config		\
 TQM860M_config		\
 TQM862M_config		\
 TQM866M_config:		unconfig
 	@ >include/config.h
 	@[ -z "$(findstring _LCD,$@)" ] || \
 		{ echo "#define CONFIG_LCD"		>>include/config.h ; \
 		  echo "#define CONFIG_NEC_NL6448BC20"	>>include/config.h ; \
 		  echo "... with LCD display" ; \
 		}
 	@./mkconfig -a $(call xtract_8xx,$@) ppc mpc8xx tqm8xx
 TTTech_config:	unconfig
 	@echo "#define CONFIG_LCD" >include/config.h
 	@echo "#define CONFIG_SHARP_LQ104V7DS01" >>include/config.h
 	@./mkconfig -a TQM823L ppc mpc8xx tqm8xx
 uc100_config	:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx uc100
 v37_config:	unconfig
 	@echo "#define CONFIG_LCD" >include/config.h
 	@echo "#define CONFIG_SHARP_LQ084V1DG21" >>include/config.h
 	@./mkconfig $(@:_config=) ppc mpc8xx v37
 wtk_config:	unconfig
 	@echo "#define CONFIG_LCD" >include/config.h
 	@echo "#define CONFIG_SHARP_LQ065T9DR51U" >>include/config.h
 	@./mkconfig -a TQM823L ppc mpc8xx tqm8xx
 #########################################################################
 ## PPC4xx Systems
 #########################################################################
 xtract_4xx = $(subst _25,,$(subst _33,,$(subst _BA,,$(subst _ME,,$(subst _HI,,$(subst _config,,$1))))))
 ADCIOP_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx adciop esd
 APC405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx apc405 esd
 AR405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx ar405 esd
 ASH405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx ash405 esd
 bamboo_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx bamboo amcc
 bubinga_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx bubinga amcc
 CANBT_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx canbt esd
 CATcenter_config	\
 CATcenter_25_config	\
 CATcenter_33_config:	unconfig
 	@ echo "/* CATcenter uses PPChameleon Model ME */"  > include/config.h
 	@ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 1" >> include/config.h
 	@[ -z "$(findstring _25,$@)" ] || \
 		{ echo "#define CONFIG_PPCHAMELEON_CLK_25" >>include/config.h ; \
 		  echo "SysClk = 25MHz" ; \
 		}
 	@[ -z "$(findstring _33,$@)" ] || \
 		{ echo "#define CONFIG_PPCHAMELEON_CLK_33" >>include/config.h ; \
 		  echo "SysClk = 33MHz" ; \
 		}
 	@./mkconfig -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave
 CPCI405_config	\
 CPCI4052_config	\
 CPCI405DT_config	\
 CPCI405AB_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx cpci405 esd
 	@echo "BOARD_REVISION = $(@:_config=)"	>>include/config.mk
 CPCI440_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx cpci440 esd
 CPCIISER4_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx cpciiser4 esd
 CRAYL1_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx L1 cray
 csb272_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx csb272
 csb472_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx csb472
 DASA_SIM_config: unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx dasa_sim esd
 DP405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx dp405 esd
 DU405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx du405 esd
 ebony_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx ebony amcc
 ERIC_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx eric
 EXBITGEN_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx exbitgen
 G2000_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx g2000
 HH405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx hh405 esd
 HUB405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx hub405 esd
 JSE_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx jse
 MIP405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx mip405 mpl
 MIP405T_config:	unconfig
 	@echo "#define CONFIG_MIP405T" >include/config.h
 	@echo "Enable subset config for MIP405T"
 	@./mkconfig -a MIP405 ppc ppc4xx mip405 mpl
 ML2_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx ml2
 ml300_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx ml300 xilinx
 ocotea_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx ocotea amcc
 OCRTC_config		\
 ORSG_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx ocrtc esd
 PCI405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx pci405 esd
 PIP405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx pip405 mpl
 PLU405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx plu405 esd
 PMC405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx pmc405 esd
 PPChameleonEVB_config		\
 PPChameleonEVB_BA_25_config	\
 PPChameleonEVB_ME_25_config	\
 PPChameleonEVB_HI_25_config	\
 PPChameleonEVB_BA_33_config	\
 PPChameleonEVB_ME_33_config	\
 PPChameleonEVB_HI_33_config:	unconfig
 	@ >include/config.h
 	@[ -z "$(findstring EVB_BA,$@)" ] || \
 		{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 0" >>include/config.h ; \
 		  echo "... BASIC model" ; \
 		}
 	@[ -z "$(findstring EVB_ME,$@)" ] || \
 		{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 1" >>include/config.h ; \
 		  echo "... MEDIUM model" ; \
 		}
 	@[ -z "$(findstring EVB_HI,$@)" ] || \
 		{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 2" >>include/config.h ; \
 		  echo "... HIGH-END model" ; \
 		}
 	@[ -z "$(findstring _25,$@)" ] || \
 		{ echo "#define CONFIG_PPCHAMELEON_CLK_25" >>include/config.h ; \
 		  echo "SysClk = 25MHz" ; \
 		}
 	@[ -z "$(findstring _33,$@)" ] || \
 		{ echo "#define CONFIG_PPCHAMELEON_CLK_33" >>include/config.h ; \
 		  echo "SysClk = 33MHz" ; \
 		}
 	@./mkconfig -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave
 sbc405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx sbc405
 sycamore_config:	unconfig
 	@echo "Configuring for sycamore board as subset of walnut..."
 	@./mkconfig -a walnut ppc ppc4xx walnut amcc
 VOH405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx voh405 esd
 VOM405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx vom405 esd
 W7OLMC_config	\
 W7OLMG_config: unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx w7o
 walnut_config: unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx walnut amcc
 WUH405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx wuh405 esd
 XPEDITE1K_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx xpedite1k
 yosemite_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx yosemite amcc
 yellowstone_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx yellowstone amcc
 #########################################################################
 ## MPC8220 Systems
 #########################################################################
 Alaska8220_config	\
 Yukon8220_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8220 alaska
 sorcery_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8220 sorcery
 #########################################################################
 ## MPC824x Systems
 #########################################################################
 xtract_82xx = $(subst _BIGFLASH,,$(subst _ROMBOOT,,$(subst _L2,,$(subst _266MHz,,$(subst _300MHz,,$(subst _config,,$1))))))
 A3000_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x a3000
 BMW_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x bmw
 CPC45_config	\
 CPC45_ROMBOOT_config:	unconfig
 	@./mkconfig $(call xtract_82xx,$@) ppc mpc824x cpc45
 	@cd ./include ;				\
 	if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
 		echo "CONFIG_BOOT_ROM = y" >> config.mk ; \
 		echo "... booting from 8-bit flash" ; \
 	else \
 		echo "CONFIG_BOOT_ROM = n" >> config.mk ; \
 		echo "... booting from 64-bit flash" ; \
 	fi; \
 	echo "export CONFIG_BOOT_ROM" >> config.mk;
 CU824_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x cu824
 debris_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x debris etin
 eXalion_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x eXalion
 HIDDEN_DRAGON_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x hidden_dragon
 MOUSSE_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x mousse
 MUSENKI_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x musenki
 MVBLUE_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x mvblue
 OXC_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x oxc
 PN62_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x pn62
 Sandpoint8240_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x sandpoint
 Sandpoint8245_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x sandpoint
 sbc8240_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x sbc8240
 SL8245_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x sl8245
 utx8245_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x utx8245
 cobra5272_config :		unconfig
 	@./mkconfig $(@:_config=) m68k mcf52x2 cobra5272
 #########################################################################
 ## MPC8260 Systems
 #########################################################################
 atc_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 atc
 cogent_mpc8260_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 cogent
 CPU86_config	\
 CPU86_ROMBOOT_config: unconfig
 	@./mkconfig $(call xtract_82xx,$@) ppc mpc8260 cpu86
 	@cd ./include ;				\
 	if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
 		echo "CONFIG_BOOT_ROM = y" >> config.mk ; \
 		echo "... booting from 8-bit flash" ; \
 	else \
 		echo "CONFIG_BOOT_ROM = n" >> config.mk ; \
 		echo "... booting from 64-bit flash" ; \
 	fi; \
 	echo "export CONFIG_BOOT_ROM" >> config.mk;
 CPU87_config	\
 CPU87_ROMBOOT_config: unconfig
 	@./mkconfig $(call xtract_82xx,$@) ppc mpc8260 cpu87
 	@cd ./include ;				\
 	if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
 		echo "CONFIG_BOOT_ROM = y" >> config.mk ; \
 		echo "... booting from 8-bit flash" ; \
 	else \
 		echo "CONFIG_BOOT_ROM = n" >> config.mk ; \
 		echo "... booting from 64-bit flash" ; \
 	fi; \
 	echo "export CONFIG_BOOT_ROM" >> config.mk;
+ep8248_config	\
+ep8248E_config	:	unconfig
+	@./mkconfig ep8248 ppc mpc8260 ep8248
 ep8260_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 ep8260
 gw8260_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 gw8260
 hymod_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 hymod
 IDS8247_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 ids8247
 IPHASE4539_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 iphase4539
 ISPAN_config		\
 ISPAN_REVB_config:	unconfig
 	@if [ "$(findstring _REVB_,$@)" ] ; then \
 		echo "#define CFG_REV_B" > include/config.h ; \
 	fi
 	@./mkconfig -a ISPAN ppc mpc8260 ispan
 MPC8260ADS_config	\
 MPC8260ADS_lowboot_config	\
 MPC8260ADS_33MHz_config	\
 MPC8260ADS_33MHz_lowboot_config	\
 MPC8260ADS_40MHz_config	\
 MPC8260ADS_40MHz_lowboot_config	\
 MPC8272ADS_config	\
 MPC8272ADS_lowboot_config	\
 PQ2FADS_config		\
 PQ2FADS_lowboot_config		\
 PQ2FADS-VR_config	\
 PQ2FADS-VR_lowboot_config	\
 PQ2FADS-ZU_config	\
 PQ2FADS-ZU_lowboot_config	\
 PQ2FADS-ZU_66MHz_config	\
 PQ2FADS-ZU_66MHz_lowboot_config	\
 	:		unconfig
 	$(if $(findstring PQ2FADS,$@), \
 	@echo "#define CONFIG_ADSTYPE CFG_PQ2FADS" > include/config.h, \
 	@echo "#define CONFIG_ADSTYPE CFG_"$(subst MPC,,$(word 1,$(subst _, ,$@))) > include/config.h)
 	$(if $(findstring MHz,$@), \
 	@echo "#define CONFIG_8260_CLKIN" $(subst MHz,,$(word 2,$(subst _, ,$@)))"000000" >> include/config.h, \
 	$(if $(findstring VR,$@), \
 	@echo "#define CONFIG_8260_CLKIN 66000000" >> include/config.h))
 	@[ -z "$(findstring lowboot_,$@)" ] || \
 		{ echo "TEXT_BASE = 0xFF800000" >board/mpc8260ads/config.tmp ; \
 		  echo "... with lowboot configuration" ; \
 		}
 	@./mkconfig -a MPC8260ADS ppc mpc8260 mpc8260ads
 MPC8266ADS_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 mpc8266ads
 # PM825/PM826 default configuration:  small (= 8 MB) Flash / boot from 64-bit flash
 PM825_config	\
 PM825_ROMBOOT_config	\
 PM825_BIGFLASH_config	\
 PM825_ROMBOOT_BIGFLASH_config	\
 PM826_config	\
 PM826_ROMBOOT_config	\
 PM826_BIGFLASH_config	\
 PM826_ROMBOOT_BIGFLASH_config:	unconfig
 	@if [ "$(findstring PM825_,$@)" ] ; then \
 		echo "#define CONFIG_PCI"	>include/config.h ; \
 	else \
 		>include/config.h ; \
 	fi
 	@if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
 		echo "... booting from 8-bit flash" ; \
 		echo "#define CONFIG_BOOT_ROM" >>include/config.h ; \
 		echo "TEXT_BASE = 0xFF800000" >board/pm826/config.tmp ; \
 		if [ "$(findstring _BIGFLASH_,$@)" ] ; then \
 			echo "... with 32 MB Flash" ; \
 			echo "#define CONFIG_FLASH_32MB" >>include/config.h ; \
 		fi; \
 	else \
 		echo "... booting from 64-bit flash" ; \
 		if [ "$(findstring _BIGFLASH_,$@)" ] ; then \
 			echo "... with 32 MB Flash" ; \
 			echo "#define CONFIG_FLASH_32MB" >>include/config.h ; \
 			echo "TEXT_BASE = 0x40000000" >board/pm826/config.tmp ; \
 		else \
 			echo "TEXT_BASE = 0xFF000000" >board/pm826/config.tmp ; \
 		fi; \
 	fi
 	@./mkconfig -a PM826 ppc mpc8260 pm826
 PM828_config	\
 PM828_PCI_config	\
 PM828_ROMBOOT_config	\
 PM828_ROMBOOT_PCI_config:	unconfig
 	@if [ -z "$(findstring _PCI_,$@)" ] ; then \
 		echo "#define CONFIG_PCI"  >>include/config.h ; \
 		echo "... with PCI enabled" ; \
 	else \
 		>include/config.h ; \
 	fi
 	@if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
 		echo "... booting from 8-bit flash" ; \
 		echo "#define CONFIG_BOOT_ROM" >>include/config.h ; \
 		echo "TEXT_BASE = 0xFF800000" >board/pm826/config.tmp ; \
 	fi
 	@./mkconfig -a PM828 ppc mpc8260 pm828
 ppmc8260_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 ppmc8260
 Rattler8248_config	\
 Rattler_config:		unconfig
 	$(if $(findstring 8248,$@), \
 	@echo "#define CONFIG_MPC8248" > include/config.h)
 	@./mkconfig -a Rattler ppc mpc8260 rattler
 RPXsuper_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 rpxsuper
 rsdproto_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 rsdproto
 sacsng_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 sacsng
 sbc8260_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 sbc8260
 SCM_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 SCM siemens
 TQM8255_AA_config \
 TQM8260_AA_config \
 TQM8260_AB_config \
 TQM8260_AC_config \
 TQM8260_AD_config \
 TQM8260_AE_config \
 TQM8260_AF_config \
 TQM8260_AG_config \
 TQM8260_AH_config \
 TQM8265_AA_config:  unconfig
 	@case "$@" in \
 	TQM8255_AA_config) CTYPE=MPC8255; CFREQ=300; CACHE=no;  BMODE=8260;;  \
 	TQM8260_AA_config) CTYPE=MPC8260; CFREQ=200; CACHE=no;  BMODE=8260;; \
 	TQM8260_AB_config) CTYPE=MPC8260; CFREQ=200; CACHE=yes; BMODE=60x;;  \
 	TQM8260_AC_config) CTYPE=MPC8260; CFREQ=200; CACHE=yes; BMODE=60x;;  \
 	TQM8260_AD_config) CTYPE=MPC8260; CFREQ=300; CACHE=no;  BMODE=60x;;  \
 	TQM8260_AE_config) CTYPE=MPC8260; CFREQ=266; CACHE=no;  BMODE=8260;; \
 	TQM8260_AF_config) CTYPE=MPC8260; CFREQ=300; CACHE=no;  BMODE=60x;;  \
 	TQM8260_AG_config) CTYPE=MPC8260; CFREQ=300; CACHE=no;  BMODE=8260;; \
 	TQM8260_AH_config) CTYPE=MPC8260; CFREQ=300; CACHE=yes; BMODE=60x;;  \
 	TQM8265_AA_config) CTYPE=MPC8265; CFREQ=300; CACHE=no;  BMODE=60x;;  \
 	esac; \
 	>include/config.h ; \
 	if [ "$${CTYPE}" != "MPC8260" ] ; then \
 		echo "#define CONFIG_$${CTYPE}"	>>include/config.h ; \
 	fi; \
 	echo "#define CONFIG_$${CFREQ}MHz"	>>include/config.h ; \
 	echo "... with $${CFREQ}MHz system clock" ; \
 	if [ "$${CACHE}" == "yes" ] ; then \
 		echo "#define CONFIG_L2_CACHE"	>>include/config.h ; \
 		echo "... with L2 Cache support" ; \
 	else \
 		echo "#undef CONFIG_L2_CACHE"	>>include/config.h ; \
 		echo "... without L2 Cache support" ; \
 	fi; \
 	if [ "$${BMODE}" == "60x" ] ; then \
 		echo "#define CONFIG_BUSMODE_60x" >>include/config.h ; \
 		echo "... with 60x Bus Mode" ; \
 	else \
 		echo "#undef CONFIG_BUSMODE_60x"  >>include/config.h ; \
 		echo "... without 60x Bus Mode" ; \
 	fi
 	@./mkconfig -a TQM8260 ppc mpc8260 tqm8260
 VoVPN-GW_66MHz_config	\
 VoVPN-GW_100MHz_config:		unconfig
 	@echo "#define CONFIG_CLKIN_$(word 2,$(subst _, ,$@))" > include/config.h
 	@./mkconfig -a VoVPN-GW ppc mpc8260 vovpn-gw funkwerk
 ZPC1900_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 zpc1900
 #========================================================================
 # M68K
 #========================================================================
 #########################################################################
 ## Coldfire
 #########################################################################
 M5272C3_config :		unconfig
 	@./mkconfig $(@:_config=) m68k mcf52x2 m5272c3
 M5282EVB_config :		unconfig
 	@./mkconfig $(@:_config=) m68k mcf52x2 m5282evb
 TASREG_config :		unconfig
 	@./mkconfig $(@:_config=) m68k mcf52x2 tasreg esd
 #########################################################################
 ## MPC83xx Systems
 #########################################################################
 MPC8349ADS_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc83xx mpc8349ads
 #########################################################################
 ## MPC85xx Systems
 #########################################################################
 MPC8540ADS_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx mpc8540ads
 MPC8540EVAL_config \
 MPC8540EVAL_33_config \
 MPC8540EVAL_66_config \
 MPC8540EVAL_33_slave_config \
 MPC8540EVAL_66_slave_config:      unconfig
 	@echo "" >include/config.h ; \
 	if [ "$(findstring _33_,$@)" ] ; then \
 		echo -n "... 33 MHz PCI" ; \
 	else \
 		echo "#define CONFIG_SYSCLK_66M" >>include/config.h ; \
 		echo -n "... 66 MHz PCI" ; \
 	fi ; \
 	if [ "$(findstring _slave_,$@)" ] ; then \
 		echo "#define CONFIG_PCI_SLAVE" >>include/config.h ; \
 		echo " slave" ; \
 	else \
 		echo " host" ; \
 	fi
 	@./mkconfig -a MPC8540EVAL ppc mpc85xx mpc8540eval
 MPC8560ADS_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx mpc8560ads
 MPC8541CDS_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx mpc8541cds cds
 MPC8548CDS_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx mpc8548cds cds
 MPC8555CDS_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx mpc8555cds cds
 PM854_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx pm854
 PM856_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx pm856
 sbc8540_config \
 sbc8540_33_config \
 sbc8540_66_config:	unconfig
 	@if [ "$(findstring _66_,$@)" ] ; then \
 		echo "#define CONFIG_PCI_66"	>>include/config.h ; \
 		echo "... 66 MHz PCI" ; \
 	else \
 		>include/config.h ; \
 		echo "... 33 MHz PCI" ; \
 	fi
 	@./mkconfig -a SBC8540 ppc mpc85xx sbc8560
 sbc8560_config \
 sbc8560_33_config \
 sbc8560_66_config:      unconfig
 	@if [ "$(findstring _66_,$@)" ] ; then \
 		echo "#define CONFIG_PCI_66"	>>include/config.h ; \
 		echo "... 66 MHz PCI" ; \
 	else \
 		>include/config.h ; \
 		echo "... 33 MHz PCI" ; \
 	fi
 	@./mkconfig -a sbc8560 ppc mpc85xx sbc8560
 stxgp3_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx stxgp3
 TQM8540_config:      unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx tqm8540
 TQM8560_config:      unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx tqm8560
 #########################################################################
 ## 74xx/7xx Systems
 #########################################################################
 AmigaOneG3SE_config:	unconfig
 	@./mkconfig $(@:_config=) ppc 74xx_7xx AmigaOneG3SE MAI
 BAB7xx_config: unconfig
 	@./mkconfig $(@:_config=) ppc 74xx_7xx bab7xx eltec
 CPCI750_config:        unconfig
 	@./mkconfig CPCI750 ppc 74xx_7xx cpci750 esd
 DB64360_config:  unconfig
 	@./mkconfig DB64360 ppc 74xx_7xx db64360 Marvell
 DB64460_config:  unconfig
 	@./mkconfig DB64460 ppc 74xx_7xx db64460 Marvell
 ELPPC_config: unconfig
 	@./mkconfig $(@:_config=) ppc 74xx_7xx elppc eltec
 EVB64260_config	\
 EVB64260_750CX_config:	unconfig
 	@./mkconfig EVB64260 ppc 74xx_7xx evb64260
 P3G4_config: unconfig
 	@./mkconfig $(@:_config=) ppc 74xx_7xx evb64260
 PCIPPC2_config \
 PCIPPC6_config: unconfig
 	@./mkconfig $(@:_config=) ppc 74xx_7xx pcippc2
 ZUMA_config:	unconfig
 	@./mkconfig $(@:_config=) ppc 74xx_7xx evb64260
 #========================================================================
 # ARM
 #========================================================================
 #########################################################################
 ## StrongARM Systems
 #########################################################################
 assabet_config	:	unconfig
 	@./mkconfig $(@:_config=) arm sa1100 assabet
 dnp1110_config	:	unconfig
 	@./mkconfig $(@:_config=) arm sa1100 dnp1110
 gcplus_config	:	unconfig
 	@./mkconfig $(@:_config=) arm sa1100 gcplus
 lart_config	:	unconfig
 	@./mkconfig $(@:_config=) arm sa1100 lart
 shannon_config	:	unconfig
 	@./mkconfig $(@:_config=) arm sa1100 shannon
 #########################################################################
 ## ARM92xT Systems
 #########################################################################
 xtract_trab = $(subst _bigram,,$(subst _bigflash,,$(subst _old,,$(subst _config,,$1))))
 xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,,$(subst _cs_autoboot,,$(subst _config,,$1))))
 xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
 at91rm9200dk_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm920t at91rm9200dk NULL at91rm9200
 cmc_pu2_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
 integratorap_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm926ejs integratorap
 integratorcp_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm926ejs integratorcp
 lpd7a400_config \
 lpd7a404_config:	unconfig
 	@./mkconfig $(@:_config=) arm lh7a40x lpd7a40x
 mx1ads_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm920t mx1ads NULL imx
 mx1fs2_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm920t mx1fs2 NULL imx
 omap1510inn_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm925t omap1510inn
 omap5912osk_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm926ejs omap5912osk
 omap1610inn_config \
 omap1610inn_cs0boot_config \
 omap1610inn_cs3boot_config \
 omap1610inn_cs_autoboot_config \
 omap1610h2_config \
 omap1610h2_cs0boot_config \
 omap1610h2_cs3boot_config \
 omap1610h2_cs_autoboot_config:	unconfig
 	@if [ "$(findstring _cs0boot_, $@)" ] ; then \
 		echo "#define CONFIG_CS0_BOOT" >> ./include/config.h ; \
 		echo "... configured for CS0 boot"; \
 	elif [ "$(findstring _cs_autoboot_, $@)" ] ; then \
 		echo "#define CONFIG_CS_AUTOBOOT" >> ./include/config.h ; \
 		echo "... configured for CS_AUTO boot"; \
 	else \
 		echo "#define CONFIG_CS3_BOOT" >> ./include/config.h ; \
 		echo "... configured for CS3 boot"; \
 	fi;
 	@./mkconfig -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn
 omap730p2_config \
 omap730p2_cs0boot_config \
 omap730p2_cs3boot_config :	unconfig
 	@if [ "$(findstring _cs0boot_, $@)" ] ; then \
 		echo "#define CONFIG_CS0_BOOT" >> ./include/config.h ; \
 		echo "... configured for CS0 boot"; \
 	else \
 		echo "#define CONFIG_CS3_BOOT" >> ./include/config.h ; \
 		echo "... configured for CS3 boot"; \
 	fi;
 	@./mkconfig -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2
 scb9328_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm920t scb9328 NULL imx
 smdk2400_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm920t smdk2400 NULL s3c24x0
 smdk2410_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm920t smdk2410 NULL s3c24x0
 SX1_config :		unconfig
 	@./mkconfig $(@:_config=) arm arm925t sx1
 # TRAB default configuration:	8 MB Flash, 32 MB RAM
 trab_config \
 trab_bigram_config \
 trab_bigflash_config \
 trab_old_config:	unconfig
 	@ >include/config.h
 	@[ -z "$(findstring _bigram,$@)" ] || \
 		{ echo "#define CONFIG_FLASH_8MB"  >>include/config.h ; \
 		  echo "#define CONFIG_RAM_32MB"   >>include/config.h ; \
 		  echo "... with 8 MB Flash, 32 MB RAM" ; \
 		}
 	@[ -z "$(findstring _bigflash,$@)" ] || \
 		{ echo "#define CONFIG_FLASH_16MB" >>include/config.h ; \
 		  echo "#define CONFIG_RAM_16MB"   >>include/config.h ; \
 		  echo "... with 16 MB Flash, 16 MB RAM" ; \
 		  echo "TEXT_BASE = 0x0CF40000" >board/trab/config.tmp ; \
 		}
 	@[ -z "$(findstring _old,$@)" ] || \
 		{ echo "#define CONFIG_FLASH_8MB"  >>include/config.h ; \
 		  echo "#define CONFIG_RAM_16MB"   >>include/config.h ; \
 		  echo "... with 8 MB Flash, 16 MB RAM" ; \
 		  echo "TEXT_BASE = 0x0CF40000" >board/trab/config.tmp ; \
 		}
 	@./mkconfig -a $(call xtract_trab,$@) arm arm920t trab NULL s3c24x0
 VCMA9_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm920t vcma9 mpl s3c24x0
 versatile_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm926ejs versatile
 voiceblue_smallflash_config	\
 voiceblue_config:	unconfig
 	@if [ "$(findstring _smallflash_,$@)" ] ; then \
 		echo "... boot from lower flash bank" ; \
 		echo "#define VOICEBLUE_SMALL_FLASH" >>include/config.h ; \
 		echo "VOICEBLUE_SMALL_FLASH=y" >board/voiceblue/config.tmp ; \
 	else \
 		echo "... boot from upper flash bank" ; \
 		>include/config.h ; \
 		echo "VOICEBLUE_SMALL_FLASH=n" >board/voiceblue/config.tmp ; \
 	fi
 	@./mkconfig -a voiceblue arm arm925t voiceblue
 cm4008_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm920t cm4008 NULL ks8695
 cm41xx_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm920t cm41xx NULL ks8695
 #########################################################################
 ## S3C44B0 Systems
 #########################################################################
 B2_config	:	unconfig
 	@./mkconfig $(@:_config=) arm s3c44b0 B2 dave
 #########################################################################
 ## ARM720T Systems
 #########################################################################
 ep7312_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm720t ep7312
 impa7_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm720t impa7
 modnet50_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm720t modnet50
 evb4510_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm720t evb4510
 #########################################################################
 ## XScale Systems
 #########################################################################
 adsvix_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa adsvix
 cerf250_config :	unconfig
 	@./mkconfig $(@:_config=) arm pxa cerf250
 cradle_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa cradle
 csb226_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa csb226
 innokom_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa innokom
 ixdp425_config	:	unconfig
 	@./mkconfig $(@:_config=) arm ixp ixdp425
 lubbock_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa lubbock
 logodl_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa logodl
 wepep250_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa wepep250
 xaeniax_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa xaeniax
 xm250_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa xm250
 xsengine_config :	unconfig
 	@./mkconfig $(@:_config=) arm pxa xsengine
 #########################################################################
 ## ARM1136 Systems
 #########################################################################
 omap2420h4_config :    unconfig
 	@./mkconfig $(@:_config=) arm arm1136 omap2420h4
 #========================================================================
 # i386
 #========================================================================
 #########################################################################
 ## AMD SC520 CDP
 #########################################################################
 sc520_cdp_config	:	unconfig
 	@./mkconfig $(@:_config=) i386 i386 sc520_cdp
 sc520_spunk_config	:	unconfig
 	@./mkconfig $(@:_config=) i386 i386 sc520_spunk
 sc520_spunk_rel_config	:	unconfig
 	@./mkconfig $(@:_config=) i386 i386 sc520_spunk
 #========================================================================
 # MIPS
 #========================================================================
 #########################################################################
 ## MIPS32 4Kc
 #########################################################################
 xtract_incaip = $(subst _100MHz,,$(subst _133MHz,,$(subst _150MHz,,$(subst _config,,$1))))
 incaip_100MHz_config	\
 incaip_133MHz_config	\
 incaip_150MHz_config	\
 incaip_config: unconfig
 	@ >include/config.h
 	@[ -z "$(findstring _100MHz,$@)" ] || \
 		{ echo "#define CPU_CLOCK_RATE 100000000" >>include/config.h ; \
 		  echo "... with 100MHz system clock" ; \
 		}
 	@[ -z "$(findstring _133MHz,$@)" ] || \
 		{ echo "#define CPU_CLOCK_RATE 133000000" >>include/config.h ; \
 		  echo "... with 133MHz system clock" ; \
 		}
 	@[ -z "$(findstring _150MHz,$@)" ] || \
 		{ echo "#define CPU_CLOCK_RATE 150000000" >>include/config.h ; \
 		  echo "... with 150MHz system clock" ; \
 		}
 	@./mkconfig -a $(call xtract_incaip,$@) mips mips incaip
 tb0229_config: unconfig
 	@./mkconfig $(@:_config=) mips mips tb0229
 #########################################################################
 ## MIPS32 AU1X00
 #########################################################################
 dbau1000_config		: 	unconfig
 	@ >include/config.h
 	@echo "#define CONFIG_DBAU1000 1" >>include/config.h
 	@./mkconfig -a dbau1x00 mips mips dbau1x00
 dbau1100_config		: 	unconfig
 	@ >include/config.h
 	@echo "#define CONFIG_DBAU1100 1" >>include/config.h
 	@./mkconfig -a dbau1x00 mips mips dbau1x00
 dbau1500_config		: 	unconfig
 	@ >include/config.h
 	@echo "#define CONFIG_DBAU1500 1" >>include/config.h
 	@./mkconfig -a dbau1x00 mips mips dbau1x00
 dbau1550_config		:	unconfig
 	@ >include/config.h
 	@echo "#define CONFIG_DBAU1550 1" >>include/config.h
 	@./mkconfig -a dbau1x00 mips mips dbau1x00
 dbau1550_el_config	:	unconfig
 	@ >include/config.h
 	@echo "#define CONFIG_DBAU1550 1" >>include/config.h
 	@./mkconfig -a dbau1x00 mips mips dbau1x00 "" little
 #########################################################################
 ## MIPS64 5Kc
 #########################################################################
 purple_config :		unconfig
 	@./mkconfig $(@:_config=) mips mips purple
 #========================================================================
 # Nios
 #========================================================================
 #########################################################################
 ## Nios32
 #########################################################################
 DK1C20_safe_32_config		\
 DK1C20_standard_32_config	\
 DK1C20_config:	unconfig
 	@ >include/config.h
 	@[ -z "$(findstring _safe_32,$@)" ] || \
 		{ echo "#define CONFIG_NIOS_SAFE_32 1" >>include/config.h ; \
 		  echo "... NIOS 'safe_32' configuration" ; \
 		}
 	@[ -z "$(findstring _standard_32,$@)" ] || \
 		{ echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \
 		  echo "... NIOS 'standard_32' configuration" ; \
 		}
 	@[ -z "$(findstring DK1C20_config,$@)" ] || \
 		{ echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \
 		  echo "... NIOS 'standard_32' configuration (DEFAULT)" ; \
 		}
 	@./mkconfig -a DK1C20 nios nios dk1c20 altera
 DK1S10_safe_32_config		\
 DK1S10_standard_32_config	\
 DK1S10_mtx_ldk_20_config	\
 DK1S10_config:	unconfig
 	@ >include/config.h
 	@[ -z "$(findstring _safe_32,$@)" ] || \
 		{ echo "#define CONFIG_NIOS_SAFE_32 1" >>include/config.h ; \
 		  echo "... NIOS 'safe_32' configuration" ; \
 		}
 	@[ -z "$(findstring _standard_32,$@)" ] || \
 		{ echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \
 		  echo "... NIOS 'standard_32' configuration" ; \
 		}
 	@[ -z "$(findstring _mtx_ldk_20,$@)" ] || \
 		{ echo "#define CONFIG_NIOS_MTX_LDK_20 1" >>include/config.h ; \
 		  echo "... NIOS 'mtx_ldk_20' configuration" ; \
 		}
 	@[ -z "$(findstring DK1S10_config,$@)" ] || \
 		{ echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \
 		  echo "... NIOS 'standard_32' configuration (DEFAULT)" ; \
 		}
 	@./mkconfig -a DK1S10 nios nios dk1s10 altera
 ADNPESC1_DNPEVA2_base_32_config	\
 ADNPESC1_base_32_config		\
 ADNPESC1_config: unconfig
 	@ >include/config.h
 	@[ -z "$(findstring _DNPEVA2,$@)" ] || \
 		{ echo "#define CONFIG_DNPEVA2 1" >>include/config.h ; \
 		  echo "... DNP/EVA2 configuration" ; \
 		}
 	@[ -z "$(findstring _base_32,$@)" ] || \
 		{ echo "#define CONFIG_NIOS_BASE_32 1" >>include/config.h ; \
 		  echo "... NIOS 'base_32' configuration" ; \
 		}
 	@[ -z "$(findstring ADNPESC1_config,$@)" ] || \
 		{ echo "#define CONFIG_NIOS_BASE_32 1" >>include/config.h ; \
 		  echo "... NIOS 'base_32' configuration (DEFAULT)" ; \
 		}
 	@./mkconfig -a ADNPESC1 nios nios adnpesc1 ssv
 #########################################################################
 ## Nios-II
 #########################################################################
 PK1C20_config : unconfig
 	@./mkconfig  PK1C20 nios2 nios2 pk1c20 psyent
 PCI5441_config : unconfig
 	@./mkconfig  PCI5441 nios2 nios2 pci5441 psyent
 #========================================================================
 # MicroBlaze
 #========================================================================
 #########################################################################
 ## Microblaze
 #########################################################################
 suzaku_config:	unconfig
 	@ >include/config.h
 	@echo "#define CONFIG_SUZAKU 1" >> include/config.h
 	@./mkconfig -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno
 #########################################################################
 #########################################################################
 clean:
 	find . -type f \
 		\( -name 'core' -o -name '*.bak' -o -name '*~' \
 		-o -name '*.o'  -o -name '*.a'  \) -print \
 		| xargs rm -f
 	rm -f examples/hello_world examples/timer \
 	      examples/eepro100_eeprom examples/sched \
 	      examples/mem_to_mem_idma2intr examples/82559_eeprom \
 	      examples/test_burst
 	rm -f tools/img2srec tools/mkimage tools/envcrc tools/gen_eth_addr
 	rm -f tools/mpc86x_clk tools/ncb
 	rm -f tools/easylogo/easylogo tools/bmp_logo
 	rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend
 	rm -f tools/env/fw_printenv tools/env/fw_setenv
 	rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image
 	rm -f board/trab/trab_fkt
 clobber:	clean
 	find . -type f \( -name .depend \
 		-o -name '*.srec' -o -name '*.bin' -o -name u-boot.img \) \
 		-print0 \
 		| xargs -0 rm -f
 	rm -f $(OBJS) *.bak tags TAGS
 	rm -fr *.*~
 	rm -f u-boot u-boot.map u-boot.hex $(ALL)
 	rm -f tools/crc32.c tools/environment.c tools/env/crc32.c
 	rm -f tools/inca-swap-bytes cpu/mpc824x/bedbug_603e.c
 	rm -f include/asm/proc include/asm/arch include/asm
 mrproper \
 distclean:	clobber unconfig
 backup:
 	F=`basename $(TOPDIR)` ; cd .. ; \
 	gtar --force-local -zcvf `date "+$$F-%Y-%m-%d-%T.tar.gz"` $$F
 #########################################################################

board/amcc/bamboo/bamboo.c

Diff comments View file @ f901a83

 /*
  * (C) Copyright 2005
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #include <common.h>
 #include <asm/processor.h>
 #include <spd_sdram.h>
 #include <ppc440.h>
 #include "bamboo.h"
 void ext_bus_cntlr_init(void);
 void configure_ppc440ep_pins(void);
 gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
 #if 0
-{                                          /* GPIO   Alternate1       Alternate2        Alternate3 */
+{	   /* GPIO   Alternate1	      Alternate2	Alternate3 */
-	{
+    {
-		/* GPIO Core 0 */
+	/* GPIO Core 0 */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0  -> EBC_ADDR(7)      DMA_REQ(2) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0	-> EBC_ADDR(7)	    DMA_REQ(2) */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1  -> EBC_ADDR(6)      DMA_ACK(2) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1	-> EBC_ADDR(6)	    DMA_ACK(2) */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2  -> EBC_ADDR(5)      DMA_EOT/TC(2) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2	-> EBC_ADDR(5)	    DMA_EOT/TC(2) */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3  -> EBC_ADDR(4)      DMA_REQ(3) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3	-> EBC_ADDR(4)	    DMA_REQ(3) */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4  -> EBC_ADDR(3)      DMA_ACK(3) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4	-> EBC_ADDR(3)	    DMA_ACK(3) */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6  -> EBC_CS_N(1) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6	-> EBC_CS_N(1) */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7  -> EBC_CS_N(2) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7	-> EBC_CS_N(2) */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8  -> EBC_CS_N(3) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8	-> EBC_CS_N(3) */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9  -> EBC_CS_N(4) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9	 -> EBC_CS_N(4) */
-		{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
+	{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 ->                  USB2D_RXVALID */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 ->		    USB2D_RXVALID */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ      USB2D_RXERROR */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ	    USB2D_RXERROR */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 ->                  USB2D_TXVALID */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 ->		    USB2D_TXVALID */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA     USB2D_PAD_SUSPNDM */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA	    USB2D_PAD_SUSPNDM */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK      USB2D_XCVRSELECT */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK	    USB2D_XCVRSELECT */
-		{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ   USB2D_TERMSELECT */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ   USB2D_TERMSELECT */
-			},
+    },
-	{
+    {
-		/* GPIO Core 1 */
+	/* GPIO Core 1 */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0  -> USB2D_OPMODE0 */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0	-> USB2D_OPMODE0 */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1  -> USB2D_OPMODE1 */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1	-> USB2D_OPMODE1 */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2  -> UART0_DCD_N      UART1_DSR_CTS_N   UART2_SOUT */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2	-> UART0_DCD_N	    UART1_DSR_CTS_N   UART2_SOUT */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3  -> UART0_8PIN_DSR_N UART1_RTS_DTR_N   UART2_SIN */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3	-> UART0_8PIN_DSR_N UART1_RTS_DTR_N   UART2_SIN */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4  -> UART0_8PIN_CTS_N                   UART3_SIN */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4	-> UART0_8PIN_CTS_N		      UART3_SIN */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5  -> UART0_RTS_N */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5	-> UART0_RTS_N */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6  -> UART0_DTR_N      UART1_SOUT */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6	-> UART0_DTR_N	    UART1_SOUT */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7  -> UART0_RI_N       UART1_SIN */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7	-> UART0_RI_N	    UART1_SIN */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8  -> UIC_IRQ(0) */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8	-> UIC_IRQ(0) */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9  -> UIC_IRQ(1) */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9	-> UIC_IRQ(1) */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4)       DMA_ACK(1) */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4)	    DMA_ACK(1) */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6)       DMA_EOT/TC(1) */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6)	    DMA_EOT/TC(1) */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7)       DMA_REQ(0) */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7)	    DMA_REQ(0) */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8)       DMA_ACK(0) */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8)	    DMA_ACK(0) */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9)       DMA_EOT/TC(0) */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9)	    DMA_EOT/TC(0) */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 ->  | */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 ->  | */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 ->  | */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 ->  | */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 ->  | */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 ->   \     Can be unselected thru TraceSelect Bit */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 ->   \	   Can be unselected thru TraceSelect Bit */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 ->   /        in PowerPC440EP Chip */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 ->   /	      in PowerPC440EP Chip */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 ->  | */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 ->  | */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 ->  | */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 ->  | */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 ->  | */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 ->  | */
-		{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
-			}
+    }
 };
 #endif
 /*----------------------------------------------------------------------------+
   | EBC Devices Characteristics
-  |   Peripheral Bank Access Parameters       -   EBC0_BnAP
+  |   Peripheral Bank Access Parameters	      -	  EBC0_BnAP
-  |   Peripheral Bank Configuration Register  -   EBC0_BnCR
+  |   Peripheral Bank Configuration Register  -	  EBC0_BnCR
   +----------------------------------------------------------------------------*/
 /* Small Flash */
-#define EBC0_BNAP_SMALL_FLASH           EBC0_BNAP_BME_DISABLED      |	\
+#define EBC0_BNAP_SMALL_FLASH				\
-	EBC0_BNAP_TWT_ENCODE(6)     |					\
+	EBC0_BNAP_BME_DISABLED			|	\
-	EBC0_BNAP_CSN_ENCODE(0)     |					\
+	EBC0_BNAP_TWT_ENCODE(6)			|	\
-	EBC0_BNAP_OEN_ENCODE(1)     |					\
+	EBC0_BNAP_CSN_ENCODE(0)	    		|	\
-	EBC0_BNAP_WBN_ENCODE(1)     |					\
+	EBC0_BNAP_OEN_ENCODE(1)	    		|	\
-	EBC0_BNAP_WBF_ENCODE(3)     |					\
+	EBC0_BNAP_WBN_ENCODE(1)	    		|	\
-	EBC0_BNAP_TH_ENCODE(1)      |					\
+	EBC0_BNAP_WBF_ENCODE(3)	    		|	\
-	EBC0_BNAP_RE_ENABLED        |					\
+	EBC0_BNAP_TH_ENCODE(1)	    		|	\
-	EBC0_BNAP_SOR_DELAYED       |					\
+	EBC0_BNAP_RE_ENABLED	    		|	\
-	EBC0_BNAP_BEM_WRITEONLY     |					\
+	EBC0_BNAP_SOR_DELAYED	    		|	\
+	EBC0_BNAP_BEM_WRITEONLY	    		|	\
 	EBC0_BNAP_PEN_DISABLED
-#define EBC0_BNCR_SMALL_FLASH_CS0       EBC0_BNCR_BAS_ENCODE(0xFFF00000)    | \
+#define EBC0_BNCR_SMALL_FLASH_CS0			\
-	EBC0_BNCR_BS_1MB                    |				\
+	EBC0_BNCR_BAS_ENCODE(0xFFF00000)    	| 	\
-	EBC0_BNCR_BU_RW                     |				\
+	EBC0_BNCR_BS_1MB		    	|	\
+	EBC0_BNCR_BU_RW			    	|	\
 	EBC0_BNCR_BW_8BIT
-#define EBC0_BNCR_SMALL_FLASH_CS4       EBC0_BNCR_BAS_ENCODE(0x87800000)    | \
+#define EBC0_BNCR_SMALL_FLASH_CS4			\
-	EBC0_BNCR_BS_8MB                    |				\
+	EBC0_BNCR_BAS_ENCODE(0x87800000)    	| 	\
-	EBC0_BNCR_BU_RW                     |				\
+	EBC0_BNCR_BS_8MB		    	|	\
+	EBC0_BNCR_BU_RW			    	|	\
 	EBC0_BNCR_BW_16BIT
 /* Large Flash or SRAM */
-#define EBC0_BNAP_LARGE_FLASH_OR_SRAM   EBC0_BNAP_BME_DISABLED      |	\
+#define EBC0_BNAP_LARGE_FLASH_OR_SRAM			\
-	EBC0_BNAP_TWT_ENCODE(8)     |					\
+	EBC0_BNAP_BME_DISABLED	    		|	\
-	EBC0_BNAP_CSN_ENCODE(0)     |					\
+	EBC0_BNAP_TWT_ENCODE(8)	    		|	\
-	EBC0_BNAP_OEN_ENCODE(1)     |					\
+	EBC0_BNAP_CSN_ENCODE(0)	    		|	\
-	EBC0_BNAP_WBN_ENCODE(1)     |					\
+	EBC0_BNAP_OEN_ENCODE(1)	    		|	\
-	EBC0_BNAP_WBF_ENCODE(1)     |					\
+	EBC0_BNAP_WBN_ENCODE(1)	    		|	\
-	EBC0_BNAP_TH_ENCODE(2)      |					\
+	EBC0_BNAP_WBF_ENCODE(1)	    		|	\
-	EBC0_BNAP_SOR_DELAYED       |					\
+	EBC0_BNAP_TH_ENCODE(2)	    		|	\
-	EBC0_BNAP_BEM_RW            |					\
+	EBC0_BNAP_SOR_DELAYED	    		|	\
+	EBC0_BNAP_BEM_RW	    		|	\
 	EBC0_BNAP_PEN_DISABLED
-#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0   EBC0_BNCR_BAS_ENCODE(0xFF800000)    | \
+#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0   		\
-	EBC0_BNCR_BS_8MB                    |				\
+	EBC0_BNCR_BAS_ENCODE(0xFF800000)	| 	\
-	EBC0_BNCR_BU_RW                     |				\
+	EBC0_BNCR_BS_8MB		    	|	\
+	EBC0_BNCR_BU_RW			    	|	\
 	EBC0_BNCR_BW_16BIT
-#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4   EBC0_BNCR_BAS_ENCODE(0x87800000)    | \
+#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4   		\
-	EBC0_BNCR_BS_8MB                    |				\
+	EBC0_BNCR_BAS_ENCODE(0x87800000)	| 	\
-	EBC0_BNCR_BU_RW                     |				\
+	EBC0_BNCR_BS_8MB		    	|	\
+	EBC0_BNCR_BU_RW			    	|	\
 	EBC0_BNCR_BW_16BIT
 /* NVRAM - FPGA */
-#define EBC0_BNAP_NVRAM_FPGA            EBC0_BNAP_BME_DISABLED      |	\
+#define EBC0_BNAP_NVRAM_FPGA				\
-	EBC0_BNAP_TWT_ENCODE(9)     |					\
+	EBC0_BNAP_BME_DISABLED	    		|	\
-	EBC0_BNAP_CSN_ENCODE(0)     |					\
+	EBC0_BNAP_TWT_ENCODE(9)	    		|	\
-	EBC0_BNAP_OEN_ENCODE(1)     |					\
+	EBC0_BNAP_CSN_ENCODE(0)	    		|	\
-	EBC0_BNAP_WBN_ENCODE(1)     |					\
+	EBC0_BNAP_OEN_ENCODE(1)	    		|	\
-	EBC0_BNAP_WBF_ENCODE(0)     |					\
+	EBC0_BNAP_WBN_ENCODE(1)	    		|	\
-	EBC0_BNAP_TH_ENCODE(2)      |					\
+	EBC0_BNAP_WBF_ENCODE(0)	    		|	\
-	EBC0_BNAP_RE_ENABLED        |					\
+	EBC0_BNAP_TH_ENCODE(2)	    		|	\
-	EBC0_BNAP_SOR_DELAYED       |					\
+	EBC0_BNAP_RE_ENABLED	    		|	\
-	EBC0_BNAP_BEM_WRITEONLY     |					\
+	EBC0_BNAP_SOR_DELAYED	    		|	\
+	EBC0_BNAP_BEM_WRITEONLY	    		|	\
 	EBC0_BNAP_PEN_DISABLED
-#define EBC0_BNCR_NVRAM_FPGA_CS5        EBC0_BNCR_BAS_ENCODE(0x80000000)    | \
+#define EBC0_BNCR_NVRAM_FPGA_CS5			\
-	EBC0_BNCR_BS_1MB                    |				\
+	EBC0_BNCR_BAS_ENCODE(0x80000000)    	| 	\
-	EBC0_BNCR_BU_RW                     |				\
+	EBC0_BNCR_BS_1MB		    	|	\
+	EBC0_BNCR_BU_RW			    	|	\
 	EBC0_BNCR_BW_8BIT
 /* Nand Flash */
-#define EBC0_BNAP_NAND_FLASH            EBC0_BNAP_BME_DISABLED      |	\
+#define EBC0_BNAP_NAND_FLASH				\
-	EBC0_BNAP_TWT_ENCODE(3)     |					\
+	EBC0_BNAP_BME_DISABLED	    		|	\
-	EBC0_BNAP_CSN_ENCODE(0)     |					\
+	EBC0_BNAP_TWT_ENCODE(3)	    		|	\
-	EBC0_BNAP_OEN_ENCODE(0)     |					\
+	EBC0_BNAP_CSN_ENCODE(0)	    		|	\
-	EBC0_BNAP_WBN_ENCODE(0)     |					\
+	EBC0_BNAP_OEN_ENCODE(0)	    		|	\
-	EBC0_BNAP_WBF_ENCODE(0)     |					\
+	EBC0_BNAP_WBN_ENCODE(0)	    		|	\
-	EBC0_BNAP_TH_ENCODE(1)      |					\
+	EBC0_BNAP_WBF_ENCODE(0)	    		|	\
-	EBC0_BNAP_RE_ENABLED        |					\
+	EBC0_BNAP_TH_ENCODE(1)	    		|	\
-	EBC0_BNAP_SOR_NOT_DELAYED   |					\
+	EBC0_BNAP_RE_ENABLED	    		|	\
-	EBC0_BNAP_BEM_RW            |					\
+	EBC0_BNAP_SOR_NOT_DELAYED   		|	\
+	EBC0_BNAP_BEM_RW	    		|	\
 	EBC0_BNAP_PEN_DISABLED
-#define EBC0_BNCR_NAND_FLASH_CS0        0xB8400000
+#define EBC0_BNCR_NAND_FLASH_CS0	0xB8400000
 /* NAND0 */
-#define EBC0_BNCR_NAND_FLASH_CS1        EBC0_BNCR_BAS_ENCODE(0x90000000)    | \
+#define EBC0_BNCR_NAND_FLASH_CS1			\
-	EBC0_BNCR_BS_1MB                    |				\
+	EBC0_BNCR_BAS_ENCODE(0x90000000)    	| 	\
-	EBC0_BNCR_BU_RW                     |				\
+	EBC0_BNCR_BS_1MB		    	|	\
+	EBC0_BNCR_BU_RW			    	|	\
 	EBC0_BNCR_BW_32BIT
 /* NAND1 - Bank2 */
-#define EBC0_BNCR_NAND_FLASH_CS2        EBC0_BNCR_BAS_ENCODE(0x94000000)    | \
+#define EBC0_BNCR_NAND_FLASH_CS2			\
-	EBC0_BNCR_BS_1MB                    |				\
+	EBC0_BNCR_BAS_ENCODE(0x94000000)    	| 	\
-	EBC0_BNCR_BU_RW                     |				\
+	EBC0_BNCR_BS_1MB		    	|	\
+	EBC0_BNCR_BU_RW			    	|	\
 	EBC0_BNCR_BW_32BIT
 /* NAND1 - Bank3 */
-#define EBC0_BNCR_NAND_FLASH_CS3        EBC0_BNCR_BAS_ENCODE(0x94000000)    | \
+#define EBC0_BNCR_NAND_FLASH_CS3			\
-	EBC0_BNCR_BS_1MB                    |				\
+	EBC0_BNCR_BAS_ENCODE(0x94000000)    	| 	\
-	EBC0_BNCR_BU_RW                     |				\
+	EBC0_BNCR_BS_1MB		    	|	\
+	EBC0_BNCR_BU_RW			    	|	\
 	EBC0_BNCR_BW_32BIT
 int board_early_init_f(void)
 {
 	ext_bus_cntlr_init();
 	/*--------------------------------------------------------------------
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 *-------------------------------------------------------------------*/
 	mtdcr(uic0sr, 0xffffffff);	/* clear all */
 	mtdcr(uic0er, 0x00000000);	/* disable all */
 	mtdcr(uic0cr, 0x00000009);	/* ATI & UIC1 crit are critical */
 	mtdcr(uic0pr, 0xfffffe13);	/* per ref-board manual */
 	mtdcr(uic0tr, 0x01c00008);	/* per ref-board manual */
 	mtdcr(uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
 	mtdcr(uic0sr, 0xffffffff);	/* clear all */
 	mtdcr(uic1sr, 0xffffffff);	/* clear all */
 	mtdcr(uic1er, 0x00000000);	/* disable all */
 	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
 	mtdcr(uic1pr, 0xffffe0ff);	/* per ref-board manual */
 	mtdcr(uic1tr, 0x00ffc000);	/* per ref-board manual */
 	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
 	mtdcr(uic1sr, 0xffffffff);	/* clear all */
 	/*--------------------------------------------------------------------
 	 * Setup the GPIO pins
 	 *-------------------------------------------------------------------*/
 	out32(GPIO0_OSRL,  0x00000400);
 	out32(GPIO0_OSRH,  0x00000000);
 	out32(GPIO0_TSRL,  0x00000400);
 	out32(GPIO0_TSRH,  0x00000000);
 	out32(GPIO0_ISR1L, 0x00000000);
 	out32(GPIO0_ISR1H, 0x00000000);
 	out32(GPIO0_ISR2L, 0x00000000);
 	out32(GPIO0_ISR2H, 0x00000000);
 	out32(GPIO0_ISR3L, 0x00000000);
 	out32(GPIO0_ISR3H, 0x00000000);
 	out32(GPIO1_OSRL,  0x0C380000);
 	out32(GPIO1_OSRH,  0x00000000);
 	out32(GPIO1_TSRL,  0x0C380000);
 	out32(GPIO1_TSRH,  0x00000000);
 	out32(GPIO1_ISR1L, 0x0FC30000);
 	out32(GPIO1_ISR1H, 0x00000000);
 	out32(GPIO1_ISR2L, 0x0C010000);
 	out32(GPIO1_ISR2H, 0x00000000);
 	out32(GPIO1_ISR3L, 0x01400000);
 	out32(GPIO1_ISR3H, 0x00000000);
 	configure_ppc440ep_pins();
 	return 0;
 }
 int checkboard(void)
 {
 	sys_info_t sysinfo;
 	unsigned char *s = getenv("serial#");
 	get_sys_info(&sysinfo);
 	printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
 	if (s != NULL) {
 		puts(", serial# ");
 		puts(s);
 	}
 	putc('\n');
 	printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
 	printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
 	printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
 	printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
 	printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
 	return (0);
 }
 /*************************************************************************
  *
  * fixed_sdram_init -- Bamboo has one bank onboard sdram (plus DIMM)
  *
  * Fixed memory is composed of :
- *      MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
+ *	MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
- *      13 row add bits, 10 column add bits (but 12 row used only).
+ *	13 row add bits, 10 column add bits (but 12 row used only).
- *      ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
+ *	ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
- *      12 row add bits, 10 column add bits.
+ *	12 row add bits, 10 column add bits.
- *      Prepare a subset (only the used ones) of SPD data
+ *	Prepare a subset (only the used ones) of SPD data
  *
- *      Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
+ *	Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
- *      the corresponding bank is divided by 2 due to number of Row addresses
+ *	the corresponding bank is divided by 2 due to number of Row addresses
- *      12 in the ECC module
+ *	12 in the ECC module
  *
- *  Assumes:    64 MB, ECC, non-registered
+ *  Assumes:	64 MB, ECC, non-registered
- *              PLB @ 133 MHz
+ *		PLB @ 133 MHz
  *
  ************************************************************************/
 void fixed_sdram_init(void)
 {
 	/*
 	 * clear this first, if the DDR is enabled by a debugger
 	 * then you can not make changes.
 	 */
 	mtsdram(mem_cfg0, 0x00000000);	/* Disable EEC */
 	/*--------------------------------------------------------------------
 	 * Setup for board-specific specific mem
 	 *------------------------------------------------------------------*/
 	/*
 	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
 	 */
 	mtsdram(mem_b0cr, 0x00082001);
 	mtsdram(mem_b1cr, 0x00000000);
 	mtsdram(mem_b2cr, 0x00000000);
 	mtsdram(mem_b3cr, 0x00000000);
 }
 long int initdram (int board_type)
 {
 	long dram_size = 0;
 	/*
 	 * First init bank0 (onboard sdram) and then configure the DIMM-slots
 	 */
 	fixed_sdram_init();
 	dram_size = spd_sdram (0);
 	return dram_size;
 }
 #if defined(CFG_DRAM_TEST)
 int testdram(void)
 {
 	unsigned long *mem = (unsigned long *)0;
 	const unsigned long kend = (1024 / sizeof(unsigned long));
 	unsigned long k, n;
 	mtmsr(0);
 	for (k = 0; k < CFG_KBYTES_SDRAM;
 	     ++k, mem += (1024 / sizeof(unsigned long))) {
 		if ((k & 1023) == 0) {
 			printf("%3d MB\r", k / 1024);
 		}
 		memset(mem, 0xaaaaaaaa, 1024);
 		for (n = 0; n < kend; ++n) {
 			if (mem[n] != 0xaaaaaaaa) {
 				printf("SDRAM test fails at: %08x\n",
 				       (uint) & mem[n]);
 				return 1;
 			}
 		}
 		memset(mem, 0x55555555, 1024);
 		for (n = 0; n < kend; ++n) {
 			if (mem[n] != 0x55555555) {
 				printf("SDRAM test fails at: %08x\n",
 				       (uint) & mem[n]);
 				return 1;
 			}
 		}
 	}
 	printf("SDRAM test passes\n");
 	return 0;
 }
 #endif
 /*************************************************************************
  *  pci_pre_init
  *
  *  This routine is called just prior to registering the hose and gives
  *  the board the opportunity to check things. Returning a value of zero
  *  indicates that things are bad & PCI initialization should be aborted.
  *
  *	Different boards may wish to customize the pci controller structure
  *	(add regions, override default access routines, etc) or perform
  *	certain pre-initialization actions.
  *
  ************************************************************************/
 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
 int pci_pre_init(struct pci_controller *hose)
 {
 	unsigned long strap;
 	unsigned long addr;
 	/*--------------------------------------------------------------------------+
 	 *	Bamboo is always configured as the host & requires the
 	 *	PCI arbiter to be enabled.
 	 *--------------------------------------------------------------------------*/
 	mfsdr(sdr_sdstp1, strap);
 	if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
 		printf("PCI: SDR0_STRP1[PAE] not set.\n");
 		printf("PCI: Configuration aborted.\n");
 		return 0;
 	}
 	/*-------------------------------------------------------------------------+
 	  | Set priority for all PLB3 devices to 0.
 	  | Set PLB3 arbiter to fair mode.
 	  +-------------------------------------------------------------------------*/
 	mfsdr(sdr_amp1, addr);
 	mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
 	addr = mfdcr(plb3_acr);
 	mtdcr(plb3_acr, addr | 0x80000000);
 	/*-------------------------------------------------------------------------+
 	  | Set priority for all PLB4 devices to 0.
 	  +-------------------------------------------------------------------------*/
 	mfsdr(sdr_amp0, addr);
 	mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
 	addr = mfdcr(plb4_acr) | 0xa0000000;	/* Was 0x8---- */
 	mtdcr(plb4_acr, addr);
 	/*-------------------------------------------------------------------------+
 	  | Set Nebula PLB4 arbiter to fair mode.
 	  +-------------------------------------------------------------------------*/
 	/* Segment0 */
 	addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
 	addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
 	addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
 	addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
 	mtdcr(plb0_acr, addr);
 	/* Segment1 */
 	addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
 	addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
 	addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
 	addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
 	mtdcr(plb1_acr, addr);
 	return 1;
 }
 #endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
 /*************************************************************************
  *  pci_target_init
  *
  *	The bootstrap configuration provides default settings for the pci
  *	inbound map (PIM). But the bootstrap config choices are limited and
  *	may not be sufficient for a given board.
  *
  ************************************************************************/
 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller *hose)
 {
 	/*--------------------------------------------------------------------------+
 	 * Set up Direct MMIO registers
 	 *--------------------------------------------------------------------------*/
 	/*--------------------------------------------------------------------------+
 	  | PowerPC440 EP PCI Master configuration.
 	  | Map one 1Gig range of PLB/processor addresses to PCI memory space.
 	  |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
 	  |   Use byte reversed out routines to handle endianess.
 	  | Make this region non-prefetchable.
 	  +--------------------------------------------------------------------------*/
 	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
 	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
 	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);	/* PMM0 PCI Low Address */
 	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
 	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
 	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
-	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
 	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
 	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
 	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
 	out32r(PCIX0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
 	out32r(PCIX0_PTM1LA, 0);	/* Local Addr. Reg */
 	out32r(PCIX0_PTM2MS, 0);	/* Memory Size/Attribute */
 	out32r(PCIX0_PTM2LA, 0);	/* Local Addr. Reg */
 	/*--------------------------------------------------------------------------+
 	 * Set up Configuration registers
 	 *--------------------------------------------------------------------------*/
 	/* Program the board's subsystem id/vendor id */
 	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
 			      CFG_PCI_SUBSYS_VENDORID);
 	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
 	/* Configure command register as bus master */
 	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
 	/* 240nS PCI clock */
 	pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
 	/* No error reporting */
 	pci_write_config_word(0, PCI_ERREN, 0);
 	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 }
 #endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 /*************************************************************************
  *  pci_master_init
  *
  ************************************************************************/
 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
 void pci_master_init(struct pci_controller *hose)
 {
 	unsigned short temp_short;
 	/*--------------------------------------------------------------------------+
 	  | Write the PowerPC440 EP PCI Configuration regs.
 	  |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
 	  |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
 	  +--------------------------------------------------------------------------*/
 	pci_read_config_word(0, PCI_COMMAND, &temp_short);
 	pci_write_config_word(0, PCI_COMMAND,
 			      temp_short | PCI_COMMAND_MASTER |
 			      PCI_COMMAND_MEMORY);
 }
 #endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
 /*************************************************************************
  *  is_pci_host
  *
  *	This routine is called to determine if a pci scan should be
  *	performed. With various hardware environments (especially cPCI and
  *	PPMC) it's insufficient to depend on the state of the arbiter enable
  *	bit in the strap register, or generic host/adapter assumptions.
  *
  *	Rather than hard-code a bad assumption in the general 440 code, the
  *	440 pci code requires the board to decide at runtime.
  *
  *	Return 0 for adapter mode, non-zero for host (monarch) mode.
  *
  *
  ************************************************************************/
 #if defined(CONFIG_PCI)
 int is_pci_host(struct pci_controller *hose)
 {
 	/* Bamboo is always configured as host. */
 	return (1);
 }
 #endif				/* defined(CONFIG_PCI) */
 /*----------------------------------------------------------------------------+
   | is_powerpc440ep_pass1.
   +----------------------------------------------------------------------------*/
 int is_powerpc440ep_pass1(void)
 {
 	unsigned long pvr;
 	pvr = get_pvr();
 	if (pvr == PVR_POWERPC_440EP_PASS1)
 		return TRUE;
 	else if (pvr == PVR_POWERPC_440EP_PASS2)
 		return FALSE;
 	else {
 		printf("brdutil error 3\n");
 		for (;;)
 			;
 	}
 	return(FALSE);
 }
 /*----------------------------------------------------------------------------+
   | is_nand_selected.
   +----------------------------------------------------------------------------*/
 int is_nand_selected(void)
 {
 	return FALSE; /* test-only */
 }
 /*----------------------------------------------------------------------------+
   | config_on_ebc_cs4_is_small_flash => from EPLD
   +----------------------------------------------------------------------------*/
 unsigned char config_on_ebc_cs4_is_small_flash(void)
 {
 	/* Not implemented yet => returns constant value */
 	return TRUE;
 }
 /*----------------------------------------------------------------------------+
   | Ext_bus_cntlr_init.
   | Initialize the external bus controller
   +----------------------------------------------------------------------------*/
 void ext_bus_cntlr_init(void)
 {
 	unsigned long sdr0_pstrp0, sdr0_sdstp1;
 	unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
-	int           computed_boot_device = BOOT_DEVICE_UNKNOWN;
+	int	      computed_boot_device = BOOT_DEVICE_UNKNOWN;
 	unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
 	unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
 	unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
 	unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
 	unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
 	/*-------------------------------------------------------------------------+
 	  |
 	  |  PART 1 : Initialize EBC Bank 5
 	  |  ==============================
 	  | Bank5 is always associated to the NVRAM/EPLD.
 	  | It has to be initialized prior to other banks settings computation since
 	  | some board registers values may be needed
 	  |
 	  +-------------------------------------------------------------------------*/
 	/* NVRAM - FPGA */
 	mtebc(pb5ap, EBC0_BNAP_NVRAM_FPGA);
 	mtebc(pb5cr, EBC0_BNCR_NVRAM_FPGA_CS5);
 	/*-------------------------------------------------------------------------+
 	  |
 	  |  PART 2 : Determine which boot device was selected
 	  |  =========================================
 	  |
 	  |  Read Pin Strap Register in PPC440EP
 	  |  In case of boot from IIC, read Serial Device Strap Register1
 	  |
 	  |  Result can either be :
 	  |   - Boot from EBC 8bits    => SMALL FLASH
 	  |   - Boot from EBC 16bits   => Large Flash or SRAM
 	  |   - Boot from NAND Flash
 	  |   - Boot from PCI
 	  |
 	  +-------------------------------------------------------------------------*/
 	/* Read Pin Strap Register in PPC440EP */
 	mfsdr(sdr_pstrp0, sdr0_pstrp0);
 	bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
 	/*-------------------------------------------------------------------------+
 	  |  PPC440EP Pass1
 	  +-------------------------------------------------------------------------*/
 	if (is_powerpc440ep_pass1() == TRUE) {
 		switch(bootstrap_settings) {
 		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
 			/* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
 			/* Boot from Small Flash */
 			computed_boot_device = BOOT_FROM_SMALL_FLASH;
 			break;
 		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
 			/* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
 			/* Boot from PCI */
 			computed_boot_device = BOOT_FROM_PCI;
 			break;
 		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
 			/* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
 			/* Boot from Nand Flash */
 			computed_boot_device = BOOT_FROM_NAND_FLASH0;
 			break;
 		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
 			/* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
 			/* Boot from Small Flash */
 			computed_boot_device = BOOT_FROM_SMALL_FLASH;
 			break;
 		case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
 		case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
 			/* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
 			/* Read Serial Device Strap Register1 in PPC440EP */
 			mfsdr(sdr_sdstp1, sdr0_sdstp1);
-			boot_selection  = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
+			boot_selection	= sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
-			ebc_boot_size   = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
+			ebc_boot_size	= sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
 			switch(boot_selection) {
 			case SDR0_SDSTP1_BOOT_SEL_EBC:
 				switch(ebc_boot_size) {
 				case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
 					computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
 					break;
 				case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
 					computed_boot_device = BOOT_FROM_SMALL_FLASH;
 					break;
 				}
 				break;
 			case SDR0_SDSTP1_BOOT_SEL_PCI:
 				computed_boot_device = BOOT_FROM_PCI;
 				break;
 			case SDR0_SDSTP1_BOOT_SEL_NDFC:
 				computed_boot_device = BOOT_FROM_NAND_FLASH0;
 				break;
 			}
 			break;
 		}
 	}
 	/*-------------------------------------------------------------------------+
 	  |  PPC440EP Pass2
 	  +-------------------------------------------------------------------------*/
 	else {
 		switch(bootstrap_settings) {
 		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
 			/* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
 			/* Boot from Small Flash */
 			computed_boot_device = BOOT_FROM_SMALL_FLASH;
 			break;
 		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
 			/* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
 			/* Boot from PCI */
 			computed_boot_device = BOOT_FROM_PCI;
 			break;
 		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
 			/* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
 			/* Boot from Nand Flash */
 			computed_boot_device = BOOT_FROM_NAND_FLASH0;
 			break;
 		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
 			/* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
 			/* Boot from Large Flash or SRAM */
 			computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
 			break;
 		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
 			/* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
 			/* Boot from Large Flash or SRAM */
 			computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
 			break;
 		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
 			/* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
 			/* Boot from PCI */
 			computed_boot_device = BOOT_FROM_PCI;
 			break;
 		case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
 		case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
 			/* Default Strap Settings 5-7 */
 			/* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
 			/* Read Serial Device Strap Register1 in PPC440EP */
 			mfsdr(sdr_sdstp1, sdr0_sdstp1);
-			boot_selection  = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
+			boot_selection	= sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
-			ebc_boot_size   = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
+			ebc_boot_size	= sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
 			switch(boot_selection) {
 			case SDR0_SDSTP1_BOOT_SEL_EBC:
 				switch(ebc_boot_size) {
 				case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
 					computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
 					break;
 				case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
 					computed_boot_device = BOOT_FROM_SMALL_FLASH;
 					break;
 				}
 				break;
 			case SDR0_SDSTP1_BOOT_SEL_PCI:
 				computed_boot_device = BOOT_FROM_PCI;
 				break;
 			case SDR0_SDSTP1_BOOT_SEL_NDFC:
 				computed_boot_device = BOOT_FROM_NAND_FLASH0;
 				break;
 			}
 			break;
 		}
 	}
 	/*-------------------------------------------------------------------------+
 	  |
 	  |  PART 3 : Compute EBC settings depending on selected boot device
 	  |  ======   ======================================================
 	  |
 	  | Resulting EBC init will be among following configurations :
 	  |
 	  |  - Boot from EBC 8bits => boot from SMALL FLASH selected
-	  |            EBC-CS0     = Small Flash
+	  |	       EBC-CS0	   = Small Flash
-	  |            EBC-CS1,2,3 = NAND Flash or
+	  |	       EBC-CS1,2,3 = NAND Flash or
-	  |                         Exp.Slot depending on Soft Config
+	  |			    Exp.Slot depending on Soft Config
-	  |            EBC-CS4     = SRAM/Large Flash or
+	  |	       EBC-CS4	   = SRAM/Large Flash or
-	  |                         Large Flash/SRAM depending on jumpers
+	  |			    Large Flash/SRAM depending on jumpers
-	  |            EBC-CS5     = NVRAM / EPLD
+	  |	       EBC-CS5	   = NVRAM / EPLD
 	  |
 	  |  - Boot from EBC 16bits => boot from Large Flash or SRAM selected
-	  |            EBC-CS0     = SRAM/Large Flash or
+	  |	       EBC-CS0	   = SRAM/Large Flash or
-	  |                          Large Flash/SRAM depending on jumpers
+	  |			     Large Flash/SRAM depending on jumpers
-	  |            EBC-CS1,2,3 = NAND Flash or
+	  |	       EBC-CS1,2,3 = NAND Flash or
-	  |                          Exp.Slot depending on Software Configuration
+	  |			     Exp.Slot depending on Software Configuration
-	  |            EBC-CS4     = Small Flash
+	  |	       EBC-CS4	   = Small Flash
-	  |            EBC-CS5     = NVRAM / EPLD
+	  |	       EBC-CS5	   = NVRAM / EPLD
 	  |
 	  |  - Boot from NAND Flash
-	  |            EBC-CS0     = NAND Flash0
+	  |	       EBC-CS0	   = NAND Flash0
-	  |            EBC-CS1,2,3 = NAND Flash1
+	  |	       EBC-CS1,2,3 = NAND Flash1
-	  |            EBC-CS4     = SRAM/Large Flash or
+	  |	       EBC-CS4	   = SRAM/Large Flash or
-	  |                          Large Flash/SRAM depending on jumpers
+	  |			     Large Flash/SRAM depending on jumpers
-	  |            EBC-CS5     = NVRAM / EPLD
+	  |	       EBC-CS5	   = NVRAM / EPLD
 	  |
 	  |    - Boot from PCI
-	  |            EBC-CS0     = ...
+	  |	       EBC-CS0	   = ...
-	  |            EBC-CS1,2,3 = NAND Flash or
+	  |	       EBC-CS1,2,3 = NAND Flash or
-	  |                          Exp.Slot depending on Software Configuration
+	  |			     Exp.Slot depending on Software Configuration
-	  |            EBC-CS4     = SRAM/Large Flash or
+	  |	       EBC-CS4	   = SRAM/Large Flash or
-	  |                          Large Flash/SRAM or
+	  |			     Large Flash/SRAM or
-	  |                          Small Flash depending on jumpers
+	  |			     Small Flash depending on jumpers
-	  |            EBC-CS5     = NVRAM / EPLD
+	  |	       EBC-CS5	   = NVRAM / EPLD
 	  |
 	  +-------------------------------------------------------------------------*/
 	switch(computed_boot_device) {
 		/*------------------------------------------------------------------------- */
-        case BOOT_FROM_SMALL_FLASH:
+	case BOOT_FROM_SMALL_FLASH:
 		/*------------------------------------------------------------------------- */
 		ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
 		ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
 		if ((is_nand_selected()) == TRUE) {
 			/* NAND Flash */
 			ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
 			ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
 			/*ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
 			  ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
 			  ebc0_cs3_bnap_value = EBC0_BNAP_NAND_FLASH;
 			  ebc0_cs3_bncr_value = EBC0_BNCR_NAND_FLASH_CS3;*/
 			ebc0_cs2_bnap_value = 0;
 			ebc0_cs2_bncr_value = 0;
 			ebc0_cs3_bnap_value = 0;
 			ebc0_cs3_bncr_value = 0;
 		} else {
 			/* Expansion Slot */
 			ebc0_cs1_bnap_value = 0;
 			ebc0_cs1_bncr_value = 0;
 			ebc0_cs2_bnap_value = 0;
 			ebc0_cs2_bncr_value = 0;
 			ebc0_cs3_bnap_value = 0;
 			ebc0_cs3_bncr_value = 0;
 		}
 		ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
 		ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
 		break;
 		/*------------------------------------------------------------------------- */
-        case BOOT_FROM_LARGE_FLASH_OR_SRAM:
+	case BOOT_FROM_LARGE_FLASH_OR_SRAM:
 		/*------------------------------------------------------------------------- */
 		ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
 		ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
 		if ((is_nand_selected()) == TRUE) {
 			/* NAND Flash */
 			ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
 			ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
 			ebc0_cs2_bnap_value = 0;
 			ebc0_cs2_bncr_value = 0;
 			ebc0_cs3_bnap_value = 0;
 			ebc0_cs3_bncr_value = 0;
 		} else {
 			/* Expansion Slot */
 			ebc0_cs1_bnap_value = 0;
 			ebc0_cs1_bncr_value = 0;
 			ebc0_cs2_bnap_value = 0;
 			ebc0_cs2_bncr_value = 0;
 			ebc0_cs3_bnap_value = 0;
 			ebc0_cs3_bncr_value = 0;
 		}
 		ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
 		ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
 		break;
 		/*------------------------------------------------------------------------- */
-        case BOOT_FROM_NAND_FLASH0:
+	case BOOT_FROM_NAND_FLASH0:
 		/*------------------------------------------------------------------------- */
 		ebc0_cs0_bnap_value = 0;
 		ebc0_cs0_bncr_value = 0;
 		ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
 		ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
 		ebc0_cs2_bnap_value = 0;
 		ebc0_cs2_bncr_value = 0;
 		ebc0_cs3_bnap_value = 0;
 		ebc0_cs3_bncr_value = 0;
 		/* Large Flash or SRAM */
 		ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
 		ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
 		break;
 		/*------------------------------------------------------------------------- */
-        case BOOT_FROM_PCI:
+	case BOOT_FROM_PCI:
 		/*------------------------------------------------------------------------- */
 		ebc0_cs0_bnap_value = 0;
 		ebc0_cs0_bncr_value = 0;
 		if ((is_nand_selected()) == TRUE) {
 			/* NAND Flash */
 			ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
 			ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
 			ebc0_cs2_bnap_value = 0;
 			ebc0_cs2_bncr_value = 0;
 			ebc0_cs3_bnap_value = 0;
 			ebc0_cs3_bncr_value = 0;
 		} else {
 			/* Expansion Slot */
 			ebc0_cs1_bnap_value = 0;
 			ebc0_cs1_bncr_value = 0;
 			ebc0_cs2_bnap_value = 0;
 			ebc0_cs2_bncr_value = 0;
 			ebc0_cs3_bnap_value = 0;
 			ebc0_cs3_bncr_value = 0;
 		}
 		if ((config_on_ebc_cs4_is_small_flash()) == TRUE) {
 			/* Small Flash */
 			ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
 			ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
 		} else {
 			/* Large Flash or SRAM */
 			ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
 			ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
 		}
 		break;
 		/*------------------------------------------------------------------------- */
-        case BOOT_DEVICE_UNKNOWN:
+	case BOOT_DEVICE_UNKNOWN:
 		/*------------------------------------------------------------------------- */
 		/* Error */
 		break;
 	}
 	/*-------------------------------------------------------------------------+
 	  | Initialize EBC CONFIG
 	  +-------------------------------------------------------------------------*/
 	mtdcr(ebccfga, xbcfg);
-	mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN        |
+	mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN	   |
-	      EBC0_CFG_PTD_ENABLED        |
+	      EBC0_CFG_PTD_ENABLED	  |
-	      EBC0_CFG_RTC_2048PERCLK     |
+	      EBC0_CFG_RTC_2048PERCLK	  |
-	      EBC0_CFG_EMPL_LOW           |
+	      EBC0_CFG_EMPL_LOW		  |
-	      EBC0_CFG_EMPH_LOW           |
+	      EBC0_CFG_EMPH_LOW		  |
-	      EBC0_CFG_CSTC_DRIVEN        |
+	      EBC0_CFG_CSTC_DRIVEN	  |
-	      EBC0_CFG_BPF_ONEDW          |
+	      EBC0_CFG_BPF_ONEDW	  |
-	      EBC0_CFG_EMS_8BIT           |
+	      EBC0_CFG_EMS_8BIT		  |
-	      EBC0_CFG_PME_DISABLED       |
+	      EBC0_CFG_PME_DISABLED	  |
-	      EBC0_CFG_PMT_ENCODE(0)      );
+	      EBC0_CFG_PMT_ENCODE(0)	  );
 	/*-------------------------------------------------------------------------+
 	  | Initialize EBC Bank 0-4
 	  +-------------------------------------------------------------------------*/
 	/* EBC Bank0 */
 	mtebc(pb0ap, ebc0_cs0_bnap_value);
 	mtebc(pb0cr, ebc0_cs0_bncr_value);
 	/* EBC Bank1 */
 	mtebc(pb1ap, ebc0_cs1_bnap_value);
 	mtebc(pb1cr, ebc0_cs1_bncr_value);
 	/* EBC Bank2 */
 	mtebc(pb2ap, ebc0_cs2_bnap_value);
 	mtebc(pb2cr, ebc0_cs2_bncr_value);
 	/* EBC Bank3 */
 	mtebc(pb3ap, ebc0_cs3_bnap_value);
 	mtebc(pb3cr, ebc0_cs3_bncr_value);
 	/* EBC Bank4 */
 	mtebc(pb4ap, ebc0_cs4_bnap_value);
 	mtebc(pb4cr, ebc0_cs4_bncr_value);
 	return;
 }
 /*----------------------------------------------------------------------------+
   | get_uart_configuration.
   +----------------------------------------------------------------------------*/
 uart_config_nb_t get_uart_configuration(void)
 {
 	return (L4); /* test-only */
 }
 /*----------------------------------------------------------------------------+
   | set_phy_configuration_through_fpga => to EPLD
   +----------------------------------------------------------------------------*/
 void set_phy_configuration_through_fpga(zmii_config_t config)
 {
 	unsigned long fpga_selection_reg;
 	fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
 	switch(config)
 	{
-        case ZMII_CONFIGURATION_IS_MII:
+	case ZMII_CONFIGURATION_IS_MII:
 		fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
 		break;
-        case ZMII_CONFIGURATION_IS_RMII:
+	case ZMII_CONFIGURATION_IS_RMII:
 		fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
 		break;
-        case ZMII_CONFIGURATION_IS_SMII:
+	case ZMII_CONFIGURATION_IS_SMII:
 		fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
 		break;
-        case ZMII_CONFIGURATION_UNKNOWN:
+	case ZMII_CONFIGURATION_UNKNOWN:
-        default:
+	default:
 		break;
 	}
 	out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
 }
 /*----------------------------------------------------------------------------+
   | scp_selection_in_fpga.
   +----------------------------------------------------------------------------*/
 void scp_selection_in_fpga(void)
 {
 	unsigned long fpga_selection_2_reg;
 	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
 	fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
 	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
 }
 /*----------------------------------------------------------------------------+
   | iic1_selection_in_fpga.
   +----------------------------------------------------------------------------*/
 void iic1_selection_in_fpga(void)
 {
 	unsigned long fpga_selection_2_reg;
 	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
 	fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
 	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
 }
 /*----------------------------------------------------------------------------+
   | dma_a_b_selection_in_fpga.
   +----------------------------------------------------------------------------*/
 void dma_a_b_selection_in_fpga(void)
 {
 	unsigned long fpga_selection_2_reg;
 	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
 	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
 }
 /*----------------------------------------------------------------------------+
   | dma_a_b_unselect_in_fpga.
   +----------------------------------------------------------------------------*/
 void dma_a_b_unselect_in_fpga(void)
 {
 	unsigned long fpga_selection_2_reg;
 	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
 	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
 }
 /*----------------------------------------------------------------------------+
   | dma_c_d_selection_in_fpga.
   +----------------------------------------------------------------------------*/
 void dma_c_d_selection_in_fpga(void)
 {
 	unsigned long fpga_selection_2_reg;
 	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
 	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
 }
 /*----------------------------------------------------------------------------+
   | dma_c_d_unselect_in_fpga.
   +----------------------------------------------------------------------------*/
 void dma_c_d_unselect_in_fpga(void)
 {
 	unsigned long fpga_selection_2_reg;
 	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
 	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
 }
 /*----------------------------------------------------------------------------+
   | usb2_device_selection_in_fpga.
   +----------------------------------------------------------------------------*/
 void usb2_device_selection_in_fpga(void)
 {
 	unsigned long fpga_selection_1_reg;
 	fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
 	out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
 }
 /*----------------------------------------------------------------------------+
   | usb2_device_reset_through_fpga.
   +----------------------------------------------------------------------------*/
 void usb2_device_reset_through_fpga(void)
 {
 	/* Perform soft Reset pulse */
 	unsigned long fpga_reset_reg;
 	int i;
 	fpga_reset_reg = in8(FPGA_RESET_REG);
 	out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
 	for (i=0; i<500; i++)
 		udelay(1000);
 	out8(FPGA_RESET_REG,fpga_reset_reg);
 }
 /*----------------------------------------------------------------------------+
   | usb2_host_selection_in_fpga.
   +----------------------------------------------------------------------------*/
 void usb2_host_selection_in_fpga(void)
 {
 	unsigned long fpga_selection_1_reg;
 	fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
 	out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
 }
 /*----------------------------------------------------------------------------+
   | ndfc_selection_in_fpga.
   +----------------------------------------------------------------------------*/
 void ndfc_selection_in_fpga(void)
 {
 	unsigned long fpga_selection_1_reg;
 	fpga_selection_1_reg  = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
 	fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
 	/*fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2; */
 	/*fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3; */
 	out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
 }
 /*----------------------------------------------------------------------------+
   | uart_selection_in_fpga.
   +----------------------------------------------------------------------------*/
 void uart_selection_in_fpga(uart_config_nb_t uart_config)
 {
 	/* FPGA register */
-	unsigned char   fpga_selection_3_reg;
+	unsigned char	fpga_selection_3_reg;
 	/* Read FPGA Reagister */
 	fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
 	switch (uart_config)
 	{
 	case L1:
 		/* ----------------------------------------------------------------------- */
-		/* L1 configuration:    UART0 = 8 pins */
+		/* L1 configuration:	UART0 = 8 pins */
 		/* ----------------------------------------------------------------------- */
 		/* Configure FPGA */
-		fpga_selection_3_reg    = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
+		fpga_selection_3_reg	= fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
-		fpga_selection_3_reg    = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
+		fpga_selection_3_reg	= fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
 		out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
 		break;
 	case L2:
 		/* ----------------------------------------------------------------------- */
-		/* L2 configuration:    UART0 = 4 pins */
+		/* L2 configuration:	UART0 = 4 pins */
-		/*                      UART1 = 4 pins */
+		/*			UART1 = 4 pins */
 		/* ----------------------------------------------------------------------- */
 		/* Configure FPGA */
-		fpga_selection_3_reg    = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
+		fpga_selection_3_reg	= fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
-		fpga_selection_3_reg    = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
+		fpga_selection_3_reg	= fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
 		out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
 		break;
 	case L3:
 		/* ----------------------------------------------------------------------- */
-		/* L3 configuration:    UART0 = 4 pins */
+		/* L3 configuration:	UART0 = 4 pins */
-		/*                      UART1 = 2 pins */
+		/*			UART1 = 2 pins */
-		/*                      UART2 = 2 pins */
+		/*			UART2 = 2 pins */
 		/* ----------------------------------------------------------------------- */
 		/* Configure FPGA */
-		fpga_selection_3_reg    = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
+		fpga_selection_3_reg	= fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
-		fpga_selection_3_reg    = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
+		fpga_selection_3_reg	= fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
 		out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
 		break;
 	case L4:
 		/* Configure FPGA */
-		fpga_selection_3_reg    = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
+		fpga_selection_3_reg	= fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
-		fpga_selection_3_reg    = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
+		fpga_selection_3_reg	= fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
 		out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
 		break;
 	default:
 		/* Unsupported UART configuration number */
 		for (;;)
 			;
 		break;
 	}
 }
 /*----------------------------------------------------------------------------+
   | init_default_gpio
   +----------------------------------------------------------------------------*/
 void init_default_gpio(void)
 {
 	int i;
 	/* Init GPIO0 */
 	for(i=0; i<GPIO_MAX; i++)
 	{
-		gpio_tab[GPIO0][i].add    = GPIO0_BASE;
+		gpio_tab[GPIO0][i].add	  = GPIO0_BASE;
 		gpio_tab[GPIO0][i].in_out = GPIO_DIS;
 		gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
 	}
 	/* Init GPIO1 */
 	for(i=0; i<GPIO_MAX; i++)
 	{
-		gpio_tab[GPIO1][i].add    = GPIO1_BASE;
+		gpio_tab[GPIO1][i].add	  = GPIO1_BASE;
 		gpio_tab[GPIO1][i].in_out = GPIO_DIS;
 		gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
 	}
 	/* EBC_CS_N(5) - GPIO0_10 */
 	gpio_tab[GPIO0][10].in_out    = GPIO_OUT;
 	gpio_tab[GPIO0][10].alt_nb    = GPIO_ALT1;
 	/* EBC_CS_N(4) - GPIO0_9 */
 	gpio_tab[GPIO0][9].in_out    = GPIO_OUT;
 	gpio_tab[GPIO0][9].alt_nb    = GPIO_ALT1;
 }
 /*----------------------------------------------------------------------------+
   | update_uart_ios
   +------------------------------------------------------------------------------
   |
   | Set UART Configuration in PowerPC440EP
   |
   | +---------------------------------------------------------------------+
-  | | Configuartion   |   Connector   | Nb of pins | Pins   | Associated  |
+  | | Configuartion   |	  Connector   | Nb of pins | Pins   | Associated  |
-  | |    Number       |   Port Name   |  available | naming |   CORE      |
+  | |	 Number	      |	  Port Name   |	 available | naming |	CORE	  |
   | +-----------------+---------------+------------+--------+-------------+
-  | |     L1          |   Port_A      |     8      | UART   | UART core 0 |
+  | |	  L1	      |	  Port_A      |	    8	   | UART   | UART core 0 |
   | +-----------------+---------------+------------+--------+-------------+
-  | |     L2          |   Port_A      |     4      | UART1  | UART core 0 |
+  | |	  L2	      |	  Port_A      |	    4	   | UART1  | UART core 0 |
-  | |    (L2D)        |   Port_B      |     4      | UART2  | UART core 1 |
+  | |	 (L2D)	      |	  Port_B      |	    4	   | UART2  | UART core 1 |
   | +-----------------+---------------+------------+--------+-------------+
-  | |     L3          |   Port_A      |     4      | UART1  | UART core 0 |
+  | |	  L3	      |	  Port_A      |	    4	   | UART1  | UART core 0 |
-  | |    (L3D)        |   Port_B      |     2      | UART2  | UART core 1 |
+  | |	 (L3D)	      |	  Port_B      |	    2	   | UART2  | UART core 1 |
-  | |                 |   Port_C      |     2      | UART3  | UART core 2 |
+  | |		      |	  Port_C      |	    2	   | UART3  | UART core 2 |
   | +-----------------+---------------+------------+--------+-------------+
-  | |                 |   Port_A      |     2      | UART1  | UART core 0 |
+  | |		      |	  Port_A      |	    2	   | UART1  | UART core 0 |
-  | |     L4          |   Port_B      |     2      | UART2  | UART core 1 |
+  | |	  L4	      |	  Port_B      |	    2	   | UART2  | UART core 1 |
-  | |    (L4D)        |   Port_C      |     2      | UART3  | UART core 2 |
+  | |	 (L4D)	      |	  Port_C      |	    2	   | UART3  | UART core 2 |
-  | |                 |   Port_D      |     2      | UART4  | UART core 3 |
+  | |		      |	  Port_D      |	    2	   | UART4  | UART core 3 |
   | +-----------------+---------------+------------+--------+-------------+
   |
   |  Involved GPIOs
   |
   | +------------------------------------------------------------------------------+
-  | |  GPIO   |   Aternate 1     | I/O |  Alternate 2    | I/O | Alternate 3 | I/O |
+  | |  GPIO   |	  Aternate 1	 | I/O |  Alternate 2	 | I/O | Alternate 3 | I/O |
   | +---------+------------------+-----+-----------------+-----+-------------+-----+
-  | | GPIO1_2 | UART0_DCD_N      |  I  | UART1_DSR_CTS_N |  I  | UART2_SOUT  |  O  |
+  | | GPIO1_2 | UART0_DCD_N	 |  I  | UART1_DSR_CTS_N |  I  | UART2_SOUT  |	O  |
-  | | GPIO1_3 | UART0_8PIN_DSR_N |  I  | UART1_RTS_DTR_N |  O  | UART2_SIN   |  I  |
+  | | GPIO1_3 | UART0_8PIN_DSR_N |  I  | UART1_RTS_DTR_N |  O  | UART2_SIN   |	I  |
-  | | GPIO1_4 | UART0_8PIN_CTS_N |  I  | NA              |  NA | UART3_SIN   |  I  |
+  | | GPIO1_4 | UART0_8PIN_CTS_N |  I  | NA		 |  NA | UART3_SIN   |	I  |
-  | | GPIO1_5 | UART0_RTS_N      |  O  | NA              |  NA | UART3_SOUT  |  O  |
+  | | GPIO1_5 | UART0_RTS_N	 |  O  | NA		 |  NA | UART3_SOUT  |	O  |
-  | | GPIO1_6 | UART0_DTR_N      |  O  | UART1_SOUT      |  O  | NA          |  NA |
+  | | GPIO1_6 | UART0_DTR_N	 |  O  | UART1_SOUT	 |  O  | NA	     |	NA |
-  | | GPIO1_7 | UART0_RI_N       |  I  | UART1_SIN       |  I  | NA          |  NA |
+  | | GPIO1_7 | UART0_RI_N	 |  I  | UART1_SIN	 |  I  | NA	     |	NA |
   | +------------------------------------------------------------------------------+
   |
   |
   +----------------------------------------------------------------------------*/
 void update_uart_ios(uart_config_nb_t uart_config)
 {
 	switch (uart_config)
 	{
 	case L1:
 		/* ----------------------------------------------------------------------- */
-		/* L1 configuration:    UART0 = 8 pins */
+		/* L1 configuration:	UART0 = 8 pins */
 		/* ----------------------------------------------------------------------- */
 		/* Update GPIO Configuration Table */
 		gpio_tab[GPIO1][2].in_out = GPIO_IN;
 		gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
 		gpio_tab[GPIO1][3].in_out = GPIO_IN;
 		gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
 		gpio_tab[GPIO1][4].in_out = GPIO_IN;
 		gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
 		gpio_tab[GPIO1][5].in_out = GPIO_OUT;
 		gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
 		gpio_tab[GPIO1][6].in_out = GPIO_OUT;
 		gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
 		gpio_tab[GPIO1][7].in_out = GPIO_IN;
 		gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
 		break;
 	case L2:
 		/* ----------------------------------------------------------------------- */
-		/* L2 configuration:    UART0 = 4 pins */
+		/* L2 configuration:	UART0 = 4 pins */
-		/*                      UART1 = 4 pins */
+		/*			UART1 = 4 pins */
 		/* ----------------------------------------------------------------------- */
 		/* Update GPIO Configuration Table */
 		gpio_tab[GPIO1][2].in_out = GPIO_IN;
 		gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
 		gpio_tab[GPIO1][3].in_out = GPIO_OUT;
 		gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
 		gpio_tab[GPIO1][4].in_out = GPIO_IN;
 		gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
 		gpio_tab[GPIO1][5].in_out = GPIO_OUT;
 		gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
 		gpio_tab[GPIO1][6].in_out = GPIO_OUT;
 		gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
 		gpio_tab[GPIO1][7].in_out = GPIO_IN;
 		gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
 		break;
 	case L3:
 		/* ----------------------------------------------------------------------- */
-		/* L3 configuration:    UART0 = 4 pins */
+		/* L3 configuration:	UART0 = 4 pins */
-		/*                      UART1 = 2 pins */
+		/*			UART1 = 2 pins */
-		/*                      UART2 = 2 pins */
+		/*			UART2 = 2 pins */
 		/* ----------------------------------------------------------------------- */
 		/* Update GPIO Configuration Table */
 		gpio_tab[GPIO1][2].in_out = GPIO_OUT;
 		gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
 		gpio_tab[GPIO1][3].in_out = GPIO_IN;
 		gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
 		gpio_tab[GPIO1][4].in_out = GPIO_IN;
 		gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
 		gpio_tab[GPIO1][5].in_out = GPIO_OUT;
 		gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
 		gpio_tab[GPIO1][6].in_out = GPIO_OUT;
 		gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
 		gpio_tab[GPIO1][7].in_out = GPIO_IN;
 		gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
 		break;
 	case L4:
 		/* ----------------------------------------------------------------------- */
-		/* L4 configuration:    UART0 = 2 pins */
+		/* L4 configuration:	UART0 = 2 pins */
-		/*                      UART1 = 2 pins */
+		/*			UART1 = 2 pins */
-		/*                      UART2 = 2 pins */
+		/*			UART2 = 2 pins */
-		/*                      UART3 = 2 pins */
+		/*			UART3 = 2 pins */
 		/* ----------------------------------------------------------------------- */
 		/* Update GPIO Configuration Table */
 		gpio_tab[GPIO1][2].in_out = GPIO_OUT;
 		gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
 		gpio_tab[GPIO1][3].in_out = GPIO_IN;
 		gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
 		gpio_tab[GPIO1][4].in_out = GPIO_IN;
 		gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
 		gpio_tab[GPIO1][5].in_out = GPIO_OUT;
 		gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
 		gpio_tab[GPIO1][6].in_out = GPIO_OUT;
 		gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
 		gpio_tab[GPIO1][7].in_out = GPIO_IN;
 		gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
 		break;
 	default:
 		/* Unsupported UART configuration number */
 		printf("ERROR - Unsupported UART configuration number.\n\n");
 		for (;;)
 			;
 		break;
 	}
 	/* Set input Selection Register on Alt_Receive for UART Input Core */
 	out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
 	out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
 	out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
 }
 /*----------------------------------------------------------------------------+
   | update_ndfc_ios(void).
   +----------------------------------------------------------------------------*/
 void update_ndfc_ios(void)
 {
-        /* Update GPIO Configuration Table */
+	/* Update GPIO Configuration Table */
-        gpio_tab[GPIO0][6].in_out = GPIO_OUT;       /* EBC_CS_N(1) */
+	gpio_tab[GPIO0][6].in_out = GPIO_OUT;	    /* EBC_CS_N(1) */
-        gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
+	gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
 #if 0
-        gpio_tab[GPIO0][7].in_out = GPIO_OUT;       /* EBC_CS_N(2) */
+	gpio_tab[GPIO0][7].in_out = GPIO_OUT;	    /* EBC_CS_N(2) */
 	gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
-	gpio_tab[GPIO0][7].in_out = GPIO_OUT;       /* EBC_CS_N(3) */
+	gpio_tab[GPIO0][7].in_out = GPIO_OUT;	    /* EBC_CS_N(3) */
 	gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
 #endif
 }
 /*----------------------------------------------------------------------------+
   | update_zii_ios(void).
   +----------------------------------------------------------------------------*/
 void update_zii_ios(void)
 {
-        /* Update GPIO Configuration Table */
+	/* Update GPIO Configuration Table */
-        gpio_tab[GPIO0][12].in_out = GPIO_IN;       /* ZII_p0Rxd(0) */
+	gpio_tab[GPIO0][12].in_out = GPIO_IN;	    /* ZII_p0Rxd(0) */
-        gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
+	gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
-        gpio_tab[GPIO0][13].in_out = GPIO_IN;       /* ZII_p0Rxd(1) */
+	gpio_tab[GPIO0][13].in_out = GPIO_IN;	    /* ZII_p0Rxd(1) */
-        gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
+	gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
-        gpio_tab[GPIO0][14].in_out = GPIO_IN;       /* ZII_p0Rxd(2) */
+	gpio_tab[GPIO0][14].in_out = GPIO_IN;	    /* ZII_p0Rxd(2) */
-        gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
+	gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
-        gpio_tab[GPIO0][15].in_out = GPIO_IN;       /* ZII_p0Rxd(3) */
+	gpio_tab[GPIO0][15].in_out = GPIO_IN;	    /* ZII_p0Rxd(3) */
-        gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
+	gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
-        gpio_tab[GPIO0][16].in_out = GPIO_OUT;      /* ZII_p0Txd(0) */
+	gpio_tab[GPIO0][16].in_out = GPIO_OUT;	    /* ZII_p0Txd(0) */
-        gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
+	gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
-        gpio_tab[GPIO0][17].in_out = GPIO_OUT;      /* ZII_p0Txd(1) */
+	gpio_tab[GPIO0][17].in_out = GPIO_OUT;	    /* ZII_p0Txd(1) */
-        gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
+	gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
-        gpio_tab[GPIO0][18].in_out = GPIO_OUT;      /* ZII_p0Txd(2) */
+	gpio_tab[GPIO0][18].in_out = GPIO_OUT;	    /* ZII_p0Txd(2) */
-        gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
+	gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
-        gpio_tab[GPIO0][19].in_out = GPIO_OUT;      /* ZII_p0Txd(3) */
+	gpio_tab[GPIO0][19].in_out = GPIO_OUT;	    /* ZII_p0Txd(3) */
-        gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
+	gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
-        gpio_tab[GPIO0][20].in_out = GPIO_IN;       /* ZII_p0Rx_er */
+	gpio_tab[GPIO0][20].in_out = GPIO_IN;	    /* ZII_p0Rx_er */
-        gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
+	gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
-        gpio_tab[GPIO0][21].in_out = GPIO_IN;       /* ZII_p0Rx_dv */
+	gpio_tab[GPIO0][21].in_out = GPIO_IN;	    /* ZII_p0Rx_dv */
-        gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
+	gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
-        gpio_tab[GPIO0][22].in_out = GPIO_IN;       /* ZII_p0Crs */
+	gpio_tab[GPIO0][22].in_out = GPIO_IN;	    /* ZII_p0Crs */
-        gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
+	gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
-        gpio_tab[GPIO0][23].in_out = GPIO_OUT;      /* ZII_p0Tx_er */
+	gpio_tab[GPIO0][23].in_out = GPIO_OUT;	    /* ZII_p0Tx_er */
-        gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
+	gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
-        gpio_tab[GPIO0][24].in_out = GPIO_OUT;      /* ZII_p0Tx_en */
+	gpio_tab[GPIO0][24].in_out = GPIO_OUT;	    /* ZII_p0Tx_en */
-        gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
+	gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
-        gpio_tab[GPIO0][25].in_out = GPIO_IN;       /* ZII_p0Col */
+	gpio_tab[GPIO0][25].in_out = GPIO_IN;	    /* ZII_p0Col */
-        gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
+	gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
 }
 /*----------------------------------------------------------------------------+
   | update_uic_0_3_irq_ios().
   +----------------------------------------------------------------------------*/
 void update_uic_0_3_irq_ios(void)
 {
-	gpio_tab[GPIO1][8].in_out = GPIO_IN;        /* UIC_IRQ(0) */
+	gpio_tab[GPIO1][8].in_out = GPIO_IN;	    /* UIC_IRQ(0) */
 	gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
-	gpio_tab[GPIO1][9].in_out = GPIO_IN;        /* UIC_IRQ(1) */
+	gpio_tab[GPIO1][9].in_out = GPIO_IN;	    /* UIC_IRQ(1) */
 	gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
-	gpio_tab[GPIO1][10].in_out = GPIO_IN;       /* UIC_IRQ(2) */
+	gpio_tab[GPIO1][10].in_out = GPIO_IN;	    /* UIC_IRQ(2) */
 	gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
-	gpio_tab[GPIO1][11].in_out = GPIO_IN;       /* UIC_IRQ(3) */
+	gpio_tab[GPIO1][11].in_out = GPIO_IN;	    /* UIC_IRQ(3) */
 	gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
 }
 /*----------------------------------------------------------------------------+
   | update_uic_4_9_irq_ios().
   +----------------------------------------------------------------------------*/
 void update_uic_4_9_irq_ios(void)
 {
-	gpio_tab[GPIO1][12].in_out = GPIO_IN;       /* UIC_IRQ(4) */
+	gpio_tab[GPIO1][12].in_out = GPIO_IN;	    /* UIC_IRQ(4) */
 	gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
-	gpio_tab[GPIO1][13].in_out = GPIO_IN;       /* UIC_IRQ(6) */
+	gpio_tab[GPIO1][13].in_out = GPIO_IN;	    /* UIC_IRQ(6) */
 	gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
-	gpio_tab[GPIO1][14].in_out = GPIO_IN;       /* UIC_IRQ(7) */
+	gpio_tab[GPIO1][14].in_out = GPIO_IN;	    /* UIC_IRQ(7) */
 	gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
-	gpio_tab[GPIO1][15].in_out = GPIO_IN;       /* UIC_IRQ(8) */
+	gpio_tab[GPIO1][15].in_out = GPIO_IN;	    /* UIC_IRQ(8) */
 	gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
-	gpio_tab[GPIO1][16].in_out = GPIO_IN;       /* UIC_IRQ(9) */
+	gpio_tab[GPIO1][16].in_out = GPIO_IN;	    /* UIC_IRQ(9) */
 	gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
 }
 /*----------------------------------------------------------------------------+
   | update_dma_a_b_ios().
   +----------------------------------------------------------------------------*/
 void update_dma_a_b_ios(void)
 {
-	gpio_tab[GPIO1][12].in_out = GPIO_OUT;      /* DMA_ACK(1) */
+	gpio_tab[GPIO1][12].in_out = GPIO_OUT;	    /* DMA_ACK(1) */
 	gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
-	gpio_tab[GPIO1][13].in_out = GPIO_BI;       /* DMA_EOT/TC(1) */
+	gpio_tab[GPIO1][13].in_out = GPIO_BI;	    /* DMA_EOT/TC(1) */
 	gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
-	gpio_tab[GPIO1][14].in_out = GPIO_IN;       /* DMA_REQ(0) */
+	gpio_tab[GPIO1][14].in_out = GPIO_IN;	    /* DMA_REQ(0) */
 	gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
-	gpio_tab[GPIO1][15].in_out = GPIO_OUT;      /* DMA_ACK(0) */
+	gpio_tab[GPIO1][15].in_out = GPIO_OUT;	    /* DMA_ACK(0) */
 	gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
-	gpio_tab[GPIO1][16].in_out = GPIO_BI;       /* DMA_EOT/TC(0) */
+	gpio_tab[GPIO1][16].in_out = GPIO_BI;	    /* DMA_EOT/TC(0) */
 	gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
 }
 /*----------------------------------------------------------------------------+
   | update_dma_c_d_ios().
   +----------------------------------------------------------------------------*/
 void update_dma_c_d_ios(void)
 {
-	gpio_tab[GPIO0][0].in_out = GPIO_IN;        /* DMA_REQ(2) */
+	gpio_tab[GPIO0][0].in_out = GPIO_IN;	    /* DMA_REQ(2) */
 	gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
-	gpio_tab[GPIO0][1].in_out = GPIO_OUT;       /* DMA_ACK(2) */
+	gpio_tab[GPIO0][1].in_out = GPIO_OUT;	    /* DMA_ACK(2) */
 	gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
-	gpio_tab[GPIO0][2].in_out = GPIO_BI;        /* DMA_EOT/TC(2) */
+	gpio_tab[GPIO0][2].in_out = GPIO_BI;	    /* DMA_EOT/TC(2) */
 	gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
-	gpio_tab[GPIO0][3].in_out = GPIO_IN;        /* DMA_REQ(3) */
+	gpio_tab[GPIO0][3].in_out = GPIO_IN;	    /* DMA_REQ(3) */
 	gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
-	gpio_tab[GPIO0][4].in_out = GPIO_OUT;       /* DMA_ACK(3) */
+	gpio_tab[GPIO0][4].in_out = GPIO_OUT;	    /* DMA_ACK(3) */
 	gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
-	gpio_tab[GPIO0][5].in_out = GPIO_BI;        /* DMA_EOT/TC(3) */
+	gpio_tab[GPIO0][5].in_out = GPIO_BI;	    /* DMA_EOT/TC(3) */
 	gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
 }
 /*----------------------------------------------------------------------------+
   | update_ebc_master_ios().
   +----------------------------------------------------------------------------*/
 void update_ebc_master_ios(void)
 {
-	gpio_tab[GPIO0][27].in_out = GPIO_IN;       /* EXT_EBC_REQ */
+	gpio_tab[GPIO0][27].in_out = GPIO_IN;	    /* EXT_EBC_REQ */
 	gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
-	gpio_tab[GPIO0][29].in_out = GPIO_OUT;      /* EBC_EXT_HDLA */
+	gpio_tab[GPIO0][29].in_out = GPIO_OUT;	    /* EBC_EXT_HDLA */
 	gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
-	gpio_tab[GPIO0][30].in_out = GPIO_OUT;      /* EBC_EXT_ACK */
+	gpio_tab[GPIO0][30].in_out = GPIO_OUT;	    /* EBC_EXT_ACK */
 	gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
-	gpio_tab[GPIO0][31].in_out = GPIO_OUT;      /* EBC_EXR_BUSREQ */
+	gpio_tab[GPIO0][31].in_out = GPIO_OUT;	    /* EBC_EXR_BUSREQ */
 	gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
 }
 /*----------------------------------------------------------------------------+
   | update_usb2_device_ios().
   +----------------------------------------------------------------------------*/
 void update_usb2_device_ios(void)
 {
-	gpio_tab[GPIO0][26].in_out = GPIO_IN;       /* USB2D_RXVALID */
+	gpio_tab[GPIO0][26].in_out = GPIO_IN;	    /* USB2D_RXVALID */
 	gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
-	gpio_tab[GPIO0][27].in_out = GPIO_IN;       /* USB2D_RXERROR */
+	gpio_tab[GPIO0][27].in_out = GPIO_IN;	    /* USB2D_RXERROR */
 	gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
-	gpio_tab[GPIO0][28].in_out = GPIO_OUT;      /* USB2D_TXVALID */
+	gpio_tab[GPIO0][28].in_out = GPIO_OUT;	    /* USB2D_TXVALID */
 	gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
-	gpio_tab[GPIO0][29].in_out = GPIO_OUT;      /* USB2D_PAD_SUSPNDM */
+	gpio_tab[GPIO0][29].in_out = GPIO_OUT;	    /* USB2D_PAD_SUSPNDM */
 	gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
-	gpio_tab[GPIO0][30].in_out = GPIO_OUT;      /* USB2D_XCVRSELECT */
+	gpio_tab[GPIO0][30].in_out = GPIO_OUT;	    /* USB2D_XCVRSELECT */
 	gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
-	gpio_tab[GPIO0][31].in_out = GPIO_OUT;      /* USB2D_TERMSELECT */
+	gpio_tab[GPIO0][31].in_out = GPIO_OUT;	    /* USB2D_TERMSELECT */
 	gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
-	gpio_tab[GPIO1][0].in_out = GPIO_OUT;       /* USB2D_OPMODE0 */
+	gpio_tab[GPIO1][0].in_out = GPIO_OUT;	    /* USB2D_OPMODE0 */
 	gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
-	gpio_tab[GPIO1][1].in_out = GPIO_OUT;       /* USB2D_OPMODE1 */
+	gpio_tab[GPIO1][1].in_out = GPIO_OUT;	    /* USB2D_OPMODE1 */
 	gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
 }
 /*----------------------------------------------------------------------------+
   | update_pci_patch_ios().
   +----------------------------------------------------------------------------*/
 void update_pci_patch_ios(void)
 {
-	gpio_tab[GPIO0][29].in_out = GPIO_OUT;      /* EBC_EXT_HDLA */
+	gpio_tab[GPIO0][29].in_out = GPIO_OUT;	    /* EBC_EXT_HDLA */
 	gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
 }
 /*----------------------------------------------------------------------------+
   |   set_chip_gpio_configuration(unsigned char gpio_core)
   |   Put the core impacted by clock modification and sharing in reset.
   |   Config the select registers to resolve the sharing depending of the config.
   |   Configure the GPIO registers.
   |
   +----------------------------------------------------------------------------*/
 void set_chip_gpio_configuration(unsigned char gpio_core)
 {
 	unsigned char i=0, j=0, reg_offset = 0;
 	unsigned long gpio_reg, gpio_core_add;
 	/* GPIO config of the GPIOs 0 to 31 */
 	for (i=0; i<GPIO_MAX; i++, j++)
 	{
 		if (i == GPIO_MAX/2)
 		{
 			reg_offset = 4;
 			j = i-16;
 		}
 		gpio_core_add = gpio_tab[gpio_core][i].add;
 		if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
 		     (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
 		{
 			switch (gpio_tab[gpio_core][i].alt_nb)
 			{
 			case GPIO_SEL:
 				break;
 			case GPIO_ALT1:
 				gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
 				gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
 				out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
 				break;
 			case GPIO_ALT2:
 				gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
 				gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
 				out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
 				break;
 			case GPIO_ALT3:
 				gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
 				gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
 				out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
 				break;
 			}
 		}
 		if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
 		     (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
 		{
 			switch (gpio_tab[gpio_core][i].alt_nb)
 			{
 			case GPIO_SEL:
 				break;
 			case GPIO_ALT1:
 				gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
 				gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
 				out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
 				gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
 				gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
 				out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
 				break;
 			case GPIO_ALT2:
 				gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
 				gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
 				out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
 				gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
 				gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
 				out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
 				break;
 			case GPIO_ALT3:
 				gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
 				gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
 				out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
 				gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
 				gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
 				out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
 				break;
 			}
 		}
 	}
 }
 /*----------------------------------------------------------------------------+
   | force_bup_core_selection.
   +----------------------------------------------------------------------------*/
 void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
 {
 	/* Pointer invalid */
 	if (core_select_P == NULL)
 	{
 		printf("Configuration invalid pointer 1\n");
 		for (;;)
 			;
 	}
 	/* L4 Selection */
-	*(core_select_P+UART_CORE0)            = CORE_SELECTED;
+	*(core_select_P+UART_CORE0)	       = CORE_SELECTED;
-	*(core_select_P+UART_CORE1)            = CORE_SELECTED;
+	*(core_select_P+UART_CORE1)	       = CORE_SELECTED;
-	*(core_select_P+UART_CORE2)            = CORE_SELECTED;
+	*(core_select_P+UART_CORE2)	       = CORE_SELECTED;
-	*(core_select_P+UART_CORE3)            = CORE_SELECTED;
+	*(core_select_P+UART_CORE3)	       = CORE_SELECTED;
 	/* RMII Selection */
-	*(core_select_P+RMII_SEL)               = CORE_SELECTED;
+	*(core_select_P+RMII_SEL)		= CORE_SELECTED;
 	/* External Interrupt 0-9 selection */
-	*(core_select_P+UIC_0_3)                = CORE_SELECTED;
+	*(core_select_P+UIC_0_3)		= CORE_SELECTED;
-	*(core_select_P+UIC_4_9)                = CORE_SELECTED;
+	*(core_select_P+UIC_4_9)		= CORE_SELECTED;
-	*(core_select_P+SCP_CORE)            = CORE_SELECTED;
+	*(core_select_P+SCP_CORE)	     = CORE_SELECTED;
-	*(core_select_P+DMA_CHANNEL_CD)            = CORE_SELECTED;
+	*(core_select_P+DMA_CHANNEL_CD)		   = CORE_SELECTED;
-	*(core_select_P+PACKET_REJ_FUNC_AVAIL)            = CORE_SELECTED;
+	*(core_select_P+PACKET_REJ_FUNC_AVAIL)		  = CORE_SELECTED;
-	*(core_select_P+USB1_DEVICE)            = CORE_SELECTED;
+	*(core_select_P+USB1_DEVICE)		= CORE_SELECTED;
 	*config_val_P = CONFIG_IS_VALID;
 }
 /*----------------------------------------------------------------------------+
   | configure_ppc440ep_pins.
   +----------------------------------------------------------------------------*/
 void configure_ppc440ep_pins(void)
 {
 	uart_config_nb_t uart_configuration;
 	config_validity_t config_val = CONFIG_IS_INVALID;
 	/* Create Core Selection Table */
 	core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
 		{
-			CORE_NOT_SELECTED,      /* IIC_CORE, */
+			CORE_NOT_SELECTED,	/* IIC_CORE, */
-			CORE_NOT_SELECTED,      /* SPC_CORE, */
+			CORE_NOT_SELECTED,	/* SPC_CORE, */
-			CORE_NOT_SELECTED,      /* DMA_CHANNEL_AB, */
+			CORE_NOT_SELECTED,	/* DMA_CHANNEL_AB, */
-			CORE_NOT_SELECTED,      /* UIC_4_9, */
+			CORE_NOT_SELECTED,	/* UIC_4_9, */
-			CORE_NOT_SELECTED,      /* USB2_HOST, */
+			CORE_NOT_SELECTED,	/* USB2_HOST, */
-			CORE_NOT_SELECTED,      /* DMA_CHANNEL_CD, */
+			CORE_NOT_SELECTED,	/* DMA_CHANNEL_CD, */
-			CORE_NOT_SELECTED,      /* USB2_DEVICE, */
+			CORE_NOT_SELECTED,	/* USB2_DEVICE, */
-			CORE_NOT_SELECTED,      /* PACKET_REJ_FUNC_AVAIL, */
+			CORE_NOT_SELECTED,	/* PACKET_REJ_FUNC_AVAIL, */
-			CORE_NOT_SELECTED,      /* USB1_DEVICE, */
+			CORE_NOT_SELECTED,	/* USB1_DEVICE, */
-			CORE_NOT_SELECTED,      /* EBC_MASTER, */
+			CORE_NOT_SELECTED,	/* EBC_MASTER, */
-			CORE_NOT_SELECTED,      /* NAND_FLASH, */
+			CORE_NOT_SELECTED,	/* NAND_FLASH, */
-			CORE_NOT_SELECTED,      /* UART_CORE0, */
+			CORE_NOT_SELECTED,	/* UART_CORE0, */
-			CORE_NOT_SELECTED,      /* UART_CORE1, */
+			CORE_NOT_SELECTED,	/* UART_CORE1, */
-			CORE_NOT_SELECTED,      /* UART_CORE2, */
+			CORE_NOT_SELECTED,	/* UART_CORE2, */
-			CORE_NOT_SELECTED,      /* UART_CORE3, */
+			CORE_NOT_SELECTED,	/* UART_CORE3, */
-			CORE_NOT_SELECTED,      /* MII_SEL, */
+			CORE_NOT_SELECTED,	/* MII_SEL, */
-			CORE_NOT_SELECTED,      /* RMII_SEL, */
+			CORE_NOT_SELECTED,	/* RMII_SEL, */
-			CORE_NOT_SELECTED,      /* SMII_SEL, */
+			CORE_NOT_SELECTED,	/* SMII_SEL, */
-			CORE_NOT_SELECTED,      /* PACKET_REJ_FUNC_EN */
+			CORE_NOT_SELECTED,	/* PACKET_REJ_FUNC_EN */
-			CORE_NOT_SELECTED,      /* UIC_0_3 */
+			CORE_NOT_SELECTED,	/* UIC_0_3 */
-			CORE_NOT_SELECTED,      /* USB1_HOST */
+			CORE_NOT_SELECTED,	/* USB1_HOST */
-			CORE_NOT_SELECTED       /* PCI_PATCH */
+			CORE_NOT_SELECTED	/* PCI_PATCH */
 		};
 	/* Table Default Initialisation + FPGA Access */
 	init_default_gpio();
 	set_chip_gpio_configuration(GPIO0);
 	set_chip_gpio_configuration(GPIO1);
 	/* Update Table */
 	force_bup_core_selection(ppc440ep_core_selection, &config_val);
 #if 0 /* test-only */
 	/* If we are running PIBS 1, force known configuration */
 	update_core_selection_table(ppc440ep_core_selection, &config_val);
 #endif
 	/*----------------------------------------------------------------------------+
 	  | SDR + ios table update + fpga initialization
 	  +----------------------------------------------------------------------------*/
-	unsigned long sdr0_pfc1     = 0;
+	unsigned long sdr0_pfc1	    = 0;
-	unsigned long sdr0_usb0     = 0;
+	unsigned long sdr0_usb0	    = 0;
-	unsigned long sdr0_mfr      = 0;
+	unsigned long sdr0_mfr	    = 0;
 	/* PCI Always selected */
 	/* I2C Selection */
 	if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
 	{
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
 		iic1_selection_in_fpga();
 	}
 	/* SCP Selection */
 	if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
 	{
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
 		scp_selection_in_fpga();
 	}
 	/* UIC 0:3 Selection */
 	if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
 	{
 		update_uic_0_3_irq_ios();
 		dma_a_b_unselect_in_fpga();
 	}
 	/* UIC 4:9 Selection */
 	if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
 	{
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
 		update_uic_4_9_irq_ios();
 	}
 	/* DMA AB Selection */
 	if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
 	{
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
 		update_dma_a_b_ios();
 		dma_a_b_selection_in_fpga();
 	}
 	/* DMA CD Selection */
 	if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
 	{
 		update_dma_c_d_ios();
 		dma_c_d_selection_in_fpga();
 	}
 	/* EBC Master Selection */
 	if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
 	{
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
 		update_ebc_master_ios();
 	}
 	/* PCI Patch Enable */
 	if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
 	{
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
 		update_pci_patch_ios();
 	}
 	/* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
 	if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
 	{
 		/* Not Implemented in PowerPC 440EP Pass1-Pass2 */
 		printf("Invalid configuration => USB2 Host selected\n");
 		for (;;)
 			;
 		/*usb2_host_selection_in_fpga(); */
 	}
 	/* USB2.0 Device Selection */
 	if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
 	{
 		update_usb2_device_ios();
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
 		mfsdr(sdr_usb0, sdr0_usb0);
 		sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
 		sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
 		mtsdr(sdr_usb0, sdr0_usb0);
 		usb2_device_selection_in_fpga();
 	}
 	/* USB1.1 Device Selection */
 	if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
 	{
 		mfsdr(sdr_usb0, sdr0_usb0);
 		sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
 		sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
 		mtsdr(sdr_usb0, sdr0_usb0);
 	}
 	/* USB1.1 Host Selection */
 	if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
 	{
 		mfsdr(sdr_usb0, sdr0_usb0);
 		sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
 		sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
 		mtsdr(sdr_usb0, sdr0_usb0);
 	}
 	/* NAND Flash Selection */
 	if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
 	{
 		update_ndfc_ios();
 		mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL   |
-		      SDR0_CUST0_NDFC_ENABLE    |
+		      SDR0_CUST0_NDFC_ENABLE	|
-		      SDR0_CUST0_NDFC_BW_8_BIT  |
+		      SDR0_CUST0_NDFC_BW_8_BIT	|
-		      SDR0_CUST0_NDFC_ARE_MASK  |
+		      SDR0_CUST0_NDFC_ARE_MASK	|
 		      SDR0_CUST0_CHIPSELGAT_EN1 );
 		/*SDR0_CUST0_CHIPSELGAT_EN2 ); */
 		/*SDR0_CUST0_CHIPSELGAT_EN3 ); */
 		ndfc_selection_in_fpga();
 	}
 	else
 	{
 		/* Set Mux on EMAC */
 		mtsdr(sdr_cust0, SDR0_CUST0_MUX_EMAC_SEL);
 	}
 	/* MII Selection */
 	if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
 	{
 		update_zii_ios();
 		mfsdr(sdr_mfr, sdr0_mfr);
 		sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
 		mtsdr(sdr_mfr, sdr0_mfr);
 		set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
 	}
 	/* RMII Selection */
 	if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
 	{
 		update_zii_ios();
 		mfsdr(sdr_mfr, sdr0_mfr);
 		sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
 		mtsdr(sdr_mfr, sdr0_mfr);
 		set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
 	}
 	/* SMII Selection */
 	if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
 	{
 		update_zii_ios();
 		mfsdr(sdr_mfr, sdr0_mfr);
 		sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
 		mtsdr(sdr_mfr, sdr0_mfr);
 		set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
 	}
 	/* UART Selection */
 	uart_configuration = get_uart_configuration();
 	switch (uart_configuration)
 	{
-	case L1:         /* L1 Selection */
+	case L1:	 /* L1 Selection */
 		/* UART0 8 pins Only */
 		/*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
-		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS;   /* Chip Pb */
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS;	  /* Chip Pb */
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
 		break;
-	case L2:         /* L2 Selection */
+	case L2:	 /* L2 Selection */
 		/* UART0 and UART1 4 pins */
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
 		break;
-	case L3:         /* L3 Selection */
+	case L3:	 /* L3 Selection */
 		/* UART0 4 pins, UART1 and UART2 2 pins */
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
 		break;
-	case L4:         /* L4 Selection */
+	case L4:	 /* L4 Selection */
 		/* UART0, UART1, UART2 and UART3 2 pins */
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
 		break;
 	}
 	update_uart_ios(uart_configuration);
 	/* UART Selection in all cases */
 	uart_selection_in_fpga(uart_configuration);
 	/* Packet Reject Function Available */
 	if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
 	{
 		/* Set UPR Bit in SDR0_PFC1 Register */
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
 	}
 	/* Packet Reject Function Enable */
 	if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
 	{
 		mfsdr(sdr_mfr, sdr0_mfr);
 		sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
 		mtsdr(sdr_mfr, sdr0_mfr);
 	}
 	/* Perform effective access to hardware */
 	mtsdr(sdr_pfc1, sdr0_pfc1);
 	set_chip_gpio_configuration(GPIO0);
 	set_chip_gpio_configuration(GPIO1);
 	/* USB2.0 Device Reset must be done after GPIO setting */
 	if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
 		usb2_device_reset_through_fpga();
 }

board/amcc/bamboo/bamboo.h

Diff comments View file @ f901a83

board/ep8248/Makefile

Diff comments View file @ f901a83

File was created	1	#
	2	# (C) Copyright 2001
	3	# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	#
	5	# See file CREDITS for list of people who contributed to this
	6	# project.
	7	#
	8	# This program is free software; you can redistribute it and/or
	9	# modify it under the terms of the GNU General Public License as
	10	# published by the Free Software Foundation; either version 2 of
	11	# the License, or (at your option) any later version.
	12	#
	13	# This program is distributed in the hope that it will be useful,
	14	# but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	# GNU General Public License for more details.
	17	#
	18	# You should have received a copy of the GNU General Public License
	19	# along with this program; if not, write to the Free Software
	20	# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	# MA 02111-1307 USA
	22	#
	23
	24	include $(TOPDIR)/config.mk
	25
	26	LIB = lib$(BOARD).a
	27
	28	OBJS := $(BOARD).o
	29
	30	$(LIB): $(OBJS) $(SOBJS)
	31	$(AR) crv $@ $(OBJS)
	32
	33	clean:
	34	rm -f $(SOBJS) $(OBJS)
	35
	36	distclean: clean
	37	rm -f $(LIB) core *.bak .depend
	38
	39	#########################################################################
	40
	41	.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
	42	$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
	43
	44	-include .depend
	45
	46	#########################################################################
	47

board/ep8248/config.mk

Diff comments View file @ f901a83

File was created	1	#
	2	# (C) Copyright 2001
	3	# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	#
	5	# Modified by, Yuli Barcohen, Arabella Software Ltd. <yuli@arabellasw.com>
	6	#
	7	# See file CREDITS for list of people who contributed to this
	8	# project.
	9	#
	10	# This program is free software; you can redistribute it and/or
	11	# modify it under the terms of the GNU General Public License as
	12	# published by the Free Software Foundation; either version 2 of
	13	# the License, or (at your option) any later version.
	14	#
	15	# This program is distributed in the hope that it will be useful,
	16	# but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	# GNU General Public License for more details.
	19	#
	20	# You should have received a copy of the GNU General Public License
	21	# along with this program; if not, write to the Free Software
	22	# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	# MA 02111-1307 USA
	24	#
	25
	26	#
	27	# EP82xx series boards by Embedded Planet
	28	#
	29
	30	TEXT_BASE = 0xFFF00000
	31

board/ep8248/ep8248.c

Diff comments View file @ f901a83

File was created	1	/*
	2	* Copyright (C) 2004 Arabella Software Ltd.
	3	* Yuli Barcohen <yuli@arabellasw.com>
	4	*
	5	* Support for Embedded Planet EP8248 boards.
	6	* Tested on EP8248E.
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#include <common.h>
	28	#include <mpc8260.h>
	29	#include <ioports.h>
	30
	31	/*
	32	* I/O Port configuration table
	33	*
	34	* if conf is 1, then that port pin will be configured at boot time
	35	* according to the five values podr/pdir/ppar/psor/pdat for that entry
	36	*/
	37
	38	#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
	39	#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
	40
	41	const iop_conf_t iop_conf_tab[4][32] = {
	42
	43	/* Port A */
	44	{ /* conf ppar psor pdir podr pdat */
	45	/* PA31 / { CFG_FCC1, 1, 1, 0, 0, 0 }, / FCC1 MII COL */
	46	/* PA30 / { CFG_FCC1, 1, 1, 0, 0, 0 }, / FCC1 MII CRS */
	47	/* PA29 / { CFG_FCC1, 1, 1, 1, 0, 0 }, / FCC1 MII TX_ER */
	48	/* PA28 / { CFG_FCC1, 1, 1, 1, 0, 0 }, / FCC1 MII TX_EN */
	49	/* PA27 / { CFG_FCC1, 1, 1, 0, 0, 0 }, / FCC1 MII RX_DV */
	50	/* PA26 / { CFG_FCC1, 1, 1, 0, 0, 0 }, / FCC1 MII RX_ER */
	51	/* PA25 / { 0, 0, 0, 0, 0, 0 }, / PA25 */
	52	/* PA24 / { 0, 0, 0, 0, 0, 0 }, / PA24 */
	53	/* PA23 / { 0, 0, 0, 0, 0, 0 }, / PA23 */
	54	/* PA22 / { 0, 0, 0, 0, 0, 0 }, / PA22 */
	55	/* PA21 / { CFG_FCC1, 1, 0, 1, 0, 0 }, / FCC1 MII TxD[3] */
	56	/* PA20 / { CFG_FCC1, 1, 0, 1, 0, 0 }, / FCC1 MII TxD[2] */
	57	/* PA19 / { CFG_FCC1, 1, 0, 1, 0, 0 }, / FCC1 MII TxD[1] */
	58	/* PA18 / { CFG_FCC1, 1, 0, 1, 0, 0 }, / FCC1 MII TxD[0] */
	59	/* PA17 / { CFG_FCC1, 1, 0, 0, 0, 0 }, / FCC1 MII RxD[0] */
	60	/* PA16 / { CFG_FCC1, 1, 0, 0, 0, 0 }, / FCC1 MII RxD[1] */
	61	/* PA15 / { CFG_FCC1, 1, 0, 0, 0, 0 }, / FCC1 MII RxD[2] */
	62	/* PA14 / { CFG_FCC1, 1, 0, 0, 0, 0 }, / FCC1 MII RxD[3] */
	63	/* PA13 / { 0, 0, 0, 0, 0, 0 }, / PA13 */
	64	/* PA12 / { 0, 0, 0, 0, 0, 0 }, / PA12 */
	65	/* PA11 / { 0, 0, 0, 0, 0, 0 }, / PA11 */
	66	/* PA10 / { 0, 0, 0, 0, 0, 0 }, / PA10 */
	67	/* PA9 / { 0, 1, 0, 1, 0, 0 }, / SMC2 TxD */
	68	/* PA8 / { 0, 1, 0, 0, 0, 0 }, / SMC2 RxD */
	69	/* PA7 / { 0, 0, 0, 0, 0, 0 }, / PA7 */
	70	/* PA6 / { 0, 0, 0, 0, 0, 0 }, / PA6 */
	71	/* PA5 / { 0, 0, 0, 0, 0, 0 }, / PA5 */
	72	/* PA4 / { 0, 0, 0, 0, 0, 0 }, / PA4 */
	73	/* PA3 / { 0, 0, 0, 0, 0, 0 }, / PA3 */
	74	/* PA2 / { 0, 0, 0, 0, 0, 0 }, / PA2 */
	75	/* PA1 / { 0, 0, 0, 0, 0, 0 }, / PA1 */
	76	/* PA0 / { 0, 0, 0, 0, 0, 0 } / PA0 */
	77	},
	78
	79	/* Port B */
	80	{ /* conf ppar psor pdir podr pdat */
	81	/* PB31 / { CFG_FCC2, 1, 0, 1, 0, 0 }, / FCC2 MII TX_ER */
	82	/* PB30 / { CFG_FCC2, 1, 0, 0, 0, 0 }, / FCC2 MII RX_DV */
	83	/* PB29 / { CFG_FCC2, 1, 1, 1, 0, 0 }, / FCC2 MII TX_EN */
	84	/* PB28 / { CFG_FCC2, 1, 0, 0, 0, 0 }, / FCC2 MII RX_ER */
	85	/* PB27 / { CFG_FCC2, 1, 0, 0, 0, 0 }, / FCC2 MII COL */
	86	/* PB26 / { CFG_FCC2, 1, 0, 0, 0, 0 }, / FCC2 MII CRS */
	87	/* PB25 / { CFG_FCC2, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[3] */
	88	/* PB24 / { CFG_FCC2, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[2] */
	89	/* PB23 / { CFG_FCC2, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[1] */
	90	/* PB22 / { CFG_FCC2, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[0] */
	91	/* PB21 / { CFG_FCC2, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[0] */
	92	/* PB20 / { CFG_FCC2, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[1] */
	93	/* PB19 / { CFG_FCC2, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[2] */
	94	/* PB18 / { CFG_FCC2, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[3] */
	95	/* PB17 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	96	/* PB16 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	97	/* PB15 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	98	/* PB14 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	99	/* PB13 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	100	/* PB12 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	101	/* PB11 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	102	/* PB10 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	103	/* PB9 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	104	/* PB8 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	105	/* PB7 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	106	/* PB6 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	107	/* PB5 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	108	/* PB4 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	109	/* PB3 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	110	/* PB2 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	111	/* PB1 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	112	/* PB0 / { 0, 0, 0, 0, 0, 0 } / non-existent */
	113	},
	114
	115	/* Port C */
	116	{ /* conf ppar psor pdir podr pdat */
	117	/* PC31 / { 0, 0, 0, 0, 0, 0 }, / PC31 */
	118	/* PC30 / { 0, 0, 0, 0, 0, 0 }, / PC30 */
	119	/* PC29 / { 0, 0, 0, 0, 0, 0 }, / PC29 */
	120	/* PC28 / { 0, 0, 0, 0, 0, 0 }, / PC28 */
	121	/* PC27 / { 0, 0, 0, 0, 0, 0 }, / PC27 */
	122	/* PC26 / { 0, 0, 0, 0, 0, 0 }, / PC26 */
	123	/* PC25 / { 0, 0, 0, 0, 0, 0 }, / PC25 */
	124	/* PC24 / { 0, 0, 0, 0, 0, 0 }, / PC24 */
	125	/* PC23 / { 0, 0, 0, 0, 0, 0 }, / PC23 */
	126	/* PC22 / { CFG_FCC1, 1, 0, 0, 0, 0 }, / FCC1 RxClk (CLK10) */
	127	/* PC21 / { CFG_FCC1, 1, 0, 0, 0, 0 }, / FCC1 TxClk (CLK11) */
	128	/* PC20 / { 0, 0, 0, 0, 0, 0 }, / PC20 */
	129	/* PC19 / { CFG_FCC2, 1, 0, 0, 0, 0 }, / FCC2 RxClk (CLK13) */
	130	/* PC18 / { CFG_FCC2, 1, 0, 0, 0, 0 }, / FCC2 TxClk (CLK14) */
	131	/* PC17 / { 0, 0, 0, 0, 0, 0 }, / PC17 */
	132	/* PC16 / { 0, 0, 0, 0, 0, 0 }, / PC16 */
	133	/* PC15 / { 0, 0, 0, 0, 0, 0 }, / PC15 */
	134	/* PC14 / { 0, 0, 0, 0, 0, 0 }, / PC14 */
	135	/* PC13 / { 0, 0, 0, 0, 0, 0 }, / PC13 */
	136	/* PC12 / { 0, 0, 0, 0, 0, 0 }, / PC12 */
	137	/* PC11 / { 0, 0, 0, 0, 0, 0 }, / PC11 */
	138	/* PC10 / { 0, 0, 0, 0, 0, 0 }, / PC10 */
	139	/* PC9 / { 1, 0, 0, 1, 0, 1 }, / MDIO */
	140	/* PC8 / { 1, 0, 0, 1, 0, 1 }, / MDC */
	141	/* PC7 / { 0, 0, 0, 0, 0, 0 }, / PC7 */
	142	/* PC6 / { 0, 0, 0, 0, 0, 0 }, / PC6 */
	143	/* PC5 / { 1, 1, 0, 1, 0, 0 }, / SMC1 TxD */
	144	/* PC4 / { 1, 1, 0, 0, 0, 0 }, / SMC1 RxD */
	145	/* PC3 / { 0, 0, 0, 0, 0, 0 }, / PC3 */
	146	/* PC2 / { 0, 0, 0, 0, 0, 0 }, / PC2 */
	147	/* PC1 / { 0, 0, 0, 0, 0, 0 }, / PC1 */
	148	/* PC0 / { 0, 0, 0, 0, 0, 0 }, / PC0 */
	149	},
	150
	151	/* Port D */
	152	{ /* conf ppar psor pdir podr pdat */
	153	/* PD31 / { 1, 1, 0, 0, 0, 0 }, / SCC1 RxD */
	154	/* PD30 / { 1, 1, 1, 1, 0, 0 }, / SCC1 TxD */
	155	/* PD29 / { 0, 0, 0, 0, 0, 0 }, / PD29 */
	156	/* PD28 / { 0, 0, 0, 0, 0, 0 }, / PD28 */
	157	/* PD27 / { 0, 0, 0, 0, 0, 0 }, / PD27 */
	158	/* PD26 / { 0, 0, 0, 0, 0, 0 }, / PD26 */
	159	/* PD25 / { 0, 0, 0, 0, 0, 0 }, / PD25 */
	160	/* PD24 / { 0, 0, 0, 0, 0, 0 }, / PD24 */
	161	/* PD23 / { 0, 0, 0, 0, 0, 0 }, / PD23 */
	162	/* PD22 / { 0, 0, 0, 0, 0, 0 }, / PD22 */
	163	/* PD21 / { 0, 0, 0, 0, 0, 0 }, / PD21 */
	164	/* PD20 / { 0, 0, 0, 0, 0, 0 }, / PD20 */
	165	/* PD19 / { 0, 0, 0, 0, 0, 0 }, / PD19 */
	166	/* PD18 / { 0, 0, 0, 0, 0, 0 }, / PD18 */
	167	/* PD17 / { 0, 0, 0, 0, 0, 0 }, / PD17 */
	168	/* PD16 / { 0, 0, 0, 0, 0, 0 }, / PD16 */
	169	/* PD15 / { 1, 1, 1, 0, 1, 0 }, / I2C SDA */
	170	/* PD14 / { 1, 1, 1, 0, 1, 0 }, / I2C SCL */
	171	/* PD13 / { 0, 0, 0, 0, 0, 0 }, / PD13 */
	172	/* PD12 / { 0, 0, 0, 0, 0, 0 }, / PD12 */
	173	/* PD11 / { 0, 0, 0, 0, 0, 0 }, / PD11 */
	174	/* PD10 / { 0, 0, 0, 0, 0, 0 }, / PD10 */
	175	/* PD9 / { 0, 0, 0, 0, 0, 0 }, / PD9 */
	176	/* PD8 / { 0, 0, 0, 0, 0, 0 }, / PD8 */
	177	/* PD7 / { 0, 0, 0, 0, 0, 0 }, / PD7 */
	178	/* PD6 / { 0, 0, 0, 0, 0, 0 }, / PD6 */
	179	/* PD5 / { 0, 0, 0, 0, 0, 0 }, / PD5 */
	180	/* PD4 / { 0, 0, 0, 0, 0, 0 }, / PD4 */
	181	/* PD3 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	182	/* PD2 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	183	/* PD1 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	184	/* PD0 / { 0, 0, 0, 0, 0, 0 } / non-existent */
	185	}
	186	};
	187
	188	int board_early_init_f (void)
	189	{
	190	vu_char bcsr = (vu_char )CFG_BCSR;
	191
	192	bcsr[4] \|= 0x30; /* Turn the LEDs off */
	193
	194	#if defined(CONFIG_CONS_ON_SMC) \|\| defined(CONFIG_KGDB_ON_SMC)
	195	bcsr[6] \|= 0x10;
	196	#endif
	197	#if defined(CONFIG_CONS_ON_SCC) \|\| defined(CONFIG_KGDB_ON_SCC)
	198	bcsr[7] \|= 0x10;
	199	#endif
	200
	201	#if CFG_FCC1
	202	bcsr[8] \|= 0xC0;
	203	#endif /* CFG_FCC1 */
	204	#if CFG_FCC2
	205	bcsr[8] \|= 0x30;
	206	#endif /* CFG_FCC2 */
	207
	208	return 0;
	209	}
	210
	211	long int initdram(int board_type)
	212	{
	213	vu_char bcsr = (vu_char )CFG_BCSR;
	214	long int msize = 16L << (bcsr[2] & 3);
	215
	216	#ifndef CFG_RAMBOOT
	217	volatile immap_t immap = (immap_t )CFG_IMMR;
	218	volatile memctl8260_t *memctl = &immap->im_memctl;
	219	vu_char ramaddr = (vu_char )CFG_SDRAM_BASE;
	220	uchar c = 0xFF;
	221	uint psdmr = CFG_PSDMR;
	222	int i;
	223
	224	immap->im_siu_conf.sc_ppc_acr = 0x02;
	225	immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
	226	immap->im_siu_conf.sc_tescr1 = 0x00004000;
	227
	228	memctl->memc_mptpr = CFG_MPTPR;
	229
	230	/* Initialise 60x bus SDRAM */
	231	memctl->memc_psrt = CFG_PSRT;
	232	memctl->memc_or1 = CFG_SDRAM_OR;
	233	memctl->memc_br1 = CFG_SDRAM_BR;
	234	memctl->memc_psdmr = psdmr \| PSDMR_OP_PREA; /* Precharge all banks */
	235	*ramaddr = c;
	236	memctl->memc_psdmr = psdmr \| PSDMR_OP_CBRR; /* CBR refresh */
	237	for (i = 0; i < 8; i++)
	238	*ramaddr = c;
	239	memctl->memc_psdmr = psdmr \| PSDMR_OP_MRW; /* Mode Register write */
	240	*ramaddr = c;
	241	memctl->memc_psdmr = psdmr \| PSDMR_RFEN; /* Refresh enable */
	242	*ramaddr = c;
	243	#endif /* !CFG_RAMBOOT */
	244
	245	/* Return total 60x bus SDRAM size */
	246	return msize * 1024 * 1024;
	247	}
	248
	249	int checkboard(void)
	250	{
	251	vu_char bcsr = (vu_char )CFG_BCSR;
	252
	253	puts("Board: ");
	254	switch (bcsr[0]) {
	255	case 0x0C:
	256	printf("EP8248E 1.0 CPLD revision %d\n", bcsr[1]);
	257	break;
	258	default:
	259	printf("unknown: ID=%02X\n", bcsr[0]);
	260	}
	261
	262	return 0;
	263	}
	264

board/ep8248/u-boot.lds

Diff comments View file @ f901a83

File was created	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* Modified by Yuli Barcohen <yuli@arabellasw.com>
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	OUTPUT_ARCH(powerpc)
	27	SECTIONS
	28	{
	29	/* Read-only sections, merged into text segment: */
	30	. = + SIZEOF_HEADERS;
	31	.interp : { *(.interp) }
	32	.hash : { *(.hash) }
	33	.dynsym : { *(.dynsym) }
	34	.dynstr : { *(.dynstr) }
	35	.rel.text : { *(.rel.text) }
	36	.rela.text : { *(.rela.text) }
	37	.rel.data : { *(.rel.data) }
	38	.rela.data : { *(.rela.data) }
	39	.rel.rodata : { *(.rel.rodata) }
	40	.rela.rodata : { *(.rela.rodata) }
	41	.rel.got : { *(.rel.got) }
	42	.rela.got : { *(.rela.got) }
	43	.rel.ctors : { *(.rel.ctors) }
	44	.rela.ctors : { *(.rela.ctors) }
	45	.rel.dtors : { *(.rel.dtors) }
	46	.rela.dtors : { *(.rela.dtors) }
	47	.rel.bss : { *(.rel.bss) }
	48	.rela.bss : { *(.rela.bss) }
	49	.rel.plt : { *(.rel.plt) }
	50	.rela.plt : { *(.rela.plt) }
	51	.init : { *(.init) }
	52	.plt : { *(.plt) }
	53	.text :
	54	{
	55	cpu/mpc8260/start.o (.text)
	56	*(.text)
	57	*(.fixup)
	58	*(.got1)
	59	. = ALIGN(16);
	60	*(.rodata)
	61	*(.rodata1)
	62	*(.rodata.str1.4)
	63	}
	64	.fini : { *(.fini) } =0
	65	.ctors : { *(.ctors) }
	66	.dtors : { *(.dtors) }
	67
	68	/* Read-write section, merged into data segment: */
	69	. = (. + 0x0FFF) & 0xFFFFF000;
	70	_erotext = .;
	71	PROVIDE (erotext = .);
	72	.reloc :
	73	{
	74	*(.got)
	75	_GOT2_TABLE_ = .;
	76	*(.got2)
	77	_FIXUP_TABLE_ = .;
	78	*(.fixup)
	79	}
	80	__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
	81	__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
	82
	83	.data :
	84	{
	85	*(.data)
	86	*(.data1)
	87	*(.sdata)
	88	*(.sdata2)
	89	*(.dynamic)
	90	CONSTRUCTORS
	91	}
	92	_edata = .;
	93	PROVIDE (edata = .);
	94
	95	__u_boot_cmd_start = .;
	96	.u_boot_cmd : { *(.u_boot_cmd) }
	97	__u_boot_cmd_end = .;
	98
	99
	100	__start___ex_table = .;
	101	__ex_table : { *(__ex_table) }
	102	__stop___ex_table = .;
	103
	104	. = ALIGN(4096);
	105	__init_begin = .;
	106	.text.init : { *(.text.init) }
	107	.data.init : { *(.data.init) }
	108	. = ALIGN(4096);
	109	__init_end = .;
	110
	111	__bss_start = .;
	112	.bss :
	113	{
	114	(.sbss) (.scommon)
	115	*(.dynbss)
	116	*(.bss)
	117	*(COMMON)
	118	}
	119	_end = . ;
	120	PROVIDE (end = .);
	121	}
	122	ENTRY(_start)
	123

cpu/ppc4xx/start.S

Diff comments View file @ f901a83

1	/*	1	/*
2	* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>	2	* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3	* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>	3	* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4	* Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>	4	* Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5	*	5	*
6	* See file CREDITS for list of people who contributed to this	6	* See file CREDITS for list of people who contributed to this
7	* project.	7	* project.
8	*	8	*
9	* This program is free software; you can redistribute it and/or	9	* This program is free software; you can redistribute it and/or
10	* modify it under the terms of the GNU General Public License as	10	* modify it under the terms of the GNU General Public License as
11	* published by the Free Software Foundation; either version 2 of	11	* published by the Free Software Foundation; either version 2 of
12	* the License, or (at your option) any later version.	12	* the License, or (at your option) any later version.
13	*	13	*
14	* This program is distributed in the hope that it will be useful,	14	* This program is distributed in the hope that it will be useful,
15	* but WITHOUT ANY WARRANTY; without even the implied warranty of	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17	* GNU General Public License for more details.	17	* GNU General Public License for more details.
18	*	18	*
19	* You should have received a copy of the GNU General Public License	19	* You should have received a copy of the GNU General Public License
20	* along with this program; if not, write to the Free Software	20	* along with this program; if not, write to the Free Software
21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22	* MA 02111-1307 USA	22	* MA 02111-1307 USA
23	*/	23	*/
24	/------------------------------------------------------------------------------+ /	24	/------------------------------------------------------------------------------+ /
25	/* */	25	/* */
26	/* This source code has been made available to you by IBM on an AS-IS */	26	/* This source code has been made available to you by IBM on an AS-IS */
27	/* basis. Anyone receiving this source is licensed under IBM */	27	/* basis. Anyone receiving this source is licensed under IBM */
28	/* copyrights to use it in any way he or she deems fit, including */	28	/* copyrights to use it in any way he or she deems fit, including */
29	/* copying it, modifying it, compiling it, and redistributing it either */	29	/* copying it, modifying it, compiling it, and redistributing it either */
30	/* with or without modifications. No license under IBM patents or */	30	/* with or without modifications. No license under IBM patents or */
31	/* patent applications is to be implied by the copyright license. */	31	/* patent applications is to be implied by the copyright license. */
32	/* */	32	/* */
33	/* Any user of this software should understand that IBM cannot provide */	33	/* Any user of this software should understand that IBM cannot provide */
34	/* technical support for this software and will not be responsible for */	34	/* technical support for this software and will not be responsible for */
35	/* any consequences resulting from the use of this software. */	35	/* any consequences resulting from the use of this software. */
36	/* */	36	/* */
37	/* Any person who transfers this source code or any derivative work */	37	/* Any person who transfers this source code or any derivative work */
38	/* must include the IBM copyright notice, this paragraph, and the */	38	/* must include the IBM copyright notice, this paragraph, and the */
39	/* preceding two paragraphs in the transferred software. */	39	/* preceding two paragraphs in the transferred software. */
40	/* */	40	/* */
41	/* COPYRIGHT I B M CORPORATION 1995 */	41	/* COPYRIGHT I B M CORPORATION 1995 */
42	/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */	42	/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */
43	/------------------------------------------------------------------------------- /	43	/------------------------------------------------------------------------------- /
44		44
45	/* U-Boot - Startup Code for IBM 4xx PowerPC based Embedded Boards	45	/* U-Boot - Startup Code for IBM 4xx PowerPC based Embedded Boards
46	*	46	*
47	*	47	*
48	* The processor starts at 0xfffffffc and the code is executed	48	* The processor starts at 0xfffffffc and the code is executed
49	* from flash/rom.	49	* from flash/rom.
50	* in memory, but as long we don't jump around before relocating.	50	* in memory, but as long we don't jump around before relocating.
51	* board_init lies at a quite high address and when the cpu has	51	* board_init lies at a quite high address and when the cpu has
52	* jumped there, everything is ok.	52	* jumped there, everything is ok.
53	* This works because the cpu gives the FLASH (CS0) the whole	53	* This works because the cpu gives the FLASH (CS0) the whole
54	* address space at startup, and board_init lies as a echo of	54	* address space at startup, and board_init lies as a echo of
55	* the flash somewhere up there in the memorymap.	55	* the flash somewhere up there in the memorymap.
56	*	56	*
57	* board_init will change CS0 to be positioned at the correct	57	* board_init will change CS0 to be positioned at the correct
58	* address and (s)dram will be positioned at address 0	58	* address and (s)dram will be positioned at address 0
59	*/	59	*/
60	#include <config.h>	60	#include <config.h>
61	#include <mpc8xx.h>	61	#include <mpc8xx.h>
62	#include <ppc4xx.h>	62	#include <ppc4xx.h>
63	#include <version.h>	63	#include <version.h>
64		64
65	#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */	65	#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
66		66
67	#include <ppc_asm.tmpl>	67	#include <ppc_asm.tmpl>
68	#include <ppc_defs.h>	68	#include <ppc_defs.h>
69		69
70	#include <asm/cache.h>	70	#include <asm/cache.h>
71	#include <asm/mmu.h>	71	#include <asm/mmu.h>
72		72
73	#ifndef CONFIG_IDENT_STRING	73	#ifndef CONFIG_IDENT_STRING
74	#define CONFIG_IDENT_STRING ""	74	#define CONFIG_IDENT_STRING ""
75	#endif	75	#endif
76		76
77	#ifdef CFG_INIT_DCACHE_CS	77	#ifdef CFG_INIT_DCACHE_CS
78	# if (CFG_INIT_DCACHE_CS == 0)	78	# if (CFG_INIT_DCACHE_CS == 0)
79	# define PBxAP pb0ap	79	# define PBxAP pb0ap
80	# define PBxCR pb0cr	80	# define PBxCR pb0cr
81	# endif	81	# endif
82	# if (CFG_INIT_DCACHE_CS == 1)	82	# if (CFG_INIT_DCACHE_CS == 1)
83	# define PBxAP pb1ap	83	# define PBxAP pb1ap
84	# define PBxCR pb1cr	84	# define PBxCR pb1cr
85	# endif	85	# endif
86	# if (CFG_INIT_DCACHE_CS == 2)	86	# if (CFG_INIT_DCACHE_CS == 2)
87	# define PBxAP pb2ap	87	# define PBxAP pb2ap
88	# define PBxCR pb2cr	88	# define PBxCR pb2cr
89	# endif	89	# endif
90	# if (CFG_INIT_DCACHE_CS == 3)	90	# if (CFG_INIT_DCACHE_CS == 3)
91	# define PBxAP pb3ap	91	# define PBxAP pb3ap
92	# define PBxCR pb3cr	92	# define PBxCR pb3cr
93	# endif	93	# endif
94	# if (CFG_INIT_DCACHE_CS == 4)	94	# if (CFG_INIT_DCACHE_CS == 4)
95	# define PBxAP pb4ap	95	# define PBxAP pb4ap
96	# define PBxCR pb4cr	96	# define PBxCR pb4cr
97	# endif	97	# endif
98	# if (CFG_INIT_DCACHE_CS == 5)	98	# if (CFG_INIT_DCACHE_CS == 5)
99	# define PBxAP pb5ap	99	# define PBxAP pb5ap
100	# define PBxCR pb5cr	100	# define PBxCR pb5cr
101	# endif	101	# endif
102	# if (CFG_INIT_DCACHE_CS == 6)	102	# if (CFG_INIT_DCACHE_CS == 6)
103	# define PBxAP pb6ap	103	# define PBxAP pb6ap
104	# define PBxCR pb6cr	104	# define PBxCR pb6cr
105	# endif	105	# endif
106	# if (CFG_INIT_DCACHE_CS == 7)	106	# if (CFG_INIT_DCACHE_CS == 7)
107	# define PBxAP pb7ap	107	# define PBxAP pb7ap
108	# define PBxCR pb7cr	108	# define PBxCR pb7cr
109	# endif	109	# endif
110	#endif /* CFG_INIT_DCACHE_CS */	110	#endif /* CFG_INIT_DCACHE_CS */
111		111
112	/* We don't want the MMU yet.	112	/* We don't want the MMU yet.
113	*/	113	*/
114	#undef MSR_KERNEL	114	#undef MSR_KERNEL
115	#define MSR_KERNEL ( MSR_ME ) /* Machine Check */	115	#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
116		116
117		117
118	.extern ext_bus_cntlr_init	118	.extern ext_bus_cntlr_init
119	.extern sdram_init	119	.extern sdram_init
120		120
121	/*	121	/*
122	* Set up GOT: Global Offset Table	122	* Set up GOT: Global Offset Table
123	*	123	*
124	* Use r14 to access the GOT	124	* Use r14 to access the GOT
125	*/	125	*/
126	START_GOT	126	START_GOT
127	GOT_ENTRY(_GOT2_TABLE_)	127	GOT_ENTRY(_GOT2_TABLE_)
128	GOT_ENTRY(_FIXUP_TABLE_)	128	GOT_ENTRY(_FIXUP_TABLE_)
129		129
130	GOT_ENTRY(_start)	130	GOT_ENTRY(_start)
131	GOT_ENTRY(_start_of_vectors)	131	GOT_ENTRY(_start_of_vectors)
132	GOT_ENTRY(_end_of_vectors)	132	GOT_ENTRY(_end_of_vectors)
133	GOT_ENTRY(transfer_to_handler)	133	GOT_ENTRY(transfer_to_handler)
134		134
135	GOT_ENTRY(__init_end)	135	GOT_ENTRY(__init_end)
136	GOT_ENTRY(_end)	136	GOT_ENTRY(_end)
137	GOT_ENTRY(__bss_start)	137	GOT_ENTRY(__bss_start)
138	END_GOT	138	END_GOT
139		139
140	/*	140	/*
141	* 440 Startup -- on reset only the top 4k of the effective	141	* 440 Startup -- on reset only the top 4k of the effective
142	* address space is mapped in by an entry in the instruction	142	* address space is mapped in by an entry in the instruction
143	* and data shadow TLB. The .bootpg section is located in the	143	* and data shadow TLB. The .bootpg section is located in the
144	* top 4k & does only what's necessary to map in the the rest	144	* top 4k & does only what's necessary to map in the the rest
145	* of the boot rom. Once the boot rom is mapped in we can	145	* of the boot rom. Once the boot rom is mapped in we can
146	* proceed with normal startup.	146	* proceed with normal startup.
147	*	147	*
148	* NOTE: CS0 only covers the top 2MB of the effective address	148	* NOTE: CS0 only covers the top 2MB of the effective address
149	* space after reset.	149	* space after reset.
150	*/	150	*/
151		151
152	#if defined(CONFIG_440)	152	#if defined(CONFIG_440)
153	.section .bootpg,"ax"	153	.section .bootpg,"ax"
154	.globl _start_440	154	.globl _start_440
155		155
156	/**************************************************************************/	156	/**************************************************************************/
157	_start_440:	157	_start_440:
158	/----------------------------------------------------------------/	158	/----------------------------------------------------------------/
159	/* Clear and set up some registers. */	159	/* Clear and set up some registers. */
160	/----------------------------------------------------------------/	160	/----------------------------------------------------------------/
161	iccci r0,r0 /* NOTE: operands not used for 440 */	161	iccci r0,r0 /* NOTE: operands not used for 440 */
162	dccci r0,r0 /* NOTE: operands not used for 440 */	162	dccci r0,r0 /* NOTE: operands not used for 440 */
163	sync	163	sync
164	li r0,0	164	li r0,0
165	mtspr srr0,r0	165	mtspr srr0,r0
166	mtspr srr1,r0	166	mtspr srr1,r0
167	mtspr csrr0,r0	167	mtspr csrr0,r0
168	mtspr csrr1,r0	168	mtspr csrr1,r0
169	#if defined (CONFIG_440_GX) /* NOTE: 440GX adds machine check status regs */	169	#if defined (CONFIG_440_GX) /* NOTE: 440GX adds machine check status regs */
170	mtspr mcsrr0,r0	170	mtspr mcsrr0,r0
171	mtspr mcsrr1,r0	171	mtspr mcsrr1,r0
172	mfspr r1, mcsr	172	mfspr r1, mcsr
173	mtspr mcsr,r1	173	mtspr mcsr,r1
174	#endif	174	#endif
175	/----------------------------------------------------------------/	175	/----------------------------------------------------------------/
176	/* Initialize debug */	176	/* Initialize debug */
177	/----------------------------------------------------------------/	177	/----------------------------------------------------------------/
178	mtspr dbcr0,r0	178	mtspr dbcr0,r0
179	mtspr dbcr1,r0	179	mtspr dbcr1,r0
180	mtspr dbcr2,r0	180	mtspr dbcr2,r0
181	mtspr iac1,r0	181	mtspr iac1,r0
182	mtspr iac2,r0	182	mtspr iac2,r0
183	mtspr iac3,r0	183	mtspr iac3,r0
184	mtspr dac1,r0	184	mtspr dac1,r0
185	mtspr dac2,r0	185	mtspr dac2,r0
186	mtspr dvc1,r0	186	mtspr dvc1,r0
187	mtspr dvc2,r0	187	mtspr dvc2,r0
188		188
189	mfspr r1,dbsr	189	mfspr r1,dbsr
190	mtspr dbsr,r1 /* Clear all valid bits */	190	mtspr dbsr,r1 /* Clear all valid bits */
191		191
192	/----------------------------------------------------------------/	192	/----------------------------------------------------------------/
193	/* CCR0 init */	193	/* CCR0 init */
194	/----------------------------------------------------------------/	194	/----------------------------------------------------------------/
195	/* Disable store gathering & broadcast, guarantee inst/data	195	/* Disable store gathering & broadcast, guarantee inst/data
196	* cache block touch, force load/store alignment	196	* cache block touch, force load/store alignment
197	* (see errata 1.12: 440_33)	197	* (see errata 1.12: 440_33)
198	*/	198	*/
199	lis r1,0x0030 /* store gathering & broadcast disable */	199	lis r1,0x0030 /* store gathering & broadcast disable */
200	ori r1,r1,0x6000 /* cache touch */	200	ori r1,r1,0x6000 /* cache touch */
201	mtspr ccr0,r1	201	mtspr ccr0,r1
202		202
203	/----------------------------------------------------------------/	203	/----------------------------------------------------------------/
204	/* Setup interrupt vectors */	204	/* Setup interrupt vectors */
205	/----------------------------------------------------------------/	205	/----------------------------------------------------------------/
206	mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */	206	mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */
207	li r1,0x0100	207	li r1,0x0100
208	mtspr ivor0,r1 /* Critical input */	208	mtspr ivor0,r1 /* Critical input */
209	li r1,0x0200	209	li r1,0x0200
210	mtspr ivor1,r1 /* Machine check */	210	mtspr ivor1,r1 /* Machine check */
211	li r1,0x0300	211	li r1,0x0300
212	mtspr ivor2,r1 /* Data storage */	212	mtspr ivor2,r1 /* Data storage */
213	li r1,0x0400	213	li r1,0x0400
214	mtspr ivor3,r1 /* Instruction storage */	214	mtspr ivor3,r1 /* Instruction storage */
215	li r1,0x0500	215	li r1,0x0500
216	mtspr ivor4,r1 /* External interrupt */	216	mtspr ivor4,r1 /* External interrupt */
217	li r1,0x0600	217	li r1,0x0600
218	mtspr ivor5,r1 /* Alignment */	218	mtspr ivor5,r1 /* Alignment */
219	li r1,0x0700	219	li r1,0x0700
220	mtspr ivor6,r1 /* Program check */	220	mtspr ivor6,r1 /* Program check */
221	li r1,0x0800	221	li r1,0x0800
222	mtspr ivor7,r1 /* Floating point unavailable */	222	mtspr ivor7,r1 /* Floating point unavailable */
223	li r1,0x0c00	223	li r1,0x0c00
224	mtspr ivor8,r1 /* System call */	224	mtspr ivor8,r1 /* System call */
225	li r1,0x1000	225	li r1,0x1000
226	mtspr ivor10,r1 /* Decrementer (PIT for 440) */	226	mtspr ivor10,r1 /* Decrementer (PIT for 440) */
227	li r1,0x1400	227	li r1,0x1400
228	mtspr ivor13,r1 /* Data TLB error */	228	mtspr ivor13,r1 /* Data TLB error */
229	li r1,0x1300	229	li r1,0x1300
230	mtspr ivor14,r1 /* Instr TLB error */	230	mtspr ivor14,r1 /* Instr TLB error */
231	li r1,0x2000	231	li r1,0x2000
232	mtspr ivor15,r1 /* Debug */	232	mtspr ivor15,r1 /* Debug */
233		233
234	/----------------------------------------------------------------/	234	/----------------------------------------------------------------/
235	/* Configure cache regions */	235	/* Configure cache regions */
236	/----------------------------------------------------------------/	236	/----------------------------------------------------------------/
237	mtspr inv0,r0	237	mtspr inv0,r0
238	mtspr inv1,r0	238	mtspr inv1,r0
239	mtspr inv2,r0	239	mtspr inv2,r0
240	mtspr inv3,r0	240	mtspr inv3,r0
241	mtspr dnv0,r0	241	mtspr dnv0,r0
242	mtspr dnv1,r0	242	mtspr dnv1,r0
243	mtspr dnv2,r0	243	mtspr dnv2,r0
244	mtspr dnv3,r0	244	mtspr dnv3,r0
245	mtspr itv0,r0	245	mtspr itv0,r0
246	mtspr itv1,r0	246	mtspr itv1,r0
247	mtspr itv2,r0	247	mtspr itv2,r0
248	mtspr itv3,r0	248	mtspr itv3,r0
249	mtspr dtv0,r0	249	mtspr dtv0,r0
250	mtspr dtv1,r0	250	mtspr dtv1,r0
251	mtspr dtv2,r0	251	mtspr dtv2,r0
252	mtspr dtv3,r0	252	mtspr dtv3,r0
253		253
254	/----------------------------------------------------------------/	254	/----------------------------------------------------------------/
255	/* Cache victim limits */	255	/* Cache victim limits */
256	/----------------------------------------------------------------/	256	/----------------------------------------------------------------/
257	/* floors 0, ceiling max to use the entire cache -- nothing locked	257	/* floors 0, ceiling max to use the entire cache -- nothing locked
258	*/	258	*/
259	lis r1,0x0001	259	lis r1,0x0001
260	ori r1,r1,0xf800	260	ori r1,r1,0xf800
261	mtspr ivlim,r1	261	mtspr ivlim,r1
262	mtspr dvlim,r1	262	mtspr dvlim,r1
263		263
264	/----------------------------------------------------------------/	264	/----------------------------------------------------------------/
265	/* Clear all TLB entries -- TID = 0, TS = 0 */	265	/* Clear all TLB entries -- TID = 0, TS = 0 */
266	/----------------------------------------------------------------/	266	/----------------------------------------------------------------/
267	mtspr mmucr,r0	267	mtspr mmucr,r0
268	li r1,0x003f /* 64 TLB entries */	268	li r1,0x003f /* 64 TLB entries */
269	mtctr r1	269	mtctr r1
270	0: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/	270	0: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
271	subi r1,r1,0x0001	271	subi r1,r1,0x0001
272	bdnz 0b	272	bdnz 0b
273		273
274	/----------------------------------------------------------------/	274	/----------------------------------------------------------------/
275	/* TLB entry setup -- step thru tlbtab */	275	/* TLB entry setup -- step thru tlbtab */
276	/----------------------------------------------------------------/	276	/----------------------------------------------------------------/
277	bl tlbtab /* Get tlbtab pointer */	277	bl tlbtab /* Get tlbtab pointer */
278	mr r5,r0	278	mr r5,r0
279	li r1,0x003f /* 64 TLB entries max */	279	li r1,0x003f /* 64 TLB entries max */
280	mtctr r1	280	mtctr r1
281	li r4,0 /* TLB # */	281	li r4,0 /* TLB # */
282		282
283	addi r5,r5,-4	283	addi r5,r5,-4
284	1: lwzu r0,4(r5)	284	1: lwzu r0,4(r5)
285	cmpwi r0,0	285	cmpwi r0,0
286	beq 2f /* 0 marks end */	286	beq 2f /* 0 marks end */
287	lwzu r1,4(r5)	287	lwzu r1,4(r5)
288	lwzu r2,4(r5)	288	lwzu r2,4(r5)
289	tlbwe r0,r4,0 /* TLB Word 0 */	289	tlbwe r0,r4,0 /* TLB Word 0 */
290	tlbwe r1,r4,1 /* TLB Word 1 */	290	tlbwe r1,r4,1 /* TLB Word 1 */
291	tlbwe r2,r4,2 /* TLB Word 2 */	291	tlbwe r2,r4,2 /* TLB Word 2 */
292	addi r4,r4,1 /* Next TLB */	292	addi r4,r4,1 /* Next TLB */
293	bdnz 1b	293	bdnz 1b
294		294
295	/----------------------------------------------------------------/	295	/----------------------------------------------------------------/
296	/* Continue from 'normal' start */	296	/* Continue from 'normal' start */
297	/----------------------------------------------------------------/	297	/----------------------------------------------------------------/
298	2: bl 3f	298	2: bl 3f
299	b _start	299	b _start
300		300
301	3: li r0,0	301	3: li r0,0
302	mtspr srr1,r0 /* Keep things disabled for now */	302	mtspr srr1,r0 /* Keep things disabled for now */
303	mflr r1	303	mflr r1
304	mtspr srr0,r1	304	mtspr srr0,r1
305	rfi	305	rfi
306	#endif /* CONFIG_440 */	306	#endif /* CONFIG_440 */
307		307
308	/*	308	/*
309	* r3 - 1st arg to board_init(): IMMP pointer	309	* r3 - 1st arg to board_init(): IMMP pointer
310	* r4 - 2nd arg to board_init(): boot flag	310	* r4 - 2nd arg to board_init(): boot flag
311	*/	311	*/
312	.text	312	.text
313	.long 0x27051956 /* U-Boot Magic Number */	313	.long 0x27051956 /* U-Boot Magic Number */
314	.globl version_string	314	.globl version_string
315	version_string:	315	version_string:
316	.ascii U_BOOT_VERSION	316	.ascii U_BOOT_VERSION
317	.ascii " (", __DATE__, " - ", __TIME__, ")"	317	.ascii " (", __DATE__, " - ", __TIME__, ")"
318	.ascii CONFIG_IDENT_STRING, "\0"	318	.ascii CONFIG_IDENT_STRING, "\0"
319		319
320	/*	320	/*
321	* Maybe this should be moved somewhere else because the current	321	* Maybe this should be moved somewhere else because the current
322	* location (0x100) is where the CriticalInput Execption should be.	322	* location (0x100) is where the CriticalInput Execption should be.
323	*/	323	*/
324	. = EXC_OFF_SYS_RESET	324	. = EXC_OFF_SYS_RESET
325	.globl _start	325	.globl _start
326	_start:	326	_start:
327		327
328	/*****************************************************************************/	328	/*****************************************************************************/
329	#if defined(CONFIG_440)	329	#if defined(CONFIG_440)
330		330
331	/----------------------------------------------------------------/	331	/----------------------------------------------------------------/
332	/* Clear and set up some registers. */	332	/* Clear and set up some registers. */
333	/----------------------------------------------------------------/	333	/----------------------------------------------------------------/
334	li r0,0x0000	334	li r0,0x0000
335	lis r1,0xffff	335	lis r1,0xffff
336	mtspr dec,r0 /* prevent dec exceptions */	336	mtspr dec,r0 /* prevent dec exceptions */
337	mtspr tbl,r0 /* prevent fit & wdt exceptions */	337	mtspr tbl,r0 /* prevent fit & wdt exceptions */
338	mtspr tbu,r0	338	mtspr tbu,r0
339	mtspr tsr,r1 /* clear all timer exception status */	339	mtspr tsr,r1 /* clear all timer exception status */
340	mtspr tcr,r0 /* disable all */	340	mtspr tcr,r0 /* disable all */
341	mtspr esr,r0 /* clear exception syndrome register */	341	mtspr esr,r0 /* clear exception syndrome register */
342	mtxer r0 /* clear integer exception register */	342	mtxer r0 /* clear integer exception register */
343	#if !defined(CONFIG_440_GX)	343	#if !defined(CONFIG_440_GX)
344	lis r1,0x0002 /* set CE bit (Critical Exceptions) */	344	lis r1,0x0002 /* set CE bit (Critical Exceptions) */
345	ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */	345	ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */
346	mtmsr r1 /* change MSR */	346	mtmsr r1 /* change MSR */
347	#elif !defined(CONFIG_440_EP) && !defined(CONFIG_440_GR)	347	#elif !defined(CONFIG_440_EP) && !defined(CONFIG_440_GR)
348	bl __440gx_msr_set	348	bl __440gx_msr_set
349	b __440gx_msr_continue	349	b __440gx_msr_continue
350		350
351	__440gx_msr_set:	351	__440gx_msr_set:
352	lis r1, 0x0002 /* set CE bit (Critical Exceptions) */	352	lis r1, 0x0002 /* set CE bit (Critical Exceptions) */
353	ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */	353	ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */
354	mtspr srr1,r1	354	mtspr srr1,r1
355	mflr r1	355	mflr r1
356	mtspr srr0,r1	356	mtspr srr0,r1
357	rfi	357	rfi
358	__440gx_msr_continue:	358	__440gx_msr_continue:
359	#endif	359	#endif
360		360
361	/----------------------------------------------------------------/	361	/----------------------------------------------------------------/
362	/* Debug setup -- some (not very good) ice's need an event*/	362	/* Debug setup -- some (not very good) ice's need an event*/
363	/* to establish control :-( Define CFG_INIT_DBCR to the dbsr */	363	/* to establish control :-( Define CFG_INIT_DBCR to the dbsr */
364	/* value you need in this case 0x8cff 0000 should do the trick */	364	/* value you need in this case 0x8cff 0000 should do the trick */
365	/----------------------------------------------------------------/	365	/----------------------------------------------------------------/
366	#if defined(CFG_INIT_DBCR)	366	#if defined(CFG_INIT_DBCR)
367	lis r1,0xffff	367	lis r1,0xffff
368	ori r1,r1,0xffff	368	ori r1,r1,0xffff
369	mtspr dbsr,r1 /* Clear all status bits */	369	mtspr dbsr,r1 /* Clear all status bits */
370	lis r0,CFG_INIT_DBCR@h	370	lis r0,CFG_INIT_DBCR@h
371	ori r0,r0,CFG_INIT_DBCR@l	371	ori r0,r0,CFG_INIT_DBCR@l
372	mtspr dbcr0,r0	372	mtspr dbcr0,r0
373	isync	373	isync
374	#endif	374	#endif
375		375
376	/----------------------------------------------------------------/	376	/----------------------------------------------------------------/
377	/* Setup the internal SRAM */	377	/* Setup the internal SRAM */
378	/----------------------------------------------------------------/	378	/----------------------------------------------------------------/
379	li r0,0	379	li r0,0
380	#if defined(CONFIG_440_EP) \|\| defined(CONFIG_440_GR)	380	#if defined(CONFIG_440_EP) \|\| defined(CONFIG_440_GR)
381	/* Clear Dcache to use as RAM */	381	/* Clear Dcache to use as RAM */
382	addis r3,r0,CFG_INIT_RAM_ADDR@h	382	addis r3,r0,CFG_INIT_RAM_ADDR@h
383	ori r3,r3,CFG_INIT_RAM_ADDR@l	383	ori r3,r3,CFG_INIT_RAM_ADDR@l
384	addis r4,r0,CFG_INIT_RAM_END@h	384	addis r4,r0,CFG_INIT_RAM_END@h
385	ori r4,r4,CFG_INIT_RAM_END@l	385	ori r4,r4,CFG_INIT_RAM_END@l
386	rlwinm. r5,r4,0,27,31	386	rlwinm. r5,r4,0,27,31
387	rlwinm r5,r4,27,5,31	387	rlwinm r5,r4,27,5,31
388	beq ..d_ran	388	beq ..d_ran
389	addi r5,r5,0x0001	389	addi r5,r5,0x0001
390	..d_ran:	390	..d_ran:
391	mtctr r5	391	mtctr r5
392	..d_ag:	392	..d_ag:
393	dcbz r0,r3	393	dcbz r0,r3
394	addi r3,r3,32	394	addi r3,r3,32
395	bdnz ..d_ag	395	bdnz ..d_ag
396	#else	396	#else
397	#if defined (CONFIG_440_GX)	397	#if defined (CONFIG_440_GX)
398	mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */	398	mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
399	#endif	399	#endif
400	mtdcr isram0_sb1cr,r0 /* Disable bank 1 */	400	mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
401		401
402	li r2,0x7fff	402	li r2,0x7fff
403	ori r2,r2,0xffff	403	ori r2,r2,0xffff
404	mfdcr r1,isram0_dpc	404	mfdcr r1,isram0_dpc
405	and r1,r1,r2 /* Disable parity check */	405	and r1,r1,r2 /* Disable parity check */
406	mtdcr isram0_dpc,r1	406	mtdcr isram0_dpc,r1
407	mfdcr r1,isram0_pmeg	407	mfdcr r1,isram0_pmeg
408	andis. r1,r1,r2 /* Disable pwr mgmt */	408	andis. r1,r1,r2 /* Disable pwr mgmt */
409	mtdcr isram0_pmeg,r1	409	mtdcr isram0_pmeg,r1
410		410
411	lis r1,0x8000 /* BAS = 8000_0000 */	411	lis r1,0x8000 /* BAS = 8000_0000 */
412	#if defined(CONFIG_440_GX)	412	#if defined(CONFIG_440_GX)
413	ori r1,r1,0x0980 /* first 64k */	413	ori r1,r1,0x0980 /* first 64k */
414	mtdcr isram0_sb0cr,r1	414	mtdcr isram0_sb0cr,r1
415	lis r1,0x8001	415	lis r1,0x8001
416	ori r1,r1,0x0980 /* second 64k */	416	ori r1,r1,0x0980 /* second 64k */
417	mtdcr isram0_sb1cr,r1	417	mtdcr isram0_sb1cr,r1
418	lis r1, 0x8002	418	lis r1, 0x8002
419	ori r1,r1, 0x0980 /* third 64k */	419	ori r1,r1, 0x0980 /* third 64k */
420	mtdcr isram0_sb2cr,r1	420	mtdcr isram0_sb2cr,r1
421	lis r1, 0x8003	421	lis r1, 0x8003
422	ori r1,r1, 0x0980 /* fourth 64k */	422	ori r1,r1, 0x0980 /* fourth 64k */
423	mtdcr isram0_sb3cr,r1	423	mtdcr isram0_sb3cr,r1
424	#else	424	#else
425	ori r1,r1,0x0380 /* 8k rw */	425	ori r1,r1,0x0380 /* 8k rw */
426	mtdcr isram0_sb0cr,r1	426	mtdcr isram0_sb0cr,r1
427	#endif	427	#endif
428	#endif	428	#endif
429		429
430	/----------------------------------------------------------------/	430	/----------------------------------------------------------------/
431	/* Setup the stack in internal SRAM */	431	/* Setup the stack in internal SRAM */
432	/----------------------------------------------------------------/	432	/----------------------------------------------------------------/
433	lis r1,CFG_INIT_RAM_ADDR@h	433	lis r1,CFG_INIT_RAM_ADDR@h
434	ori r1,r1,CFG_INIT_SP_OFFSET@l	434	ori r1,r1,CFG_INIT_SP_OFFSET@l
435		435
436	li r0,0	436	li r0,0
437	stwu r0,-4(r1)	437	stwu r0,-4(r1)
438	stwu r0,-4(r1) /* Terminate call chain */	438	stwu r0,-4(r1) /* Terminate call chain */
439		439
440	stwu r1,-8(r1) /* Save back chain and move SP */	440	stwu r1,-8(r1) /* Save back chain and move SP */
441	lis r0,RESET_VECTOR@h /* Address of reset vector */	441	lis r0,RESET_VECTOR@h /* Address of reset vector */
442	ori r0,r0, RESET_VECTOR@l	442	ori r0,r0, RESET_VECTOR@l
443	stwu r1,-8(r1) /* Save back chain and move SP */	443	stwu r1,-8(r1) /* Save back chain and move SP */
444	stw r0,+12(r1) /* Save return addr (underflow vect) */	444	stw r0,+12(r1) /* Save return addr (underflow vect) */
445		445
446	GET_GOT	446	GET_GOT
447	bl board_init_f	447	bl board_init_f
448		448
449	#endif /* CONFIG_440 */	449	#endif /* CONFIG_440 */
450		450
451	/*****************************************************************************/	451	/*****************************************************************************/
452	#ifdef CONFIG_IOP480	452	#ifdef CONFIG_IOP480
453	/----------------------------------------------------------------------- /	453	/----------------------------------------------------------------------- /
454	/* Set up some machine state registers. */	454	/* Set up some machine state registers. */
455	/----------------------------------------------------------------------- /	455	/----------------------------------------------------------------------- /
456	addi r0,r0,0x0000 /* initialize r0 to zero */	456	addi r0,r0,0x0000 /* initialize r0 to zero */
457	mtspr esr,r0 /* clear Exception Syndrome Reg */	457	mtspr esr,r0 /* clear Exception Syndrome Reg */
458	mttcr r0 /* timer control register */	458	mttcr r0 /* timer control register */
459	mtexier r0 /* disable all interrupts */	459	mtexier r0 /* disable all interrupts */
460	addi r4,r0,0x1000 /* set ME bit (Machine Exceptions) */	460	addi r4,r0,0x1000 /* set ME bit (Machine Exceptions) */
461	oris r4,r4,0x2 /* set CE bit (Critical Exceptions) */	461	oris r4,r4,0x2 /* set CE bit (Critical Exceptions) */
462	mtmsr r4 /* change MSR */	462	mtmsr r4 /* change MSR */
463	addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */	463	addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
464	ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */	464	ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
465	mtdbsr r4 /* clear/reset the dbsr */	465	mtdbsr r4 /* clear/reset the dbsr */
466	mtexisr r4 /* clear all pending interrupts */	466	mtexisr r4 /* clear all pending interrupts */
467	addis r4,r0,0x8000	467	addis r4,r0,0x8000
468	mtexier r4 /* enable critical exceptions */	468	mtexier r4 /* enable critical exceptions */
469	addis r4,r0,0x0000 /* assume 403GCX - enable core clk */	469	addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
470	ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */	470	ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
471	mtiocr r4 /* since bit not used) & DRC to latch */	471	mtiocr r4 /* since bit not used) & DRC to latch */
472	/* data bus on rising edge of CAS */	472	/* data bus on rising edge of CAS */
473	/----------------------------------------------------------------------- /	473	/----------------------------------------------------------------------- /
474	/* Clear XER. */	474	/* Clear XER. */
475	/----------------------------------------------------------------------- /	475	/----------------------------------------------------------------------- /
476	mtxer r0	476	mtxer r0
477	/----------------------------------------------------------------------- /	477	/----------------------------------------------------------------------- /
478	/* Invalidate i-cache and d-cache TAG arrays. */	478	/* Invalidate i-cache and d-cache TAG arrays. */
479	/----------------------------------------------------------------------- /	479	/----------------------------------------------------------------------- /
480	addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */	480	addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
481	addi r4,0,1024 /* 1/4 of I-cache */	481	addi r4,0,1024 /* 1/4 of I-cache */
482	..cloop:	482	..cloop:
483	iccci 0,r3	483	iccci 0,r3
484	iccci r4,r3	484	iccci r4,r3
485	dccci 0,r3	485	dccci 0,r3
486	addic. r3,r3,-16 /* move back one cache line */	486	addic. r3,r3,-16 /* move back one cache line */
487	bne ..cloop /* loop back to do rest until r3 = 0 */	487	bne ..cloop /* loop back to do rest until r3 = 0 */
488		488
489	/* */	489	/* */
490	/* initialize IOP480 so it can read 1 MB code area for SRAM spaces */	490	/* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
491	/* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */	491	/* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
492	/* */	492	/* */
493		493
494	/* first copy IOP480 register base address into r3 */	494	/* first copy IOP480 register base address into r3 */
495	addis r3,0,0x5000 /* IOP480 register base address hi */	495	addis r3,0,0x5000 /* IOP480 register base address hi */
496	/* ori r3,r3,0x0000 / IOP480 register base address lo */	496	/* ori r3,r3,0x0000 / IOP480 register base address lo */
497		497
498	#ifdef CONFIG_ADCIOP	498	#ifdef CONFIG_ADCIOP
499	/* use r4 as the working variable */	499	/* use r4 as the working variable */
500	/* turn on CS3 (LOCCTL.7) */	500	/* turn on CS3 (LOCCTL.7) */
501	lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */	501	lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
502	andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */	502	andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
503	stw r4,0x84(r3) /* LOCTL is at offset 0x84 */	503	stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
504	#endif	504	#endif
505		505
506	#ifdef CONFIG_DASA_SIM	506	#ifdef CONFIG_DASA_SIM
507	/* use r4 as the working variable */	507	/* use r4 as the working variable */
508	/* turn on MA17 (LOCCTL.7) */	508	/* turn on MA17 (LOCCTL.7) */
509	lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */	509	lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
510	ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */	510	ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
511	stw r4,0x84(r3) /* LOCTL is at offset 0x84 */	511	stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
512	#endif	512	#endif
513		513
514	/* turn on MA16..13 (LCS0BRD.12 = 0) */	514	/* turn on MA16..13 (LCS0BRD.12 = 0) */
515	lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */	515	lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
516	andi. r4,r4,0xefff /* make bit 12 = 0 */	516	andi. r4,r4,0xefff /* make bit 12 = 0 */
517	stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */	517	stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
518		518
519	/* make sure above stores all comlete before going on */	519	/* make sure above stores all comlete before going on */
520	sync	520	sync
521		521
522	/* last thing, set local init status done bit (DEVINIT.31) */	522	/* last thing, set local init status done bit (DEVINIT.31) */
523	lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */	523	lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
524	oris r4,r4,0x8000 /* make bit 31 = 1 */	524	oris r4,r4,0x8000 /* make bit 31 = 1 */
525	stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */	525	stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
526		526
527	/* clear all pending interrupts and disable all interrupts */	527	/* clear all pending interrupts and disable all interrupts */
528	li r4,-1 /* set p1 to 0xffffffff */	528	li r4,-1 /* set p1 to 0xffffffff */
529	stw r4,0x1b0(r3) /* clear all pending interrupts */	529	stw r4,0x1b0(r3) /* clear all pending interrupts */
530	stw r4,0x1b8(r3) /* clear all pending interrupts */	530	stw r4,0x1b8(r3) /* clear all pending interrupts */
531	li r4,0 /* set r4 to 0 */	531	li r4,0 /* set r4 to 0 */
532	stw r4,0x1b4(r3) /* disable all interrupts */	532	stw r4,0x1b4(r3) /* disable all interrupts */
533	stw r4,0x1bc(r3) /* disable all interrupts */	533	stw r4,0x1bc(r3) /* disable all interrupts */
534		534
535	/* make sure above stores all comlete before going on */	535	/* make sure above stores all comlete before going on */
536	sync	536	sync
537		537
538	/----------------------------------------------------------------------- /	538	/----------------------------------------------------------------------- /
539	/* Enable two 128MB cachable regions. */	539	/* Enable two 128MB cachable regions. */
540	/----------------------------------------------------------------------- /	540	/----------------------------------------------------------------------- /
541	addis r1,r0,0x8000	541	addis r1,r0,0x8000
542	addi r1,r1,0x0001	542	addi r1,r1,0x0001
543	mticcr r1 /* instruction cache */	543	mticcr r1 /* instruction cache */
544		544
545	addis r1,r0,0x0000	545	addis r1,r0,0x0000
546	addi r1,r1,0x0000	546	addi r1,r1,0x0000
547	mtdccr r1 /* data cache */	547	mtdccr r1 /* data cache */
548		548
549	addis r1,r0,CFG_INIT_RAM_ADDR@h	549	addis r1,r0,CFG_INIT_RAM_ADDR@h
550	ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */	550	ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */
551	li r0, 0 /* Make room for stack frame header and */	551	li r0, 0 /* Make room for stack frame header and */
552	stwu r0, -4(r1) /* clear final stack frame so that */	552	stwu r0, -4(r1) /* clear final stack frame so that */
553	stwu r0, -4(r1) /* stack backtraces terminate cleanly */	553	stwu r0, -4(r1) /* stack backtraces terminate cleanly */
554		554
555	GET_GOT /* initialize GOT access */	555	GET_GOT /* initialize GOT access */
556		556
557	bl board_init_f /* run first part of init code (from Flash) */	557	bl board_init_f /* run first part of init code (from Flash) */
558		558
559	#endif /* CONFIG_IOP480 */	559	#endif /* CONFIG_IOP480 */
560		560
561	/*****************************************************************************/	561	/*****************************************************************************/
562	#if defined(CONFIG_405GP) \|\| defined(CONFIG_405CR) \|\| defined(CONFIG_405) \|\| defined(CONFIG_405EP)	562	#if defined(CONFIG_405GP) \|\| defined(CONFIG_405CR) \|\| defined(CONFIG_405) \|\| defined(CONFIG_405EP)
563	/----------------------------------------------------------------------- /	563	/----------------------------------------------------------------------- /
564	/* Clear and set up some registers. */	564	/* Clear and set up some registers. */
565	/----------------------------------------------------------------------- /	565	/----------------------------------------------------------------------- /
566	addi r4,r0,0x0000	566	addi r4,r0,0x0000
567	mtspr sgr,r4	567	mtspr sgr,r4
568	mtspr dcwr,r4	568	mtspr dcwr,r4
569	mtesr r4 /* clear Exception Syndrome Reg */	569	mtesr r4 /* clear Exception Syndrome Reg */
570	mttcr r4 /* clear Timer Control Reg */	570	mttcr r4 /* clear Timer Control Reg */
571	mtxer r4 /* clear Fixed-Point Exception Reg */	571	mtxer r4 /* clear Fixed-Point Exception Reg */
572	mtevpr r4 /* clear Exception Vector Prefix Reg */	572	mtevpr r4 /* clear Exception Vector Prefix Reg */
573	addi r4,r0,0x1000 /* set ME bit (Machine Exceptions) */	573	addi r4,r0,0x1000 /* set ME bit (Machine Exceptions) */
574	oris r4,r4,0x0002 /* set CE bit (Critical Exceptions) */	574	oris r4,r4,0x0002 /* set CE bit (Critical Exceptions) */
575	mtmsr r4 /* change MSR */	575	mtmsr r4 /* change MSR */
576	addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */	576	addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
577	/* dbsr is cleared by setting bits to 1) */	577	/* dbsr is cleared by setting bits to 1) */
578	mtdbsr r4 /* clear/reset the dbsr */	578	mtdbsr r4 /* clear/reset the dbsr */
579		579
580	/----------------------------------------------------------------------- /	580	/----------------------------------------------------------------------- /
581	/* Invalidate I and D caches. Enable I cache for defined memory regions */	581	/* Invalidate I and D caches. Enable I cache for defined memory regions */
582	/* to speed things up. Leave the D cache disabled for now. It will be */	582	/* to speed things up. Leave the D cache disabled for now. It will be */
583	/* enabled/left disabled later based on user selected menu options. */	583	/* enabled/left disabled later based on user selected menu options. */
584	/* Be aware that the I cache may be disabled later based on the menu */	584	/* Be aware that the I cache may be disabled later based on the menu */
585	/* options as well. See miscLib/main.c. */	585	/* options as well. See miscLib/main.c. */
586	/----------------------------------------------------------------------- /	586	/----------------------------------------------------------------------- /
587	bl invalidate_icache	587	bl invalidate_icache
588	bl invalidate_dcache	588	bl invalidate_dcache
589		589
590	/----------------------------------------------------------------------- /	590	/----------------------------------------------------------------------- /
591	/* Enable two 128MB cachable regions. */	591	/* Enable two 128MB cachable regions. */
592	/----------------------------------------------------------------------- /	592	/----------------------------------------------------------------------- /
593	addis r4,r0,0x8000	593	addis r4,r0,0x8000
594	addi r4,r4,0x0001	594	addi r4,r4,0x0001
595	mticcr r4 /* instruction cache */	595	mticcr r4 /* instruction cache */
596	isync	596	isync
597		597
598	addis r4,r0,0x0000	598	addis r4,r0,0x0000
599	addi r4,r4,0x0000	599	addi r4,r4,0x0000
600	mtdccr r4 /* data cache */	600	mtdccr r4 /* data cache */
601		601
602	#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))	602	#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
603	/----------------------------------------------------------------------- /	603	/----------------------------------------------------------------------- /
604	/* Tune the speed and size for flash CS0 */	604	/* Tune the speed and size for flash CS0 */
605	/----------------------------------------------------------------------- /	605	/----------------------------------------------------------------------- /
606	bl ext_bus_cntlr_init	606	bl ext_bus_cntlr_init
607	#endif	607	#endif
608		608
609	#if defined(CONFIG_405EP)	609	#if defined(CONFIG_405EP)
610	/----------------------------------------------------------------------- /	610	/----------------------------------------------------------------------- /
611	/* DMA Status, clear to come up clean */	611	/* DMA Status, clear to come up clean */
612	/----------------------------------------------------------------------- /	612	/----------------------------------------------------------------------- /
613	addis r3,r0, 0xFFFF /* Clear all existing DMA status */	613	addis r3,r0, 0xFFFF /* Clear all existing DMA status */
614	ori r3,r3, 0xFFFF	614	ori r3,r3, 0xFFFF
615	mtdcr dmasr, r3	615	mtdcr dmasr, r3
616		616
617	bl ppc405ep_init /* do ppc405ep specific init */	617	bl ppc405ep_init /* do ppc405ep specific init */
618	#endif /* CONFIG_405EP */	618	#endif /* CONFIG_405EP */
619		619
620	#if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)	620	#if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
621	/********************************************************************	621	/********************************************************************
622	* Setup OCM - On Chip Memory	622	* Setup OCM - On Chip Memory
623	*******************************************************************/	623	*******************************************************************/
624	/* Setup OCM */	624	/* Setup OCM */
625	lis r0, 0x7FFF	625	lis r0, 0x7FFF
626	ori r0, r0, 0xFFFF	626	ori r0, r0, 0xFFFF
627	mfdcr r3, ocmiscntl /* get instr-side IRAM config */	627	mfdcr r3, ocmiscntl /* get instr-side IRAM config */
628	mfdcr r4, ocmdscntl /* get data-side IRAM config */	628	mfdcr r4, ocmdscntl /* get data-side IRAM config */
629	and r3, r3, r0 /* disable data-side IRAM */	629	and r3, r3, r0 /* disable data-side IRAM */
630	and r4, r4, r0 /* disable data-side IRAM */	630	and r4, r4, r0 /* disable data-side IRAM */
631	mtdcr ocmiscntl, r3 /* set instr-side IRAM config */	631	mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
632	mtdcr ocmdscntl, r4 /* set data-side IRAM config */	632	mtdcr ocmdscntl, r4 /* set data-side IRAM config */
633	isync	633	isync
634		634
635	addis r3, 0, CFG_OCM_DATA_ADDR@h /* OCM location */	635	addis r3, 0, CFG_OCM_DATA_ADDR@h /* OCM location */
636	mtdcr ocmdsarc, r3	636	mtdcr ocmdsarc, r3
637	addis r4, 0, 0xC000 /* OCM data area enabled */	637	addis r4, 0, 0xC000 /* OCM data area enabled */
638	mtdcr ocmdscntl, r4	638	mtdcr ocmdscntl, r4
639	isync	639	isync
640	#endif	640	#endif
641		641
642	/----------------------------------------------------------------------- /	642	/----------------------------------------------------------------------- /
643	/* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */	643	/* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
644	/----------------------------------------------------------------------- /	644	/----------------------------------------------------------------------- /
645	#ifdef CFG_INIT_DCACHE_CS	645	#ifdef CFG_INIT_DCACHE_CS
646	/----------------------------------------------------------------------- /	646	/----------------------------------------------------------------------- /
647	/* Memory Bank x (nothingness) initialization 1GB+64MEG */	647	/* Memory Bank x (nothingness) initialization 1GB+64MEG */
648	/* used as temporary stack pointer for stage0 */	648	/* used as temporary stack pointer for stage0 */
649	/----------------------------------------------------------------------- /	649	/----------------------------------------------------------------------- /
650	li r4,PBxAP	650	li r4,PBxAP
651	mtdcr ebccfga,r4	651	mtdcr ebccfga,r4
652	lis r4,0x0380	652	lis r4,0x0380
653	ori r4,r4,0x0480	653	ori r4,r4,0x0480
654	mtdcr ebccfgd,r4	654	mtdcr ebccfgd,r4
655		655
656	addi r4,0,PBxCR	656	addi r4,0,PBxCR
657	mtdcr ebccfga,r4	657	mtdcr ebccfga,r4
658	lis r4,0x400D	658	lis r4,0x400D
659	ori r4,r4,0xa000	659	ori r4,r4,0xa000
660	mtdcr ebccfgd,r4	660	mtdcr ebccfgd,r4
661		661
662	/* turn on data chache for this region */	662	/* turn on data chache for this region */
663	lis r4,0x0080	663	lis r4,0x0080
664	mtdccr r4	664	mtdccr r4
665		665
666	/* set stack pointer and clear stack to known value */	666	/* set stack pointer and clear stack to known value */
667		667
668	lis r1,CFG_INIT_RAM_ADDR@h	668	lis r1,CFG_INIT_RAM_ADDR@h
669	ori r1,r1,CFG_INIT_SP_OFFSET@l	669	ori r1,r1,CFG_INIT_SP_OFFSET@l
670		670
671	li r4,2048 /* we store 2048 words to stack */	671	li r4,2048 /* we store 2048 words to stack */
672	mtctr r4	672	mtctr r4
673		673
674	lis r2,CFG_INIT_RAM_ADDR@h /* we also clear data area */	674	lis r2,CFG_INIT_RAM_ADDR@h /* we also clear data area */
675	ori r2,r2,CFG_INIT_RAM_END@l /* so cant copy value from r1 */	675	ori r2,r2,CFG_INIT_RAM_END@l /* so cant copy value from r1 */
676		676
677	lis r4,0xdead /* we store 0xdeaddead in the stack */	677	lis r4,0xdead /* we store 0xdeaddead in the stack */
678	ori r4,r4,0xdead	678	ori r4,r4,0xdead
679		679
680	..stackloop:	680	..stackloop:
681	stwu r4,-4(r2)	681	stwu r4,-4(r2)
682	bdnz ..stackloop	682	bdnz ..stackloop
683		683
684	li r0, 0 /* Make room for stack frame header and */	684	li r0, 0 /* Make room for stack frame header and */
685	stwu r0, -4(r1) /* clear final stack frame so that */	685	stwu r0, -4(r1) /* clear final stack frame so that */
686	stwu r0, -4(r1) /* stack backtraces terminate cleanly */	686	stwu r0, -4(r1) /* stack backtraces terminate cleanly */
687	/*	687	/*
688	* Set up a dummy frame to store reset vector as return address.	688	* Set up a dummy frame to store reset vector as return address.
689	* this causes stack underflow to reset board.	689	* this causes stack underflow to reset board.
690	*/	690	*/
691	stwu r1, -8(r1) /* Save back chain and move SP */	691	stwu r1, -8(r1) /* Save back chain and move SP */
692	addis r0, 0, RESET_VECTOR@h /* Address of reset vector */	692	addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
693	ori r0, r0, RESET_VECTOR@l	693	ori r0, r0, RESET_VECTOR@l
694	stwu r1, -8(r1) /* Save back chain and move SP */	694	stwu r1, -8(r1) /* Save back chain and move SP */
695	stw r0, +12(r1) /* Save return addr (underflow vect) */	695	stw r0, +12(r1) /* Save return addr (underflow vect) */
696		696
697	#elif defined(CFG_TEMP_STACK_OCM) && \	697	#elif defined(CFG_TEMP_STACK_OCM) && \
698	(defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE))	698	(defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE))
699	/*	699	/*
700	* Stack in OCM.	700	* Stack in OCM.
701	*/	701	*/
702		702
703	/* Set up Stack at top of OCM */	703	/* Set up Stack at top of OCM */
704	lis r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@h	704	lis r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@h
705	ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@l	705	ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@l
706		706
707	/* Set up a zeroized stack frame so that backtrace works right */	707	/* Set up a zeroized stack frame so that backtrace works right */
708	li r0, 0	708	li r0, 0
709	stwu r0, -4(r1)	709	stwu r0, -4(r1)
710	stwu r0, -4(r1)	710	stwu r0, -4(r1)
711		711
712	/*	712	/*
713	* Set up a dummy frame to store reset vector as return address.	713	* Set up a dummy frame to store reset vector as return address.
714	* this causes stack underflow to reset board.	714	* this causes stack underflow to reset board.
715	*/	715	*/
716	stwu r1, -8(r1) /* Save back chain and move SP */	716	stwu r1, -8(r1) /* Save back chain and move SP */
717	lis r0, RESET_VECTOR@h /* Address of reset vector */	717	lis r0, RESET_VECTOR@h /* Address of reset vector */
718	ori r0, r0, RESET_VECTOR@l	718	ori r0, r0, RESET_VECTOR@l
719	stwu r1, -8(r1) /* Save back chain and move SP */	719	stwu r1, -8(r1) /* Save back chain and move SP */
720	stw r0, +12(r1) /* Save return addr (underflow vect) */	720	stw r0, +12(r1) /* Save return addr (underflow vect) */
721	#endif /* CFG_INIT_DCACHE_CS */	721	#endif /* CFG_INIT_DCACHE_CS */
722		722
723	/----------------------------------------------------------------------- /	723	/----------------------------------------------------------------------- /
724	/* Initialize SDRAM Controller */	724	/* Initialize SDRAM Controller */
725	/----------------------------------------------------------------------- /	725	/----------------------------------------------------------------------- /
726	bl sdram_init	726	bl sdram_init
727		727
728	/*	728	/*
729	* Setup temporary stack pointer only for boards	729	* Setup temporary stack pointer only for boards
730	* that do not use SDRAM SPD I2C stuff since it	730	* that do not use SDRAM SPD I2C stuff since it
731	* is already initialized to use DCACHE or OCM	731	* is already initialized to use DCACHE or OCM
732	* stacks.	732	* stacks.
733	*/	733	*/
734	#if !(defined(CFG_INIT_DCACHE_CS) \|\| defined(CFG_TEMP_STACK_OCM))	734	#if !(defined(CFG_INIT_DCACHE_CS) \|\| defined(CFG_TEMP_STACK_OCM))
735	lis r1, CFG_INIT_RAM_ADDR@h	735	lis r1, CFG_INIT_RAM_ADDR@h
736	ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */	736	ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
737		737
738	li r0, 0 /* Make room for stack frame header and */	738	li r0, 0 /* Make room for stack frame header and */
739	stwu r0, -4(r1) /* clear final stack frame so that */	739	stwu r0, -4(r1) /* clear final stack frame so that */
740	stwu r0, -4(r1) /* stack backtraces terminate cleanly */	740	stwu r0, -4(r1) /* stack backtraces terminate cleanly */
741	/*	741	/*
742	* Set up a dummy frame to store reset vector as return address.	742	* Set up a dummy frame to store reset vector as return address.
743	* this causes stack underflow to reset board.	743	* this causes stack underflow to reset board.
744	*/	744	*/
745	stwu r1, -8(r1) /* Save back chain and move SP */	745	stwu r1, -8(r1) /* Save back chain and move SP */
746	lis r0, RESET_VECTOR@h /* Address of reset vector */	746	lis r0, RESET_VECTOR@h /* Address of reset vector */
747	ori r0, r0, RESET_VECTOR@l	747	ori r0, r0, RESET_VECTOR@l
748	stwu r1, -8(r1) /* Save back chain and move SP */	748	stwu r1, -8(r1) /* Save back chain and move SP */
749	stw r0, +12(r1) /* Save return addr (underflow vect) */	749	stw r0, +12(r1) /* Save return addr (underflow vect) */
750	#endif /* !(CFG_INIT_DCACHE_CS \|\| !CFG_TEM_STACK_OCM) */	750	#endif /* !(CFG_INIT_DCACHE_CS \|\| !CFG_TEM_STACK_OCM) */
751		751
752	GET_GOT /* initialize GOT access */	752	GET_GOT /* initialize GOT access */
753		753
754	bl cpu_init_f /* run low-level CPU init code (from Flash) */	754	bl cpu_init_f /* run low-level CPU init code (from Flash) */
755		755
756	/* NEVER RETURNS! */	756	/* NEVER RETURNS! */
757	bl board_init_f /* run first part of init code (from Flash) */	757	bl board_init_f /* run first part of init code (from Flash) */
758		758
759	#endif /* CONFIG_405GP \|\| CONFIG_405CR \|\| CONFIG_405 \|\| CONFIG_405EP */	759	#endif /* CONFIG_405GP \|\| CONFIG_405CR \|\| CONFIG_405 \|\| CONFIG_405EP */
760	/----------------------------------------------------------------------- /	760	/----------------------------------------------------------------------- /
761		761
762		762
763	/*****************************************************************************/	763	/*****************************************************************************/
764	.globl _start_of_vectors	764	.globl _start_of_vectors
765	_start_of_vectors:	765	_start_of_vectors:
766		766
767	#if 0	767	#if 0
768	/TODO Fixup _start above so we can do this/	768	/TODO Fixup _start above so we can do this/
769	/* Critical input. */	769	/* Critical input. */
770	CRIT_EXCEPTION(0x100, CritcalInput, CritcalInputException)	770	CRIT_EXCEPTION(0x100, CritcalInput, CritcalInputException)
771	#endif	771	#endif
772		772
773	/* Machine check */	773	/* Machine check */
774	CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)	774	CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
775		775
776	/* Data Storage exception. */	776	/* Data Storage exception. */
777	STD_EXCEPTION(0x300, DataStorage, UnknownException)	777	STD_EXCEPTION(0x300, DataStorage, UnknownException)
778		778
779	/* Instruction Storage exception. */	779	/* Instruction Storage exception. */
780	STD_EXCEPTION(0x400, InstStorage, UnknownException)	780	STD_EXCEPTION(0x400, InstStorage, UnknownException)
781		781
782	/* External Interrupt exception. */	782	/* External Interrupt exception. */
783	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)	783	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
784		784
785	/* Alignment exception. */	785	/* Alignment exception. */
786	. = 0x600	786	. = 0x600
787	Alignment:	787	Alignment:
788	EXCEPTION_PROLOG	788	EXCEPTION_PROLOG
789	mfspr r4,DAR	789	mfspr r4,DAR
790	stw r4,_DAR(r21)	790	stw r4,_DAR(r21)
791	mfspr r5,DSISR	791	mfspr r5,DSISR
792	stw r5,_DSISR(r21)	792	stw r5,_DSISR(r21)
793	addi r3,r1,STACK_FRAME_OVERHEAD	793	addi r3,r1,STACK_FRAME_OVERHEAD
794	li r20,MSR_KERNEL	794	li r20,MSR_KERNEL
795	rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */	795	rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
796	lwz r6,GOT(transfer_to_handler)	796	lwz r6,GOT(transfer_to_handler)
797	mtlr r6	797	mtlr r6
798	blrl	798	blrl
799	.L_Alignment:	799	.L_Alignment:
800	.long AlignmentException - _start + EXC_OFF_SYS_RESET	800	.long AlignmentException - _start + EXC_OFF_SYS_RESET
801	.long int_return - _start + EXC_OFF_SYS_RESET	801	.long int_return - _start + EXC_OFF_SYS_RESET
802		802
803	/* Program check exception */	803	/* Program check exception */
804	. = 0x700	804	. = 0x700
805	ProgramCheck:	805	ProgramCheck:
806	EXCEPTION_PROLOG	806	EXCEPTION_PROLOG
807	addi r3,r1,STACK_FRAME_OVERHEAD	807	addi r3,r1,STACK_FRAME_OVERHEAD
808	li r20,MSR_KERNEL	808	li r20,MSR_KERNEL
809	rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */	809	rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
810	lwz r6,GOT(transfer_to_handler)	810	lwz r6,GOT(transfer_to_handler)
811	mtlr r6	811	mtlr r6
812	blrl	812	blrl
813	.L_ProgramCheck:	813	.L_ProgramCheck:
814	.long ProgramCheckException - _start + EXC_OFF_SYS_RESET	814	.long ProgramCheckException - _start + EXC_OFF_SYS_RESET
815	.long int_return - _start + EXC_OFF_SYS_RESET	815	.long int_return - _start + EXC_OFF_SYS_RESET
816		816
817	/* No FPU on MPC8xx. This exception is not supposed to happen.	817	/* No FPU on MPC8xx. This exception is not supposed to happen.
818	*/	818	*/
819	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)	819	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
820		820
821	/* I guess we could implement decrementer, and may have	821	/* I guess we could implement decrementer, and may have
822	* to someday for timekeeping.	822	* to someday for timekeeping.
823	*/	823	*/
824	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)	824	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
825	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)	825	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
826	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)	826	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
827	STD_EXCEPTION(0xc00, SystemCall, UnknownException)	827	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
828	STD_EXCEPTION(0xd00, SingleStep, UnknownException)	828	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
829		829
830	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)	830	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
831	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)	831	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
832		832
833	/* On the MPC8xx, this is a software emulation interrupt. It occurs	833	/* On the MPC8xx, this is a software emulation interrupt. It occurs
834	* for all unimplemented and illegal instructions.	834	* for all unimplemented and illegal instructions.
835	*/	835	*/
836	STD_EXCEPTION(0x1000, PIT, PITException)	836	STD_EXCEPTION(0x1000, PIT, PITException)
837		837
838	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)	838	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
839	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)	839	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
840	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)	840	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
841	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)	841	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
842		842
843	STD_EXCEPTION(0x1500, Reserved5, UnknownException)	843	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
844	STD_EXCEPTION(0x1600, Reserved6, UnknownException)	844	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
845	STD_EXCEPTION(0x1700, Reserved7, UnknownException)	845	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
846	STD_EXCEPTION(0x1800, Reserved8, UnknownException)	846	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
847	STD_EXCEPTION(0x1900, Reserved9, UnknownException)	847	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
848	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)	848	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
849	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)	849	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
850		850
851	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)	851	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
852	STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)	852	STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
853	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)	853	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
854	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)	854	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
855		855
856	CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )	856	CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
857		857
858	.globl _end_of_vectors	858	.globl _end_of_vectors
859	_end_of_vectors:	859	_end_of_vectors:
860		860
861		861
862	. = 0x2100	862	. = 0x2100
863		863
864	/*	864	/*
865	* This code finishes saving the registers to the exception frame	865	* This code finishes saving the registers to the exception frame
866	* and jumps to the appropriate handler for the exception.	866	* and jumps to the appropriate handler for the exception.
867	* Register r21 is pointer into trap frame, r1 has new stack pointer.	867	* Register r21 is pointer into trap frame, r1 has new stack pointer.
868	*/	868	*/
869	.globl transfer_to_handler	869	.globl transfer_to_handler
870	transfer_to_handler:	870	transfer_to_handler:
871	stw r22,_NIP(r21)	871	stw r22,_NIP(r21)
872	lis r22,MSR_POW@h	872	lis r22,MSR_POW@h
873	andc r23,r23,r22	873	andc r23,r23,r22
874	stw r23,_MSR(r21)	874	stw r23,_MSR(r21)
875	SAVE_GPR(7, r21)	875	SAVE_GPR(7, r21)
876	SAVE_4GPRS(8, r21)	876	SAVE_4GPRS(8, r21)
877	SAVE_8GPRS(12, r21)	877	SAVE_8GPRS(12, r21)
878	SAVE_8GPRS(24, r21)	878	SAVE_8GPRS(24, r21)
879	#if 0	879	#if 0
880	andi. r23,r23,MSR_PR	880	andi. r23,r23,MSR_PR
881	mfspr r23,SPRG3 /* if from user, fix up tss.regs */	881	mfspr r23,SPRG3 /* if from user, fix up tss.regs */
882	beq 2f	882	beq 2f
883	addi r24,r1,STACK_FRAME_OVERHEAD	883	addi r24,r1,STACK_FRAME_OVERHEAD
884	stw r24,PT_REGS(r23)	884	stw r24,PT_REGS(r23)
885	2: addi r2,r23,-TSS /* set r2 to current */	885	2: addi r2,r23,-TSS /* set r2 to current */
886	tovirt(r2,r2,r23)	886	tovirt(r2,r2,r23)
887	#endif	887	#endif
888	mflr r23	888	mflr r23
889	andi. r24,r23,0x3f00 /* get vector offset */	889	andi. r24,r23,0x3f00 /* get vector offset */
890	stw r24,TRAP(r21)	890	stw r24,TRAP(r21)
891	li r22,0	891	li r22,0
892	stw r22,RESULT(r21)	892	stw r22,RESULT(r21)
893	mtspr SPRG2,r22 /* r1 is now kernel sp */	893	mtspr SPRG2,r22 /* r1 is now kernel sp */
894	#if 0	894	#if 0
895	addi r24,r2,TASK_STRUCT_SIZE /* check for kernel stack overflow */	895	addi r24,r2,TASK_STRUCT_SIZE /* check for kernel stack overflow */
896	cmplw 0,r1,r2	896	cmplw 0,r1,r2
897	cmplw 1,r1,r24	897	cmplw 1,r1,r24
898	crand 1,1,4	898	crand 1,1,4
899	bgt stack_ovf /* if r2 < r1 < r2+TASK_STRUCT_SIZE */	899	bgt stack_ovf /* if r2 < r1 < r2+TASK_STRUCT_SIZE */
900	#endif	900	#endif
901	lwz r24,0(r23) /* virtual address of handler */	901	lwz r24,0(r23) /* virtual address of handler */
902	lwz r23,4(r23) /* where to go when done */	902	lwz r23,4(r23) /* where to go when done */
903	mtspr SRR0,r24	903	mtspr SRR0,r24
904	mtspr SRR1,r20	904	mtspr SRR1,r20
905	mtlr r23	905	mtlr r23
906	SYNC	906	SYNC
907	rfi /* jump to handler, enable MMU */	907	rfi /* jump to handler, enable MMU */
908		908
909	int_return:	909	int_return:
910	mfmsr r28 /* Disable interrupts */	910	mfmsr r28 /* Disable interrupts */
911	li r4,0	911	li r4,0
912	ori r4,r4,MSR_EE	912	ori r4,r4,MSR_EE
913	andc r28,r28,r4	913	andc r28,r28,r4
914	SYNC /* Some chip revs need this... */	914	SYNC /* Some chip revs need this... */
915	mtmsr r28	915	mtmsr r28
916	SYNC	916	SYNC
917	lwz r2,_CTR(r1)	917	lwz r2,_CTR(r1)
918	lwz r0,_LINK(r1)	918	lwz r0,_LINK(r1)
919	mtctr r2	919	mtctr r2
920	mtlr r0	920	mtlr r0
921	lwz r2,_XER(r1)	921	lwz r2,_XER(r1)
922	lwz r0,_CCR(r1)	922	lwz r0,_CCR(r1)
923	mtspr XER,r2	923	mtspr XER,r2
924	mtcrf 0xFF,r0	924	mtcrf 0xFF,r0
925	REST_10GPRS(3, r1)	925	REST_10GPRS(3, r1)
926	REST_10GPRS(13, r1)	926	REST_10GPRS(13, r1)
927	REST_8GPRS(23, r1)	927	REST_8GPRS(23, r1)
928	REST_GPR(31, r1)	928	REST_GPR(31, r1)
929	lwz r2,_NIP(r1) /* Restore environment */	929	lwz r2,_NIP(r1) /* Restore environment */
930	lwz r0,_MSR(r1)	930	lwz r0,_MSR(r1)
931	mtspr SRR0,r2	931	mtspr SRR0,r2
932	mtspr SRR1,r0	932	mtspr SRR1,r0
933	lwz r0,GPR0(r1)	933	lwz r0,GPR0(r1)
934	lwz r2,GPR2(r1)	934	lwz r2,GPR2(r1)
935	lwz r1,GPR1(r1)	935	lwz r1,GPR1(r1)
936	SYNC	936	SYNC
937	rfi	937	rfi
938		938
939	crit_return:	939	crit_return:
940	mfmsr r28 /* Disable interrupts */	940	mfmsr r28 /* Disable interrupts */
941	li r4,0	941	li r4,0
942	ori r4,r4,MSR_EE	942	ori r4,r4,MSR_EE
943	andc r28,r28,r4	943	andc r28,r28,r4
944	SYNC /* Some chip revs need this... */	944	SYNC /* Some chip revs need this... */
945	mtmsr r28	945	mtmsr r28
946	SYNC	946	SYNC
947	lwz r2,_CTR(r1)	947	lwz r2,_CTR(r1)
948	lwz r0,_LINK(r1)	948	lwz r0,_LINK(r1)
949	mtctr r2	949	mtctr r2
950	mtlr r0	950	mtlr r0
951	lwz r2,_XER(r1)	951	lwz r2,_XER(r1)
952	lwz r0,_CCR(r1)	952	lwz r0,_CCR(r1)
953	mtspr XER,r2	953	mtspr XER,r2
954	mtcrf 0xFF,r0	954	mtcrf 0xFF,r0
955	REST_10GPRS(3, r1)	955	REST_10GPRS(3, r1)
956	REST_10GPRS(13, r1)	956	REST_10GPRS(13, r1)
957	REST_8GPRS(23, r1)	957	REST_8GPRS(23, r1)
958	REST_GPR(31, r1)	958	REST_GPR(31, r1)
959	lwz r2,_NIP(r1) /* Restore environment */	959	lwz r2,_NIP(r1) /* Restore environment */
960	lwz r0,_MSR(r1)	960	lwz r0,_MSR(r1)
961	mtspr 990,r2 /* SRR2 */	961	mtspr 990,r2 /* SRR2 */
962	mtspr 991,r0 /* SRR3 */	962	mtspr 991,r0 /* SRR3 */
963	lwz r0,GPR0(r1)	963	lwz r0,GPR0(r1)
964	lwz r2,GPR2(r1)	964	lwz r2,GPR2(r1)
965	lwz r1,GPR1(r1)	965	lwz r1,GPR1(r1)
966	SYNC	966	SYNC
967	rfci	967	rfci
968		968
969	/* Cache functions.	969	/* Cache functions.
970	*/	970	*/
971	invalidate_icache:	971	invalidate_icache:
972	iccci r0,r0 /* for 405, iccci invalidates the */	972	iccci r0,r0 /* for 405, iccci invalidates the */
973	blr /* entire I cache */	973	blr /* entire I cache */
974		974
975	invalidate_dcache:	975	invalidate_dcache:
976	addi r6,0,0x0000 /* clear GPR 6 */	976	addi r6,0,0x0000 /* clear GPR 6 */
977	/* Do loop for # of dcache congruence classes. */	977	/* Do loop for # of dcache congruence classes. */
978	#if defined(CONFIG_440_GX) \|\| defined(CONFIG_440_EP) \|\| defined(CONFIG_440_GR)	978	#if defined(CONFIG_440_GX) \|\| defined(CONFIG_440_EP) \|\| defined(CONFIG_440_GR)
979	lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */	979	lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */
980	ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l	980	ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
981	#else	981	#else
982	addi r7,r0, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)	982	addi r7,r0, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
983	#endif	983	#endif
984	/* NOTE: dccci invalidates both */	984	/* NOTE: dccci invalidates both */
985	mtctr r7 /* ways in the D cache */	985	mtctr r7 /* ways in the D cache */
986	..dcloop:	986	..dcloop:
987	dccci 0,r6 /* invalidate line */	987	dccci 0,r6 /* invalidate line */
988	addi r6,r6, CFG_CACHELINE_SIZE /* bump to next line */	988	addi r6,r6, CFG_CACHELINE_SIZE /* bump to next line */
989	bdnz ..dcloop	989	bdnz ..dcloop
990	blr	990	blr
991		991
992	flush_dcache:	992	flush_dcache:
993	addis r9,r0,0x0002 /* set mask for EE and CE msr bits */	993	addis r9,r0,0x0002 /* set mask for EE and CE msr bits */
994	ori r9,r9,0x8000	994	ori r9,r9,0x8000
995	mfmsr r12 /* save msr */	995	mfmsr r12 /* save msr */
996	andc r9,r12,r9	996	andc r9,r12,r9
997	mtmsr r9 /* disable EE and CE */	997	mtmsr r9 /* disable EE and CE */
998	addi r10,r0,0x0001 /* enable data cache for unused memory */	998	addi r10,r0,0x0001 /* enable data cache for unused memory */
999	mfdccr r9 /* region 0xF8000000-0xFFFFFFFF via */	999	mfdccr r9 /* region 0xF8000000-0xFFFFFFFF via */
1000	or r10,r10,r9 /* bit 31 in dccr */	1000	or r10,r10,r9 /* bit 31 in dccr */
1001	mtdccr r10	1001	mtdccr r10
1002		1002
1003	/* do loop for # of congruence classes. */	1003	/* do loop for # of congruence classes. */
1004	#if defined(CONFIG_440_GX) \|\| defined(CONFIG_440_EP) \|\| defined(CONFIG_440_GR)	1004	#if defined(CONFIG_440_GX) \|\| defined(CONFIG_440_EP) \|\| defined(CONFIG_440_GR)
1005	lis r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS: for large cache sizes */	1005	lis r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS: for large cache sizes */
1006	ori r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l	1006	ori r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
1007	lis r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */	1007	lis r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */
1008	ori r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */	1008	ori r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */
1009	#else	1009	#else
1010	addi r10,r0,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)	1010	addi r10,r0,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
1011	addi r11,r0,(CFG_DCACHE_SIZE / 2) /* D cache set size - 2 way sets */	1011	addi r11,r0,(CFG_DCACHE_SIZE / 2) /* D cache set size - 2 way sets */
1012	#endif	1012	#endif
1013	mtctr r10	1013	mtctr r10
1014	addi r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */	1014	addi r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */
1015	add r11,r10,r11 /* add to get to other side of cache line */	1015	add r11,r10,r11 /* add to get to other side of cache line */
1016	..flush_dcache_loop:	1016	..flush_dcache_loop:
1017	lwz r3,0(r10) /* least recently used side */	1017	lwz r3,0(r10) /* least recently used side */
1018	lwz r3,0(r11) /* the other side */	1018	lwz r3,0(r11) /* the other side */
1019	dccci r0,r11 /* invalidate both sides */	1019	dccci r0,r11 /* invalidate both sides */
1020	addi r10,r10,CFG_CACHELINE_SIZE /* bump to next line */	1020	addi r10,r10,CFG_CACHELINE_SIZE /* bump to next line */
1021	addi r11,r11,CFG_CACHELINE_SIZE /* bump to next line */	1021	addi r11,r11,CFG_CACHELINE_SIZE /* bump to next line */
1022	bdnz ..flush_dcache_loop	1022	bdnz ..flush_dcache_loop
1023	sync /* allow memory access to complete */	1023	sync /* allow memory access to complete */
1024	mtdccr r9 /* restore dccr */	1024	mtdccr r9 /* restore dccr */
1025	mtmsr r12 /* restore msr */	1025	mtmsr r12 /* restore msr */
1026	blr	1026	blr
1027		1027
1028	.globl icache_enable	1028	.globl icache_enable
1029	icache_enable:	1029	icache_enable:
1030	mflr r8	1030	mflr r8
1031	bl invalidate_icache	1031	bl invalidate_icache
1032	mtlr r8	1032	mtlr r8
1033	isync	1033	isync
1034	addis r3,r0, 0x8000 /* set bit 0 */	1034	addis r3,r0, 0x8000 /* set bit 0 */
1035	mticcr r3	1035	mticcr r3
1036	blr	1036	blr
1037		1037
1038	.globl icache_disable	1038	.globl icache_disable
1039	icache_disable:	1039	icache_disable:
1040	addis r3,r0, 0x0000 /* clear bit 0 */	1040	addis r3,r0, 0x0000 /* clear bit 0 */
1041	mticcr r3	1041	mticcr r3
1042	isync	1042	isync
1043	blr	1043	blr
1044		1044
1045	.globl icache_status	1045	.globl icache_status
1046	icache_status:	1046	icache_status:
1047	mficcr r3	1047	mficcr r3
1048	srwi r3, r3, 31 /* >>31 => select bit 0 */	1048	srwi r3, r3, 31 /* >>31 => select bit 0 */
1049	blr	1049	blr
1050		1050
1051	.globl dcache_enable	1051	.globl dcache_enable
1052	dcache_enable:	1052	dcache_enable:
1053	mflr r8	1053	mflr r8
1054	bl invalidate_dcache	1054	bl invalidate_dcache
1055	mtlr r8	1055	mtlr r8
1056	isync	1056	isync
1057	addis r3,r0, 0x8000 /* set bit 0 */	1057	addis r3,r0, 0x8000 /* set bit 0 */
1058	mtdccr r3	1058	mtdccr r3
1059	blr	1059	blr
1060		1060
1061	.globl dcache_disable	1061	.globl dcache_disable
1062	dcache_disable:	1062	dcache_disable:
1063	mflr r8	1063	mflr r8
1064	bl flush_dcache	1064	bl flush_dcache
1065	mtlr r8	1065	mtlr r8
1066	addis r3,r0, 0x0000 /* clear bit 0 */	1066	addis r3,r0, 0x0000 /* clear bit 0 */
1067	mtdccr r3	1067	mtdccr r3
1068	blr	1068	blr
1069		1069
1070	.globl dcache_status	1070	.globl dcache_status
1071	dcache_status:	1071	dcache_status:
1072	mfdccr r3	1072	mfdccr r3
1073	srwi r3, r3, 31 /* >>31 => select bit 0 */	1073	srwi r3, r3, 31 /* >>31 => select bit 0 */
1074	blr	1074	blr
1075		1075
1076	.globl get_pvr	1076	.globl get_pvr
1077	get_pvr:	1077	get_pvr:
1078	mfspr r3, PVR	1078	mfspr r3, PVR
1079	blr	1079	blr
1080		1080
1081	#if !defined(CONFIG_440)	1081	#if !defined(CONFIG_440)
1082	.globl wr_pit	1082	.globl wr_pit
1083	wr_pit:	1083	wr_pit:
1084	mtspr pit, r3	1084	mtspr pit, r3
1085	blr	1085	blr
1086	#endif	1086	#endif
1087		1087
1088	.globl wr_tcr	1088	.globl wr_tcr
1089	wr_tcr:	1089	wr_tcr:
1090	mtspr tcr, r3	1090	mtspr tcr, r3
1091	blr	1091	blr
1092		1092
1093	/------------------------------------------------------------------------------- /	1093	/------------------------------------------------------------------------------- /
1094	/* Function: in8 */	1094	/* Function: in8 */
1095	/* Description: Input 8 bits */	1095	/* Description: Input 8 bits */
1096	/------------------------------------------------------------------------------- /	1096	/------------------------------------------------------------------------------- /
1097	.globl in8	1097	.globl in8
1098	in8:	1098	in8:
1099	lbz r3,0x0000(r3)	1099	lbz r3,0x0000(r3)
1100	blr	1100	blr
1101		1101
1102	/------------------------------------------------------------------------------- /	1102	/------------------------------------------------------------------------------- /
1103	/* Function: out8 */	1103	/* Function: out8 */
1104	/* Description: Output 8 bits */	1104	/* Description: Output 8 bits */
1105	/------------------------------------------------------------------------------- /	1105	/------------------------------------------------------------------------------- /
1106	.globl out8	1106	.globl out8
1107	out8:	1107	out8:
1108	stb r4,0x0000(r3)	1108	stb r4,0x0000(r3)
1109	blr	1109	blr
1110		1110
1111	/------------------------------------------------------------------------------- /	1111	/------------------------------------------------------------------------------- /
1112	/* Function: out16 */	1112	/* Function: out16 */
1113	/* Description: Output 16 bits */	1113	/* Description: Output 16 bits */
1114	/------------------------------------------------------------------------------- /	1114	/------------------------------------------------------------------------------- /
1115	.globl out16	1115	.globl out16
1116	out16:	1116	out16:
1117	sth r4,0x0000(r3)	1117	sth r4,0x0000(r3)
1118	blr	1118	blr
1119		1119
1120	/------------------------------------------------------------------------------- /	1120	/------------------------------------------------------------------------------- /
1121	/* Function: out16r */	1121	/* Function: out16r */
1122	/* Description: Byte reverse and output 16 bits */	1122	/* Description: Byte reverse and output 16 bits */
1123	/------------------------------------------------------------------------------- /	1123	/------------------------------------------------------------------------------- /
1124	.globl out16r	1124	.globl out16r
1125	out16r:	1125	out16r:
1126	sthbrx r4,r0,r3	1126	sthbrx r4,r0,r3
1127	blr	1127	blr
1128		1128
1129	/------------------------------------------------------------------------------- /	1129	/------------------------------------------------------------------------------- /
1130	/* Function: out32 */	1130	/* Function: out32 */
1131	/* Description: Output 32 bits */	1131	/* Description: Output 32 bits */
1132	/------------------------------------------------------------------------------- /	1132	/------------------------------------------------------------------------------- /
1133	.globl out32	1133	.globl out32
1134	out32:	1134	out32:
1135	stw r4,0x0000(r3)	1135	stw r4,0x0000(r3)
1136	blr	1136	blr
1137		1137
1138	/------------------------------------------------------------------------------- /	1138	/------------------------------------------------------------------------------- /
1139	/* Function: out32r */	1139	/* Function: out32r */
1140	/* Description: Byte reverse and output 32 bits */	1140	/* Description: Byte reverse and output 32 bits */
1141	/------------------------------------------------------------------------------- /	1141	/------------------------------------------------------------------------------- /
1142	.globl out32r	1142	.globl out32r
1143	out32r:	1143	out32r:
1144	stwbrx r4,r0,r3	1144	stwbrx r4,r0,r3
1145	blr	1145	blr
1146		1146
1147	/------------------------------------------------------------------------------- /	1147	/------------------------------------------------------------------------------- /
1148	/* Function: in16 */	1148	/* Function: in16 */
1149	/* Description: Input 16 bits */	1149	/* Description: Input 16 bits */
1150	/------------------------------------------------------------------------------- /	1150	/------------------------------------------------------------------------------- /
1151	.globl in16	1151	.globl in16
1152	in16:	1152	in16:
1153	lhz r3,0x0000(r3)	1153	lhz r3,0x0000(r3)
1154	blr	1154	blr
1155		1155
1156	/------------------------------------------------------------------------------- /	1156	/------------------------------------------------------------------------------- /
1157	/* Function: in16r */	1157	/* Function: in16r */
1158	/* Description: Input 16 bits and byte reverse */	1158	/* Description: Input 16 bits and byte reverse */
1159	/------------------------------------------------------------------------------- /	1159	/------------------------------------------------------------------------------- /
1160	.globl in16r	1160	.globl in16r
1161	in16r:	1161	in16r:
1162	lhbrx r3,r0,r3	1162	lhbrx r3,r0,r3
1163	blr	1163	blr
1164		1164
1165	/------------------------------------------------------------------------------- /	1165	/------------------------------------------------------------------------------- /
1166	/* Function: in32 */	1166	/* Function: in32 */
1167	/* Description: Input 32 bits */	1167	/* Description: Input 32 bits */
1168	/------------------------------------------------------------------------------- /	1168	/------------------------------------------------------------------------------- /
1169	.globl in32	1169	.globl in32
1170	in32:	1170	in32:
1171	lwz 3,0x0000(3)	1171	lwz 3,0x0000(3)
1172	blr	1172	blr
1173		1173
1174	/------------------------------------------------------------------------------- /	1174	/------------------------------------------------------------------------------- /
1175	/* Function: in32r */	1175	/* Function: in32r */
1176	/* Description: Input 32 bits and byte reverse */	1176	/* Description: Input 32 bits and byte reverse */
1177	/------------------------------------------------------------------------------- /	1177	/------------------------------------------------------------------------------- /
1178	.globl in32r	1178	.globl in32r
1179	in32r:	1179	in32r:
1180	lwbrx r3,r0,r3	1180	lwbrx r3,r0,r3
1181	blr	1181	blr
1182		1182
1183	/------------------------------------------------------------------------------- /	1183	/------------------------------------------------------------------------------- /
1184	/* Function: ppcDcbf */	1184	/* Function: ppcDcbf */
1185	/* Description: Data Cache block flush */	1185	/* Description: Data Cache block flush */
1186	/* Input: r3 = effective address */	1186	/* Input: r3 = effective address */
1187	/* Output: none. */	1187	/* Output: none. */
1188	/------------------------------------------------------------------------------- /	1188	/------------------------------------------------------------------------------- /
1189	.globl ppcDcbf	1189	.globl ppcDcbf
1190	ppcDcbf:	1190	ppcDcbf:
1191	dcbf r0,r3	1191	dcbf r0,r3
1192	blr	1192	blr
1193		1193
1194	/------------------------------------------------------------------------------- /	1194	/------------------------------------------------------------------------------- /
1195	/* Function: ppcDcbi */	1195	/* Function: ppcDcbi */
1196	/* Description: Data Cache block Invalidate */	1196	/* Description: Data Cache block Invalidate */
1197	/* Input: r3 = effective address */	1197	/* Input: r3 = effective address */
1198	/* Output: none. */	1198	/* Output: none. */
1199	/------------------------------------------------------------------------------- /	1199	/------------------------------------------------------------------------------- /
1200	.globl ppcDcbi	1200	.globl ppcDcbi
1201	ppcDcbi:	1201	ppcDcbi:
1202	dcbi r0,r3	1202	dcbi r0,r3
1203	blr	1203	blr
1204		1204
1205	/------------------------------------------------------------------------------- /	1205	/------------------------------------------------------------------------------- /
1206	/* Function: ppcSync */	1206	/* Function: ppcSync */
1207	/* Description: Processor Synchronize */	1207	/* Description: Processor Synchronize */
1208	/* Input: none. */	1208	/* Input: none. */
1209	/* Output: none. */	1209	/* Output: none. */
1210	/------------------------------------------------------------------------------- /	1210	/------------------------------------------------------------------------------- /
1211	.globl ppcSync	1211	.globl ppcSync
1212	ppcSync:	1212	ppcSync:
1213	sync	1213	sync
1214	blr	1214	blr
1215		1215
1216	/------------------------------------------------------------------------------/	1216	/------------------------------------------------------------------------------/
1217		1217
1218	/*	1218	/*
1219	* void relocate_code (addr_sp, gd, addr_moni)	1219	* void relocate_code (addr_sp, gd, addr_moni)
1220	*	1220	*
1221	* This "function" does not return, instead it continues in RAM	1221	* This "function" does not return, instead it continues in RAM
1222	* after relocating the monitor code.	1222	* after relocating the monitor code.
1223	*	1223	*
1224	* r3 = dest	1224	* r3 = dest
1225	* r4 = src	1225	* r4 = src
1226	* r5 = length in bytes	1226	* r5 = length in bytes
1227	* r6 = cachelinesize	1227	* r6 = cachelinesize
1228	*/	1228	*/
1229	.globl relocate_code	1229	.globl relocate_code
1230	relocate_code:	1230	relocate_code:
1231	#if defined(CONFIG_440_EP) \|\| defined(CONFIG_440_GR)	1231	#if defined(CONFIG_440_EP) \|\| defined(CONFIG_440_GR)
1232	dccci 0,0 /* Invalidate data cache, now no longer our stack */	1232	dccci 0,0 /* Invalidate data cache, now no longer our stack */
1233	sync	1233	sync
1234	addi r1,r0,0x0000 /* Tlb entry #0 */	1234	addi r1,r0,0x0000 /* Tlb entry #0 */
1235	tlbre r0,r1,0x0002 /* Read contents */	1235	tlbre r0,r1,0x0002 /* Read contents */
1236	ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */	1236	ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1237	tlbwe r0,r1,0x0002 /* Save it out */	1237	tlbwe r0,r1,0x0002 /* Save it out */
1238	isync	1238	isync
1239	#endif	1239	#endif
1240	mr r1, r3 /* Set new stack pointer */	1240	mr r1, r3 /* Set new stack pointer */
1241	mr r9, r4 /* Save copy of Init Data pointer */	1241	mr r9, r4 /* Save copy of Init Data pointer */
1242	mr r10, r5 /* Save copy of Destination Address */	1242	mr r10, r5 /* Save copy of Destination Address */
1243		1243
1244	mr r3, r5 /* Destination Address */	1244	mr r3, r5 /* Destination Address */
1245	lis r4, CFG_MONITOR_BASE@h /* Source Address */	1245	lis r4, CFG_MONITOR_BASE@h /* Source Address */
1246	ori r4, r4, CFG_MONITOR_BASE@l	1246	ori r4, r4, CFG_MONITOR_BASE@l
1247	lwz r5, GOT(__init_end)	1247	lwz r5, GOT(__init_end)
1248	sub r5, r5, r4	1248	sub r5, r5, r4
1249	li r6, CFG_CACHELINE_SIZE /* Cache Line Size */	1249	li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
1250		1250
1251	/*	1251	/*
1252	* Fix GOT pointer:	1252	* Fix GOT pointer:
1253	*	1253	*
1254	* New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address	1254	* New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
1255	*	1255	*
1256	* Offset:	1256	* Offset:
1257	*/	1257	*/
1258	sub r15, r10, r4	1258	sub r15, r10, r4
1259		1259
1260	/* First our own GOT */	1260	/* First our own GOT */
1261	add r14, r14, r15	1261	add r14, r14, r15
1262	/* the the one used by the C code */	1262	/* the the one used by the C code */
1263	add r30, r30, r15	1263	add r30, r30, r15
1264		1264
1265	/*	1265	/*
1266	* Now relocate code	1266	* Now relocate code
1267	*/	1267	*/
1268		1268
1269	cmplw cr1,r3,r4	1269	cmplw cr1,r3,r4
1270	addi r0,r5,3	1270	addi r0,r5,3
1271	srwi. r0,r0,2	1271	srwi. r0,r0,2
1272	beq cr1,4f /* In place copy is not necessary */	1272	beq cr1,4f /* In place copy is not necessary */
1273	beq 7f /* Protect against 0 count */	1273	beq 7f /* Protect against 0 count */
1274	mtctr r0	1274	mtctr r0
1275	bge cr1,2f	1275	bge cr1,2f
1276		1276
1277	la r8,-4(r4)	1277	la r8,-4(r4)
1278	la r7,-4(r3)	1278	la r7,-4(r3)
1279	1: lwzu r0,4(r8)	1279	1: lwzu r0,4(r8)
1280	stwu r0,4(r7)	1280	stwu r0,4(r7)
1281	bdnz 1b	1281	bdnz 1b
1282	b 4f	1282	b 4f
1283		1283
1284	2: slwi r0,r0,2	1284	2: slwi r0,r0,2
1285	add r8,r4,r0	1285	add r8,r4,r0
1286	add r7,r3,r0	1286	add r7,r3,r0
1287	3: lwzu r0,-4(r8)	1287	3: lwzu r0,-4(r8)
1288	stwu r0,-4(r7)	1288	stwu r0,-4(r7)
1289	bdnz 3b	1289	bdnz 3b
1290		1290
1291	/*	1291	/*
1292	* Now flush the cache: note that we must start from a cache aligned	1292	* Now flush the cache: note that we must start from a cache aligned
1293	* address. Otherwise we might miss one cache line.	1293	* address. Otherwise we might miss one cache line.
1294	*/	1294	*/
1295	4: cmpwi r6,0	1295	4: cmpwi r6,0
1296	add r5,r3,r5	1296	add r5,r3,r5
1297	beq 7f /* Always flush prefetch queue in any case */	1297	beq 7f /* Always flush prefetch queue in any case */
1298	subi r0,r6,1	1298	subi r0,r6,1
1299	andc r3,r3,r0	1299	andc r3,r3,r0
1300	mr r4,r3	1300	mr r4,r3
1301	5: dcbst 0,r4	1301	5: dcbst 0,r4
1302	add r4,r4,r6	1302	add r4,r4,r6
1303	cmplw r4,r5	1303	cmplw r4,r5
1304	blt 5b	1304	blt 5b
1305	sync /* Wait for all dcbst to complete on bus */	1305	sync /* Wait for all dcbst to complete on bus */
1306	mr r4,r3	1306	mr r4,r3
1307	6: icbi 0,r4	1307	6: icbi 0,r4
1308	add r4,r4,r6	1308	add r4,r4,r6
1309	cmplw r4,r5	1309	cmplw r4,r5
1310	blt 6b	1310	blt 6b
1311	7: sync /* Wait for all icbi to complete on bus */	1311	7: sync /* Wait for all icbi to complete on bus */
1312	isync	1312	isync
1313		1313
1314	/*	1314	/*
1315	* We are done. Do not return, instead branch to second part of board	1315	* We are done. Do not return, instead branch to second part of board
1316	* initialization, now running from RAM.	1316	* initialization, now running from RAM.
1317	*/	1317	*/
1318		1318
1319	addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET	1319	addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
1320	mtlr r0	1320	mtlr r0
1321	blr /* NEVER RETURNS! */	1321	blr /* NEVER RETURNS! */
1322		1322
1323	in_ram:	1323	in_ram:
1324		1324
1325	/*	1325	/*
1326	* Relocation Function, r14 point to got2+0x8000	1326	* Relocation Function, r14 point to got2+0x8000
1327	*	1327	*
1328	* Adjust got2 pointers, no need to check for 0, this code	1328	* Adjust got2 pointers, no need to check for 0, this code
1329	* already puts a few entries in the table.	1329	* already puts a few entries in the table.
1330	*/	1330	*/
1331	li r0,__got2_entries@sectoff@l	1331	li r0,__got2_entries@sectoff@l
1332	la r3,GOT(_GOT2_TABLE_)	1332	la r3,GOT(_GOT2_TABLE_)
1333	lwz r11,GOT(_GOT2_TABLE_)	1333	lwz r11,GOT(_GOT2_TABLE_)
1334	mtctr r0	1334	mtctr r0
1335	sub r11,r3,r11	1335	sub r11,r3,r11
1336	addi r3,r3,-4	1336	addi r3,r3,-4
1337	1: lwzu r0,4(r3)	1337	1: lwzu r0,4(r3)
1338	add r0,r0,r11	1338	add r0,r0,r11
1339	stw r0,0(r3)	1339	stw r0,0(r3)
1340	bdnz 1b	1340	bdnz 1b
1341		1341
1342	/*	1342	/*
1343	* Now adjust the fixups and the pointers to the fixups	1343	* Now adjust the fixups and the pointers to the fixups
1344	* in case we need to move ourselves again.	1344	* in case we need to move ourselves again.
1345	*/	1345	*/
1346	2: li r0,__fixup_entries@sectoff@l	1346	2: li r0,__fixup_entries@sectoff@l
1347	lwz r3,GOT(_FIXUP_TABLE_)	1347	lwz r3,GOT(_FIXUP_TABLE_)
1348	cmpwi r0,0	1348	cmpwi r0,0
1349	mtctr r0	1349	mtctr r0
1350	addi r3,r3,-4	1350	addi r3,r3,-4
1351	beq 4f	1351	beq 4f
1352	3: lwzu r4,4(r3)	1352	3: lwzu r4,4(r3)
1353	lwzux r0,r4,r11	1353	lwzux r0,r4,r11
1354	add r0,r0,r11	1354	add r0,r0,r11
1355	stw r10,0(r3)	1355	stw r10,0(r3)
1356	stw r0,0(r4)	1356	stw r0,0(r4)
1357	bdnz 3b	1357	bdnz 3b
1358	4:	1358	4:
1359	clear_bss:	1359	clear_bss:
1360	/*	1360	/*
1361	* Now clear BSS segment	1361	* Now clear BSS segment
1362	*/	1362	*/
1363	lwz r3,GOT(__bss_start)	1363	lwz r3,GOT(__bss_start)
1364	lwz r4,GOT(_end)	1364	lwz r4,GOT(_end)
1365		1365
1366	cmplw 0, r3, r4	1366	cmplw 0, r3, r4
1367	beq 6f	1367	beq 6f
1368		1368
1369	li r0, 0	1369	li r0, 0
1370	5:	1370	5:
1371	stw r0, 0(r3)	1371	stw r0, 0(r3)
1372	addi r3, r3, 4	1372	addi r3, r3, 4
1373	cmplw 0, r3, r4	1373	cmplw 0, r3, r4
1374	bne 5b	1374	bne 5b
1375	6:	1375	6:
1376		1376
1377	mr r3, r9 /* Init Data pointer */	1377	mr r3, r9 /* Init Data pointer */
1378	mr r4, r10 /* Destination Address */	1378	mr r4, r10 /* Destination Address */
1379	bl board_init_r	1379	bl board_init_r
1380		1380
1381	/*	1381	/*
1382	* Copy exception vector code to low memory	1382	* Copy exception vector code to low memory
1383	*	1383	*
1384	* r3: dest_addr	1384	* r3: dest_addr
1385	* r7: source address, r8: end address, r9: target address	1385	* r7: source address, r8: end address, r9: target address
1386	*/	1386	*/
1387	.globl trap_init	1387	.globl trap_init
1388	trap_init:	1388	trap_init:
1389	lwz r7, GOT(_start)	1389	lwz r7, GOT(_start)
1390	lwz r8, GOT(_end_of_vectors)	1390	lwz r8, GOT(_end_of_vectors)
1391		1391
1392	li r9, 0x100 /* reset vector always at 0x100 */	1392	li r9, 0x100 /* reset vector always at 0x100 */
1393		1393
1394	cmplw 0, r7, r8	1394	cmplw 0, r7, r8
1395	bgelr /* return if r7>=r8 - just in case */	1395	bgelr /* return if r7>=r8 - just in case */
1396		1396
1397	mflr r4 /* save link register */	1397	mflr r4 /* save link register */
1398	1:	1398	1:
1399	lwz r0, 0(r7)	1399	lwz r0, 0(r7)
1400	stw r0, 0(r9)	1400	stw r0, 0(r9)
1401	addi r7, r7, 4	1401	addi r7, r7, 4
1402	addi r9, r9, 4	1402	addi r9, r9, 4
1403	cmplw 0, r7, r8	1403	cmplw 0, r7, r8
1404	bne 1b	1404	bne 1b
1405		1405
1406	/*	1406	/*
1407	* relocate `hdlr' and `int_return' entries	1407	* relocate `hdlr' and `int_return' entries
1408	*/	1408	*/
1409	li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET	1409	li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
1410	li r8, Alignment - _start + EXC_OFF_SYS_RESET	1410	li r8, Alignment - _start + EXC_OFF_SYS_RESET
1411	2:	1411	2:
1412	bl trap_reloc	1412	bl trap_reloc
1413	addi r7, r7, 0x100 /* next exception vector */	1413	addi r7, r7, 0x100 /* next exception vector */
1414	cmplw 0, r7, r8	1414	cmplw 0, r7, r8
1415	blt 2b	1415	blt 2b
1416		1416
1417	li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET	1417	li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
1418	bl trap_reloc	1418	bl trap_reloc
1419		1419
1420	li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET	1420	li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
1421	bl trap_reloc	1421	bl trap_reloc
1422		1422
1423	li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET	1423	li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
1424	li r8, SystemCall - _start + EXC_OFF_SYS_RESET	1424	li r8, SystemCall - _start + EXC_OFF_SYS_RESET
1425	3:	1425	3:
1426	bl trap_reloc	1426	bl trap_reloc
1427	addi r7, r7, 0x100 /* next exception vector */	1427	addi r7, r7, 0x100 /* next exception vector */
1428	cmplw 0, r7, r8	1428	cmplw 0, r7, r8
1429	blt 3b	1429	blt 3b
1430		1430
1431	li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET	1431	li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
1432	li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET	1432	li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
1433	4:	1433	4:
1434	bl trap_reloc	1434	bl trap_reloc
1435	addi r7, r7, 0x100 /* next exception vector */	1435	addi r7, r7, 0x100 /* next exception vector */
1436	cmplw 0, r7, r8	1436	cmplw 0, r7, r8
1437	blt 4b	1437	blt 4b
1438		1438
1439	mtlr r4 /* restore link register */	1439	mtlr r4 /* restore link register */
1440	blr	1440	blr
1441		1441
1442	/*	1442	/*
1443	* Function: relocate entries for one exception vector	1443	* Function: relocate entries for one exception vector
1444	*/	1444	*/
1445	trap_reloc:	1445	trap_reloc:
1446	lwz r0, 0(r7) /* hdlr ... */	1446	lwz r0, 0(r7) /* hdlr ... */
1447	add r0, r0, r3 /* ... += dest_addr */	1447	add r0, r0, r3 /* ... += dest_addr */
1448	stw r0, 0(r7)	1448	stw r0, 0(r7)
1449		1449
1450	lwz r0, 4(r7) /* int_return ... */	1450	lwz r0, 4(r7) /* int_return ... */
1451	add r0, r0, r3 /* ... += dest_addr */	1451	add r0, r0, r3 /* ... += dest_addr */
1452	stw r0, 4(r7)	1452	stw r0, 4(r7)
1453		1453
1454	blr	1454	blr
1455		1455
1456		1456
1457	/**************************************************************************/	1457	/**************************************************************************/
1458	/* PPC405EP specific stuff */	1458	/* PPC405EP specific stuff */
1459	/**************************************************************************/	1459	/**************************************************************************/
1460	#ifdef CONFIG_405EP	1460	#ifdef CONFIG_405EP
1461	ppc405ep_init:	1461	ppc405ep_init:
1462		1462
1463	#ifdef CONFIG_BUBINGA	1463	#ifdef CONFIG_BUBINGA
1464	/*	1464	/*
1465	* Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate	1465	* Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1466	* function) to support FPGA and NVRAM accesses below.	1466	* function) to support FPGA and NVRAM accesses below.
1467	*/	1467	*/
1468		1468
1469	lis r3,GPIO0_OSRH@h /* config GPIO output select */	1469	lis r3,GPIO0_OSRH@h /* config GPIO output select */
1470	ori r3,r3,GPIO0_OSRH@l	1470	ori r3,r3,GPIO0_OSRH@l
1471	lis r4,CFG_GPIO0_OSRH@h	1471	lis r4,CFG_GPIO0_OSRH@h
1472	ori r4,r4,CFG_GPIO0_OSRH@l	1472	ori r4,r4,CFG_GPIO0_OSRH@l
1473	stw r4,0(r3)	1473	stw r4,0(r3)
1474	lis r3,GPIO0_OSRL@h	1474	lis r3,GPIO0_OSRL@h
1475	ori r3,r3,GPIO0_OSRL@l	1475	ori r3,r3,GPIO0_OSRL@l
1476	lis r4,CFG_GPIO0_OSRL@h	1476	lis r4,CFG_GPIO0_OSRL@h
1477	ori r4,r4,CFG_GPIO0_OSRL@l	1477	ori r4,r4,CFG_GPIO0_OSRL@l
1478	stw r4,0(r3)	1478	stw r4,0(r3)
1479		1479
1480	lis r3,GPIO0_ISR1H@h /* config GPIO input select */	1480	lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1481	ori r3,r3,GPIO0_ISR1H@l	1481	ori r3,r3,GPIO0_ISR1H@l
1482	lis r4,CFG_GPIO0_ISR1H@h	1482	lis r4,CFG_GPIO0_ISR1H@h
1483	ori r4,r4,CFG_GPIO0_ISR1H@l	1483	ori r4,r4,CFG_GPIO0_ISR1H@l
1484	stw r4,0(r3)	1484	stw r4,0(r3)
1485	lis r3,GPIO0_ISR1L@h	1485	lis r3,GPIO0_ISR1L@h
1486	ori r3,r3,GPIO0_ISR1L@l	1486	ori r3,r3,GPIO0_ISR1L@l
1487	lis r4,CFG_GPIO0_ISR1L@h	1487	lis r4,CFG_GPIO0_ISR1L@h
1488	ori r4,r4,CFG_GPIO0_ISR1L@l	1488	ori r4,r4,CFG_GPIO0_ISR1L@l
1489	stw r4,0(r3)	1489	stw r4,0(r3)
1490		1490
1491	lis r3,GPIO0_TSRH@h /* config GPIO three-state select */	1491	lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1492	ori r3,r3,GPIO0_TSRH@l	1492	ori r3,r3,GPIO0_TSRH@l
1493	lis r4,CFG_GPIO0_TSRH@h	1493	lis r4,CFG_GPIO0_TSRH@h
1494	ori r4,r4,CFG_GPIO0_TSRH@l	1494	ori r4,r4,CFG_GPIO0_TSRH@l
1495	stw r4,0(r3)	1495	stw r4,0(r3)
1496	lis r3,GPIO0_TSRL@h	1496	lis r3,GPIO0_TSRL@h
1497	ori r3,r3,GPIO0_TSRL@l	1497	ori r3,r3,GPIO0_TSRL@l
1498	lis r4,CFG_GPIO0_TSRL@h	1498	lis r4,CFG_GPIO0_TSRL@h
1499	ori r4,r4,CFG_GPIO0_TSRL@l	1499	ori r4,r4,CFG_GPIO0_TSRL@l
1500	stw r4,0(r3)	1500	stw r4,0(r3)
1501		1501
1502	lis r3,GPIO0_TCR@h /* config GPIO driver output enables */	1502	lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1503	ori r3,r3,GPIO0_TCR@l	1503	ori r3,r3,GPIO0_TCR@l
1504	lis r4,CFG_GPIO0_TCR@h	1504	lis r4,CFG_GPIO0_TCR@h
1505	ori r4,r4,CFG_GPIO0_TCR@l	1505	ori r4,r4,CFG_GPIO0_TCR@l
1506	stw r4,0(r3)	1506	stw r4,0(r3)
1507		1507
1508	li r3,pb1ap /* program EBC bank 1 for RTC access */	1508	li r3,pb1ap /* program EBC bank 1 for RTC access */
1509	mtdcr ebccfga,r3	1509	mtdcr ebccfga,r3
1510	lis r3,CFG_EBC_PB1AP@h	1510	lis r3,CFG_EBC_PB1AP@h
1511	ori r3,r3,CFG_EBC_PB1AP@l	1511	ori r3,r3,CFG_EBC_PB1AP@l
1512	mtdcr ebccfgd,r3	1512	mtdcr ebccfgd,r3
1513	li r3,pb1cr	1513	li r3,pb1cr
1514	mtdcr ebccfga,r3	1514	mtdcr ebccfga,r3
1515	lis r3,CFG_EBC_PB1CR@h	1515	lis r3,CFG_EBC_PB1CR@h
1516	ori r3,r3,CFG_EBC_PB1CR@l	1516	ori r3,r3,CFG_EBC_PB1CR@l
1517	mtdcr ebccfgd,r3	1517	mtdcr ebccfgd,r3
1518		1518
1519	li r3,pb1ap /* program EBC bank 1 for RTC access */	1519	li r3,pb1ap /* program EBC bank 1 for RTC access */
1520	mtdcr ebccfga,r3	1520	mtdcr ebccfga,r3
1521	lis r3,CFG_EBC_PB1AP@h	1521	lis r3,CFG_EBC_PB1AP@h
1522	ori r3,r3,CFG_EBC_PB1AP@l	1522	ori r3,r3,CFG_EBC_PB1AP@l
1523	mtdcr ebccfgd,r3	1523	mtdcr ebccfgd,r3
1524	li r3,pb1cr	1524	li r3,pb1cr
1525	mtdcr ebccfga,r3	1525	mtdcr ebccfga,r3
1526	lis r3,CFG_EBC_PB1CR@h	1526	lis r3,CFG_EBC_PB1CR@h
1527	ori r3,r3,CFG_EBC_PB1CR@l	1527	ori r3,r3,CFG_EBC_PB1CR@l
1528	mtdcr ebccfgd,r3	1528	mtdcr ebccfgd,r3
1529		1529
1530	li r3,pb4ap /* program EBC bank 4 for FPGA access */	1530	li r3,pb4ap /* program EBC bank 4 for FPGA access */
1531	mtdcr ebccfga,r3	1531	mtdcr ebccfga,r3
1532	lis r3,CFG_EBC_PB4AP@h	1532	lis r3,CFG_EBC_PB4AP@h
1533	ori r3,r3,CFG_EBC_PB4AP@l	1533	ori r3,r3,CFG_EBC_PB4AP@l
1534	mtdcr ebccfgd,r3	1534	mtdcr ebccfgd,r3
1535	li r3,pb4cr	1535	li r3,pb4cr
1536	mtdcr ebccfga,r3	1536	mtdcr ebccfga,r3
1537	lis r3,CFG_EBC_PB4CR@h	1537	lis r3,CFG_EBC_PB4CR@h
1538	ori r3,r3,CFG_EBC_PB4CR@l	1538	ori r3,r3,CFG_EBC_PB4CR@l
1539	mtdcr ebccfgd,r3	1539	mtdcr ebccfgd,r3
1540	#endif	1540	#endif
1541		1541
1542	addi r3,0,CPC0_PCI_HOST_CFG_EN	1542	addi r3,0,CPC0_PCI_HOST_CFG_EN
1543	#ifdef CONFIG_BUBINGA	1543	#ifdef CONFIG_BUBINGA
1544	/*	1544	/*
1545	!-----------------------------------------------------------------------	1545	!-----------------------------------------------------------------------
1546	! Check FPGA for PCI internal/external arbitration	1546	! Check FPGA for PCI internal/external arbitration
1547	! If board is set to internal arbitration, update cpc0_pci	1547	! If board is set to internal arbitration, update cpc0_pci
1548	!-----------------------------------------------------------------------	1548	!-----------------------------------------------------------------------
1549	*/	1549	*/
1550	addis r5,r0,FPGA_REG1@h /* set offset for FPGA_REG1 */	1550	addis r5,r0,FPGA_REG1@h /* set offset for FPGA_REG1 */
1551	ori r5,r5,FPGA_REG1@l	1551	ori r5,r5,FPGA_REG1@l
1552	lbz r5,0x0(r5) /* read to get PCI arb selection */	1552	lbz r5,0x0(r5) /* read to get PCI arb selection */
1553	andi. r6,r5,FPGA_REG1_PCI_INT_ARB /* using internal arbiter ?*/	1553	andi. r6,r5,FPGA_REG1_PCI_INT_ARB /* using internal arbiter ?*/
1554	beq ..pci_cfg_set /* if not set, then bypass reg write*/	1554	beq ..pci_cfg_set /* if not set, then bypass reg write*/
1555	#endif	1555	#endif
1556	ori r3,r3,CPC0_PCI_ARBIT_EN	1556	ori r3,r3,CPC0_PCI_ARBIT_EN
1557	..pci_cfg_set:	1557	..pci_cfg_set:
1558	mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/	1558	mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/
1559		1559
1560	/*	1560	/*
1561	!-----------------------------------------------------------------------	1561	!-----------------------------------------------------------------------
1562	! Check to see if chip is in bypass mode.	1562	! Check to see if chip is in bypass mode.
1563	! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a	1563	! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1564	! CPU reset Otherwise, skip this step and keep going.	1564	! CPU reset Otherwise, skip this step and keep going.
1565	! Note: Running BIOS in bypass mode is not supported since PLB speed	1565	! Note: Running BIOS in bypass mode is not supported since PLB speed
1566	! will not be fast enough for the SDRAM (min 66MHz)	1566	! will not be fast enough for the SDRAM (min 66MHz)
1567	!-----------------------------------------------------------------------	1567	!-----------------------------------------------------------------------
1568	*/	1568	*/
1569	mfdcr r5, CPC0_PLLMR1	1569	mfdcr r5, CPC0_PLLMR1
1570	rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */	1570	rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1571	cmpi cr0,0,r4,0x1	1571	cmpi cr0,0,r4,0x1
1572		1572
1573	beq pll_done /* if SSCS =b'1' then PLL has */	1573	beq pll_done /* if SSCS =b'1' then PLL has */
1574	/* already been set */	1574	/* already been set */
1575	/* and CPU has been reset */	1575	/* and CPU has been reset */
1576	/* so skip to next section */	1576	/* so skip to next section */
1577		1577
1578	#ifdef CONFIG_BUBINGA	1578	#ifdef CONFIG_BUBINGA
1579	/*	1579	/*
1580	!-----------------------------------------------------------------------	1580	!-----------------------------------------------------------------------
1581	! Read NVRAM to get value to write in PLLMR.	1581	! Read NVRAM to get value to write in PLLMR.
1582	! If value has not been correctly saved, write default value	1582	! If value has not been correctly saved, write default value
1583	! Default config values (assuming on-board 33MHz SYS_CLK) are above.	1583	! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1584	! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.	1584	! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1585	!	1585	!
1586	! WARNING: This code assumes the first three words in the nvram_t	1586	! WARNING: This code assumes the first three words in the nvram_t
1587	! structure in openbios.h. Changing the beginning of	1587	! structure in openbios.h. Changing the beginning of
1588	! the structure will break this code.	1588	! the structure will break this code.
1589	!	1589	!
1590	!-----------------------------------------------------------------------	1590	!-----------------------------------------------------------------------
1591	*/	1591	*/
1592	addis r3,0,NVRAM_BASE@h	1592	addis r3,0,NVRAM_BASE@h
1593	addi r3,r3,NVRAM_BASE@l	1593	addi r3,r3,NVRAM_BASE@l
1594		1594
1595	lwz r4, 0(r3)	1595	lwz r4, 0(r3)
1596	addis r5,0,NVRVFY1@h	1596	addis r5,0,NVRVFY1@h
1597	addi r5,r5,NVRVFY1@l	1597	addi r5,r5,NVRVFY1@l
1598	cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/	1598	cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1599	bne ..no_pllset	1599	bne ..no_pllset
1600	addi r3,r3,4	1600	addi r3,r3,4
1601	lwz r4, 0(r3)	1601	lwz r4, 0(r3)
1602	addis r5,0,NVRVFY2@h	1602	addis r5,0,NVRVFY2@h
1603	addi r5,r5,NVRVFY2@l	1603	addi r5,r5,NVRVFY2@l
1604	cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */	1604	cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1605	bne ..no_pllset	1605	bne ..no_pllset
1606	addi r3,r3,8 /* Skip over conf_size */	1606	addi r3,r3,8 /* Skip over conf_size */
1607	lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */	1607	lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1608	lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */	1608	lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1609	rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */	1609	rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1610	cmpi cr0,0,r5,1 /* See if PLL is locked */	1610	cmpi cr0,0,r5,1 /* See if PLL is locked */
1611	beq pll_write	1611	beq pll_write
1612	..no_pllset:	1612	..no_pllset:
1613	#endif /* CONFIG_BUBINGA */	1613	#endif /* CONFIG_BUBINGA */
1614		1614
1615	addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */	1615	addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1616	ori r3,r3,PLLMR0_DEFAULT@l /* */	1616	ori r3,r3,PLLMR0_DEFAULT@l /* */
1617	addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */	1617	addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1618	ori r4,r4,PLLMR1_DEFAULT@l /* */	1618	ori r4,r4,PLLMR1_DEFAULT@l /* */
1619		1619
1620	b pll_write /* Write the CPC0_PLLMR with new value */	1620	b pll_write /* Write the CPC0_PLLMR with new value */
1621		1621
1622	pll_done:	1622	pll_done:
1623	/*	1623	/*
1624	!-----------------------------------------------------------------------	1624	!-----------------------------------------------------------------------
1625	! Clear Soft Reset Register	1625	! Clear Soft Reset Register
1626	! This is needed to enable PCI if not booting from serial EPROM	1626	! This is needed to enable PCI if not booting from serial EPROM
1627	!-----------------------------------------------------------------------	1627	!-----------------------------------------------------------------------
1628	*/	1628	*/
1629	addi r3, 0, 0x0	1629	addi r3, 0, 0x0
1630	mtdcr CPC0_SRR, r3	1630	mtdcr CPC0_SRR, r3
1631		1631
1632	addis r3,0,0x0010	1632	addis r3,0,0x0010
1633	mtctr r3	1633	mtctr r3
1634	pci_wait:	1634	pci_wait:
1635	bdnz pci_wait	1635	bdnz pci_wait
1636		1636
1637	blr /* return to main code */	1637	blr /* return to main code */
1638		1638
1639	/*	1639	/*
1640	!-----------------------------------------------------------------------------	1640	!-----------------------------------------------------------------------------
1641	! Function: pll_write	1641	! Function: pll_write
1642	! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation	1642	! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1643	! That is:	1643	! That is:
1644	! 1. Pll is first disabled (de-activated by putting in bypass mode)	1644	! 1. Pll is first disabled (de-activated by putting in bypass mode)
1645	! 2. PLL is reset	1645	! 2. PLL is reset
1646	! 3. Clock dividers are set while PLL is held in reset and bypassed	1646	! 3. Clock dividers are set while PLL is held in reset and bypassed
1647	! 4. PLL Reset is cleared	1647	! 4. PLL Reset is cleared
1648	! 5. Wait 100us for PLL to lock	1648	! 5. Wait 100us for PLL to lock
1649	! 6. A core reset is performed	1649	! 6. A core reset is performed
1650	! Input: r3 = Value to write to CPC0_PLLMR0	1650	! Input: r3 = Value to write to CPC0_PLLMR0
1651	! Input: r4 = Value to write to CPC0_PLLMR1	1651	! Input: r4 = Value to write to CPC0_PLLMR1
1652	! Output r3 = none	1652	! Output r3 = none
1653	!-----------------------------------------------------------------------------	1653	!-----------------------------------------------------------------------------
1654	*/	1654	*/
1655	pll_write:	1655	pll_write:
1656	mfdcr r5, CPC0_UCR	1656	mfdcr r5, CPC0_UCR
1657	andis. r5,r5,0xFFFF	1657	andis. r5,r5,0xFFFF
1658	ori r5,r5,0x0101 /* Stop the UART clocks */	1658	ori r5,r5,0x0101 /* Stop the UART clocks */
1659	mtdcr CPC0_UCR,r5 /* Before changing PLL */	1659	mtdcr CPC0_UCR,r5 /* Before changing PLL */
1660		1660
1661	mfdcr r5, CPC0_PLLMR1	1661	mfdcr r5, CPC0_PLLMR1
1662	rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */	1662	rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
1663	mtdcr CPC0_PLLMR1,r5	1663	mtdcr CPC0_PLLMR1,r5
1664	oris r5,r5,0x4000 /* Set PLL Reset */	1664	oris r5,r5,0x4000 /* Set PLL Reset */
1665	mtdcr CPC0_PLLMR1,r5	1665	mtdcr CPC0_PLLMR1,r5
1666		1666
1667	mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */	1667	mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
1668	rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */	1668	rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
1669	oris r5,r5,0x4000 /* Set PLL Reset */	1669	oris r5,r5,0x4000 /* Set PLL Reset */
1670	mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */	1670	mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
1671	rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */	1671	rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
1672	mtdcr CPC0_PLLMR1,r5	1672	mtdcr CPC0_PLLMR1,r5
1673		1673
1674	/*	1674	/*
1675	! Wait min of 100us for PLL to lock.	1675	! Wait min of 100us for PLL to lock.
1676	! See CMOS 27E databook for more info.	1676	! See CMOS 27E databook for more info.
1677	! At 200MHz, that means waiting 20,000 instructions	1677	! At 200MHz, that means waiting 20,000 instructions
1678	*/	1678	*/
1679	addi r3,0,20000 /* 2000 = 0x4e20 */	1679	addi r3,0,20000 /* 2000 = 0x4e20 */
1680	mtctr r3	1680	mtctr r3
1681	pll_wait:	1681	pll_wait:
1682	bdnz pll_wait	1682	bdnz pll_wait
1683		1683
1684	oris r5,r5,0x8000 /* Enable PLL */	1684	oris r5,r5,0x8000 /* Enable PLL */
1685	mtdcr CPC0_PLLMR1,r5 /* Engage */	1685	mtdcr CPC0_PLLMR1,r5 /* Engage */
1686		1686
1687	/*	1687	/*
1688	* Reset CPU to guarantee timings are OK	1688	* Reset CPU to guarantee timings are OK
1689	* Not sure if this is needed...	1689	* Not sure if this is needed...
1690	*/	1690	*/
1691	addis r3,0,0x1000	1691	addis r3,0,0x1000
1692	mtspr dbcr0,r3 /* This will cause a CPU core reset, and */	1692	mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
1693	/* execution will continue from the poweron */	1693	/* execution will continue from the poweron */
1694	/* vector of 0xfffffffc */	1694	/* vector of 0xfffffffc */
1695	#endif /* CONFIG_405EP */	1695	#endif /* CONFIG_405EP */
1696		1696

doc/README.mpc83xxads

Diff comments View file @ f901a83

 Freescale MPC83xx ADS Boards
 -----------------------------------------
 0. Toolchain / Building
-    % setenv CROSS_COMPILE /usr/powerpc/bin/powerpc-linux-
+    $ PATH=$PATH:/usr/powerpc/bin
+    $ CROSS_COMPILE=powerpc-linux-
+    $ export PATH CROSS_COMPILE
-    % /usr/powerpc/bin/powerpc-linux-gcc -v
+    $ powerpc-linux-gcc -v
     Reading specs from /usr/powerpc/lib/gcc/powerpc-linux/3.4.3/specs
     Configured with: ../configure --prefix=/usr/powerpc
     --exec-prefix=/usr/powerpc --target=powerpc-linux --enable-shared
     --disable-nls --disable-multilib --enable-languages=c,c++,ada,f77,objc
     Thread model: posix
     gcc version 3.4.3 (Debian)
-    % /usr/powerpc/bin/powerpc-linux-as -v
+    $ powerpc-linux-as -v
     GNU assembler version 2.15 (powerpc-linux) using BFD version 2.15
-    % make MPC8349ADS_config
+    $ make MPC8349ADS_config
     Configuring for MPC8349ADS board...
-    % make
+    $ make
 1. Board Switches and Jumpers
 2. Memory Map
 2.1. The memory map should look pretty much like this:
      0x0000_0000     0x7fff_ffff     DDR		     2G
      0x8000_0000     0x9fff_ffff     PCI MEM		     512M
      0xc000_0000     0xdfff_ffff     Rapid IO		     512M
      0xe000_0000     0xe00f_ffff     CCSR		     1M
      0xe200_0000     0xe2ff_ffff     PCI IO		     16M
      0xf000_0000     0xf7ff_ffff     SDRAM		     128M
      0xf800_0000     0xf80f_ffff     BCSR		     1M
      0xfe00_0000     0xffff_ffff     FLASH (boot bank)	     16M
 3. Definitions
 3.1 Explanation of NEW definitions in:
 	include/configs/MPC8349ADS.h
     CONFIG_MPC83xx	    MPC83xx family
     CONFIG_MPC8349	    MPC8349 specific
     CONFIG_MPC8349ADS	    MPC8349ADS board specific
     CONFIG_TSEC_ENET	    Use on-chip 10/100/1000 ethernet
 4. Compilation
     Assuming you're using BASH shell:
 	export CROSS_COMPILE=your-cross-compile-prefix
 	cd u-boot
 	make distclean
 	make MPC8349ADS_config
 	make
 5. Downloading and Flashing Images
 5.0 Download over serial line using Kermit:
 	loadb
 	[Drop to kermit:
 	    ^\c
 	    send <u-boot-bin-image>
 	    c
 	]
     Or via tftp:
-        tftp 10000 u-boot.bin
+	tftp 10000 u-boot.bin
 5.1 Reflash U-boot Image using U-boot
     tftp 10000 u-boot.bin
     protect off fe000000 fe09ffff
     erase fe000000 fe09ffff
     cp.b 10000 fe000000 xxxx
 or
     cp.b 10000 fe000000 a0000
 You might have to supply the correct byte count for 'xxxx' from
 the TFTP.  Maybe a0000 will work too, that corresponds to the
 erased sectors.
 6. Notes

include/configs/ep8248.h

Diff comments View file @ f901a83

File was created	1	/*
	2	* Copyright (C) 2004 Arabella Software Ltd.
	3	* Yuli Barcohen <yuli@arabellasw.com>
	4	*
	5	* U-Boot configuration for Embedded Planet EP8248 boards.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#ifndef __CONFIG_H
	27	#define __CONFIG_H
	28
	29	#define CONFIG_MPC8248
	30	#define CPU_ID_STR "MPC8248"
	31
	32	#define CONFIG_EP8248 /* Embedded Planet EP8248 board */
	33
	34	#undef DEBUG
	35
	36	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
	37
	38	/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
	39	#define CONFIG_ENV_OVERWRITE
	40
	41	/*
	42	* Select serial console configuration
	43	*
	44	* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
	45	* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
	46	* for SCC).
	47	*/
	48	#define CONFIG_CONS_ON_SMC /* Console is on SMC */
	49	#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
	50	#undef CONFIG_CONS_NONE /* It's not on external UART */
	51	#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
	52
	53	#define CFG_BCSR 0xFA000000
	54
	55	/*
	56	* Select ethernet configuration
	57	*
	58	* If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
	59	* then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
	60	* SCC, 1-3 for FCC)
	61	*
	62	* If CONFIG_ETHER_NONE is defined, then either the ethernet routines
	63	* must be defined elsewhere (as for the console), or CFG_CMD_NET must
	64	* be removed from CONFIG_COMMANDS to remove support for networking.
	65	*/
	66	#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
	67	#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
	68	#undef CONFIG_ETHER_NONE /* No external Ethernet */
	69
	70	#ifdef CONFIG_ETHER_ON_FCC
	71
	72	#define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */
	73
	74	#if (CONFIG_ETHER_INDEX == 1)
	75
	76	/* - Rx clock is CLK10
	77	* - Tx clock is CLK11
	78	* - BDs/buffers on 60x bus
	79	* - Full duplex
	80	*/
	81	#define CFG_CMXFCR_MASK (CMXFCR_FC1 \| CMXFCR_RF1CS_MSK \| CMXFCR_TF1CS_MSK)
	82	#define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10 \| CMXFCR_TF1CS_CLK11)
	83	#define CFG_CPMFCR_RAMTYPE 0
	84	#define CFG_FCC_PSMR (FCC_PSMR_FDE \| FCC_PSMR_LPB)
	85
	86	#elif (CONFIG_ETHER_INDEX == 2)
	87
	88	/* - Rx clock is CLK13
	89	* - Tx clock is CLK14
	90	* - BDs/buffers on 60x bus
	91	* - Full duplex
	92	*/
	93	#define CFG_CMXFCR_MASK (CMXFCR_FC2 \| CMXFCR_RF2CS_MSK \| CMXFCR_TF2CS_MSK)
	94	#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 \| CMXFCR_TF2CS_CLK14)
	95	#define CFG_CPMFCR_RAMTYPE 0
	96	#define CFG_FCC_PSMR (FCC_PSMR_FDE \| FCC_PSMR_LPB)
	97
	98	#endif /* CONFIG_ETHER_INDEX */
	99
	100	#define CONFIG_MII /* MII PHY management */
	101	#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
	102	/*
	103	* GPIO pins used for bit-banged MII communications
	104	*/
	105	#define MDIO_PORT 0 /* Not used - implemented in BCSR */
	106	#define MDIO_ACTIVE ((vu_char )(CFG_BCSR + 8) &= 0xFB)
	107	#define MDIO_TRISTATE ((vu_char )(CFG_BCSR + 8) \|= 0x04)
	108	#define MDIO_READ ((vu_char )(CFG_BCSR + 8) & 1)
	109
	110	#define MDIO(bit) if(bit) (vu_char )(CFG_BCSR + 8) \|= 0x01; \
	111	else (vu_char )(CFG_BCSR + 8) &= 0xFE
	112
	113	#define MDC(bit) if(bit) (vu_char )(CFG_BCSR + 8) \|= 0x02; \
	114	else (vu_char )(CFG_BCSR + 8) &= 0xFD
	115
	116	#define MIIDELAY udelay(1)
	117
	118	#endif /* CONFIG_ETHER_ON_FCC */
	119
	120	#ifndef CONFIG_8260_CLKIN
	121	#define CONFIG_8260_CLKIN 66000000 /* in Hz */
	122	#endif
	123
	124	#define CONFIG_BAUDRATE 38400
	125
	126	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
	127	\| CFG_CMD_DHCP \
	128	\| CFG_CMD_ECHO \
	129	\| CFG_CMD_I2C \
	130	\| CFG_CMD_IMMAP \
	131	\| CFG_CMD_MII \
	132	\| CFG_CMD_PING \
	133	)
	134
	135	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	136	#include <cmd_confdefs.h>
	137
	138	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	139	#define CONFIG_BOOTCOMMAND "bootm FF860000" /* autoboot command */
	140	#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro"
	141
	142	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	143	#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
	144	#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
	145	#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
	146	#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */
	147	#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
	148	#endif
	149
	150	#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
	151	#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
	152
	153	/*
	154	* Miscellaneous configurable options
	155	*/
	156	#define CFG_HUSH_PARSER
	157	#define CFG_PROMPT_HUSH_PS2 "> "
	158	#define CFG_LONGHELP /* undef to save memory */
	159	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	160	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	161	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	162	#else
	163	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	164	#endif
	165	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	166	#define CFG_MAXARGS 16 /* max number of command args */
	167	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	168
	169	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
	170	#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
	171
	172	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	173
	174	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	175
	176	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	177
	178	#define CFG_FLASH_BASE 0xFF800000
	179	#define CFG_FLASH_CFI
	180	#define CFG_FLASH_CFI_DRIVER
	181	#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
	182	#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
	183
	184	#define CFG_DIRECT_FLASH_TFTP
	185
	186	#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
	187	#define CFG_JFFS2_FIRST_BANK 0
	188	#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS
	189	#define CFG_JFFS2_FIRST_SECTOR 0
	190	#define CFG_JFFS2_LAST_SECTOR 62
	191	#define CFG_JFFS2_SORT_FRAGMENTS
	192	#define CFG_JFFS_CUSTOM_PART
	193	#endif /* CFG_CMD_JFFS2 */
	194
	195	#if (CONFIG_COMMANDS & CFG_CMD_I2C)
	196	#define CONFIG_HARD_I2C 1 /* To enable I2C support */
	197	#define CFG_I2C_SPEED 100000 /* I2C speed */
	198	#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
	199	#endif /* CFG_CMD_I2C */
	200
	201	#define CFG_MONITOR_BASE TEXT_BASE
	202	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	203	#define CFG_RAMBOOT
	204	#endif
	205
	206	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
	207
	208	#define CFG_ENV_IS_IN_FLASH
	209
	210	#ifdef CFG_ENV_IS_IN_FLASH
	211	#define CFG_ENV_SECT_SIZE 0x20000
	212	#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
	213	#endif /* CFG_ENV_IS_IN_FLASH */
	214
	215	#define CFG_DEFAULT_IMMR 0x00010000
	216
	217	#define CFG_IMMR 0xF0000000
	218
	219	#define CFG_INIT_RAM_ADDR CFG_IMMR
	220	#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
	221	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	222	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	223	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	224
	225	/* Hard reset configuration word */
	226	#define CFG_HRCW_MASTER 0x0C40025A /* Not used - provided by FPGA */
	227	/* No slaves */
	228	#define CFG_HRCW_SLAVE1 0
	229	#define CFG_HRCW_SLAVE2 0
	230	#define CFG_HRCW_SLAVE3 0
	231	#define CFG_HRCW_SLAVE4 0
	232	#define CFG_HRCW_SLAVE5 0
	233	#define CFG_HRCW_SLAVE6 0
	234	#define CFG_HRCW_SLAVE7 0
	235
	236	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	237	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	238
	239	#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
	240	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	241
	242	#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
	243	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	244	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	245	#endif
	246
	247	#define CFG_HID0_INIT 0
	248	#define CFG_HID0_FINAL (HID0_ICE \| HID0_IFEM \| HID0_ABE)
	249
	250	#define CFG_HID2 0
	251
	252	#define CFG_SIUMCR 0x01240200
	253	#define CFG_SYPCR 0xFFFF0683
	254	#define CFG_BCR 0x00000000
	255	#define CFG_SCCR SCCR_DFBRG01
	256
	257	#define CFG_RMR RMR_CSRE
	258	#define CFG_TMCNTSC (TMCNTSC_SEC\|TMCNTSC_ALR\|TMCNTSC_TCF\|TMCNTSC_TCE)
	259	#define CFG_PISCR (PISCR_PS\|PISCR_PTF\|PISCR_PTE)
	260	#define CFG_RCCR 0
	261
	262	#define CFG_MPTPR 0x1300
	263	#define CFG_PSDMR 0x82672522
	264	#define CFG_PSRT 0x4B
	265
	266	#define CFG_SDRAM_BASE 0x00000000
	267	#define CFG_SDRAM_BR (CFG_SDRAM_BASE \| 0x00001841)
	268	#define CFG_SDRAM_OR 0xFF0030C0
	269
	270	#define CFG_BR0_PRELIM (CFG_FLASH_BASE \| 0x00001801)
	271	#define CFG_OR0_PRELIM 0xFF8008C2
	272	#define CFG_BR2_PRELIM (CFG_BCSR \| 0x00000801)
	273	#define CFG_OR2_PRELIM 0xFFF00864
	274
	275	#define CFG_RESET_ADDRESS 0xC0000000
	276
	277	#endif /* __CONFIG_H */
	278