Eric Lee / smarc-uboot

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Commit f901a83b70a586cef89682843e2d16d6c7b2288a

Authored by Wolfgang Denk
1 parent 5633796c09
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Add support for ep8248 board 

Patch by Yuli Barcohen, 12 Dec 2004

Minor code cleanup.

Showing 13 changed files with 1468 additions and 706 deletions Side-by-side Diff

... ... @@ -2,12 +2,17 @@
2 2 Changes for U-Boot 1.1.3:
3 3 ======================================================================
4 4  
  5 +* Add support for ep8248 board
  6 + Patch by Yuli Barcohen, 12 Dec 2004
  7 +
  8 + Minor code cleanup.
  9 +
5 10 * Fix baudrate setting for KGDB on MPC8260
6 11 Patch by HoJin, 11 Dec 2004
7 12  
8 13 * Fix 'mii help' text formatting
9 14 Patch by Cory Tusar, 10 Dec 2004
10   -
  15 +
11 16 * Fix return code of NFS command
12 17 Patch by Hiroshi Ito, 11 Dec 2004
13 18  
... ... @@ -32,6 +32,7 @@
32 32 Yuli Barcohen <yuli@arabellasw.com>
33 33  
34 34 Adder MPC87x/MPC852T
  35 + ep8248 MPC8248
35 36 ISPAN MPC8260
36 37 MPC8260ADS MPC826x/MPC827x/MPC8280
37 38 Rattler MPC8248
... ... @@ -99,12 +99,12 @@
99 99  
100 100 LIST_8260=" \
101 101 atc cogent_mpc8260 CPU86 CPU87 \
102   - ep8260 gw8260 hymod IPHASE4539 \
103   - ISPAN MPC8260ADS MPC8266ADS MPC8272ADS \
104   - PM826 PM828 ppmc8260 Rattler8248 \
105   - RPXsuper rsdproto sacsng sbc8260 \
106   - SCM TQM8260_AC TQM8260_AD TQM8260_AE \
107   - ZPC1900 \
  102 + ep8248 ep8260 gw8260 hymod \
  103 + IPHASE4539 ISPAN MPC8260ADS MPC8266ADS \
  104 + MPC8272ADS PM826 PM828 ppmc8260 \
  105 + Rattler8248 RPXsuper rsdproto sacsng \
  106 + sbc8260 SCM TQM8260_AC TQM8260_AD \
  107 + TQM8260_AE ZPC1900 \
108 108 "
109 109  
110 110 #########################################################################
... ... @@ -997,6 +997,10 @@
997 997 fi; \
998 998 echo "export CONFIG_BOOT_ROM" >> config.mk;
999 999  
  1000 +ep8248_config \
  1001 +ep8248E_config : unconfig
  1002 + @./mkconfig ep8248 ppc mpc8260 ep8248
  1003 +
1000 1004 ep8260_config: unconfig
1001 1005 @./mkconfig $(@:_config=) ppc mpc8260 ep8260
1002 1006  
board/amcc/bamboo/bamboo.c
Diff comments   View file @ f901a83
Changes suppressed. Click to show
... ... @@ -12,7 +12,7 @@
12 12 *
13 13 * This program is distributed in the hope that it will be useful,
14 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 16 * GNU General Public License for more details.
17 17 *
18 18 * You should have received a copy of the GNU General Public License
19 19  
20 20  
21 21  
22 22  
23 23  
24 24  
25 25  
26 26  
27 27  
28 28  
29 29  
30 30  
31 31  
32 32  
... ... @@ -32,180 +32,192 @@
32 32  
33 33 gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
34 34 #if 0
35   -{ /* GPIO Alternate1 Alternate2 Alternate3 */
36   - {
37   - /* GPIO Core 0 */
38   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */
39   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */
40   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */
41   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */
42   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */
43   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
44   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */
45   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */
46   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */
47   - { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */
48   - { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
49   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
50   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
51   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
52   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
53   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
54   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
55   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
56   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
57   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
58   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
59   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
60   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
61   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
62   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
63   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
64   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */
65   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */
66   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */
67   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */
68   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */
69   - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */
70   - },
71   - {
72   - /* GPIO Core 1 */
73   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */
74   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */
75   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */
76   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */
77   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */
78   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */
79   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */
80   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */
81   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */
82   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */
83   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
84   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
85   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */
86   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */
87   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */
88   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */
89   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */
90   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
91   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */
92   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */
93   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */
94   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */
95   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */
96   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */
97   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */
98   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */
99   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */
100   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */
101   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */
102   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */
103   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */
104   - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
105   - }
  35 +{ /* GPIO Alternate1 Alternate2 Alternate3 */
  36 + {
  37 + /* GPIO Core 0 */
  38 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */
  39 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */
  40 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */
  41 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */
  42 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */
  43 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
  44 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */
  45 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */
  46 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */
  47 + { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */
  48 + { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
  49 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
  50 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
  51 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
  52 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
  53 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
  54 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
  55 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
  56 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
  57 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
  58 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
  59 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
  60 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
  61 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
  62 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
  63 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
  64 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */
  65 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */
  66 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */
  67 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */
  68 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */
  69 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */
  70 + },
  71 + {
  72 + /* GPIO Core 1 */
  73 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */
  74 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */
  75 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */
  76 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */
  77 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */
  78 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */
  79 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */
  80 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */
  81 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */
  82 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */
  83 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
  84 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
  85 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */
  86 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */
  87 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */
  88 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */
  89 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */
  90 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
  91 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */
  92 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */
  93 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */
  94 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */
  95 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */
  96 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */
  97 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */
  98 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */
  99 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */
  100 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */
  101 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */
  102 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */
  103 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */
  104 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
  105 + }
106 106 };
107 107 #endif
108 108  
109 109 /*----------------------------------------------------------------------------+
110 110 | EBC Devices Characteristics
111   - | Peripheral Bank Access Parameters - EBC0_BnAP
112   - | Peripheral Bank Configuration Register - EBC0_BnCR
  111 + | Peripheral Bank Access Parameters - EBC0_BnAP
  112 + | Peripheral Bank Configuration Register - EBC0_BnCR
113 113 +----------------------------------------------------------------------------*/
114 114 /* Small Flash */
115   -#define EBC0_BNAP_SMALL_FLASH EBC0_BNAP_BME_DISABLED | \
116   - EBC0_BNAP_TWT_ENCODE(6) | \
117   - EBC0_BNAP_CSN_ENCODE(0) | \
118   - EBC0_BNAP_OEN_ENCODE(1) | \
119   - EBC0_BNAP_WBN_ENCODE(1) | \
120   - EBC0_BNAP_WBF_ENCODE(3) | \
121   - EBC0_BNAP_TH_ENCODE(1) | \
122   - EBC0_BNAP_RE_ENABLED | \
123   - EBC0_BNAP_SOR_DELAYED | \
124   - EBC0_BNAP_BEM_WRITEONLY | \
  115 +#define EBC0_BNAP_SMALL_FLASH \
  116 + EBC0_BNAP_BME_DISABLED | \
  117 + EBC0_BNAP_TWT_ENCODE(6) | \
  118 + EBC0_BNAP_CSN_ENCODE(0) | \
  119 + EBC0_BNAP_OEN_ENCODE(1) | \
  120 + EBC0_BNAP_WBN_ENCODE(1) | \
  121 + EBC0_BNAP_WBF_ENCODE(3) | \
  122 + EBC0_BNAP_TH_ENCODE(1) | \
  123 + EBC0_BNAP_RE_ENABLED | \
  124 + EBC0_BNAP_SOR_DELAYED | \
  125 + EBC0_BNAP_BEM_WRITEONLY | \
125 126 EBC0_BNAP_PEN_DISABLED
126 127  
127   -#define EBC0_BNCR_SMALL_FLASH_CS0 EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \
128   - EBC0_BNCR_BS_1MB | \
129   - EBC0_BNCR_BU_RW | \
  128 +#define EBC0_BNCR_SMALL_FLASH_CS0 \
  129 + EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \
  130 + EBC0_BNCR_BS_1MB | \
  131 + EBC0_BNCR_BU_RW | \
130 132 EBC0_BNCR_BW_8BIT
131 133  
132   -#define EBC0_BNCR_SMALL_FLASH_CS4 EBC0_BNCR_BAS_ENCODE(0x87800000) | \
133   - EBC0_BNCR_BS_8MB | \
134   - EBC0_BNCR_BU_RW | \
  134 +#define EBC0_BNCR_SMALL_FLASH_CS4 \
  135 + EBC0_BNCR_BAS_ENCODE(0x87800000) | \
  136 + EBC0_BNCR_BS_8MB | \
  137 + EBC0_BNCR_BU_RW | \
135 138 EBC0_BNCR_BW_16BIT
136 139  
137 140 /* Large Flash or SRAM */
138   -#define EBC0_BNAP_LARGE_FLASH_OR_SRAM EBC0_BNAP_BME_DISABLED | \
139   - EBC0_BNAP_TWT_ENCODE(8) | \
140   - EBC0_BNAP_CSN_ENCODE(0) | \
141   - EBC0_BNAP_OEN_ENCODE(1) | \
142   - EBC0_BNAP_WBN_ENCODE(1) | \
143   - EBC0_BNAP_WBF_ENCODE(1) | \
144   - EBC0_BNAP_TH_ENCODE(2) | \
145   - EBC0_BNAP_SOR_DELAYED | \
146   - EBC0_BNAP_BEM_RW | \
  141 +#define EBC0_BNAP_LARGE_FLASH_OR_SRAM \
  142 + EBC0_BNAP_BME_DISABLED | \
  143 + EBC0_BNAP_TWT_ENCODE(8) | \
  144 + EBC0_BNAP_CSN_ENCODE(0) | \
  145 + EBC0_BNAP_OEN_ENCODE(1) | \
  146 + EBC0_BNAP_WBN_ENCODE(1) | \
  147 + EBC0_BNAP_WBF_ENCODE(1) | \
  148 + EBC0_BNAP_TH_ENCODE(2) | \
  149 + EBC0_BNAP_SOR_DELAYED | \
  150 + EBC0_BNAP_BEM_RW | \
147 151 EBC0_BNAP_PEN_DISABLED
148 152  
149   -#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 EBC0_BNCR_BAS_ENCODE(0xFF800000) | \
150   - EBC0_BNCR_BS_8MB | \
151   - EBC0_BNCR_BU_RW | \
  153 +#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \
  154 + EBC0_BNCR_BAS_ENCODE(0xFF800000) | \
  155 + EBC0_BNCR_BS_8MB | \
  156 + EBC0_BNCR_BU_RW | \
152 157 EBC0_BNCR_BW_16BIT
153 158  
154 159  
155   -#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 EBC0_BNCR_BAS_ENCODE(0x87800000) | \
156   - EBC0_BNCR_BS_8MB | \
157   - EBC0_BNCR_BU_RW | \
  160 +#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \
  161 + EBC0_BNCR_BAS_ENCODE(0x87800000) | \
  162 + EBC0_BNCR_BS_8MB | \
  163 + EBC0_BNCR_BU_RW | \
158 164 EBC0_BNCR_BW_16BIT
159 165  
160 166 /* NVRAM - FPGA */
161   -#define EBC0_BNAP_NVRAM_FPGA EBC0_BNAP_BME_DISABLED | \
162   - EBC0_BNAP_TWT_ENCODE(9) | \
163   - EBC0_BNAP_CSN_ENCODE(0) | \
164   - EBC0_BNAP_OEN_ENCODE(1) | \
165   - EBC0_BNAP_WBN_ENCODE(1) | \
166   - EBC0_BNAP_WBF_ENCODE(0) | \
167   - EBC0_BNAP_TH_ENCODE(2) | \
168   - EBC0_BNAP_RE_ENABLED | \
169   - EBC0_BNAP_SOR_DELAYED | \
170   - EBC0_BNAP_BEM_WRITEONLY | \
  167 +#define EBC0_BNAP_NVRAM_FPGA \
  168 + EBC0_BNAP_BME_DISABLED | \
  169 + EBC0_BNAP_TWT_ENCODE(9) | \
  170 + EBC0_BNAP_CSN_ENCODE(0) | \
  171 + EBC0_BNAP_OEN_ENCODE(1) | \
  172 + EBC0_BNAP_WBN_ENCODE(1) | \
  173 + EBC0_BNAP_WBF_ENCODE(0) | \
  174 + EBC0_BNAP_TH_ENCODE(2) | \
  175 + EBC0_BNAP_RE_ENABLED | \
  176 + EBC0_BNAP_SOR_DELAYED | \
  177 + EBC0_BNAP_BEM_WRITEONLY | \
171 178 EBC0_BNAP_PEN_DISABLED
172 179  
173   -#define EBC0_BNCR_NVRAM_FPGA_CS5 EBC0_BNCR_BAS_ENCODE(0x80000000) | \
174   - EBC0_BNCR_BS_1MB | \
175   - EBC0_BNCR_BU_RW | \
  180 +#define EBC0_BNCR_NVRAM_FPGA_CS5 \
  181 + EBC0_BNCR_BAS_ENCODE(0x80000000) | \
  182 + EBC0_BNCR_BS_1MB | \
  183 + EBC0_BNCR_BU_RW | \
176 184 EBC0_BNCR_BW_8BIT
177 185  
178 186 /* Nand Flash */
179   -#define EBC0_BNAP_NAND_FLASH EBC0_BNAP_BME_DISABLED | \
180   - EBC0_BNAP_TWT_ENCODE(3) | \
181   - EBC0_BNAP_CSN_ENCODE(0) | \
182   - EBC0_BNAP_OEN_ENCODE(0) | \
183   - EBC0_BNAP_WBN_ENCODE(0) | \
184   - EBC0_BNAP_WBF_ENCODE(0) | \
185   - EBC0_BNAP_TH_ENCODE(1) | \
186   - EBC0_BNAP_RE_ENABLED | \
187   - EBC0_BNAP_SOR_NOT_DELAYED | \
188   - EBC0_BNAP_BEM_RW | \
  187 +#define EBC0_BNAP_NAND_FLASH \
  188 + EBC0_BNAP_BME_DISABLED | \
  189 + EBC0_BNAP_TWT_ENCODE(3) | \
  190 + EBC0_BNAP_CSN_ENCODE(0) | \
  191 + EBC0_BNAP_OEN_ENCODE(0) | \
  192 + EBC0_BNAP_WBN_ENCODE(0) | \
  193 + EBC0_BNAP_WBF_ENCODE(0) | \
  194 + EBC0_BNAP_TH_ENCODE(1) | \
  195 + EBC0_BNAP_RE_ENABLED | \
  196 + EBC0_BNAP_SOR_NOT_DELAYED | \
  197 + EBC0_BNAP_BEM_RW | \
189 198 EBC0_BNAP_PEN_DISABLED
190 199  
191 200  
192   -#define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000
  201 +#define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000
193 202  
194 203 /* NAND0 */
195   -#define EBC0_BNCR_NAND_FLASH_CS1 EBC0_BNCR_BAS_ENCODE(0x90000000) | \
196   - EBC0_BNCR_BS_1MB | \
197   - EBC0_BNCR_BU_RW | \
  204 +#define EBC0_BNCR_NAND_FLASH_CS1 \
  205 + EBC0_BNCR_BAS_ENCODE(0x90000000) | \
  206 + EBC0_BNCR_BS_1MB | \
  207 + EBC0_BNCR_BU_RW | \
198 208 EBC0_BNCR_BW_32BIT
199 209 /* NAND1 - Bank2 */
200   -#define EBC0_BNCR_NAND_FLASH_CS2 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
201   - EBC0_BNCR_BS_1MB | \
202   - EBC0_BNCR_BU_RW | \
  210 +#define EBC0_BNCR_NAND_FLASH_CS2 \
  211 + EBC0_BNCR_BAS_ENCODE(0x94000000) | \
  212 + EBC0_BNCR_BS_1MB | \
  213 + EBC0_BNCR_BU_RW | \
203 214 EBC0_BNCR_BW_32BIT
204 215  
205 216 /* NAND1 - Bank3 */
206   -#define EBC0_BNCR_NAND_FLASH_CS3 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
207   - EBC0_BNCR_BS_1MB | \
208   - EBC0_BNCR_BU_RW | \
  217 +#define EBC0_BNCR_NAND_FLASH_CS3 \
  218 + EBC0_BNCR_BAS_ENCODE(0x94000000) | \
  219 + EBC0_BNCR_BS_1MB | \
  220 + EBC0_BNCR_BU_RW | \
209 221 EBC0_BNCR_BW_32BIT
210 222  
211 223 int board_early_init_f(void)
212 224  
213 225  
... ... @@ -289,18 +301,18 @@
289 301 * fixed_sdram_init -- Bamboo has one bank onboard sdram (plus DIMM)
290 302 *
291 303 * Fixed memory is composed of :
292   - * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
293   - * 13 row add bits, 10 column add bits (but 12 row used only).
294   - * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
295   - * 12 row add bits, 10 column add bits.
296   - * Prepare a subset (only the used ones) of SPD data
  304 + * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
  305 + * 13 row add bits, 10 column add bits (but 12 row used only).
  306 + * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
  307 + * 12 row add bits, 10 column add bits.
  308 + * Prepare a subset (only the used ones) of SPD data
297 309 *
298   - * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
299   - * the corresponding bank is divided by 2 due to number of Row addresses
300   - * 12 in the ECC module
  310 + * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
  311 + * the corresponding bank is divided by 2 due to number of Row addresses
  312 + * 12 in the ECC module
301 313 *
302   - * Assumes: 64 MB, ECC, non-registered
303   - * PLB @ 133 MHz
  314 + * Assumes: 64 MB, ECC, non-registered
  315 + * PLB @ 133 MHz
304 316 *
305 317 ************************************************************************/
306 318 void fixed_sdram_init(void)
... ... @@ -469,7 +481,7 @@
469 481 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
470 482  
471 483 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
472   - out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
  484 + out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
473 485 out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
474 486 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
475 487 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
... ... @@ -593,7 +605,7 @@
593 605 {
594 606 unsigned long sdr0_pstrp0, sdr0_sdstp1;
595 607 unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
596   - int computed_boot_device = BOOT_DEVICE_UNKNOWN;
  608 + int computed_boot_device = BOOT_DEVICE_UNKNOWN;
597 609 unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
598 610 unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
599 611 unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
... ... @@ -666,8 +678,8 @@
666 678 /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
667 679 /* Read Serial Device Strap Register1 in PPC440EP */
668 680 mfsdr(sdr_sdstp1, sdr0_sdstp1);
669   - boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
670   - ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
  681 + boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
  682 + ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
671 683  
672 684 switch(boot_selection) {
673 685 case SDR0_SDSTP1_BOOT_SEL_EBC:
... ... @@ -739,8 +751,8 @@
739 751 /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
740 752 /* Read Serial Device Strap Register1 in PPC440EP */
741 753 mfsdr(sdr_sdstp1, sdr0_sdstp1);
742   - boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
743   - ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
  754 + boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
  755 + ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
744 756  
745 757 switch(boot_selection) {
746 758 case SDR0_SDSTP1_BOOT_SEL_EBC:
747 759  
748 760  
749 761  
750 762  
... ... @@ -774,42 +786,42 @@
774 786 | Resulting EBC init will be among following configurations :
775 787 |
776 788 | - Boot from EBC 8bits => boot from SMALL FLASH selected
777   - | EBC-CS0 = Small Flash
778   - | EBC-CS1,2,3 = NAND Flash or
779   - | Exp.Slot depending on Soft Config
780   - | EBC-CS4 = SRAM/Large Flash or
781   - | Large Flash/SRAM depending on jumpers
782   - | EBC-CS5 = NVRAM / EPLD
  789 + | EBC-CS0 = Small Flash
  790 + | EBC-CS1,2,3 = NAND Flash or
  791 + | Exp.Slot depending on Soft Config
  792 + | EBC-CS4 = SRAM/Large Flash or
  793 + | Large Flash/SRAM depending on jumpers
  794 + | EBC-CS5 = NVRAM / EPLD
783 795 |
784 796 | - Boot from EBC 16bits => boot from Large Flash or SRAM selected
785   - | EBC-CS0 = SRAM/Large Flash or
786   - | Large Flash/SRAM depending on jumpers
787   - | EBC-CS1,2,3 = NAND Flash or
788   - | Exp.Slot depending on Software Configuration
789   - | EBC-CS4 = Small Flash
790   - | EBC-CS5 = NVRAM / EPLD
  797 + | EBC-CS0 = SRAM/Large Flash or
  798 + | Large Flash/SRAM depending on jumpers
  799 + | EBC-CS1,2,3 = NAND Flash or
  800 + | Exp.Slot depending on Software Configuration
  801 + | EBC-CS4 = Small Flash
  802 + | EBC-CS5 = NVRAM / EPLD
791 803 |
792 804 | - Boot from NAND Flash
793   - | EBC-CS0 = NAND Flash0
794   - | EBC-CS1,2,3 = NAND Flash1
795   - | EBC-CS4 = SRAM/Large Flash or
796   - | Large Flash/SRAM depending on jumpers
797   - | EBC-CS5 = NVRAM / EPLD
  805 + | EBC-CS0 = NAND Flash0
  806 + | EBC-CS1,2,3 = NAND Flash1
  807 + | EBC-CS4 = SRAM/Large Flash or
  808 + | Large Flash/SRAM depending on jumpers
  809 + | EBC-CS5 = NVRAM / EPLD
798 810 |
799 811 | - Boot from PCI
800   - | EBC-CS0 = ...
801   - | EBC-CS1,2,3 = NAND Flash or
802   - | Exp.Slot depending on Software Configuration
803   - | EBC-CS4 = SRAM/Large Flash or
804   - | Large Flash/SRAM or
805   - | Small Flash depending on jumpers
806   - | EBC-CS5 = NVRAM / EPLD
  812 + | EBC-CS0 = ...
  813 + | EBC-CS1,2,3 = NAND Flash or
  814 + | Exp.Slot depending on Software Configuration
  815 + | EBC-CS4 = SRAM/Large Flash or
  816 + | Large Flash/SRAM or
  817 + | Small Flash depending on jumpers
  818 + | EBC-CS5 = NVRAM / EPLD
807 819 |
808 820 +-------------------------------------------------------------------------*/
809 821  
810 822 switch(computed_boot_device) {
811 823 /*------------------------------------------------------------------------- */
812   - case BOOT_FROM_SMALL_FLASH:
  824 + case BOOT_FROM_SMALL_FLASH:
813 825 /*------------------------------------------------------------------------- */
814 826 ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
815 827 ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
... ... @@ -840,7 +852,7 @@
840 852 break;
841 853  
842 854 /*------------------------------------------------------------------------- */
843   - case BOOT_FROM_LARGE_FLASH_OR_SRAM:
  855 + case BOOT_FROM_LARGE_FLASH_OR_SRAM:
844 856 /*------------------------------------------------------------------------- */
845 857 ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
846 858 ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
... ... @@ -867,7 +879,7 @@
867 879 break;
868 880  
869 881 /*------------------------------------------------------------------------- */
870   - case BOOT_FROM_NAND_FLASH0:
  882 + case BOOT_FROM_NAND_FLASH0:
871 883 /*------------------------------------------------------------------------- */
872 884 ebc0_cs0_bnap_value = 0;
873 885 ebc0_cs0_bncr_value = 0;
... ... @@ -886,7 +898,7 @@
886 898 break;
887 899  
888 900 /*------------------------------------------------------------------------- */
889   - case BOOT_FROM_PCI:
  901 + case BOOT_FROM_PCI:
890 902 /*------------------------------------------------------------------------- */
891 903 ebc0_cs0_bnap_value = 0;
892 904 ebc0_cs0_bncr_value = 0;
... ... @@ -922,7 +934,7 @@
922 934 break;
923 935  
924 936 /*------------------------------------------------------------------------- */
925   - case BOOT_DEVICE_UNKNOWN:
  937 + case BOOT_DEVICE_UNKNOWN:
926 938 /*------------------------------------------------------------------------- */
927 939 /* Error */
928 940 break;
... ... @@ -934,16 +946,16 @@
934 946 | Initialize EBC CONFIG
935 947 +-------------------------------------------------------------------------*/
936 948 mtdcr(ebccfga, xbcfg);
937   - mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN |
938   - EBC0_CFG_PTD_ENABLED |
939   - EBC0_CFG_RTC_2048PERCLK |
940   - EBC0_CFG_EMPL_LOW |
941   - EBC0_CFG_EMPH_LOW |
942   - EBC0_CFG_CSTC_DRIVEN |
943   - EBC0_CFG_BPF_ONEDW |
944   - EBC0_CFG_EMS_8BIT |
945   - EBC0_CFG_PME_DISABLED |
946   - EBC0_CFG_PMT_ENCODE(0) );
  949 + mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN |
  950 + EBC0_CFG_PTD_ENABLED |
  951 + EBC0_CFG_RTC_2048PERCLK |
  952 + EBC0_CFG_EMPL_LOW |
  953 + EBC0_CFG_EMPH_LOW |
  954 + EBC0_CFG_CSTC_DRIVEN |
  955 + EBC0_CFG_BPF_ONEDW |
  956 + EBC0_CFG_EMS_8BIT |
  957 + EBC0_CFG_PME_DISABLED |
  958 + EBC0_CFG_PMT_ENCODE(0) );
947 959  
948 960 /*-------------------------------------------------------------------------+
949 961 | Initialize EBC Bank 0-4
950 962  
951 963  
952 964  
... ... @@ -988,17 +1000,17 @@
988 1000  
989 1001 switch(config)
990 1002 {
991   - case ZMII_CONFIGURATION_IS_MII:
  1003 + case ZMII_CONFIGURATION_IS_MII:
992 1004 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
993 1005 break;
994   - case ZMII_CONFIGURATION_IS_RMII:
  1006 + case ZMII_CONFIGURATION_IS_RMII:
995 1007 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
996 1008 break;
997   - case ZMII_CONFIGURATION_IS_SMII:
  1009 + case ZMII_CONFIGURATION_IS_SMII:
998 1010 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
999 1011 break;
1000   - case ZMII_CONFIGURATION_UNKNOWN:
1001   - default:
  1012 + case ZMII_CONFIGURATION_UNKNOWN:
  1013 + default:
1002 1014 break;
1003 1015 }
1004 1016 out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
... ... @@ -1131,7 +1143,7 @@
1131 1143 void uart_selection_in_fpga(uart_config_nb_t uart_config)
1132 1144 {
1133 1145 /* FPGA register */
1134   - unsigned char fpga_selection_3_reg;
  1146 + unsigned char fpga_selection_3_reg;
1135 1147  
1136 1148 /* Read FPGA Reagister */
1137 1149 fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
1138 1150  
1139 1151  
1140 1152  
1141 1153  
1142 1154  
1143 1155  
... ... @@ -1140,43 +1152,43 @@
1140 1152 {
1141 1153 case L1:
1142 1154 /* ----------------------------------------------------------------------- */
1143   - /* L1 configuration: UART0 = 8 pins */
  1155 + /* L1 configuration: UART0 = 8 pins */
1144 1156 /* ----------------------------------------------------------------------- */
1145 1157 /* Configure FPGA */
1146   - fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1147   - fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
  1158 + fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
  1159 + fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
1148 1160 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1149 1161  
1150 1162 break;
1151 1163  
1152 1164 case L2:
1153 1165 /* ----------------------------------------------------------------------- */
1154   - /* L2 configuration: UART0 = 4 pins */
1155   - /* UART1 = 4 pins */
  1166 + /* L2 configuration: UART0 = 4 pins */
  1167 + /* UART1 = 4 pins */
1156 1168 /* ----------------------------------------------------------------------- */
1157 1169 /* Configure FPGA */
1158   - fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1159   - fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
  1170 + fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
  1171 + fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
1160 1172 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1161 1173  
1162 1174 break;
1163 1175  
1164 1176 case L3:
1165 1177 /* ----------------------------------------------------------------------- */
1166   - /* L3 configuration: UART0 = 4 pins */
1167   - /* UART1 = 2 pins */
1168   - /* UART2 = 2 pins */
  1178 + /* L3 configuration: UART0 = 4 pins */
  1179 + /* UART1 = 2 pins */
  1180 + /* UART2 = 2 pins */
1169 1181 /* ----------------------------------------------------------------------- */
1170 1182 /* Configure FPGA */
1171   - fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1172   - fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
  1183 + fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
  1184 + fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
1173 1185 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1174 1186 break;
1175 1187  
1176 1188 case L4:
1177 1189 /* Configure FPGA */
1178   - fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1179   - fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
  1190 + fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
  1191 + fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
1180 1192 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1181 1193  
1182 1194 break;
... ... @@ -1201,7 +1213,7 @@
1201 1213 /* Init GPIO0 */
1202 1214 for(i=0; i<GPIO_MAX; i++)
1203 1215 {
1204   - gpio_tab[GPIO0][i].add = GPIO0_BASE;
  1216 + gpio_tab[GPIO0][i].add = GPIO0_BASE;
1205 1217 gpio_tab[GPIO0][i].in_out = GPIO_DIS;
1206 1218 gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
1207 1219 }
... ... @@ -1209,7 +1221,7 @@
1209 1221 /* Init GPIO1 */
1210 1222 for(i=0; i<GPIO_MAX; i++)
1211 1223 {
1212   - gpio_tab[GPIO1][i].add = GPIO1_BASE;
  1224 + gpio_tab[GPIO1][i].add = GPIO1_BASE;
1213 1225 gpio_tab[GPIO1][i].in_out = GPIO_DIS;
1214 1226 gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
1215 1227 }
1216 1228  
1217 1229  
1218 1230  
1219 1231  
1220 1232  
1221 1233  
... ... @@ -1230,35 +1242,35 @@
1230 1242 | Set UART Configuration in PowerPC440EP
1231 1243 |
1232 1244 | +---------------------------------------------------------------------+
1233   - | | Configuartion | Connector | Nb of pins | Pins | Associated |
1234   - | | Number | Port Name | available | naming | CORE |
  1245 + | | Configuartion | Connector | Nb of pins | Pins | Associated |
  1246 + | | Number | Port Name | available | naming | CORE |
1235 1247 | +-----------------+---------------+------------+--------+-------------+
1236   - | | L1 | Port_A | 8 | UART | UART core 0 |
  1248 + | | L1 | Port_A | 8 | UART | UART core 0 |
1237 1249 | +-----------------+---------------+------------+--------+-------------+
1238   - | | L2 | Port_A | 4 | UART1 | UART core 0 |
1239   - | | (L2D) | Port_B | 4 | UART2 | UART core 1 |
  1250 + | | L2 | Port_A | 4 | UART1 | UART core 0 |
  1251 + | | (L2D) | Port_B | 4 | UART2 | UART core 1 |
1240 1252 | +-----------------+---------------+------------+--------+-------------+
1241   - | | L3 | Port_A | 4 | UART1 | UART core 0 |
1242   - | | (L3D) | Port_B | 2 | UART2 | UART core 1 |
1243   - | | | Port_C | 2 | UART3 | UART core 2 |
  1253 + | | L3 | Port_A | 4 | UART1 | UART core 0 |
  1254 + | | (L3D) | Port_B | 2 | UART2 | UART core 1 |
  1255 + | | | Port_C | 2 | UART3 | UART core 2 |
1244 1256 | +-----------------+---------------+------------+--------+-------------+
1245   - | | | Port_A | 2 | UART1 | UART core 0 |
1246   - | | L4 | Port_B | 2 | UART2 | UART core 1 |
1247   - | | (L4D) | Port_C | 2 | UART3 | UART core 2 |
1248   - | | | Port_D | 2 | UART4 | UART core 3 |
  1257 + | | | Port_A | 2 | UART1 | UART core 0 |
  1258 + | | L4 | Port_B | 2 | UART2 | UART core 1 |
  1259 + | | (L4D) | Port_C | 2 | UART3 | UART core 2 |
  1260 + | | | Port_D | 2 | UART4 | UART core 3 |
1249 1261 | +-----------------+---------------+------------+--------+-------------+
1250 1262 |
1251 1263 | Involved GPIOs
1252 1264 |
1253 1265 | +------------------------------------------------------------------------------+
1254   - | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O |
  1266 + | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O |
1255 1267 | +---------+------------------+-----+-----------------+-----+-------------+-----+
1256   - | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O |
1257   - | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I |
1258   - | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I |
1259   - | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O |
1260   - | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA |
1261   - | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA |
  1268 + | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O |
  1269 + | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I |
  1270 + | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I |
  1271 + | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O |
  1272 + | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA |
  1273 + | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA |
1262 1274 | +------------------------------------------------------------------------------+
1263 1275 |
1264 1276 |
... ... @@ -1270,7 +1282,7 @@
1270 1282 {
1271 1283 case L1:
1272 1284 /* ----------------------------------------------------------------------- */
1273   - /* L1 configuration: UART0 = 8 pins */
  1285 + /* L1 configuration: UART0 = 8 pins */
1274 1286 /* ----------------------------------------------------------------------- */
1275 1287 /* Update GPIO Configuration Table */
1276 1288 gpio_tab[GPIO1][2].in_out = GPIO_IN;
... ... @@ -1295,8 +1307,8 @@
1295 1307  
1296 1308 case L2:
1297 1309 /* ----------------------------------------------------------------------- */
1298   - /* L2 configuration: UART0 = 4 pins */
1299   - /* UART1 = 4 pins */
  1310 + /* L2 configuration: UART0 = 4 pins */
  1311 + /* UART1 = 4 pins */
1300 1312 /* ----------------------------------------------------------------------- */
1301 1313 /* Update GPIO Configuration Table */
1302 1314 gpio_tab[GPIO1][2].in_out = GPIO_IN;
... ... @@ -1321,9 +1333,9 @@
1321 1333  
1322 1334 case L3:
1323 1335 /* ----------------------------------------------------------------------- */
1324   - /* L3 configuration: UART0 = 4 pins */
1325   - /* UART1 = 2 pins */
1326   - /* UART2 = 2 pins */
  1336 + /* L3 configuration: UART0 = 4 pins */
  1337 + /* UART1 = 2 pins */
  1338 + /* UART2 = 2 pins */
1327 1339 /* ----------------------------------------------------------------------- */
1328 1340 /* Update GPIO Configuration Table */
1329 1341 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
... ... @@ -1348,10 +1360,10 @@
1348 1360  
1349 1361 case L4:
1350 1362 /* ----------------------------------------------------------------------- */
1351   - /* L4 configuration: UART0 = 2 pins */
1352   - /* UART1 = 2 pins */
1353   - /* UART2 = 2 pins */
1354   - /* UART3 = 2 pins */
  1363 + /* L4 configuration: UART0 = 2 pins */
  1364 + /* UART1 = 2 pins */
  1365 + /* UART2 = 2 pins */
  1366 + /* UART3 = 2 pins */
1355 1367 /* ----------------------------------------------------------------------- */
1356 1368 /* Update GPIO Configuration Table */
1357 1369 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1358 1370  
1359 1371  
... ... @@ -1394,15 +1406,15 @@
1394 1406 +----------------------------------------------------------------------------*/
1395 1407 void update_ndfc_ios(void)
1396 1408 {
1397   - /* Update GPIO Configuration Table */
1398   - gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */
1399   - gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
  1409 + /* Update GPIO Configuration Table */
  1410 + gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */
  1411 + gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
1400 1412  
1401 1413 #if 0
1402   - gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */
  1414 + gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */
1403 1415 gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1404 1416  
1405   - gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */
  1417 + gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */
1406 1418 gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1407 1419 #endif
1408 1420 }
1409 1421  
1410 1422  
1411 1423  
1412 1424  
1413 1425  
1414 1426  
1415 1427  
1416 1428  
1417 1429  
1418 1430  
1419 1431  
1420 1432  
1421 1433  
... ... @@ -1412,48 +1424,48 @@
1412 1424 +----------------------------------------------------------------------------*/
1413 1425 void update_zii_ios(void)
1414 1426 {
1415   - /* Update GPIO Configuration Table */
1416   - gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */
1417   - gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
  1427 + /* Update GPIO Configuration Table */
  1428 + gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */
  1429 + gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
1418 1430  
1419   - gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */
1420   - gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
  1431 + gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */
  1432 + gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
1421 1433  
1422   - gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */
1423   - gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
  1434 + gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */
  1435 + gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
1424 1436  
1425   - gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */
1426   - gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
  1437 + gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */
  1438 + gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
1427 1439  
1428   - gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */
1429   - gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
  1440 + gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */
  1441 + gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
1430 1442  
1431   - gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */
1432   - gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
  1443 + gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */
  1444 + gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
1433 1445  
1434   - gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */
1435   - gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
  1446 + gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */
  1447 + gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
1436 1448  
1437   - gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */
1438   - gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
  1449 + gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */
  1450 + gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
1439 1451  
1440   - gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */
1441   - gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
  1452 + gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */
  1453 + gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
1442 1454  
1443   - gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */
1444   - gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
  1455 + gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */
  1456 + gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
1445 1457  
1446   - gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */
1447   - gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
  1458 + gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */
  1459 + gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
1448 1460  
1449   - gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */
1450   - gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
  1461 + gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */
  1462 + gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
1451 1463  
1452   - gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */
1453   - gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
  1464 + gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */
  1465 + gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
1454 1466  
1455   - gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */
1456   - gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
  1467 + gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */
  1468 + gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
1457 1469  
1458 1470 }
1459 1471  
1460 1472  
1461 1473  
1462 1474  
... ... @@ -1462,16 +1474,16 @@
1462 1474 +----------------------------------------------------------------------------*/
1463 1475 void update_uic_0_3_irq_ios(void)
1464 1476 {
1465   - gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */
  1477 + gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */
1466 1478 gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
1467 1479  
1468   - gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */
  1480 + gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */
1469 1481 gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
1470 1482  
1471   - gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */
  1483 + gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */
1472 1484 gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
1473 1485  
1474   - gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */
  1486 + gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */
1475 1487 gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
1476 1488 }
1477 1489  
1478 1490  
1479 1491  
1480 1492  
1481 1493  
... ... @@ -1480,19 +1492,19 @@
1480 1492 +----------------------------------------------------------------------------*/
1481 1493 void update_uic_4_9_irq_ios(void)
1482 1494 {
1483   - gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */
  1495 + gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */
1484 1496 gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
1485 1497  
1486   - gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */
  1498 + gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */
1487 1499 gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
1488 1500  
1489   - gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */
  1501 + gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */
1490 1502 gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
1491 1503  
1492   - gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */
  1504 + gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */
1493 1505 gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
1494 1506  
1495   - gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */
  1507 + gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */
1496 1508 gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
1497 1509 }
1498 1510  
1499 1511  
1500 1512  
1501 1513  
1502 1514  
... ... @@ -1501,19 +1513,19 @@
1501 1513 +----------------------------------------------------------------------------*/
1502 1514 void update_dma_a_b_ios(void)
1503 1515 {
1504   - gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */
  1516 + gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */
1505 1517 gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
1506 1518  
1507   - gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */
  1519 + gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */
1508 1520 gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
1509 1521  
1510   - gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */
  1522 + gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */
1511 1523 gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
1512 1524  
1513   - gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */
  1525 + gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */
1514 1526 gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
1515 1527  
1516   - gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */
  1528 + gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */
1517 1529 gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
1518 1530 }
1519 1531  
1520 1532  
1521 1533  
1522 1534  
1523 1535  
1524 1536  
... ... @@ -1522,22 +1534,22 @@
1522 1534 +----------------------------------------------------------------------------*/
1523 1535 void update_dma_c_d_ios(void)
1524 1536 {
1525   - gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */
  1537 + gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */
1526 1538 gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
1527 1539  
1528   - gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */
  1540 + gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */
1529 1541 gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
1530 1542  
1531   - gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */
  1543 + gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */
1532 1544 gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
1533 1545  
1534   - gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */
  1546 + gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */
1535 1547 gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
1536 1548  
1537   - gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */
  1549 + gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */
1538 1550 gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
1539 1551  
1540   - gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */
  1552 + gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */
1541 1553 gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
1542 1554  
1543 1555 }
1544 1556  
1545 1557  
1546 1558  
... ... @@ -1547,16 +1559,16 @@
1547 1559 +----------------------------------------------------------------------------*/
1548 1560 void update_ebc_master_ios(void)
1549 1561 {
1550   - gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */
  1562 + gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */
1551 1563 gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
1552 1564  
1553   - gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
  1565 + gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
1554 1566 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1555 1567  
1556   - gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */
  1568 + gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */
1557 1569 gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
1558 1570  
1559   - gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */
  1571 + gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */
1560 1572 gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
1561 1573 }
1562 1574  
1563 1575  
1564 1576  
1565 1577  
1566 1578  
1567 1579  
1568 1580  
1569 1581  
... ... @@ -1565,28 +1577,28 @@
1565 1577 +----------------------------------------------------------------------------*/
1566 1578 void update_usb2_device_ios(void)
1567 1579 {
1568   - gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */
  1580 + gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */
1569 1581 gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
1570 1582  
1571   - gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */
  1583 + gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */
1572 1584 gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
1573 1585  
1574   - gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */
  1586 + gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */
1575 1587 gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
1576 1588  
1577   - gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */
  1589 + gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */
1578 1590 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
1579 1591  
1580   - gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */
  1592 + gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */
1581 1593 gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
1582 1594  
1583   - gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */
  1595 + gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */
1584 1596 gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
1585 1597  
1586   - gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */
  1598 + gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */
1587 1599 gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
1588 1600  
1589   - gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */
  1601 + gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */
1590 1602 gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
1591 1603  
1592 1604 }
... ... @@ -1596,7 +1608,7 @@
1596 1608 +----------------------------------------------------------------------------*/
1597 1609 void update_pci_patch_ios(void)
1598 1610 {
1599   - gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
  1611 + gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
1600 1612 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1601 1613 }
1602 1614  
1603 1615  
1604 1616  
1605 1617  
... ... @@ -1701,22 +1713,22 @@
1701 1713 }
1702 1714  
1703 1715 /* L4 Selection */
1704   - *(core_select_P+UART_CORE0) = CORE_SELECTED;
1705   - *(core_select_P+UART_CORE1) = CORE_SELECTED;
1706   - *(core_select_P+UART_CORE2) = CORE_SELECTED;
1707   - *(core_select_P+UART_CORE3) = CORE_SELECTED;
  1716 + *(core_select_P+UART_CORE0) = CORE_SELECTED;
  1717 + *(core_select_P+UART_CORE1) = CORE_SELECTED;
  1718 + *(core_select_P+UART_CORE2) = CORE_SELECTED;
  1719 + *(core_select_P+UART_CORE3) = CORE_SELECTED;
1708 1720  
1709 1721 /* RMII Selection */
1710   - *(core_select_P+RMII_SEL) = CORE_SELECTED;
  1722 + *(core_select_P+RMII_SEL) = CORE_SELECTED;
1711 1723  
1712 1724 /* External Interrupt 0-9 selection */
1713   - *(core_select_P+UIC_0_3) = CORE_SELECTED;
1714   - *(core_select_P+UIC_4_9) = CORE_SELECTED;
  1725 + *(core_select_P+UIC_0_3) = CORE_SELECTED;
  1726 + *(core_select_P+UIC_4_9) = CORE_SELECTED;
1715 1727  
1716   - *(core_select_P+SCP_CORE) = CORE_SELECTED;
1717   - *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED;
1718   - *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED;
1719   - *(core_select_P+USB1_DEVICE) = CORE_SELECTED;
  1728 + *(core_select_P+SCP_CORE) = CORE_SELECTED;
  1729 + *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED;
  1730 + *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED;
  1731 + *(core_select_P+USB1_DEVICE) = CORE_SELECTED;
1720 1732  
1721 1733 *config_val_P = CONFIG_IS_VALID;
1722 1734  
... ... @@ -1733,28 +1745,28 @@
1733 1745 /* Create Core Selection Table */
1734 1746 core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
1735 1747 {
1736   - CORE_NOT_SELECTED, /* IIC_CORE, */
1737   - CORE_NOT_SELECTED, /* SPC_CORE, */
1738   - CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */
1739   - CORE_NOT_SELECTED, /* UIC_4_9, */
1740   - CORE_NOT_SELECTED, /* USB2_HOST, */
1741   - CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */
1742   - CORE_NOT_SELECTED, /* USB2_DEVICE, */
1743   - CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */
1744   - CORE_NOT_SELECTED, /* USB1_DEVICE, */
1745   - CORE_NOT_SELECTED, /* EBC_MASTER, */
1746   - CORE_NOT_SELECTED, /* NAND_FLASH, */
1747   - CORE_NOT_SELECTED, /* UART_CORE0, */
1748   - CORE_NOT_SELECTED, /* UART_CORE1, */
1749   - CORE_NOT_SELECTED, /* UART_CORE2, */
1750   - CORE_NOT_SELECTED, /* UART_CORE3, */
1751   - CORE_NOT_SELECTED, /* MII_SEL, */
1752   - CORE_NOT_SELECTED, /* RMII_SEL, */
1753   - CORE_NOT_SELECTED, /* SMII_SEL, */
1754   - CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */
1755   - CORE_NOT_SELECTED, /* UIC_0_3 */
1756   - CORE_NOT_SELECTED, /* USB1_HOST */
1757   - CORE_NOT_SELECTED /* PCI_PATCH */
  1748 + CORE_NOT_SELECTED, /* IIC_CORE, */
  1749 + CORE_NOT_SELECTED, /* SPC_CORE, */
  1750 + CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */
  1751 + CORE_NOT_SELECTED, /* UIC_4_9, */
  1752 + CORE_NOT_SELECTED, /* USB2_HOST, */
  1753 + CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */
  1754 + CORE_NOT_SELECTED, /* USB2_DEVICE, */
  1755 + CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */
  1756 + CORE_NOT_SELECTED, /* USB1_DEVICE, */
  1757 + CORE_NOT_SELECTED, /* EBC_MASTER, */
  1758 + CORE_NOT_SELECTED, /* NAND_FLASH, */
  1759 + CORE_NOT_SELECTED, /* UART_CORE0, */
  1760 + CORE_NOT_SELECTED, /* UART_CORE1, */
  1761 + CORE_NOT_SELECTED, /* UART_CORE2, */
  1762 + CORE_NOT_SELECTED, /* UART_CORE3, */
  1763 + CORE_NOT_SELECTED, /* MII_SEL, */
  1764 + CORE_NOT_SELECTED, /* RMII_SEL, */
  1765 + CORE_NOT_SELECTED, /* SMII_SEL, */
  1766 + CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */
  1767 + CORE_NOT_SELECTED, /* UIC_0_3 */
  1768 + CORE_NOT_SELECTED, /* USB1_HOST */
  1769 + CORE_NOT_SELECTED /* PCI_PATCH */
1758 1770 };
1759 1771  
1760 1772  
... ... @@ -1773,9 +1785,9 @@
1773 1785 /*----------------------------------------------------------------------------+
1774 1786 | SDR + ios table update + fpga initialization
1775 1787 +----------------------------------------------------------------------------*/
1776   - unsigned long sdr0_pfc1 = 0;
1777   - unsigned long sdr0_usb0 = 0;
1778   - unsigned long sdr0_mfr = 0;
  1788 + unsigned long sdr0_pfc1 = 0;
  1789 + unsigned long sdr0_usb0 = 0;
  1790 + unsigned long sdr0_mfr = 0;
1779 1791  
1780 1792 /* PCI Always selected */
1781 1793  
... ... @@ -1886,9 +1898,9 @@
1886 1898 update_ndfc_ios();
1887 1899  
1888 1900 mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL |
1889   - SDR0_CUST0_NDFC_ENABLE |
1890   - SDR0_CUST0_NDFC_BW_8_BIT |
1891   - SDR0_CUST0_NDFC_ARE_MASK |
  1901 + SDR0_CUST0_NDFC_ENABLE |
  1902 + SDR0_CUST0_NDFC_BW_8_BIT |
  1903 + SDR0_CUST0_NDFC_ARE_MASK |
1892 1904 SDR0_CUST0_CHIPSELGAT_EN1 );
1893 1905 /*SDR0_CUST0_CHIPSELGAT_EN2 ); */
1894 1906 /*SDR0_CUST0_CHIPSELGAT_EN3 ); */
1895 1907  
1896 1908  
1897 1909  
1898 1910  
... ... @@ -1938,25 +1950,25 @@
1938 1950 uart_configuration = get_uart_configuration();
1939 1951 switch (uart_configuration)
1940 1952 {
1941   - case L1: /* L1 Selection */
  1953 + case L1: /* L1 Selection */
1942 1954 /* UART0 8 pins Only */
1943 1955 /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
1944   - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */
  1956 + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */
1945 1957 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
1946 1958 break;
1947   - case L2: /* L2 Selection */
  1959 + case L2: /* L2 Selection */
1948 1960 /* UART0 and UART1 4 pins */
1949 1961 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1950 1962 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1951 1963 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1952 1964 break;
1953   - case L3: /* L3 Selection */
  1965 + case L3: /* L3 Selection */
1954 1966 /* UART0 4 pins, UART1 and UART2 2 pins */
1955 1967 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1956 1968 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1957 1969 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1958 1970 break;
1959   - case L4: /* L4 Selection */
  1971 + case L4: /* L4 Selection */
1960 1972 /* UART0, UART1, UART2 and UART3 2 pins */
1961 1973 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
1962 1974 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
board/amcc/bamboo/bamboo.h
Diff comments   View file @ f901a83
... ... @@ -12,7 +12,7 @@
12 12 *
13 13 * This program is distributed in the hope that it will be useful,
14 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 16 * GNU General Public License for more details.
17 17 *
18 18 * You should have received a copy of the GNU General Public License
19 19  
20 20  
21 21  
22 22  
23 23  
24 24  
25 25  
26 26  
27 27  
28 28  
29 29  
30 30  
31 31  
32 32  
33 33  
34 34  
... ... @@ -29,107 +29,107 @@
29 29 * TLB initialization makes it correspond to logical address 0x80001FF0.
30 30 * => Done init_chip.s in bootlib
31 31 */
32   -#define FPGA_BASE_ADDR 0x80002000
  32 +#define FPGA_BASE_ADDR 0x80002000
33 33  
34 34 /*----------------------------------------------------------------------------+
35 35 | Board Jumpers Setting Register
36 36 | Board Settings provided by jumpers
37 37 +----------------------------------------------------------------------------*/
38   -#define FPGA_SETTING_REG (FPGA_BASE_ADDR+0x3)
  38 +#define FPGA_SETTING_REG (FPGA_BASE_ADDR+0x3)
39 39 /* Boot from small flash */
40   -#define FPGA_SET_REG_BOOT_SMALL_FLASH 0x80
  40 +#define FPGA_SET_REG_BOOT_SMALL_FLASH 0x80
41 41 /* Operational Flash versus SRAM position in Memory Map */
42   -#define FPGA_SET_REG_OP_CODE_SRAM_SEL_MASK 0x40
43   -#define FPGA_SET_REG_OP_CODE_FLASH_ABOVE 0x40
44   -#define FPGA_SET_REG_SRAM_ABOVE 0x00
  42 +#define FPGA_SET_REG_OP_CODE_SRAM_SEL_MASK 0x40
  43 +#define FPGA_SET_REG_OP_CODE_FLASH_ABOVE 0x40
  44 +#define FPGA_SET_REG_SRAM_ABOVE 0x00
45 45 /* Boot From NAND Flash */
46   -#define FPGA_SET_REG_BOOT_NAND_FLASH_MASK 0x40
47   -#define FPGA_SET_REG_BOOT_NAND_FLASH_SELECT 0x00
  46 +#define FPGA_SET_REG_BOOT_NAND_FLASH_MASK 0x40
  47 +#define FPGA_SET_REG_BOOT_NAND_FLASH_SELECT 0x00
48 48 /* On Board PCI Arbiter Select */
49   -#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL_MASK 0x10
50   -#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL 0x00
  49 +#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL_MASK 0x10
  50 +#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL 0x00
51 51  
52 52 /*----------------------------------------------------------------------------+
53 53 | Functions Selection Register 1
54 54 +----------------------------------------------------------------------------*/
55   -#define FPGA_SELECTION_1_REG (FPGA_BASE_ADDR+0x4)
56   -#define FPGA_SEL_1_REG_PHY_MASK 0xE0
57   -#define FPGA_SEL_1_REG_MII 0x80
58   -#define FPGA_SEL_1_REG_RMII 0x40
59   -#define FPGA_SEL_1_REG_SMII 0x20
60   -#define FPGA_SEL_1_REG_USB2_DEV_SEL 0x10 /* USB2 Device Selection */
61   -#define FPGA_SEL_1_REG_USB2_HOST_SEL 0x08 /* USB2 Host Selection */
62   -#define FPGA_SEL_1_REG_NF_SELEC_MASK 0x07 /* NF Selection Mask */
63   -#define FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1 0x04 /* NF0 Selected by NF_CS1 */
64   -#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2 0x02 /* NF1 Selected by NF_CS2 */
65   -#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3 0x01 /* NF1 Selected by NF_CS3 */
  55 +#define FPGA_SELECTION_1_REG (FPGA_BASE_ADDR+0x4)
  56 +#define FPGA_SEL_1_REG_PHY_MASK 0xE0
  57 +#define FPGA_SEL_1_REG_MII 0x80
  58 +#define FPGA_SEL_1_REG_RMII 0x40
  59 +#define FPGA_SEL_1_REG_SMII 0x20
  60 +#define FPGA_SEL_1_REG_USB2_DEV_SEL 0x10 /* USB2 Device Selection */
  61 +#define FPGA_SEL_1_REG_USB2_HOST_SEL 0x08 /* USB2 Host Selection */
  62 +#define FPGA_SEL_1_REG_NF_SELEC_MASK 0x07 /* NF Selection Mask */
  63 +#define FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1 0x04 /* NF0 Selected by NF_CS1 */
  64 +#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2 0x02 /* NF1 Selected by NF_CS2 */
  65 +#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3 0x01 /* NF1 Selected by NF_CS3 */
66 66  
67 67 /*----------------------------------------------------------------------------+
68 68 | Functions Selection Register 2
69 69 +----------------------------------------------------------------------------*/
70   -#define FPGA_SELECTION_2_REG (FPGA_BASE_ADDR+0x5)
71   -#define FPGA_SEL2_REG_IIC1_SCP_SEL_MASK 0x80 /* IIC1 / SCP Selection */
72   -#define FPGA_SEL2_REG_SEL_FRAM 0x80 /* FRAM on IIC1 bus selected - SCP Select */
73   -#define FPGA_SEL2_REG_SEL_SCP 0x80 /* Identical to SCP Selection */
74   -#define FPGA_SEL2_REG_SEL_IIC1 0x00 /* IIC1 Selection - Default Value */
75   -#define FPGA_SEL2_REG_SEL_DMA_A_B 0x40 /* DMA A & B channels selected */
76   -#define FPGA_SEL2_REG_SEL_DMA_C_D 0x20 /* DMA C & D channels selected */
77   -#define FPGA_SEL2_REG_DMA_EOT_TC_3_SEL 0x10 /* 0 = EOT - input to 440EP */
78   - /* 1 = TC - output from 440EP */
79   -#define FPGA_SEL2_REG_DMA_EOT_TC_2_SEL 0x08 /* 0 = EOT (input to 440EP) */
80   - /* 1 = TC (output from 440EP) */
81   -#define FPGA_SEL2_REG_SEL_GPIO_1 0x04 /* EBC_GPIO & USB2_GPIO selected */
82   -#define FPGA_SEL2_REG_SEL_GPIO_2 0x02 /* Ether._GPIO & UART_GPIO selected */
83   -#define FPGA_SEL2_REG_SEL_GPIO_3 0x01 /* DMA_GPIO & Trace_GPIO selected */
  70 +#define FPGA_SELECTION_2_REG (FPGA_BASE_ADDR+0x5)
  71 +#define FPGA_SEL2_REG_IIC1_SCP_SEL_MASK 0x80 /* IIC1 / SCP Selection */
  72 +#define FPGA_SEL2_REG_SEL_FRAM 0x80 /* FRAM on IIC1 bus selected - SCP Select */
  73 +#define FPGA_SEL2_REG_SEL_SCP 0x80 /* Identical to SCP Selection */
  74 +#define FPGA_SEL2_REG_SEL_IIC1 0x00 /* IIC1 Selection - Default Value */
  75 +#define FPGA_SEL2_REG_SEL_DMA_A_B 0x40 /* DMA A & B channels selected */
  76 +#define FPGA_SEL2_REG_SEL_DMA_C_D 0x20 /* DMA C & D channels selected */
  77 +#define FPGA_SEL2_REG_DMA_EOT_TC_3_SEL 0x10 /* 0 = EOT - input to 440EP */
  78 + /* 1 = TC - output from 440EP */
  79 +#define FPGA_SEL2_REG_DMA_EOT_TC_2_SEL 0x08 /* 0 = EOT (input to 440EP) */
  80 + /* 1 = TC (output from 440EP) */
  81 +#define FPGA_SEL2_REG_SEL_GPIO_1 0x04 /* EBC_GPIO & USB2_GPIO selected */
  82 +#define FPGA_SEL2_REG_SEL_GPIO_2 0x02 /* Ether._GPIO & UART_GPIO selected */
  83 +#define FPGA_SEL2_REG_SEL_GPIO_3 0x01 /* DMA_GPIO & Trace_GPIO selected */
84 84  
85 85 /*----------------------------------------------------------------------------+
86 86 | Functions Selection Register 3
87 87 +----------------------------------------------------------------------------*/
88   -#define FPGA_SELECTION_3_REG (FPGA_BASE_ADDR+0x6)
89   -#define FPGA_SEL3_REG_EXP_SLOT_EN 0x80 /* Expansion Slot enabled */
90   -#define FPGA_SEL3_REG_SEL_UART_CONFIG_MASK 0x70
91   -#define FPGA_SEL3_REG_SEL_UART_CONFIG1 0x40 /* one 8_pin UART */
92   -#define FPGA_SEL3_REG_SEL_UART_CONFIG2 0x20 /* two 4_pin UARTs */
93   -#define FPGA_SEL3_REG_SEL_UART_CONFIG3 0x10 /* one 4_pin & two 2_pin UARTs */
94   -#define FPGA_SEL3_REG_SEL_UART_CONFIG4 0x08 /* four 2_pin UARTs */
95   -#define FPGA_SEL3_REG_DTR_DSR_MODE_4_PIN_UART 0x00 /* DTR/DSR mode for 4_pin_UART */
96   -#define FPGA_SEL3_REG_RTS_CTS_MODE_4_PIN_UART 0x04 /* RTS/CTS mode for 4_pin_UART */
  88 +#define FPGA_SELECTION_3_REG (FPGA_BASE_ADDR+0x6)
  89 +#define FPGA_SEL3_REG_EXP_SLOT_EN 0x80 /* Expansion Slot enabled */
  90 +#define FPGA_SEL3_REG_SEL_UART_CONFIG_MASK 0x70
  91 +#define FPGA_SEL3_REG_SEL_UART_CONFIG1 0x40 /* one 8_pin UART */
  92 +#define FPGA_SEL3_REG_SEL_UART_CONFIG2 0x20 /* two 4_pin UARTs */
  93 +#define FPGA_SEL3_REG_SEL_UART_CONFIG3 0x10 /* one 4_pin & two 2_pin UARTs */
  94 +#define FPGA_SEL3_REG_SEL_UART_CONFIG4 0x08 /* four 2_pin UARTs */
  95 +#define FPGA_SEL3_REG_DTR_DSR_MODE_4_PIN_UART 0x00 /* DTR/DSR mode for 4_pin_UART */
  96 +#define FPGA_SEL3_REG_RTS_CTS_MODE_4_PIN_UART 0x04 /* RTS/CTS mode for 4_pin_UART */
97 97  
98 98 /*----------------------------------------------------------------------------+
99 99 | Soft Reset Register
100 100 +----------------------------------------------------------------------------*/
101   -#define FPGA_RESET_REG (FPGA_BASE_ADDR+0x7)
102   -#define FPGA_RESET_REG_RESET_USB20_DEV 0x80 /* Hard Reset of the GT3200 */
103   -#define FPGA_RESET_REG_RESET_DISPLAY 0x40 /* Hard Reset on Display Device */
104   -#define FPGA_RESET_REG_STATUS_LED_0 0x08 /* 1 = Led On */
105   -#define FPGA_RESET_REG_STATUS_LED_1 0x04 /* 1 = Led On */
106   -#define FPGA_RESET_REG_STATUS_LED_2 0x02 /* 1 = Led On */
107   -#define FPGA_RESET_REG_STATUS_LED_3 0x01 /* 1 = Led On */
  101 +#define FPGA_RESET_REG (FPGA_BASE_ADDR+0x7)
  102 +#define FPGA_RESET_REG_RESET_USB20_DEV 0x80 /* Hard Reset of the GT3200 */
  103 +#define FPGA_RESET_REG_RESET_DISPLAY 0x40 /* Hard Reset on Display Device */
  104 +#define FPGA_RESET_REG_STATUS_LED_0 0x08 /* 1 = Led On */
  105 +#define FPGA_RESET_REG_STATUS_LED_1 0x04 /* 1 = Led On */
  106 +#define FPGA_RESET_REG_STATUS_LED_2 0x02 /* 1 = Led On */
  107 +#define FPGA_RESET_REG_STATUS_LED_3 0x01 /* 1 = Led On */
108 108  
109 109  
110 110 /*----------------------------------------------------------------------------+
111 111 | SDR Configuration registers
112 112 +----------------------------------------------------------------------------*/
113 113 /* Serial Device Strap Reg 0 */
114   -#define SDR0_SDSTP0 0x0020
  114 +#define SDR0_SDSTP0 0x0020
115 115 /* Serial Device Strap Reg 1 */
116   -#define SDR0_SDSTP1 0x0021
  116 +#define SDR0_SDSTP1 0x0021
117 117 /* Serial Device Strap Reg 2 */
118   -#define SDR0_SDSTP2 SDR0_STRP2
  118 +#define SDR0_SDSTP2 SDR0_STRP2
119 119 /* Serial Device Strap Reg 3 */
120   -#define SDR0_SDSTP3 SDR0_STRP3
  120 +#define SDR0_SDSTP3 SDR0_STRP3
121 121  
122   -#define sdr_pstrp0 0x0040
  122 +#define sdr_pstrp0 0x0040
123 123  
124   -#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00006000 /* EBC Boot Size Mask */
125   -#define SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000 /* EBC 32 bits */
126   -#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000 /* EBC 16 Bits */
127   -#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */
  124 +#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00006000 /* EBC Boot Size Mask */
  125 +#define SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000 /* EBC 32 bits */
  126 +#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000 /* EBC 16 Bits */
  127 +#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */
128 128  
129   -#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00001800 /* Boot device Selection Mask */
130   -#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */
131   -#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00000800 /* PCI */
132   -#define SDR0_SDSTP1_BOOT_SEL_NDFC 0x00001000 /* NDFC */
  129 +#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00001800 /* Boot device Selection Mask */
  130 +#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */
  131 +#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00000800 /* PCI */
  132 +#define SDR0_SDSTP1_BOOT_SEL_NDFC 0x00001000 /* NDFC */
133 133  
134 134 /* Serial Device Enabled - Addr = 0xA8 */
135 135 #define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
... ... @@ -137,8 +137,8 @@
137 137 #define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
138 138  
139 139 /* Pin Straps Reg */
140   -#define SDR0_PSTRP0 0x0040
141   -#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */
  140 +#define SDR0_PSTRP0 0x0040
  141 +#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */
142 142  
143 143 #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */
144 144 #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */
145 145  
146 146  
147 147  
148 148  
149 149  
150 150  
151 151  
152 152  
153 153  
154 154  
155 155  
156 156  
157 157  
158 158  
159 159  
160 160  
161 161  
162 162  
163 163  
164 164  
165 165  
166 166  
167 167  
168 168  
169 169  
170 170  
171 171  
172 172  
173 173  
174 174  
175 175  
176 176  
177 177  
178 178  
179 179  
180 180  
181 181  
... ... @@ -153,182 +153,182 @@
153 153 | EBC Configuration Register - EBC0_CFG
154 154 +----------------------------------------------------------------------------*/
155 155 /* External Bus Three-State Control */
156   -#define EBC0_CFG_EBTC_DRIVEN 0x80000000
  156 +#define EBC0_CFG_EBTC_DRIVEN 0x80000000
157 157 /* Device-Paced Time-out Disable */
158   -#define EBC0_CFG_PTD_ENABLED 0x00000000
  158 +#define EBC0_CFG_PTD_ENABLED 0x00000000
159 159 /* Ready Timeout Count */
160   -#define EBC0_CFG_RTC_MASK 0x38000000
161   -#define EBC0_CFG_RTC_16PERCLK 0x00000000
162   -#define EBC0_CFG_RTC_32PERCLK 0x08000000
163   -#define EBC0_CFG_RTC_64PERCLK 0x10000000
164   -#define EBC0_CFG_RTC_128PERCLK 0x18000000
165   -#define EBC0_CFG_RTC_256PERCLK 0x20000000
166   -#define EBC0_CFG_RTC_512PERCLK 0x28000000
167   -#define EBC0_CFG_RTC_1024PERCLK 0x30000000
168   -#define EBC0_CFG_RTC_2048PERCLK 0x38000000
  160 +#define EBC0_CFG_RTC_MASK 0x38000000
  161 +#define EBC0_CFG_RTC_16PERCLK 0x00000000
  162 +#define EBC0_CFG_RTC_32PERCLK 0x08000000
  163 +#define EBC0_CFG_RTC_64PERCLK 0x10000000
  164 +#define EBC0_CFG_RTC_128PERCLK 0x18000000
  165 +#define EBC0_CFG_RTC_256PERCLK 0x20000000
  166 +#define EBC0_CFG_RTC_512PERCLK 0x28000000
  167 +#define EBC0_CFG_RTC_1024PERCLK 0x30000000
  168 +#define EBC0_CFG_RTC_2048PERCLK 0x38000000
169 169 /* External Master Priority Low */
170   -#define EBC0_CFG_EMPL_LOW 0x00000000
  170 +#define EBC0_CFG_EMPL_LOW 0x00000000
171 171 #define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000
172 172 #define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000
173   -#define EBC0_CFG_EMPL_HIGH 0x06000000
  173 +#define EBC0_CFG_EMPL_HIGH 0x06000000
174 174 /* External Master Priority High */
175   -#define EBC0_CFG_EMPH_LOW 0x00000000
  175 +#define EBC0_CFG_EMPH_LOW 0x00000000
176 176 #define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000
177 177 #define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000
178   -#define EBC0_CFG_EMPH_HIGH 0x01800000
  178 +#define EBC0_CFG_EMPH_HIGH 0x01800000
179 179 /* Chip Select Three-State Control */
180   -#define EBC0_CFG_CSTC_DRIVEN 0x00400000
  180 +#define EBC0_CFG_CSTC_DRIVEN 0x00400000
181 181 /* Burst Prefetch */
182   -#define EBC0_CFG_BPF_ONEDW 0x00000000
183   -#define EBC0_CFG_BPF_TWODW 0x00100000
184   -#define EBC0_CFG_BPF_FOURDW 0x00200000
  182 +#define EBC0_CFG_BPF_ONEDW 0x00000000
  183 +#define EBC0_CFG_BPF_TWODW 0x00100000
  184 +#define EBC0_CFG_BPF_FOURDW 0x00200000
185 185 /* External Master Size */
186   -#define EBC0_CFG_EMS_8BIT 0x00000000
  186 +#define EBC0_CFG_EMS_8BIT 0x00000000
187 187 /* Power Management Enable */
188   -#define EBC0_CFG_PME_DISABLED 0x00000000
189   -#define EBC0_CFG_PME_ENABLED 0x00020000
  188 +#define EBC0_CFG_PME_DISABLED 0x00000000
  189 +#define EBC0_CFG_PME_ENABLED 0x00020000
190 190 /* Power Management Timer */
191   -#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
  191 +#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
192 192  
193 193 /*----------------------------------------------------------------------------+
194 194 | Peripheral Bank Configuration Register - EBC0_BnCR
195 195 +----------------------------------------------------------------------------*/
196 196 /* BAS - Base Address Select */
197   -#define EBC0_BNCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0)
  197 +#define EBC0_BNCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0)
198 198 /* BS - Bank Size */
199   -#define EBC0_BNCR_BS_MASK 0x000E0000
200   -#define EBC0_BNCR_BS_1MB 0x00000000
201   -#define EBC0_BNCR_BS_2MB 0x00020000
202   -#define EBC0_BNCR_BS_4MB 0x00040000
203   -#define EBC0_BNCR_BS_8MB 0x00060000
204   -#define EBC0_BNCR_BS_16MB 0x00080000
205   -#define EBC0_BNCR_BS_32MB 0x000A0000
206   -#define EBC0_BNCR_BS_64MB 0x000C0000
207   -#define EBC0_BNCR_BS_128MB 0x000E0000
  199 +#define EBC0_BNCR_BS_MASK 0x000E0000
  200 +#define EBC0_BNCR_BS_1MB 0x00000000
  201 +#define EBC0_BNCR_BS_2MB 0x00020000
  202 +#define EBC0_BNCR_BS_4MB 0x00040000
  203 +#define EBC0_BNCR_BS_8MB 0x00060000
  204 +#define EBC0_BNCR_BS_16MB 0x00080000
  205 +#define EBC0_BNCR_BS_32MB 0x000A0000
  206 +#define EBC0_BNCR_BS_64MB 0x000C0000
  207 +#define EBC0_BNCR_BS_128MB 0x000E0000
208 208 /* BU - Bank Usage */
209   -#define EBC0_BNCR_BU_MASK 0x00018000
210   -#define EBC0_BNCR_BU_RO 0x00008000
211   -#define EBC0_BNCR_BU_WO 0x00010000
212   -#define EBC0_BNCR_BU_RW 0x00018000
  209 +#define EBC0_BNCR_BU_MASK 0x00018000
  210 +#define EBC0_BNCR_BU_RO 0x00008000
  211 +#define EBC0_BNCR_BU_WO 0x00010000
  212 +#define EBC0_BNCR_BU_RW 0x00018000
213 213 /* BW - Bus Width */
214   -#define EBC0_BNCR_BW_MASK 0x00006000
215   -#define EBC0_BNCR_BW_8BIT 0x00000000
216   -#define EBC0_BNCR_BW_16BIT 0x00002000
217   -#define EBC0_BNCR_BW_32BIT 0x00004000
  214 +#define EBC0_BNCR_BW_MASK 0x00006000
  215 +#define EBC0_BNCR_BW_8BIT 0x00000000
  216 +#define EBC0_BNCR_BW_16BIT 0x00002000
  217 +#define EBC0_BNCR_BW_32BIT 0x00004000
218 218  
219 219 /*----------------------------------------------------------------------------+
220 220 | Peripheral Bank Access Parameters - EBC0_BnAP
221 221 +----------------------------------------------------------------------------*/
222 222 /* Burst Mode Enable */
223   -#define EBC0_BNAP_BME_ENABLED 0x80000000
224   -#define EBC0_BNAP_BME_DISABLED 0x00000000
  223 +#define EBC0_BNAP_BME_ENABLED 0x80000000
  224 +#define EBC0_BNAP_BME_DISABLED 0x00000000
225 225 /* Transfert Wait */
226   -#define EBC0_BNAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23) /* Bits 1:8 */
  226 +#define EBC0_BNAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23) /* Bits 1:8 */
227 227 /* Chip Select On Timing */
228   -#define EBC0_BNAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18) /* Bits 12:13 */
  228 +#define EBC0_BNAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18) /* Bits 12:13 */
229 229 /* Output Enable On Timing */
230   -#define EBC0_BNAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) /* Bits 14:15 */
  230 +#define EBC0_BNAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) /* Bits 14:15 */
231 231 /* Write Back Enable On Timing */
232   -#define EBC0_BNAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14) /* Bits 16:17 */
  232 +#define EBC0_BNAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14) /* Bits 16:17 */
233 233 /* Write Back Enable Off Timing */
234   -#define EBC0_BNAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12) /* Bits 18:19 */
  234 +#define EBC0_BNAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12) /* Bits 18:19 */
235 235 /* Transfert Hold */
236   -#define EBC0_BNAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9) /* Bits 20:22 */
  236 +#define EBC0_BNAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9) /* Bits 20:22 */
237 237 /* PerReady Enable */
238   -#define EBC0_BNAP_RE_ENABLED 0x00000100
239   -#define EBC0_BNAP_RE_DISABLED 0x00000000
  238 +#define EBC0_BNAP_RE_ENABLED 0x00000100
  239 +#define EBC0_BNAP_RE_DISABLED 0x00000000
240 240 /* Sample On Ready */
241   -#define EBC0_BNAP_SOR_DELAYED 0x00000000
  241 +#define EBC0_BNAP_SOR_DELAYED 0x00000000
242 242 #define EBC0_BNAP_SOR_NOT_DELAYED 0x00000080
243 243 /* Byte Enable Mode */
244   -#define EBC0_BNAP_BEM_WRITEONLY 0x00000000
245   -#define EBC0_BNAP_BEM_RW 0x00000040
  244 +#define EBC0_BNAP_BEM_WRITEONLY 0x00000000
  245 +#define EBC0_BNAP_BEM_RW 0x00000040
246 246 /* Parity Enable */
247   -#define EBC0_BNAP_PEN_DISABLED 0x00000000
248   -#define EBC0_BNAP_PEN_ENABLED 0x00000020
  247 +#define EBC0_BNAP_PEN_DISABLED 0x00000000
  248 +#define EBC0_BNAP_PEN_ENABLED 0x00000020
249 249  
250 250 /*----------------------------------------------------------------------------+
251 251 | Define Boot devices
252 252 +----------------------------------------------------------------------------*/
253 253 /* */
254   -#define BOOT_FROM_SMALL_FLASH 0x00
255   -#define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01
256   -#define BOOT_FROM_NAND_FLASH0 0x02
257   -#define BOOT_FROM_PCI 0x03
258   -#define BOOT_DEVICE_UNKNOWN 0x04
  254 +#define BOOT_FROM_SMALL_FLASH 0x00
  255 +#define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01
  256 +#define BOOT_FROM_NAND_FLASH0 0x02
  257 +#define BOOT_FROM_PCI 0x03
  258 +#define BOOT_DEVICE_UNKNOWN 0x04
259 259  
260 260  
261   -#define PVR_POWERPC_440EP_PASS1 0x42221850
262   -#define PVR_POWERPC_440EP_PASS2 0x422218D3
  261 +#define PVR_POWERPC_440EP_PASS1 0x42221850
  262 +#define PVR_POWERPC_440EP_PASS2 0x422218D3
263 263  
264 264 #define TRUE 1
265 265 #define FALSE 0
266 266  
267   -#define GPIO_GROUP_MAX 2
268   -#define GPIO_MAX 32
269   -#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
270   -#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
271   -#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
272   -#define GPIO_MASK 0xC0000000 /* GPIO_MASK */
273   -#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
274   - /* For the other GPIO number, you must shift */
  267 +#define GPIO_GROUP_MAX 2
  268 +#define GPIO_MAX 32
  269 +#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
  270 +#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
  271 +#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
  272 +#define GPIO_MASK 0xC0000000 /* GPIO_MASK */
  273 +#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
  274 + /* For the other GPIO number, you must shift */
275 275  
276   -#define GPIO0 0
277   -#define GPIO1 1
  276 +#define GPIO0 0
  277 +#define GPIO1 1
278 278  
279 279  
280   -/*#define MAX_SELECTION_NB CORE_NB */
281   -#define MAX_CORE_SELECT_NB 22
  280 +/*#define MAX_SELECTION_NB CORE_NB */
  281 +#define MAX_CORE_SELECT_NB 22
282 282  
283 283 /*----------------------------------------------------------------------------+
284 284 | PPC440EP GPIOs addresses.
285 285 +----------------------------------------------------------------------------*/
286   -#define GPIO0_BASE 0xEF600B00
287   -#define GPIO0_REAL 0xEF600B00
  286 +#define GPIO0_BASE 0xEF600B00
  287 +#define GPIO0_REAL 0xEF600B00
288 288  
289   -#define GPIO1_BASE 0xEF600C00
290   -#define GPIO1_REAL 0xEF600C00
  289 +#define GPIO1_BASE 0xEF600C00
  290 +#define GPIO1_REAL 0xEF600C00
291 291  
292 292 /* Offsets */
293   -#define GPIOx_OR 0x00 /* GPIO Output Register */
294   -#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
295   -#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
296   -#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
297   -#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
298   -#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
299   -#define GPIOx_ODR 0x18 /* GPIO Open drain Register */
300   -#define GPIOx_IR 0x1C /* GPIO Input Register */
301   -#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
302   -#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
303   -#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
304   -#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
305   -#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
306   -#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
307   -#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
308   -#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
309   -#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
  293 +#define GPIOx_OR 0x00 /* GPIO Output Register */
  294 +#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
  295 +#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
  296 +#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
  297 +#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
  298 +#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
  299 +#define GPIOx_ODR 0x18 /* GPIO Open drain Register */
  300 +#define GPIOx_IR 0x1C /* GPIO Input Register */
  301 +#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
  302 +#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
  303 +#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
  304 +#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
  305 +#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
  306 +#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
  307 +#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
  308 +#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
  309 +#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
310 310  
311 311 /* GPIO0 */
312   -#define GPIO0_IS1L (GPIO0_BASE+GPIOx_IS1L)
313   -#define GPIO0_IS1H (GPIO0_BASE+GPIOx_IS1H)
314   -#define GPIO0_IS2L (GPIO0_BASE+GPIOx_IS2L)
315   -#define GPIO0_IS2H (GPIO0_BASE+GPIOx_IS2H)
316   -#define GPIO0_IS3L (GPIO0_BASE+GPIOx_IS3L)
317   -#define GPIO0_IS3H (GPIO0_BASE+GPIOx_IS3L)
  312 +#define GPIO0_IS1L (GPIO0_BASE+GPIOx_IS1L)
  313 +#define GPIO0_IS1H (GPIO0_BASE+GPIOx_IS1H)
  314 +#define GPIO0_IS2L (GPIO0_BASE+GPIOx_IS2L)
  315 +#define GPIO0_IS2H (GPIO0_BASE+GPIOx_IS2H)
  316 +#define GPIO0_IS3L (GPIO0_BASE+GPIOx_IS3L)
  317 +#define GPIO0_IS3H (GPIO0_BASE+GPIOx_IS3L)
318 318  
319 319 /* GPIO1 */
320   -#define GPIO1_IS1L (GPIO1_BASE+GPIOx_IS1L)
321   -#define GPIO1_IS1H (GPIO1_BASE+GPIOx_IS1H)
322   -#define GPIO1_IS2L (GPIO1_BASE+GPIOx_IS2L)
323   -#define GPIO1_IS2H (GPIO1_BASE+GPIOx_IS2H)
324   -#define GPIO1_IS3L (GPIO1_BASE+GPIOx_IS3L)
325   -#define GPIO1_IS3H (GPIO1_BASE+GPIOx_IS3L)
  320 +#define GPIO1_IS1L (GPIO1_BASE+GPIOx_IS1L)
  321 +#define GPIO1_IS1H (GPIO1_BASE+GPIOx_IS1H)
  322 +#define GPIO1_IS2L (GPIO1_BASE+GPIOx_IS2L)
  323 +#define GPIO1_IS2H (GPIO1_BASE+GPIOx_IS2H)
  324 +#define GPIO1_IS3L (GPIO1_BASE+GPIOx_IS3L)
  325 +#define GPIO1_IS3H (GPIO1_BASE+GPIOx_IS3L)
326 326  
327   -#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */
328   -#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
329   -#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
330   -#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
331   -#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
  327 +#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */
  328 +#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
  329 +#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
  330 +#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
  331 +#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
332 332  
333 333  
334 334 /*----------------------------------------------------------------------------+
335 335  
336 336  
337 337  
... ... @@ -337,27 +337,27 @@
337 337 typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
338 338 typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
339 339  
340   -typedef struct { unsigned long add; /* gpio core base address */
  340 +typedef struct { unsigned long add; /* gpio core base address */
341 341 gpio_driver_t in_out; /* Driver Setting */
342 342 gpio_select_t alt_nb; /* Selected Alternate */
343 343 } gpio_param_s;
344 344  
345 345 /*----------------------------------------------------------------------------+
346   - | XX XX
  346 + | XX XX
347 347 |
348 348 | XXXXXX XXX XX XXX XXX
349   - | XX XX X XX XX XX
350   - | XX XX X XX XX XX
351   - | XX XX XX XX XX
  349 + | XX XX X XX XX XX
  350 + | XX XX X XX XX XX
  351 + | XX XX XX XX XX
352 352 | XXXXXX XXX XXX XXXX XXXX
353 353 +----------------------------------------------------------------------------*/
354 354 /*----------------------------------------------------------------------------+
355 355 | Defines
356 356 +----------------------------------------------------------------------------*/
357 357 typedef enum zmii_config { ZMII_CONFIGURATION_UNKNOWN,
358   - ZMII_CONFIGURATION_IS_MII,
359   - ZMII_CONFIGURATION_IS_RMII,
360   - ZMII_CONFIGURATION_IS_SMII
  358 + ZMII_CONFIGURATION_IS_MII,
  359 + ZMII_CONFIGURATION_IS_RMII,
  360 + ZMII_CONFIGURATION_IS_SMII
361 361 } zmii_config_t;
362 362  
363 363 /*----------------------------------------------------------------------------+
364 364  
365 365  
... ... @@ -366,37 +366,37 @@
366 366 typedef enum uart_config_nb { L1, L2, L3, L4 } uart_config_nb_t;
367 367 typedef enum core_selection { CORE_NOT_SELECTED, CORE_SELECTED} core_selection_t;
368 368 typedef enum config_list { IIC_CORE,
369   - SCP_CORE,
370   - DMA_CHANNEL_AB,
371   - UIC_4_9,
372   - USB2_HOST,
373   - DMA_CHANNEL_CD,
374   - USB2_DEVICE,
375   - PACKET_REJ_FUNC_AVAIL,
376   - USB1_DEVICE,
377   - EBC_MASTER,
378   - NAND_FLASH,
379   - UART_CORE0,
380   - UART_CORE1,
381   - UART_CORE2,
382   - UART_CORE3,
383   - MII_SEL,
384   - RMII_SEL,
385   - SMII_SEL,
386   - PACKET_REJ_FUNC_EN,
387   - UIC_0_3,
388   - USB1_HOST,
389   - PCI_PATCH,
390   - CORE_NB
  369 + SCP_CORE,
  370 + DMA_CHANNEL_AB,
  371 + UIC_4_9,
  372 + USB2_HOST,
  373 + DMA_CHANNEL_CD,
  374 + USB2_DEVICE,
  375 + PACKET_REJ_FUNC_AVAIL,
  376 + USB1_DEVICE,
  377 + EBC_MASTER,
  378 + NAND_FLASH,
  379 + UART_CORE0,
  380 + UART_CORE1,
  381 + UART_CORE2,
  382 + UART_CORE3,
  383 + MII_SEL,
  384 + RMII_SEL,
  385 + SMII_SEL,
  386 + PACKET_REJ_FUNC_EN,
  387 + UIC_0_3,
  388 + USB1_HOST,
  389 + PCI_PATCH,
  390 + CORE_NB
391 391 } core_list_t;
392 392  
393 393 typedef enum block3_value { B3_V1, B3_V2, B3_V3, B3_V4, B3_V5,
394   - B3_V6, B3_V7, B3_V8, B3_V9, B3_V10,
395   - B3_V11, B3_V12, B3_V13, B3_V14, B3_V15,
396   - B3_V16, B3_VALUE_UNKNOWN
  394 + B3_V6, B3_V7, B3_V8, B3_V9, B3_V10,
  395 + B3_V11, B3_V12, B3_V13, B3_V14, B3_V15,
  396 + B3_V16, B3_VALUE_UNKNOWN
397 397 } block3_value_t;
398 398  
399 399 typedef enum config_validity { CONFIG_IS_VALID,
400   - CONFIG_IS_INVALID
  400 + CONFIG_IS_INVALID
401 401 } config_validity_t;
board/ep8248/Makefile
Diff comments   View file @ f901a83
  1 +#
  2 +# (C) Copyright 2001
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +LIB = lib$(BOARD).a
  27 +
  28 +OBJS := $(BOARD).o
  29 +
  30 +$(LIB): $(OBJS) $(SOBJS)
  31 + $(AR) crv $@ $(OBJS)
  32 +
  33 +clean:
  34 + rm -f $(SOBJS) $(OBJS)
  35 +
  36 +distclean: clean
  37 + rm -f $(LIB) core *.bak .depend
  38 +
  39 +#########################################################################
  40 +
  41 +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
  42 + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
  43 +
  44 +-include .depend
  45 +
  46 +#########################################################################
board/ep8248/config.mk
Diff comments   View file @ f901a83
  1 +#
  2 +# (C) Copyright 2001
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# Modified by, Yuli Barcohen, Arabella Software Ltd. <yuli@arabellasw.com>
  6 +#
  7 +# See file CREDITS for list of people who contributed to this
  8 +# project.
  9 +#
  10 +# This program is free software; you can redistribute it and/or
  11 +# modify it under the terms of the GNU General Public License as
  12 +# published by the Free Software Foundation; either version 2 of
  13 +# the License, or (at your option) any later version.
  14 +#
  15 +# This program is distributed in the hope that it will be useful,
  16 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18 +# GNU General Public License for more details.
  19 +#
  20 +# You should have received a copy of the GNU General Public License
  21 +# along with this program; if not, write to the Free Software
  22 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 +# MA 02111-1307 USA
  24 +#
  25 +
  26 +#
  27 +# EP82xx series boards by Embedded Planet
  28 +#
  29 +
  30 +TEXT_BASE = 0xFFF00000
board/ep8248/ep8248.c
Diff comments   View file @ f901a83
  1 +/*
  2 + * Copyright (C) 2004 Arabella Software Ltd.
  3 + * Yuli Barcohen <yuli@arabellasw.com>
  4 + *
  5 + * Support for Embedded Planet EP8248 boards.
  6 + * Tested on EP8248E.
  7 + *
  8 + * See file CREDITS for list of people who contributed to this
  9 + * project.
  10 + *
  11 + * This program is free software; you can redistribute it and/or
  12 + * modify it under the terms of the GNU General Public License as
  13 + * published by the Free Software Foundation; either version 2 of
  14 + * the License, or (at your option) any later version.
  15 + *
  16 + * This program is distributed in the hope that it will be useful,
  17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19 + * GNU General Public License for more details.
  20 + *
  21 + * You should have received a copy of the GNU General Public License
  22 + * along with this program; if not, write to the Free Software
  23 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 + * MA 02111-1307 USA
  25 + */
  26 +
  27 +#include <common.h>
  28 +#include <mpc8260.h>
  29 +#include <ioports.h>
  30 +
  31 +/*
  32 + * I/O Port configuration table
  33 + *
  34 + * if conf is 1, then that port pin will be configured at boot time
  35 + * according to the five values podr/pdir/ppar/psor/pdat for that entry
  36 + */
  37 +
  38 +#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
  39 +#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
  40 +
  41 +const iop_conf_t iop_conf_tab[4][32] = {
  42 +
  43 + /* Port A */
  44 + { /* conf ppar psor pdir podr pdat */
  45 + /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
  46 + /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
  47 + /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
  48 + /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
  49 + /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
  50 + /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
  51 + /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
  52 + /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
  53 + /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
  54 + /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
  55 + /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
  56 + /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
  57 + /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
  58 + /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
  59 + /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
  60 + /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
  61 + /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
  62 + /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
  63 + /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
  64 + /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
  65 + /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
  66 + /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
  67 + /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TxD */
  68 + /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RxD */
  69 + /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
  70 + /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
  71 + /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
  72 + /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
  73 + /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
  74 + /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
  75 + /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
  76 + /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
  77 + },
  78 +
  79 + /* Port B */
  80 + { /* conf ppar psor pdir podr pdat */
  81 + /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
  82 + /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
  83 + /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
  84 + /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
  85 + /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
  86 + /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
  87 + /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
  88 + /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
  89 + /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
  90 + /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
  91 + /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
  92 + /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
  93 + /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
  94 + /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
  95 + /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  96 + /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  97 + /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  98 + /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  99 + /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  100 + /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  101 + /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  102 + /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  103 + /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  104 + /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  105 + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  106 + /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  107 + /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  108 + /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  109 + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  110 + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  111 + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  112 + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
  113 + },
  114 +
  115 + /* Port C */
  116 + { /* conf ppar psor pdir podr pdat */
  117 + /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
  118 + /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
  119 + /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
  120 + /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
  121 + /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
  122 + /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
  123 + /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
  124 + /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
  125 + /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
  126 + /* PC22 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 RxClk (CLK10) */
  127 + /* PC21 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 TxClk (CLK11) */
  128 + /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
  129 + /* PC19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 RxClk (CLK13) */
  130 + /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 TxClk (CLK14) */
  131 + /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
  132 + /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
  133 + /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
  134 + /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
  135 + /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
  136 + /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
  137 + /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
  138 + /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
  139 + /* PC9 */ { 1, 0, 0, 1, 0, 1 }, /* MDIO */
  140 + /* PC8 */ { 1, 0, 0, 1, 0, 1 }, /* MDC */
  141 + /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
  142 + /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
  143 + /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TxD */
  144 + /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RxD */
  145 + /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
  146 + /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
  147 + /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
  148 + /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
  149 + },
  150 +
  151 + /* Port D */
  152 + { /* conf ppar psor pdir podr pdat */
  153 + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RxD */
  154 + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TxD */
  155 + /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
  156 + /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
  157 + /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
  158 + /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
  159 + /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
  160 + /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
  161 + /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
  162 + /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
  163 + /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
  164 + /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
  165 + /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
  166 + /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
  167 + /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
  168 + /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
  169 + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
  170 + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
  171 + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
  172 + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
  173 + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
  174 + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
  175 + /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
  176 + /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
  177 + /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
  178 + /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
  179 + /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
  180 + /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
  181 + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  182 + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  183 + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  184 + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
  185 + }
  186 +};
  187 +
  188 +int board_early_init_f (void)
  189 +{
  190 + vu_char *bcsr = (vu_char *)CFG_BCSR;
  191 +
  192 + bcsr[4] |= 0x30; /* Turn the LEDs off */
  193 +
  194 +#if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC)
  195 + bcsr[6] |= 0x10;
  196 +#endif
  197 +#if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC)
  198 + bcsr[7] |= 0x10;
  199 +#endif
  200 +
  201 +#if CFG_FCC1
  202 + bcsr[8] |= 0xC0;
  203 +#endif /* CFG_FCC1 */
  204 +#if CFG_FCC2
  205 + bcsr[8] |= 0x30;
  206 +#endif /* CFG_FCC2 */
  207 +
  208 + return 0;
  209 +}
  210 +
  211 +long int initdram(int board_type)
  212 +{
  213 + vu_char *bcsr = (vu_char *)CFG_BCSR;
  214 + long int msize = 16L << (bcsr[2] & 3);
  215 +
  216 +#ifndef CFG_RAMBOOT
  217 + volatile immap_t *immap = (immap_t *)CFG_IMMR;
  218 + volatile memctl8260_t *memctl = &immap->im_memctl;
  219 + vu_char *ramaddr = (vu_char *)CFG_SDRAM_BASE;
  220 + uchar c = 0xFF;
  221 + uint psdmr = CFG_PSDMR;
  222 + int i;
  223 +
  224 + immap->im_siu_conf.sc_ppc_acr = 0x02;
  225 + immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
  226 + immap->im_siu_conf.sc_tescr1 = 0x00004000;
  227 +
  228 + memctl->memc_mptpr = CFG_MPTPR;
  229 +
  230 + /* Initialise 60x bus SDRAM */
  231 + memctl->memc_psrt = CFG_PSRT;
  232 + memctl->memc_or1 = CFG_SDRAM_OR;
  233 + memctl->memc_br1 = CFG_SDRAM_BR;
  234 + memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
  235 + *ramaddr = c;
  236 + memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
  237 + for (i = 0; i < 8; i++)
  238 + *ramaddr = c;
  239 + memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */
  240 + *ramaddr = c;
  241 + memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */
  242 + *ramaddr = c;
  243 +#endif /* !CFG_RAMBOOT */
  244 +
  245 + /* Return total 60x bus SDRAM size */
  246 + return msize * 1024 * 1024;
  247 +}
  248 +
  249 +int checkboard(void)
  250 +{
  251 + vu_char *bcsr = (vu_char *)CFG_BCSR;
  252 +
  253 + puts("Board: ");
  254 + switch (bcsr[0]) {
  255 + case 0x0C:
  256 + printf("EP8248E 1.0 CPLD revision %d\n", bcsr[1]);
  257 + break;
  258 + default:
  259 + printf("unknown: ID=%02X\n", bcsr[0]);
  260 + }
  261 +
  262 + return 0;
  263 +}
board/ep8248/u-boot.lds
Diff comments   View file @ f901a83
  1 +/*
  2 + * (C) Copyright 2001
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * Modified by Yuli Barcohen <yuli@arabellasw.com>
  6 + *
  7 + * See file CREDITS for list of people who contributed to this
  8 + * project.
  9 + *
  10 + * This program is free software; you can redistribute it and/or
  11 + * modify it under the terms of the GNU General Public License as
  12 + * published by the Free Software Foundation; either version 2 of
  13 + * the License, or (at your option) any later version.
  14 + *
  15 + * This program is distributed in the hope that it will be useful,
  16 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18 + * GNU General Public License for more details.
  19 + *
  20 + * You should have received a copy of the GNU General Public License
  21 + * along with this program; if not, write to the Free Software
  22 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 + * MA 02111-1307 USA
  24 + */
  25 +
  26 +OUTPUT_ARCH(powerpc)
  27 +SECTIONS
  28 +{
  29 + /* Read-only sections, merged into text segment: */
  30 + . = + SIZEOF_HEADERS;
  31 + .interp : { *(.interp) }
  32 + .hash : { *(.hash) }
  33 + .dynsym : { *(.dynsym) }
  34 + .dynstr : { *(.dynstr) }
  35 + .rel.text : { *(.rel.text) }
  36 + .rela.text : { *(.rela.text) }
  37 + .rel.data : { *(.rel.data) }
  38 + .rela.data : { *(.rela.data) }
  39 + .rel.rodata : { *(.rel.rodata) }
  40 + .rela.rodata : { *(.rela.rodata) }
  41 + .rel.got : { *(.rel.got) }
  42 + .rela.got : { *(.rela.got) }
  43 + .rel.ctors : { *(.rel.ctors) }
  44 + .rela.ctors : { *(.rela.ctors) }
  45 + .rel.dtors : { *(.rel.dtors) }
  46 + .rela.dtors : { *(.rela.dtors) }
  47 + .rel.bss : { *(.rel.bss) }
  48 + .rela.bss : { *(.rela.bss) }
  49 + .rel.plt : { *(.rel.plt) }
  50 + .rela.plt : { *(.rela.plt) }
  51 + .init : { *(.init) }
  52 + .plt : { *(.plt) }
  53 + .text :
  54 + {
  55 + cpu/mpc8260/start.o (.text)
  56 + *(.text)
  57 + *(.fixup)
  58 + *(.got1)
  59 + . = ALIGN(16);
  60 + *(.rodata)
  61 + *(.rodata1)
  62 + *(.rodata.str1.4)
  63 + }
  64 + .fini : { *(.fini) } =0
  65 + .ctors : { *(.ctors) }
  66 + .dtors : { *(.dtors) }
  67 +
  68 + /* Read-write section, merged into data segment: */
  69 + . = (. + 0x0FFF) & 0xFFFFF000;
  70 + _erotext = .;
  71 + PROVIDE (erotext = .);
  72 + .reloc :
  73 + {
  74 + *(.got)
  75 + _GOT2_TABLE_ = .;
  76 + *(.got2)
  77 + _FIXUP_TABLE_ = .;
  78 + *(.fixup)
  79 + }
  80 + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
  81 + __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
  82 +
  83 + .data :
  84 + {
  85 + *(.data)
  86 + *(.data1)
  87 + *(.sdata)
  88 + *(.sdata2)
  89 + *(.dynamic)
  90 + CONSTRUCTORS
  91 + }
  92 + _edata = .;
  93 + PROVIDE (edata = .);
  94 +
  95 + __u_boot_cmd_start = .;
  96 + .u_boot_cmd : { *(.u_boot_cmd) }
  97 + __u_boot_cmd_end = .;
  98 +
  99 +
  100 + __start___ex_table = .;
  101 + __ex_table : { *(__ex_table) }
  102 + __stop___ex_table = .;
  103 +
  104 + . = ALIGN(4096);
  105 + __init_begin = .;
  106 + .text.init : { *(.text.init) }
  107 + .data.init : { *(.data.init) }
  108 + . = ALIGN(4096);
  109 + __init_end = .;
  110 +
  111 + __bss_start = .;
  112 + .bss :
  113 + {
  114 + *(.sbss) *(.scommon)
  115 + *(.dynbss)
  116 + *(.bss)
  117 + *(COMMON)
  118 + }
  119 + _end = . ;
  120 + PROVIDE (end = .);
  121 +}
  122 +ENTRY(_start)
... ... @@ -158,8 +158,8 @@
158 158 /*----------------------------------------------------------------*/
159 159 /* Clear and set up some registers. */
160 160 /*----------------------------------------------------------------*/
161   - iccci r0,r0 /* NOTE: operands not used for 440 */
162   - dccci r0,r0 /* NOTE: operands not used for 440 */
  161 + iccci r0,r0 /* NOTE: operands not used for 440 */
  162 + dccci r0,r0 /* NOTE: operands not used for 440 */
163 163 sync
164 164 li r0,0
165 165 mtspr srr0,r0
... ... @@ -167,10 +167,10 @@
167 167 mtspr csrr0,r0
168 168 mtspr csrr1,r0
169 169 #if defined (CONFIG_440_GX) /* NOTE: 440GX adds machine check status regs */
170   - mtspr mcsrr0,r0
171   - mtspr mcsrr1,r0
172   - mfspr r1, mcsr
173   - mtspr mcsr,r1
  170 + mtspr mcsrr0,r0
  171 + mtspr mcsrr1,r0
  172 + mfspr r1, mcsr
  173 + mtspr mcsr,r1
174 174 #endif
175 175 /*----------------------------------------------------------------*/
176 176 /* Initialize debug */
177 177  
178 178  
179 179  
... ... @@ -204,13 +204,13 @@
204 204 /* Setup interrupt vectors */
205 205 /*----------------------------------------------------------------*/
206 206 mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */
207   - li r1,0x0100
  207 + li r1,0x0100
208 208 mtspr ivor0,r1 /* Critical input */
209   - li r1,0x0200
  209 + li r1,0x0200
210 210 mtspr ivor1,r1 /* Machine check */
211   - li r1,0x0300
  211 + li r1,0x0300
212 212 mtspr ivor2,r1 /* Data storage */
213   - li r1,0x0400
  213 + li r1,0x0400
214 214 mtspr ivor3,r1 /* Instruction storage */
215 215 li r1,0x0500
216 216 mtspr ivor4,r1 /* External interrupt */
... ... @@ -349,8 +349,8 @@
349 349 b __440gx_msr_continue
350 350  
351 351 __440gx_msr_set:
352   - lis r1, 0x0002 /* set CE bit (Critical Exceptions) */
353   - ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */
  352 + lis r1, 0x0002 /* set CE bit (Critical Exceptions) */
  353 + ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */
354 354 mtspr srr1,r1
355 355 mflr r1
356 356 mtspr srr0,r1
357 357  
358 358  
359 359  
360 360  
... ... @@ -379,23 +379,23 @@
379 379 li r0,0
380 380 #if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
381 381 /* Clear Dcache to use as RAM */
382   - addis r3,r0,CFG_INIT_RAM_ADDR@h
383   - ori r3,r3,CFG_INIT_RAM_ADDR@l
384   - addis r4,r0,CFG_INIT_RAM_END@h
385   - ori r4,r4,CFG_INIT_RAM_END@l
  382 + addis r3,r0,CFG_INIT_RAM_ADDR@h
  383 + ori r3,r3,CFG_INIT_RAM_ADDR@l
  384 + addis r4,r0,CFG_INIT_RAM_END@h
  385 + ori r4,r4,CFG_INIT_RAM_END@l
386 386 rlwinm. r5,r4,0,27,31
387   - rlwinm r5,r4,27,5,31
388   - beq ..d_ran
389   - addi r5,r5,0x0001
  387 + rlwinm r5,r4,27,5,31
  388 + beq ..d_ran
  389 + addi r5,r5,0x0001
390 390 ..d_ran:
391   - mtctr r5
  391 + mtctr r5
392 392 ..d_ag:
393   - dcbz r0,r3
394   - addi r3,r3,32
395   - bdnz ..d_ag
  393 + dcbz r0,r3
  394 + addi r3,r3,32
  395 + bdnz ..d_ag
396 396 #else
397 397 #if defined (CONFIG_440_GX)
398   - mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
  398 + mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
399 399 #endif
400 400 mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
401 401  
402 402  
403 403  
404 404  
... ... @@ -411,16 +411,16 @@
411 411 lis r1,0x8000 /* BAS = 8000_0000 */
412 412 #if defined(CONFIG_440_GX)
413 413 ori r1,r1,0x0980 /* first 64k */
414   - mtdcr isram0_sb0cr,r1
  414 + mtdcr isram0_sb0cr,r1
415 415 lis r1,0x8001
416 416 ori r1,r1,0x0980 /* second 64k */
417   - mtdcr isram0_sb1cr,r1
  417 + mtdcr isram0_sb1cr,r1
418 418 lis r1, 0x8002
419 419 ori r1,r1, 0x0980 /* third 64k */
420   - mtdcr isram0_sb2cr,r1
  420 + mtdcr isram0_sb2cr,r1
421 421 lis r1, 0x8003
422 422 ori r1,r1, 0x0980 /* fourth 64k */
423   - mtdcr isram0_sb3cr,r1
  423 + mtdcr isram0_sb3cr,r1
424 424 #else
425 425 ori r1,r1,0x0380 /* 8k rw */
426 426 mtdcr isram0_sb0cr,r1
427 427  
... ... @@ -610,11 +610,11 @@
610 610 /*----------------------------------------------------------------------- */
611 611 /* DMA Status, clear to come up clean */
612 612 /*----------------------------------------------------------------------- */
613   - addis r3,r0, 0xFFFF /* Clear all existing DMA status */
614   - ori r3,r3, 0xFFFF
615   - mtdcr dmasr, r3
  613 + addis r3,r0, 0xFFFF /* Clear all existing DMA status */
  614 + ori r3,r3, 0xFFFF
  615 + mtdcr dmasr, r3
616 616  
617   - bl ppc405ep_init /* do ppc405ep specific init */
  617 + bl ppc405ep_init /* do ppc405ep specific init */
618 618 #endif /* CONFIG_405EP */
619 619  
620 620 #if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
... ... @@ -624,7 +624,7 @@
624 624 /* Setup OCM */
625 625 lis r0, 0x7FFF
626 626 ori r0, r0, 0xFFFF
627   - mfdcr r3, ocmiscntl /* get instr-side IRAM config */
  627 + mfdcr r3, ocmiscntl /* get instr-side IRAM config */
628 628 mfdcr r4, ocmdscntl /* get data-side IRAM config */
629 629 and r3, r3, r0 /* disable data-side IRAM */
630 630 and r4, r4, r0 /* disable data-side IRAM */
631 631  
... ... @@ -666,13 +666,13 @@
666 666 /* set stack pointer and clear stack to known value */
667 667  
668 668 lis r1,CFG_INIT_RAM_ADDR@h
669   - ori r1,r1,CFG_INIT_SP_OFFSET@l
  669 + ori r1,r1,CFG_INIT_SP_OFFSET@l
670 670  
671 671 li r4,2048 /* we store 2048 words to stack */
672 672 mtctr r4
673 673  
674 674 lis r2,CFG_INIT_RAM_ADDR@h /* we also clear data area */
675   - ori r2,r2,CFG_INIT_RAM_END@l /* so cant copy value from r1 */
  675 + ori r2,r2,CFG_INIT_RAM_END@l /* so cant copy value from r1 */
676 676  
677 677 lis r4,0xdead /* we store 0xdeaddead in the stack */
678 678 ori r4,r4,0xdead
... ... @@ -721,7 +721,7 @@
721 721 #endif /* CFG_INIT_DCACHE_CS */
722 722  
723 723 /*----------------------------------------------------------------------- */
724   - /* Initialize SDRAM Controller */
  724 + /* Initialize SDRAM Controller */
725 725 /*----------------------------------------------------------------------- */
726 726 bl sdram_init
727 727  
728 728  
... ... @@ -747,11 +747,11 @@
747 747 ori r0, r0, RESET_VECTOR@l
748 748 stwu r1, -8(r1) /* Save back chain and move SP */
749 749 stw r0, +12(r1) /* Save return addr (underflow vect) */
750   -#endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */
  750 +#endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */
751 751  
752 752 GET_GOT /* initialize GOT access */
753 753  
754   - bl cpu_init_f /* run low-level CPU init code (from Flash) */
  754 + bl cpu_init_f /* run low-level CPU init code (from Flash) */
755 755  
756 756 /* NEVER RETURNS! */
757 757 bl board_init_f /* run first part of init code (from Flash) */
... ... @@ -976,8 +976,8 @@
976 976 addi r6,0,0x0000 /* clear GPR 6 */
977 977 /* Do loop for # of dcache congruence classes. */
978 978 #if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
979   - lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */
980   - ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
  979 + lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */
  980 + ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
981 981 #else
982 982 addi r7,r0, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
983 983 #endif
984 984  
... ... @@ -1002,16 +1002,16 @@
1002 1002  
1003 1003 /* do loop for # of congruence classes. */
1004 1004 #if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
1005   - lis r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS: for large cache sizes */
1006   - ori r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
1007   - lis r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */
1008   - ori r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */
  1005 + lis r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS: for large cache sizes */
  1006 + ori r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
  1007 + lis r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */
  1008 + ori r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */
1009 1009 #else
1010 1010 addi r10,r0,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
1011 1011 addi r11,r0,(CFG_DCACHE_SIZE / 2) /* D cache set size - 2 way sets */
1012 1012 #endif
1013 1013 mtctr r10
1014   - addi r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */
  1014 + addi r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */
1015 1015 add r11,r10,r11 /* add to get to other side of cache line */
1016 1016 ..flush_dcache_loop:
1017 1017 lwz r3,0(r10) /* least recently used side */
1018 1018  
1019 1019  
... ... @@ -1229,12 +1229,12 @@
1229 1229 .globl relocate_code
1230 1230 relocate_code:
1231 1231 #if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
1232   - dccci 0,0 /* Invalidate data cache, now no longer our stack */
  1232 + dccci 0,0 /* Invalidate data cache, now no longer our stack */
1233 1233 sync
1234   - addi r1,r0,0x0000 /* Tlb entry #0 */
  1234 + addi r1,r0,0x0000 /* Tlb entry #0 */
1235 1235 tlbre r0,r1,0x0002 /* Read contents */
1236   - ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1237   - tlbwe r0,r1,0x0002 /* Save it out */
  1236 + ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
  1237 + tlbwe r0,r1,0x0002 /* Save it out */
1238 1238 isync
1239 1239 #endif
1240 1240 mr r1, r3 /* Set new stack pointer */
... ... @@ -1455,7 +1455,7 @@
1455 1455  
1456 1456  
1457 1457 /**************************************************************************/
1458   -/* PPC405EP specific stuff */
  1458 +/* PPC405EP specific stuff */
1459 1459 /**************************************************************************/
1460 1460 #ifdef CONFIG_405EP
1461 1461 ppc405ep_init:
... ... @@ -1539,7 +1539,7 @@
1539 1539 mtdcr ebccfgd,r3
1540 1540 #endif
1541 1541  
1542   - addi r3,0,CPC0_PCI_HOST_CFG_EN
  1542 + addi r3,0,CPC0_PCI_HOST_CFG_EN
1543 1543 #ifdef CONFIG_BUBINGA
1544 1544 /*
1545 1545 !-----------------------------------------------------------------------
1546 1546  
1547 1547  
1548 1548  
1549 1549  
1550 1550  
... ... @@ -1547,30 +1547,30 @@
1547 1547 ! If board is set to internal arbitration, update cpc0_pci
1548 1548 !-----------------------------------------------------------------------
1549 1549 */
1550   - addis r5,r0,FPGA_REG1@h /* set offset for FPGA_REG1 */
1551   - ori r5,r5,FPGA_REG1@l
1552   - lbz r5,0x0(r5) /* read to get PCI arb selection */
1553   - andi. r6,r5,FPGA_REG1_PCI_INT_ARB /* using internal arbiter ?*/
1554   - beq ..pci_cfg_set /* if not set, then bypass reg write*/
  1550 + addis r5,r0,FPGA_REG1@h /* set offset for FPGA_REG1 */
  1551 + ori r5,r5,FPGA_REG1@l
  1552 + lbz r5,0x0(r5) /* read to get PCI arb selection */
  1553 + andi. r6,r5,FPGA_REG1_PCI_INT_ARB /* using internal arbiter ?*/
  1554 + beq ..pci_cfg_set /* if not set, then bypass reg write*/
1555 1555 #endif
1556   - ori r3,r3,CPC0_PCI_ARBIT_EN
  1556 + ori r3,r3,CPC0_PCI_ARBIT_EN
1557 1557 ..pci_cfg_set:
1558   - mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/
  1558 + mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/
1559 1559  
1560 1560 /*
1561 1561 !-----------------------------------------------------------------------
1562 1562 ! Check to see if chip is in bypass mode.
1563 1563 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1564 1564 ! CPU reset Otherwise, skip this step and keep going.
1565   - ! Note: Running BIOS in bypass mode is not supported since PLB speed
1566   - ! will not be fast enough for the SDRAM (min 66MHz)
  1565 + ! Note: Running BIOS in bypass mode is not supported since PLB speed
  1566 + ! will not be fast enough for the SDRAM (min 66MHz)
1567 1567 !-----------------------------------------------------------------------
1568 1568 */
1569   - mfdcr r5, CPC0_PLLMR1
1570   - rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1571   - cmpi cr0,0,r4,0x1
  1569 + mfdcr r5, CPC0_PLLMR1
  1570 + rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
  1571 + cmpi cr0,0,r4,0x1
1572 1572  
1573   - beq pll_done /* if SSCS =b'1' then PLL has */
  1573 + beq pll_done /* if SSCS =b'1' then PLL has */
1574 1574 /* already been set */
1575 1575 /* and CPU has been reset */
1576 1576 /* so skip to next section */
1577 1577  
1578 1578  
1579 1579  
1580 1580  
... ... @@ -1584,40 +1584,40 @@
1584 1584 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1585 1585 !
1586 1586 ! WARNING: This code assumes the first three words in the nvram_t
1587   - ! structure in openbios.h. Changing the beginning of
1588   - ! the structure will break this code.
  1587 + ! structure in openbios.h. Changing the beginning of
  1588 + ! the structure will break this code.
1589 1589 !
1590 1590 !-----------------------------------------------------------------------
1591 1591 */
1592   - addis r3,0,NVRAM_BASE@h
1593   - addi r3,r3,NVRAM_BASE@l
  1592 + addis r3,0,NVRAM_BASE@h
  1593 + addi r3,r3,NVRAM_BASE@l
1594 1594  
1595   - lwz r4, 0(r3)
1596   - addis r5,0,NVRVFY1@h
1597   - addi r5,r5,NVRVFY1@l
1598   - cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1599   - bne ..no_pllset
1600   - addi r3,r3,4
1601   - lwz r4, 0(r3)
1602   - addis r5,0,NVRVFY2@h
1603   - addi r5,r5,NVRVFY2@l
1604   - cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1605   - bne ..no_pllset
1606   - addi r3,r3,8 /* Skip over conf_size */
1607   - lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1608   - lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1609   - rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1610   - cmpi cr0,0,r5,1 /* See if PLL is locked */
1611   - beq pll_write
  1595 + lwz r4, 0(r3)
  1596 + addis r5,0,NVRVFY1@h
  1597 + addi r5,r5,NVRVFY1@l
  1598 + cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
  1599 + bne ..no_pllset
  1600 + addi r3,r3,4
  1601 + lwz r4, 0(r3)
  1602 + addis r5,0,NVRVFY2@h
  1603 + addi r5,r5,NVRVFY2@l
  1604 + cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
  1605 + bne ..no_pllset
  1606 + addi r3,r3,8 /* Skip over conf_size */
  1607 + lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
  1608 + lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
  1609 + rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
  1610 + cmpi cr0,0,r5,1 /* See if PLL is locked */
  1611 + beq pll_write
1612 1612 ..no_pllset:
1613 1613 #endif /* CONFIG_BUBINGA */
1614 1614  
1615   - addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1616   - ori r3,r3,PLLMR0_DEFAULT@l /* */
1617   - addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1618   - ori r4,r4,PLLMR1_DEFAULT@l /* */
  1615 + addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
  1616 + ori r3,r3,PLLMR0_DEFAULT@l /* */
  1617 + addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
  1618 + ori r4,r4,PLLMR1_DEFAULT@l /* */
1619 1619  
1620   - b pll_write /* Write the CPC0_PLLMR with new value */
  1620 + b pll_write /* Write the CPC0_PLLMR with new value */
1621 1621  
1622 1622 pll_done:
1623 1623 /*
1624 1624  
1625 1625  
1626 1626  
... ... @@ -1626,27 +1626,27 @@
1626 1626 ! This is needed to enable PCI if not booting from serial EPROM
1627 1627 !-----------------------------------------------------------------------
1628 1628 */
1629   - addi r3, 0, 0x0
1630   - mtdcr CPC0_SRR, r3
  1629 + addi r3, 0, 0x0
  1630 + mtdcr CPC0_SRR, r3
1631 1631  
1632   - addis r3,0,0x0010
1633   - mtctr r3
  1632 + addis r3,0,0x0010
  1633 + mtctr r3
1634 1634 pci_wait:
1635   - bdnz pci_wait
  1635 + bdnz pci_wait
1636 1636  
1637 1637 blr /* return to main code */
1638 1638  
1639 1639 /*
1640 1640 !-----------------------------------------------------------------------------
1641   -! Function: pll_write
1642   -! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1643   -! That is:
1644   -! 1. Pll is first disabled (de-activated by putting in bypass mode)
1645   -! 2. PLL is reset
1646   -! 3. Clock dividers are set while PLL is held in reset and bypassed
1647   -! 4. PLL Reset is cleared
1648   -! 5. Wait 100us for PLL to lock
1649   -! 6. A core reset is performed
  1641 +! Function: pll_write
  1642 +! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
  1643 +! That is:
  1644 +! 1. Pll is first disabled (de-activated by putting in bypass mode)
  1645 +! 2. PLL is reset
  1646 +! 3. Clock dividers are set while PLL is held in reset and bypassed
  1647 +! 4. PLL Reset is cleared
  1648 +! 5. Wait 100us for PLL to lock
  1649 +! 6. A core reset is performed
1650 1650 ! Input: r3 = Value to write to CPC0_PLLMR0
1651 1651 ! Input: r4 = Value to write to CPC0_PLLMR1
1652 1652 ! Output r3 = none
1653 1653  
1654 1654  
1655 1655  
1656 1656  
1657 1657  
1658 1658  
... ... @@ -1655,41 +1655,41 @@
1655 1655 pll_write:
1656 1656 mfdcr r5, CPC0_UCR
1657 1657 andis. r5,r5,0xFFFF
1658   - ori r5,r5,0x0101 /* Stop the UART clocks */
1659   - mtdcr CPC0_UCR,r5 /* Before changing PLL */
  1658 + ori r5,r5,0x0101 /* Stop the UART clocks */
  1659 + mtdcr CPC0_UCR,r5 /* Before changing PLL */
1660 1660  
1661 1661 mfdcr r5, CPC0_PLLMR1
1662   - rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
1663   - mtdcr CPC0_PLLMR1,r5
1664   - oris r5,r5,0x4000 /* Set PLL Reset */
1665   - mtdcr CPC0_PLLMR1,r5
  1662 + rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
  1663 + mtdcr CPC0_PLLMR1,r5
  1664 + oris r5,r5,0x4000 /* Set PLL Reset */
  1665 + mtdcr CPC0_PLLMR1,r5
1666 1666  
1667   - mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
1668   - rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
1669   - oris r5,r5,0x4000 /* Set PLL Reset */
1670   - mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
1671   - rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
1672   - mtdcr CPC0_PLLMR1,r5
  1667 + mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
  1668 + rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
  1669 + oris r5,r5,0x4000 /* Set PLL Reset */
  1670 + mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
  1671 + rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
  1672 + mtdcr CPC0_PLLMR1,r5
1673 1673  
1674 1674 /*
1675 1675 ! Wait min of 100us for PLL to lock.
1676 1676 ! See CMOS 27E databook for more info.
1677 1677 ! At 200MHz, that means waiting 20,000 instructions
1678 1678 */
1679   - addi r3,0,20000 /* 2000 = 0x4e20 */
1680   - mtctr r3
  1679 + addi r3,0,20000 /* 2000 = 0x4e20 */
  1680 + mtctr r3
1681 1681 pll_wait:
1682   - bdnz pll_wait
  1682 + bdnz pll_wait
1683 1683  
1684   - oris r5,r5,0x8000 /* Enable PLL */
1685   - mtdcr CPC0_PLLMR1,r5 /* Engage */
  1684 + oris r5,r5,0x8000 /* Enable PLL */
  1685 + mtdcr CPC0_PLLMR1,r5 /* Engage */
1686 1686  
1687 1687 /*
1688 1688 * Reset CPU to guarantee timings are OK
1689 1689 * Not sure if this is needed...
1690 1690 */
1691 1691 addis r3,0,0x1000
1692   - mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
  1692 + mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
1693 1693 /* execution will continue from the poweron */
1694 1694 /* vector of 0xfffffffc */
1695 1695 #endif /* CONFIG_405EP */
doc/README.mpc83xxads
Diff comments   View file @ f901a83
... ... @@ -3,9 +3,11 @@
3 3  
4 4 0. Toolchain / Building
5 5  
6   - % setenv CROSS_COMPILE /usr/powerpc/bin/powerpc-linux-
  6 + $ PATH=$PATH:/usr/powerpc/bin
  7 + $ CROSS_COMPILE=powerpc-linux-
  8 + $ export PATH CROSS_COMPILE
7 9  
8   - % /usr/powerpc/bin/powerpc-linux-gcc -v
  10 + $ powerpc-linux-gcc -v
9 11 Reading specs from /usr/powerpc/lib/gcc/powerpc-linux/3.4.3/specs
10 12 Configured with: ../configure --prefix=/usr/powerpc
11 13 --exec-prefix=/usr/powerpc --target=powerpc-linux --enable-shared
12 14  
13 15  
... ... @@ -13,14 +15,14 @@
13 15 Thread model: posix
14 16 gcc version 3.4.3 (Debian)
15 17  
16   - % /usr/powerpc/bin/powerpc-linux-as -v
  18 + $ powerpc-linux-as -v
17 19 GNU assembler version 2.15 (powerpc-linux) using BFD version 2.15
18 20  
19 21  
20   - % make MPC8349ADS_config
  22 + $ make MPC8349ADS_config
21 23 Configuring for MPC8349ADS board...
22 24  
23   - % make
  25 + $ make
24 26  
25 27  
26 28 1. Board Switches and Jumpers
... ... @@ -76,7 +78,7 @@
76 78  
77 79 Or via tftp:
78 80  
79   - tftp 10000 u-boot.bin
  81 + tftp 10000 u-boot.bin
80 82  
81 83 5.1 Reflash U-boot Image using U-boot
82 84  
include/configs/ep8248.h
Diff comments   View file @ f901a83
  1 +/*
  2 + * Copyright (C) 2004 Arabella Software Ltd.
  3 + * Yuli Barcohen <yuli@arabellasw.com>
  4 + *
  5 + * U-Boot configuration for Embedded Planet EP8248 boards.
  6 + *
  7 + * See file CREDITS for list of people who contributed to this
  8 + * project.
  9 + *
  10 + * This program is free software; you can redistribute it and/or
  11 + * modify it under the terms of the GNU General Public License as
  12 + * published by the Free Software Foundation; either version 2 of
  13 + * the License, or (at your option) any later version.
  14 + *
  15 + * This program is distributed in the hope that it will be useful,
  16 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18 + * GNU General Public License for more details.
  19 + *
  20 + * You should have received a copy of the GNU General Public License
  21 + * along with this program; if not, write to the Free Software
  22 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 + * MA 02111-1307 USA
  24 + */
  25 +
  26 +#ifndef __CONFIG_H
  27 +#define __CONFIG_H
  28 +
  29 +#define CONFIG_MPC8248
  30 +#define CPU_ID_STR "MPC8248"
  31 +
  32 +#define CONFIG_EP8248 /* Embedded Planet EP8248 board */
  33 +
  34 +#undef DEBUG
  35 +
  36 +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
  37 +
  38 +/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
  39 +#define CONFIG_ENV_OVERWRITE
  40 +
  41 +/*
  42 + * Select serial console configuration
  43 + *
  44 + * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  45 + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  46 + * for SCC).
  47 + */
  48 +#define CONFIG_CONS_ON_SMC /* Console is on SMC */
  49 +#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
  50 +#undef CONFIG_CONS_NONE /* It's not on external UART */
  51 +#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
  52 +
  53 +#define CFG_BCSR 0xFA000000
  54 +
  55 +/*
  56 + * Select ethernet configuration
  57 + *
  58 + * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
  59 + * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
  60 + * SCC, 1-3 for FCC)
  61 + *
  62 + * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
  63 + * must be defined elsewhere (as for the console), or CFG_CMD_NET must
  64 + * be removed from CONFIG_COMMANDS to remove support for networking.
  65 + */
  66 +#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
  67 +#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
  68 +#undef CONFIG_ETHER_NONE /* No external Ethernet */
  69 +
  70 +#ifdef CONFIG_ETHER_ON_FCC
  71 +
  72 +#define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */
  73 +
  74 +#if (CONFIG_ETHER_INDEX == 1)
  75 +
  76 +/* - Rx clock is CLK10
  77 + * - Tx clock is CLK11
  78 + * - BDs/buffers on 60x bus
  79 + * - Full duplex
  80 + */
  81 +#define CFG_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
  82 +#define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11)
  83 +#define CFG_CPMFCR_RAMTYPE 0
  84 +#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
  85 +
  86 +#elif (CONFIG_ETHER_INDEX == 2)
  87 +
  88 +/* - Rx clock is CLK13
  89 + * - Tx clock is CLK14
  90 + * - BDs/buffers on 60x bus
  91 + * - Full duplex
  92 + */
  93 +#define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  94 +#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
  95 +#define CFG_CPMFCR_RAMTYPE 0
  96 +#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
  97 +
  98 +#endif /* CONFIG_ETHER_INDEX */
  99 +
  100 +#define CONFIG_MII /* MII PHY management */
  101 +#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
  102 +/*
  103 + * GPIO pins used for bit-banged MII communications
  104 + */
  105 +#define MDIO_PORT 0 /* Not used - implemented in BCSR */
  106 +#define MDIO_ACTIVE (*(vu_char *)(CFG_BCSR + 8) &= 0xFB)
  107 +#define MDIO_TRISTATE (*(vu_char *)(CFG_BCSR + 8) |= 0x04)
  108 +#define MDIO_READ (*(vu_char *)(CFG_BCSR + 8) & 1)
  109 +
  110 +#define MDIO(bit) if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x01; \
  111 + else *(vu_char *)(CFG_BCSR + 8) &= 0xFE
  112 +
  113 +#define MDC(bit) if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x02; \
  114 + else *(vu_char *)(CFG_BCSR + 8) &= 0xFD
  115 +
  116 +#define MIIDELAY udelay(1)
  117 +
  118 +#endif /* CONFIG_ETHER_ON_FCC */
  119 +
  120 +#ifndef CONFIG_8260_CLKIN
  121 +#define CONFIG_8260_CLKIN 66000000 /* in Hz */
  122 +#endif
  123 +
  124 +#define CONFIG_BAUDRATE 38400
  125 +
  126 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
  127 + | CFG_CMD_DHCP \
  128 + | CFG_CMD_ECHO \
  129 + | CFG_CMD_I2C \
  130 + | CFG_CMD_IMMAP \
  131 + | CFG_CMD_MII \
  132 + | CFG_CMD_PING \
  133 + )
  134 +
  135 +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  136 +#include <cmd_confdefs.h>
  137 +
  138 +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  139 +#define CONFIG_BOOTCOMMAND "bootm FF860000" /* autoboot command */
  140 +#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro"
  141 +
  142 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  143 +#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
  144 +#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
  145 +#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
  146 +#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */
  147 +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
  148 +#endif
  149 +
  150 +#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
  151 +#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
  152 +
  153 +/*
  154 + * Miscellaneous configurable options
  155 + */
  156 +#define CFG_HUSH_PARSER
  157 +#define CFG_PROMPT_HUSH_PS2 "> "
  158 +#define CFG_LONGHELP /* undef to save memory */
  159 +#define CFG_PROMPT "=> " /* Monitor Command Prompt */
  160 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  161 +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  162 +#else
  163 +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  164 +#endif
  165 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  166 +#define CFG_MAXARGS 16 /* max number of command args */
  167 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  168 +
  169 +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
  170 +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
  171 +
  172 +#define CFG_LOAD_ADDR 0x100000 /* default load address */
  173 +
  174 +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  175 +
  176 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
  177 +
  178 +#define CFG_FLASH_BASE 0xFF800000
  179 +#define CFG_FLASH_CFI
  180 +#define CFG_FLASH_CFI_DRIVER
  181 +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
  182 +#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
  183 +
  184 +#define CFG_DIRECT_FLASH_TFTP
  185 +
  186 +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
  187 +#define CFG_JFFS2_FIRST_BANK 0
  188 +#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS
  189 +#define CFG_JFFS2_FIRST_SECTOR 0
  190 +#define CFG_JFFS2_LAST_SECTOR 62
  191 +#define CFG_JFFS2_SORT_FRAGMENTS
  192 +#define CFG_JFFS_CUSTOM_PART
  193 +#endif /* CFG_CMD_JFFS2 */
  194 +
  195 +#if (CONFIG_COMMANDS & CFG_CMD_I2C)
  196 +#define CONFIG_HARD_I2C 1 /* To enable I2C support */
  197 +#define CFG_I2C_SPEED 100000 /* I2C speed */
  198 +#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
  199 +#endif /* CFG_CMD_I2C */
  200 +
  201 +#define CFG_MONITOR_BASE TEXT_BASE
  202 +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
  203 +#define CFG_RAMBOOT
  204 +#endif
  205 +
  206 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
  207 +
  208 +#define CFG_ENV_IS_IN_FLASH
  209 +
  210 +#ifdef CFG_ENV_IS_IN_FLASH
  211 +#define CFG_ENV_SECT_SIZE 0x20000
  212 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
  213 +#endif /* CFG_ENV_IS_IN_FLASH */
  214 +
  215 +#define CFG_DEFAULT_IMMR 0x00010000
  216 +
  217 +#define CFG_IMMR 0xF0000000
  218 +
  219 +#define CFG_INIT_RAM_ADDR CFG_IMMR
  220 +#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
  221 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  222 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  223 +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  224 +
  225 +/* Hard reset configuration word */
  226 +#define CFG_HRCW_MASTER 0x0C40025A /* Not used - provided by FPGA */
  227 +/* No slaves */
  228 +#define CFG_HRCW_SLAVE1 0
  229 +#define CFG_HRCW_SLAVE2 0
  230 +#define CFG_HRCW_SLAVE3 0
  231 +#define CFG_HRCW_SLAVE4 0
  232 +#define CFG_HRCW_SLAVE5 0
  233 +#define CFG_HRCW_SLAVE6 0
  234 +#define CFG_HRCW_SLAVE7 0
  235 +
  236 +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  237 +#define BOOTFLAG_WARM 0x02 /* Software reboot */
  238 +
  239 +#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
  240 +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  241 +
  242 +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
  243 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  244 +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  245 +#endif
  246 +
  247 +#define CFG_HID0_INIT 0
  248 +#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
  249 +
  250 +#define CFG_HID2 0
  251 +
  252 +#define CFG_SIUMCR 0x01240200
  253 +#define CFG_SYPCR 0xFFFF0683
  254 +#define CFG_BCR 0x00000000
  255 +#define CFG_SCCR SCCR_DFBRG01
  256 +
  257 +#define CFG_RMR RMR_CSRE
  258 +#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
  259 +#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
  260 +#define CFG_RCCR 0
  261 +
  262 +#define CFG_MPTPR 0x1300
  263 +#define CFG_PSDMR 0x82672522
  264 +#define CFG_PSRT 0x4B
  265 +
  266 +#define CFG_SDRAM_BASE 0x00000000
  267 +#define CFG_SDRAM_BR (CFG_SDRAM_BASE | 0x00001841)
  268 +#define CFG_SDRAM_OR 0xFF0030C0
  269 +
  270 +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00001801)
  271 +#define CFG_OR0_PRELIM 0xFF8008C2
  272 +#define CFG_BR2_PRELIM (CFG_BCSR | 0x00000801)
  273 +#define CFG_OR2_PRELIM 0xFFF00864
  274 +
  275 +#define CFG_RESET_ADDRESS 0xC0000000
  276 +
  277 +#endif /* __CONFIG_H */