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Commit f9023afbdfd9f27e7c38f3cce965746e56d62dd3

Authored by Anton Vorontsov
Committed by Kim Phillips
1 parent bf30bb1f7c
Exists in master and in 55 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

83xx/85xx: further localbus cleanups 

move the BRx_* and ORx_* left behind in mpc85xx.h

The same is needed for mpc8xx.h and mpc8260.h (defines are almost
the same, just few differences which needs some attention though).

But the bad news for mpc8xx and mpc8260 is that there are a lot of users
of these defines. So this cleanup I'll leave for the "better times".

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

Showing 9 changed files with 23 additions and 45 deletions Side-by-side Diff

include/asm-ppc/fsl_lbc.h
Diff comments   View file @ f9023af
... ... @@ -44,7 +44,11 @@
44 44 #define BR_MSEL_SHIFT 5
45 45 #define BR_MS_GPCM 0x00000000 /* GPCM */
46 46 #define BR_MS_FCM 0x00000020 /* FCM */
  47 +#ifdef CONFIG_MPC83xx
47 48 #define BR_MS_SDRAM 0x00000060 /* SDRAM */
  49 +#elif defined(CONFIG_MPC85xx)
  50 +#define BR_MS_SDRAM 0x00000000 /* SDRAM */
  51 +#endif
48 52 #define BR_MS_UPMA 0x00000080 /* UPMA */
49 53 #define BR_MS_UPMB 0x000000A0 /* UPMB */
50 54 #define BR_MS_UPMC 0x000000C0 /* UPMC */
... ... @@ -80,8 +84,8 @@
80 84 #define OR_GPCM_CSNT_SHIFT 11
81 85 #define OR_GPCM_ACS 0x00000600
82 86 #define OR_GPCM_ACS_SHIFT 9
83   -#define OR_GPCM_ACS_0b10 0x00000400
84   -#define OR_GPCM_ACS_0b11 0x00000600
  87 +#define OR_GPCM_ACS_DIV2 0x00000600
  88 +#define OR_GPCM_ACS_DIV4 0x00000400
85 89 #define OR_GPCM_XACS 0x00000100
86 90 #define OR_GPCM_XACS_SHIFT 8
87 91 #define OR_GPCM_SCY 0x000000F0
... ... @@ -110,6 +114,10 @@
110 114 #define OR_GPCM_EAD 0x00000001
111 115 #define OR_GPCM_EAD_SHIFT 0
112 116  
  117 +/* helpers to convert values into an OR address mask (GPCM mode) */
  118 +#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
  119 +#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20)
  120 +
113 121 #define OR_FCM_AM 0xFFFF8000
114 122 #define OR_FCM_AM_SHIFT 15
115 123 #define OR_FCM_BCTLD 0x00001000
... ... @@ -152,6 +160,11 @@
152 160 #define OR_UPM_EHTR_SHIFT 1
153 161 #define OR_UPM_EAD 0x00000001
154 162 #define OR_UPM_EAD_SHIFT 0
  163 +
  164 +#define MxMR_OP_NORM 0x00000000 /* Normal Operation */
  165 +#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */
  166 +#define MxMR_OP_WARR 0x10000000 /* Write to Array */
  167 +#define MxMR_BSEL 0x80000000 /* Bus Select */
155 168  
156 169 #define OR_SDRAM_AM 0xFFFF8000
157 170 #define OR_SDRAM_AM_SHIFT 15
include/configs/MPC8315ERDB.h
Diff comments   View file @ f9023af
... ... @@ -203,7 +203,7 @@
203 203 #define CFG_OR0_PRELIM ( (~(CFG_FLASH_SIZE - 1) << 20) \
204 204 | OR_UPM_XAM \
205 205 | OR_GPCM_CSNT \
206   - | OR_GPCM_ACS_0b11 \
  206 + | OR_GPCM_ACS_DIV2 \
207 207 | OR_GPCM_XACS \
208 208 | OR_GPCM_SCY_15 \
209 209 | OR_GPCM_TRLX \
include/configs/MPC8349EMDS.h
Diff comments   View file @ f9023af
... ... @@ -157,7 +157,7 @@
157 157 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
158 158 BR_V) /* valid */
159 159 #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
160   - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
  160 + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
161 161 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
162 162 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */
163 163 #define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */
include/configs/MPC8349ITX.h
Diff comments   View file @ f9023af
... ... @@ -211,7 +211,7 @@
211 211  
212 212 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V)
213 213 #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
214   - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
  214 + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
215 215 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
216 216 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE
217 217 #define CFG_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT))
... ... @@ -236,7 +236,7 @@
236 236  
237 237 #define CFG_LED_BASE 0xF9000000
238 238 #define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V)
239   -#define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \
  239 +#define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
240 240 OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \
241 241 OR_GPCM_EHTR | OR_GPCM_EAD)
242 242  
include/configs/MPC8360EMDS.h
Diff comments   View file @ f9023af
... ... @@ -203,7 +203,7 @@
203 203 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
204 204 BR_V) /* valid */
205 205 #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
206   - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
  206 + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
207 207 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
208 208  
209 209 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
include/configs/MPC8360ERDK.h
Diff comments   View file @ f9023af
... ... @@ -195,7 +195,7 @@
195 195 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
196 196 BR_V) /* valid */
197 197 #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
198   - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \
  198 + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
199 199 OR_GPCM_XACS | OR_GPCM_SCY_15 | \
200 200 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
201 201  
include/configs/MPC837XEMDS.h
Diff comments   View file @ f9023af
... ... @@ -239,7 +239,7 @@
239 239 #define CFG_OR0_PRELIM ( (~(CFG_FLASH_SIZE - 1) << 20) \
240 240 | OR_UPM_XAM \
241 241 | OR_GPCM_CSNT \
242   - | OR_GPCM_ACS_0b11 \
  242 + | OR_GPCM_ACS_DIV2 \
243 243 | OR_GPCM_XACS \
244 244 | OR_GPCM_SCY_15 \
245 245 | OR_GPCM_TRLX \
include/configs/TQM834x.h
Diff comments   View file @ f9023af
... ... @@ -113,7 +113,7 @@
113 113 BR_MS_GPCM | BR_PS_32 | BR_V)
114 114  
115 115 /* FLASH timing (0x0000_0c54) */
116   -#define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_0b10 | \
  116 +#define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | \
117 117 OR_GPCM_SCY_5 | OR_GPCM_TRLX)
118 118  
119 119 #define CFG_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */
... ... @@ -28,40 +28,5 @@
28 28 #define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */
29 29 #define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */
30 30  
31   -/*
32   - * Local Bus Controller - memory controller registers
33   - */
34   -#define BRx_V 0x00000001 /* Bank Valid */
35   -#define BRx_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */
36   -#define BRx_MS_SDRAM 0x00000000 /* SDRAM Machine Select */
37   -#define BRx_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */
38   -#define BRx_MS_UPMB 0x000000a0 /* U.P.M.B Machine Select */
39   -#define BRx_MS_UPMC 0x000000c0 /* U.P.M.C Machine Select */
40   -#define BRx_PS_8 0x00000800 /* 8 bit port size */
41   -#define BRx_PS_32 0x00001800 /* 32 bit port size */
42   -#define BRx_BA_MSK 0xffff8000 /* Base Address Mask */
43   -
44   -#define ORxG_EAD 0x00000001 /* External addr latch delay */
45   -#define ORxG_EHTR 0x00000002 /* Extended hold time on read */
46   -#define ORxG_TRLX 0x00000004 /* Timing relaxed */
47   -#define ORxG_SETA 0x00000008 /* External address termination */
48   -#define ORxG_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */
49   -#define ORxG_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */
50   -#define ORxG_XACS 0x00000100 /* Extra addr to CS setup */
51   -#define ORxG_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later*/
52   -#define ORxG_CSNT 0x00000800 /* Chip Select Negation Time */
53   -
54   -#define ORxU_BI 0x00000100 /* Burst Inhibit */
55   -#define ORxU_AM_MSK 0xffff8000 /* Address Mask Mask */
56   -
57   -#define MxMR_OP_NORM 0x00000000 /* Normal Operation */
58   -#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */
59   -#define MxMR_OP_WARR 0x10000000 /* Write to Array */
60   -#define MxMR_BSEL 0x80000000 /* Bus Select */
61   -
62   -/* helpers to convert values into an OR address mask (GPCM mode) */
63   -#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
64   -#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20)
65   -
66 31 #endif /* __MPC85xx_H__ */