riscv: Add Kconfig to support RISC-V

Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>

riscv: Add Kconfig to support RISC-V
Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
Rick Chen · Tom Rini
1 parent 6020faf62c
Showing 4 changed files with 93 additions and 0 deletions Side-by-side Diff
MAINTAINERS
arch/riscv/Kconfig
arch/riscv/Makefile
arch/riscv/config.mk
@@ -423,6 +423,13 @@
 T:	git git://git.denx.de/u-boot-onenand.git
 F:	drivers/mtd/onenand/
  
+RISC-V
+M:	Rick Chen <rick@andestech.com>
+S:	Maintained
+T:	git git://git.denx.de/u-boot-riscv.git
+F:	arch/riscv/
+F:	tools/prelink-riscv.c
+
 SANDBOX
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
+menu "RISCV architecture"
+	depends on RISCV
+
+config SYS_ARCH
+	default "riscv"
+
+choice
+	prompt "Target select"
+	optional
+
+config TARGET_NX25_AE250
+	bool "Support nx25-ae250"
+
+endchoice
+
+source "board/AndesTech/nx25-ae250/Kconfig"
+
+choice
+	prompt "CPU selection"
+	default CPU_RISCV_32
+
+config CPU_RISCV_32
+	bool "RISCV 32 bit"
+	select 32BIT
+	help
+	  Choose this option to build an U-Boot for RISCV32 architecture.
+
+config CPU_RISCV_64
+	bool "RISCV 64 bit"
+	select 64BIT
+	help
+	  Choose this option to build an U-Boot for RISCV64 architecture.
+
+endchoice
+
+config 32BIT
+	bool
+
+config 64BIT
+	bool
+
+endmenu
+#
+# Copyright (C) 2017 Andes Technology Corporation.
+# Rick Chen, Andes Technology Corporation <rick@andestech.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+head-y := arch/riscv/cpu/$(CPU)/start.o
+
+libs-y += arch/riscv/cpu/$(CPU)/
+libs-y += arch/riscv/lib/
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (c) 2017 Microsemi Corporation.
+# Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com>
+#
+# Copyright (C) 2017 Andes Technology Corporation
+# Rick Chen, Andes Technology Corporation <rick@andestech.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := riscv32-unknown-linux-gnu-
+endif
+
+32bit-emul		:= elf32lriscv
+64bit-emul		:= elf64lriscv
+
+ifdef CONFIG_32BIT
+PLATFORM_LDFLAGS	+= -m $(32bit-emul)
+endif
+
+ifdef CONFIG_64BIT
+PLATFORM_LDFLAGS	+= -m $(64bit-emul)
+endif
+
+CONFIG_STANDALONE_LOAD_ADDR = 0x00000000 \
+			      -T $(srctree)/examples/standalone/riscv.lds
+
+PLATFORM_CPPFLAGS	+= -ffixed-gp -fpic
+PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -gdwarf-2
+LDFLAGS_u-boot += --gc-sections -static -pie
...	...	@@ -423,6 +423,13 @@
423	423	T: git git://git.denx.de/u-boot-onenand.git
424	424	F: drivers/mtd/onenand/
425	425
	426	+RISC-V
	427	+M: Rick Chen <rick@andestech.com>
	428	+S: Maintained
	429	+T: git git://git.denx.de/u-boot-riscv.git
	430	+F: arch/riscv/
	431	+F: tools/prelink-riscv.c
	432	+
426	433	SANDBOX
427	434	M: Simon Glass <sjg@chromium.org>
428	435	S: Maintained
	1	+menu "RISCV architecture"
	2	+ depends on RISCV
	3	+
	4	+config SYS_ARCH
	5	+ default "riscv"
	6	+
	7	+choice
	8	+ prompt "Target select"
	9	+ optional
	10	+
	11	+config TARGET_NX25_AE250
	12	+ bool "Support nx25-ae250"
	13	+
	14	+endchoice
	15	+
	16	+source "board/AndesTech/nx25-ae250/Kconfig"
	17	+
	18	+choice
	19	+ prompt "CPU selection"
	20	+ default CPU_RISCV_32
	21	+
	22	+config CPU_RISCV_32
	23	+ bool "RISCV 32 bit"
	24	+ select 32BIT
	25	+ help
	26	+ Choose this option to build an U-Boot for RISCV32 architecture.
	27	+
	28	+config CPU_RISCV_64
	29	+ bool "RISCV 64 bit"
	30	+ select 64BIT
	31	+ help
	32	+ Choose this option to build an U-Boot for RISCV64 architecture.
	33	+
	34	+endchoice
	35	+
	36	+config 32BIT
	37	+ bool
	38	+
	39	+config 64BIT
	40	+ bool
	41	+
	42	+endmenu
	1	+#
	2	+# Copyright (C) 2017 Andes Technology Corporation.
	3	+# Rick Chen, Andes Technology Corporation <rick@andestech.com>
	4	+#
	5	+# SPDX-License-Identifier: GPL-2.0+
	6	+#
	7	+
	8	+head-y := arch/riscv/cpu/$(CPU)/start.o
	9	+
	10	+libs-y += arch/riscv/cpu/$(CPU)/
	11	+libs-y += arch/riscv/lib/
	1	+#
	2	+# (C) Copyright 2000-2002
	3	+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+#
	5	+# Copyright (c) 2017 Microsemi Corporation.
	6	+# Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com>
	7	+#
	8	+# Copyright (C) 2017 Andes Technology Corporation
	9	+# Rick Chen, Andes Technology Corporation <rick@andestech.com>
	10	+#
	11	+# SPDX-License-Identifier: GPL-2.0+
	12	+
	13	+ifeq ($(CROSS_COMPILE),)
	14	+CROSS_COMPILE := riscv32-unknown-linux-gnu-
	15	+endif
	16	+
	17	+32bit-emul := elf32lriscv
	18	+64bit-emul := elf64lriscv
	19	+
	20	+ifdef CONFIG_32BIT
	21	+PLATFORM_LDFLAGS += -m $(32bit-emul)
	22	+endif
	23	+
	24	+ifdef CONFIG_64BIT
	25	+PLATFORM_LDFLAGS += -m $(64bit-emul)
	26	+endif
	27	+
	28	+CONFIG_STANDALONE_LOAD_ADDR = 0x00000000 \
	29	+ -T $(srctree)/examples/standalone/riscv.lds
	30	+
	31	+PLATFORM_CPPFLAGS += -ffixed-gp -fpic
	32	+PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -gdwarf-2
	33	+LDFLAGS_u-boot += --gc-sections -static -pie