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Commit f97271612bb1767e0c0b816827603380d7d7e1b6

Authored by Marek Vasut
Committed by Stefano Babic
1 parent 0c5e26678b
Exists in master and in 50 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ARM: mxs: Add PPC-AG BG0900 board 

This board supports FEC Ethernet, SPI NOR and NAND flash.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Christoph Baumann <c.baumann@ppc-ag.de>

Showing 5 changed files with 355 additions and 0 deletions Side-by-side Diff

board/ppcag/bg0900/Makefile
Diff comments   View file @ f972716
  1 +#
  2 +# (C) Copyright 2000-2006
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# SPDX-License-Identifier: GPL-2.0+
  6 +#
  7 +
  8 +include $(TOPDIR)/config.mk
  9 +
  10 +LIB = $(obj)lib$(BOARD).o
  11 +
  12 +ifndef CONFIG_SPL_BUILD
  13 +COBJS := bg0900.o
  14 +else
  15 +COBJS := spl_boot.o
  16 +endif
  17 +
  18 +SRCS := $(COBJS:.o=.c)
  19 +OBJS := $(addprefix $(obj),$(COBJS))
  20 +
  21 +$(LIB): $(obj).depend $(OBJS)
  22 + $(call cmd_link_o_target, $(OBJS))
  23 +
  24 +#########################################################################
  25 +
  26 +# defines $(obj).depend target
  27 +include $(SRCTREE)/rules.mk
  28 +
  29 +sinclude $(obj).depend
  30 +
  31 +#########################################################################
board/ppcag/bg0900/bg0900.c
Diff comments   View file @ f972716
  1 +/*
  2 + * PPC-AG BG0900 board
  3 + *
  4 + * Copyright (C) 2013 Marek Vasut <marex@denx.de>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <asm/gpio.h>
  11 +#include <asm/io.h>
  12 +#include <asm/arch/imx-regs.h>
  13 +#include <asm/arch/iomux-mx28.h>
  14 +#include <asm/arch/clock.h>
  15 +#include <asm/arch/sys_proto.h>
  16 +#include <linux/mii.h>
  17 +#include <miiphy.h>
  18 +#include <netdev.h>
  19 +#include <errno.h>
  20 +
  21 +DECLARE_GLOBAL_DATA_PTR;
  22 +
  23 +/*
  24 + * Functions
  25 + */
  26 +int board_early_init_f(void)
  27 +{
  28 + /* IO0 clock at 480MHz */
  29 + mxs_set_ioclk(MXC_IOCLK0, 480000);
  30 + /* IO1 clock at 480MHz */
  31 + mxs_set_ioclk(MXC_IOCLK1, 480000);
  32 +
  33 + /* SSP2 clock at 160MHz */
  34 + mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
  35 +
  36 + return 0;
  37 +}
  38 +
  39 +int dram_init(void)
  40 +{
  41 + return mxs_dram_init();
  42 +}
  43 +
  44 +int board_init(void)
  45 +{
  46 + /* Adress of boot parameters */
  47 + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  48 +
  49 + return 0;
  50 +}
  51 +
  52 +#ifdef CONFIG_CMD_NET
  53 +int board_eth_init(bd_t *bis)
  54 +{
  55 + struct mxs_clkctrl_regs *clkctrl_regs =
  56 + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  57 + struct eth_device *dev;
  58 + int ret;
  59 +
  60 + ret = cpu_eth_init(bis);
  61 +
  62 + /* BG0900 uses ENET_CLK PAD to drive FEC clock */
  63 + writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
  64 + &clkctrl_regs->hw_clkctrl_enet);
  65 +
  66 + /* Reset FEC PHYs */
  67 + gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
  68 + udelay(200);
  69 + gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
  70 +
  71 + ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
  72 + if (ret) {
  73 + puts("FEC MXS: Unable to init FEC0\n");
  74 + return ret;
  75 + }
  76 +
  77 + dev = eth_get_dev_by_name("FEC0");
  78 + if (!dev) {
  79 + puts("FEC MXS: Unable to get FEC0 device entry\n");
  80 + return -EINVAL;
  81 + }
  82 +
  83 + return ret;
  84 +}
  85 +
  86 +#endif
board/ppcag/bg0900/spl_boot.c
Diff comments   View file @ f972716
  1 +/*
  2 + * PPC-AG BG0900 Boot setup
  3 + *
  4 + * Copyright (C) 2013 Marek Vasut <marex@denx.de>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <config.h>
  11 +#include <asm/io.h>
  12 +#include <asm/arch/iomux-mx28.h>
  13 +#include <asm/arch/imx-regs.h>
  14 +#include <asm/arch/sys_proto.h>
  15 +
  16 +#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
  17 +#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
  18 +#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
  19 +#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
  20 +
  21 +const iomux_cfg_t iomux_setup[] = {
  22 + /* DUART */
  23 + MX28_PAD_PWM0__DUART_RX,
  24 + MX28_PAD_PWM1__DUART_TX,
  25 +
  26 + /* GPMI NAND */
  27 + MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
  28 + MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
  29 + MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
  30 + MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
  31 + MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
  32 + MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
  33 + MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
  34 + MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
  35 + MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
  36 + MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
  37 + MX28_PAD_GPMI_RDN__GPMI_RDN |
  38 + (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
  39 + MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
  40 + MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
  41 + MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
  42 + MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
  43 +
  44 + /* FEC0 */
  45 + MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
  46 + MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
  47 + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
  48 + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
  49 + MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
  50 + MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
  51 + MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
  52 + MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
  53 + MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
  54 +
  55 + /* FEC0 Reset */
  56 + MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
  57 + (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
  58 +
  59 + /* EMI */
  60 + MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
  61 + MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
  62 + MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
  63 + MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
  64 + MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
  65 + MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
  66 + MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
  67 + MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
  68 + MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
  69 + MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
  70 + MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
  71 + MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
  72 + MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
  73 + MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
  74 + MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
  75 + MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
  76 + MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
  77 + MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
  78 + MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
  79 + MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
  80 + MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
  81 + MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
  82 + MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
  83 + MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
  84 + MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
  85 +
  86 + MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
  87 + MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
  88 + MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
  89 + MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
  90 + MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
  91 + MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
  92 + MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
  93 + MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
  94 + MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
  95 + MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
  96 + MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
  97 + MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
  98 + MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
  99 + MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
  100 + MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
  101 + MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
  102 + MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
  103 + MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
  104 + MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
  105 + MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
  106 + MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
  107 + MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
  108 + MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
  109 + MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
  110 +
  111 + /* SPI2 (for SPI flash) */
  112 + MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
  113 + MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
  114 + MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
  115 + MX28_PAD_SSP2_SS0__SSP2_D3 |
  116 + (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
  117 +};
  118 +
  119 +void mxs_adjust_memory_params(uint32_t *dram_vals)
  120 +{
  121 + dram_vals[0x98 / 4] = 0x04005003;
  122 + dram_vals[0x9c / 4] = 0x090000c8;
  123 +
  124 + dram_vals[0xa8 / 4] = 0x0036b009;
  125 + dram_vals[0xac / 4] = 0x03270612;
  126 +
  127 + dram_vals[0xb0 / 4] = 0x02020202;
  128 + dram_vals[0xb4 / 4] = 0x00c80029;
  129 +
  130 + dram_vals[0xc0 / 4] = 0x00011900;
  131 +
  132 + dram_vals[0x12c / 4] = 0x07400300;
  133 + dram_vals[0x130 / 4] = 0x07400300;
  134 + dram_vals[0x2c4 / 4] = 0x02030303;
  135 +}
  136 +
  137 +void board_init_ll(const uint32_t arg, const uint32_t *resptr)
  138 +{
  139 + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
  140 +}
... ... @@ -207,6 +207,7 @@
207 207 Active arm arm926ejs mxs freescale mx28evk mx28evk_auart_console mx28evk:MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC Fabio Estevam <fabio.estevam@freescale.com>
208 208 Active arm arm926ejs mxs freescale mx28evk mx28evk_nand mx28evk:ENV_IS_IN_NAND Fabio Estevam <fabio.estevam@freescale.com>
209 209 Active arm arm926ejs mxs olimex mx23_olinuxino mx23_olinuxino mx23_olinuxino Marek Vasut <marek.vasut@gmail.com>
  210 +Active arm arm926ejs mxs ppcag bg0900 bg0900 bg0900 Marek Vasut <marex@denx.de>
210 211 Active arm arm926ejs mxs sandisk sansa_fuze_plus sansa_fuze_plus - Marek Vasut <marek.vasut@gmail.com>
211 212 Active arm arm926ejs mxs schulercontrol sc_sps_1 sc_sps_1 - Marek Vasut <marek.vasut@gmail.com>
212 213 Active arm arm926ejs nomadik st nhk8815 nhk8815 - Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it>
include/configs/bg0900.h
Diff comments   View file @ f972716
  1 +/*
  2 + * Copyright (C) 2013 Marek Vasut <marex@denx.de>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +#ifndef __CONFIGS_BG0900_H__
  7 +#define __CONFIGS_BG0900_H__
  8 +
  9 +/* System configurations */
  10 +#define CONFIG_MX28 /* i.MX28 SoC */
  11 +
  12 +/* U-Boot Commands */
  13 +#define CONFIG_SYS_NO_FLASH
  14 +#include <config_cmd_default.h>
  15 +#define CONFIG_DISPLAY_CPUINFO
  16 +#define CONFIG_DOS_PARTITION
  17 +
  18 +#define CONFIG_CMD_BOOTZ
  19 +#define CONFIG_CMD_CACHE
  20 +#define CONFIG_CMD_DHCP
  21 +#define CONFIG_CMD_GPIO
  22 +#define CONFIG_CMD_MII
  23 +#define CONFIG_CMD_NAND
  24 +#define CONFIG_CMD_NAND_TRIMFFS
  25 +#define CONFIG_CMD_NET
  26 +#define CONFIG_CMD_NFS
  27 +#define CONFIG_CMD_PING
  28 +#define CONFIG_CMD_SAVEENV
  29 +#define CONFIG_CMD_SETEXPR
  30 +#define CONFIG_CMD_SF
  31 +#define CONFIG_CMD_SPI
  32 +
  33 +/* Memory configuration */
  34 +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
  35 +#define PHYS_SDRAM_1 0x40000000 /* Base address */
  36 +#define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */
  37 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  38 +
  39 +/* Environment */
  40 +#define CONFIG_ENV_SIZE (16 * 1024)
  41 +#define CONFIG_ENV_OVERWRITE
  42 +#define CONFIG_ENV_IS_NOWHERE
  43 +
  44 +/* FEC Ethernet on SoC */
  45 +#ifdef CONFIG_CMD_NET
  46 +#define CONFIG_FEC_MXC
  47 +#define CONFIG_NET_MULTI
  48 +#endif
  49 +
  50 +/* SPI */
  51 +#ifdef CONFIG_CMD_SPI
  52 +#define CONFIG_DEFAULT_SPI_BUS 2
  53 +#define CONFIG_DEFAULT_SPI_CS 0
  54 +#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
  55 +
  56 +/* SPI FLASH */
  57 +#ifdef CONFIG_CMD_SF
  58 +#define CONFIG_SPI_FLASH
  59 +#define CONFIG_SPI_FLASH_BAR
  60 +#define CONFIG_SPI_FLASH_STMICRO
  61 +#define CONFIG_SF_DEFAULT_BUS 2
  62 +#define CONFIG_SF_DEFAULT_CS 0
  63 +#define CONFIG_SF_DEFAULT_SPEED 40000000
  64 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
  65 +
  66 +#define CONFIG_ENV_SPI_BUS 2
  67 +#define CONFIG_ENV_SPI_CS 0
  68 +#define CONFIG_ENV_SPI_MAX_HZ 40000000
  69 +#define CONFIG_ENV_SPI_MODE SPI_MODE_0
  70 +#endif
  71 +
  72 +#endif
  73 +
  74 +/* Boot Linux */
  75 +#define CONFIG_BOOTDELAY 3
  76 +#define CONFIG_BOOTFILE "uImage"
  77 +#define CONFIG_BOOTARGS "console=ttyAMA0,115200"
  78 +#define CONFIG_BOOTCOMMAND "bootm"
  79 +#define CONFIG_LOADADDR 0x42000000
  80 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  81 +
  82 +/* Extra Environment */
  83 +#define CONFIG_EXTRA_ENV_SETTINGS \
  84 + "update_spi_firmware_filename=u-boot.sb\0" \
  85 + "update_spi_firmware_maxsz=0x80000\0" \
  86 + "update_spi_firmware=" /* Update the SPI flash firmware */ \
  87 + "if sf probe 2:0 ; then " \
  88 + "if tftp ${update_spi_firmware_filename} ; then " \
  89 + "sf erase 0x0 +${filesize} ; " \
  90 + "sf write ${loadaddr} 0x0 ${filesize} ; " \
  91 + "fi ; " \
  92 + "fi\0"
  93 +
  94 +/* The rest of the configuration is shared */
  95 +#include <configs/mxs.h>
  96 +
  97 +#endif /* __CONFIGS_BG0900_H__ */