Exynos: clock: Correct pwm source clk selection

MPLL is selected as the source clk of pwm by default Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

Exynos: clock: Correct pwm source clk selection
MPLL is selected as the source clk of pwm by default Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Padmavathi Venna · Minkyu Kang
1 parent 12a46a384d
Showing 1 changed file with 1 additions and 1 deletions Side-by-side Diff
board/samsung/smdk5250/setup.h
@@ -343,7 +343,7 @@
 #define TOP2_VAL		0x0110000
  
 /* CLK_SRC_PERIC0 */
-#define PWM_SEL		0
+#define PWM_SEL		6
 #define UART3_SEL	6
 #define UART2_SEL	6
 #define UART1_SEL	6
...	...	@@ -343,7 +343,7 @@
343	343	#define TOP2_VAL 0x0110000
344	344
345	345	/* CLK_SRC_PERIC0 */
346		-#define PWM_SEL 0
	346	+#define PWM_SEL 6
347	347	#define UART3_SEL 6
348	348	#define UART2_SEL 6
349	349	#define UART1_SEL 6