i2c: mxc: move to new subsystem

Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>

i2c: mxc: move to new subsystem
Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
trem · Heiko Schocher
1 parent 815a76f2ef
Showing 6 changed files with 93 additions and 63 deletions Side-by-side Diff
README
arch/arm/cpu/armv7/mx5/clock.c
arch/arm/cpu/armv7/mx6/clock.c
arch/arm/imx-common/Makefile
drivers/i2c/Makefile
drivers/i2c/mxc_i2c.c
@@ -2003,6 +2003,17 @@
 		  - CONFIG_SYS_I2C_PPC4XX_CH0 activate hardware channel 0
 		  - CONFIG_SYS_I2C_PPC4XX_CH1 activate hardware channel 1
  
+		- drivers/i2c/i2c_mxc.c
+		  - activate this driver with CONFIG_SYS_I2C_MXC
+		  - define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED
+		  - define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE
+		  - define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED
+		  - define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE
+		  - define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED
+		  - define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE
+		If thoses defines are not set, default value is 100000
+		for speed, and 0 for slave.
+
 		additional defines:
  
 		CONFIG_SYS_NUM_I2C_BUSES
@@ -94,7 +94,7 @@
 			MXC_CCM_CCGR2_USBOH3_60M(cg));
 }
  
-#ifdef CONFIG_I2C_MXC
+#ifdef CONFIG_SYS_I2C_MXC
 /* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 {
@@ -48,7 +48,7 @@
  
 }
  
-#ifdef CONFIG_I2C_MXC
+#ifdef CONFIG_SYS_I2C_MXC
 /* i2c_num can be from 0 - 2 */
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 {
@@ -16,7 +16,7 @@
 endif
 ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
 COBJS-y	+= timer.o cpu.o speed.o
-COBJS-$(CONFIG_I2C_MXC) += i2c-mxv7.o
+COBJS-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
 COBJS-y	+= misc.o
@@ -14,7 +14,6 @@
 COBJS-$(CONFIG_DW_I2C) += designware_i2c.o
 COBJS-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
 COBJS-$(CONFIG_I2C_MV) += mv_i2c.o
-COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o
 COBJS-$(CONFIG_I2C_MXS) += mxs_i2c.o
 COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o
 COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o
@@ -28,6 +27,7 @@
 COBJS-$(CONFIG_SYS_I2C) += i2c_core.o
 COBJS-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
 COBJS-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
+COBJS-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
 COBJS-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
 COBJS-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
 COBJS-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
@@ -102,6 +102,28 @@
 };
 #endif
  
+
+#ifndef CONFIG_SYS_MXC_I2C1_SPEED
+#define CONFIG_SYS_MXC_I2C1_SPEED 100000
+#endif
+#ifndef CONFIG_SYS_MXC_I2C2_SPEED
+#define CONFIG_SYS_MXC_I2C2_SPEED 100000
+#endif
+#ifndef CONFIG_SYS_MXC_I2C3_SPEED
+#define CONFIG_SYS_MXC_I2C3_SPEED 100000
+#endif
+
+#ifndef CONFIG_SYS_MXC_I2C1_SLAVE
+#define CONFIG_SYS_MXC_I2C1_SLAVE 0
+#endif
+#ifndef CONFIG_SYS_MXC_I2C2_SLAVE
+#define CONFIG_SYS_MXC_I2C2_SLAVE 0
+#endif
+#ifndef CONFIG_SYS_MXC_I2C3_SLAVE
+#define CONFIG_SYS_MXC_I2C3_SLAVE 0
+#endif
+
+
 /*
  * Calculate and set proper clock divider
  */
@@ -153,21 +175,6 @@
 	return 0;
 }
  
-/*
- * Get I2C Speed
- */
-static unsigned int bus_i2c_get_bus_speed(void *base)
-{
-	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
-	u8 clk_idx = readb(&i2c_regs->ifdr);
-	u8 clk_div;
-
-	for (clk_div = 0; i2c_clk_div[clk_div][1] != clk_idx; clk_div++)
-		;
-
-	return mxc_get_clock(MXC_I2C_CLK) / i2c_clk_div[clk_div][0];
-}
-
 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
  
  
@@ -410,20 +417,30 @@
  */
 static struct sram_data __attribute__((section(".data"))) srdata;
  
-void *get_base(void)
-{
-#ifdef CONFIG_SYS_I2C_BASE
-#ifdef CONFIG_I2C_MULTI_BUS
-	void *ret = srdata.i2c_data[srdata.curr_i2c_bus].base;
-	if (ret)
-		return ret;
-#endif
-	return (void *)CONFIG_SYS_I2C_BASE;
-#elif defined(CONFIG_I2C_MULTI_BUS)
-	return srdata.i2c_data[srdata.curr_i2c_bus].base;
+static void * const i2c_bases[] = {
+#if defined(CONFIG_MX25)
+	(void *)IMX_I2C_BASE,
+	(void *)IMX_I2C2_BASE,
+	(void *)IMX_I2C3_BASE
+#elif defined(CONFIG_MX27)
+	(void *)IMX_I2C1_BASE,
+	(void *)IMX_I2C2_BASE
+#elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \
+	defined(CONFIG_MX51) || defined(CONFIG_MX53) ||	\
+	defined(CONFIG_MX6)
+	(void *)I2C1_BASE_ADDR,
+	(void *)I2C2_BASE_ADDR,
+	(void *)I2C3_BASE_ADDR
+#elif defined(CONFIG_VF610)
+	(void *)I2C0_BASE_ADDR
 #else
-	return srdata.i2c_data[0].base;
+#error "architecture not supported"
 #endif
+};
+
+void *i2c_get_base(struct i2c_adapter *adap)
+{
+	return i2c_bases[adap->hwadapnr];
 }
  
 static struct i2c_parms *i2c_get_parms(void *base)
  
  
  
  
  
  
  
@@ -448,39 +465,26 @@
 	return 0;
 }
  
-#ifdef CONFIG_I2C_MULTI_BUS
-unsigned int i2c_get_bus_num(void)
+static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
+				uint addr, int alen, uint8_t *buffer,
+				int len)
 {
-	return srdata.curr_i2c_bus;
+	return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
 }
  
-int i2c_set_bus_num(unsigned bus_idx)
+static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
+				uint addr, int alen, uint8_t *buffer,
+				int len)
 {
-	if (bus_idx >= ARRAY_SIZE(srdata.i2c_data))
-		return -1;
-	if (!srdata.i2c_data[bus_idx].base)
-		return -1;
-	srdata.curr_i2c_bus = bus_idx;
-	return 0;
+	return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
 }
-#endif
  
-int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
-{
-	return bus_i2c_read(get_base(), chip, addr, alen, buf, len);
-}
-
-int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
-{
-	return bus_i2c_write(get_base(), chip, addr, alen, buf, len);
-}
-
 /*
  * Test if a chip at a given address responds (probe the chip)
  */
-int i2c_probe(uchar chip)
+static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
 {
-	return bus_i2c_write(get_base(), chip, 0, 0, NULL, 0);
+	return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
 }
  
 void bus_i2c_init(void *base, int speed, int unused,
  
  
  
  
  
@@ -510,24 +514,39 @@
 /*
  * Init I2C Bus
  */
-void i2c_init(int speed, int unused)
+static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 {
-	bus_i2c_init(get_base(), speed, unused, NULL, NULL);
+	bus_i2c_init(i2c_get_base(adap), speed, slaveaddr, NULL, NULL);
 }
  
 /*
  * Set I2C Speed
  */
-int i2c_set_bus_speed(unsigned int speed)
+static uint mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
 {
-	return bus_i2c_set_bus_speed(get_base(), speed);
+	return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
 }
  
 /*
- * Get I2C Speed
+ * Register mxc i2c adapters
  */
-unsigned int i2c_get_bus_speed(void)
-{
-	return bus_i2c_get_bus_speed(get_base());
-}
+U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
+			 mxc_i2c_read, mxc_i2c_write,
+			 mxc_i2c_set_bus_speed,
+			 CONFIG_SYS_MXC_I2C1_SPEED,
+			 CONFIG_SYS_MXC_I2C1_SLAVE, 0)
+U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
+			 mxc_i2c_read, mxc_i2c_write,
+			 mxc_i2c_set_bus_speed,
+			 CONFIG_SYS_MXC_I2C2_SPEED,
+			 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
+#if defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\
+	defined(CONFIG_MX51) || defined(CONFIG_MX53) ||\
+	defined(CONFIG_MX6)
+U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
+			 mxc_i2c_read, mxc_i2c_write,
+			 mxc_i2c_set_bus_speed,
+			 CONFIG_SYS_MXC_I2C3_SPEED,
+			 CONFIG_SYS_MXC_I2C3_SLAVE, 2)
+#endif
...	...	@@ -2003,6 +2003,17 @@
2003	2003	- CONFIG_SYS_I2C_PPC4XX_CH0 activate hardware channel 0
2004	2004	- CONFIG_SYS_I2C_PPC4XX_CH1 activate hardware channel 1
2005	2005
	2006	+ - drivers/i2c/i2c_mxc.c
	2007	+ - activate this driver with CONFIG_SYS_I2C_MXC
	2008	+ - define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED
	2009	+ - define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE
	2010	+ - define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED
	2011	+ - define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE
	2012	+ - define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED
	2013	+ - define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE
	2014	+ If thoses defines are not set, default value is 100000
	2015	+ for speed, and 0 for slave.
	2016	+
2006	2017	additional defines:
2007	2018
2008	2019	CONFIG_SYS_NUM_I2C_BUSES
...	...	@@ -94,7 +94,7 @@
94	94	MXC_CCM_CCGR2_USBOH3_60M(cg));
95	95	}
96	96
97		-#ifdef CONFIG_I2C_MXC
	97	+#ifdef CONFIG_SYS_I2C_MXC
98	98	/* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
99	99	int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
100	100	{
...	...	@@ -48,7 +48,7 @@
48	48
49	49	}
50	50
51		-#ifdef CONFIG_I2C_MXC
	51	+#ifdef CONFIG_SYS_I2C_MXC
52	52	/* i2c_num can be from 0 - 2 */
53	53	int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
54	54	{
...	...	@@ -16,7 +16,7 @@
16	16	endif
17	17	ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
18	18	COBJS-y += timer.o cpu.o speed.o
19		-COBJS-$(CONFIG_I2C_MXC) += i2c-mxv7.o
	19	+COBJS-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
20	20	endif
21	21	ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
22	22	COBJS-y += misc.o
...	...	@@ -14,7 +14,6 @@
14	14	COBJS-$(CONFIG_DW_I2C) += designware_i2c.o
15	15	COBJS-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
16	16	COBJS-$(CONFIG_I2C_MV) += mv_i2c.o
17		-COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o
18	17	COBJS-$(CONFIG_I2C_MXS) += mxs_i2c.o
19	18	COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o
20	19	COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o
...	...	@@ -28,6 +27,7 @@
28	27	COBJS-$(CONFIG_SYS_I2C) += i2c_core.o
29	28	COBJS-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
30	29	COBJS-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
	30	+COBJS-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
31	31	COBJS-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
32	32	COBJS-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
33	33	COBJS-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
...	...	@@ -102,6 +102,28 @@
102	102	};
103	103	#endif
104	104
	105	+
	106	+#ifndef CONFIG_SYS_MXC_I2C1_SPEED
	107	+#define CONFIG_SYS_MXC_I2C1_SPEED 100000
	108	+#endif
	109	+#ifndef CONFIG_SYS_MXC_I2C2_SPEED
	110	+#define CONFIG_SYS_MXC_I2C2_SPEED 100000
	111	+#endif
	112	+#ifndef CONFIG_SYS_MXC_I2C3_SPEED
	113	+#define CONFIG_SYS_MXC_I2C3_SPEED 100000
	114	+#endif
	115	+
	116	+#ifndef CONFIG_SYS_MXC_I2C1_SLAVE
	117	+#define CONFIG_SYS_MXC_I2C1_SLAVE 0
	118	+#endif
	119	+#ifndef CONFIG_SYS_MXC_I2C2_SLAVE
	120	+#define CONFIG_SYS_MXC_I2C2_SLAVE 0
	121	+#endif
	122	+#ifndef CONFIG_SYS_MXC_I2C3_SLAVE
	123	+#define CONFIG_SYS_MXC_I2C3_SLAVE 0
	124	+#endif
	125	+
	126	+
105	127	/*
106	128	* Calculate and set proper clock divider
107	129	*/
...	...	@@ -153,21 +175,6 @@
153	175	return 0;
154	176	}
155	177
156		-/*
157		- * Get I2C Speed
158		- */
159		-static unsigned int bus_i2c_get_bus_speed(void *base)
160		-{
161		- struct mxc_i2c_regs i2c_regs = (struct mxc_i2c_regs )base;
162		- u8 clk_idx = readb(&i2c_regs->ifdr);
163		- u8 clk_div;
164		-
165		- for (clk_div = 0; i2c_clk_div[clk_div][1] != clk_idx; clk_div++)
166		- ;
167		-
168		- return mxc_get_clock(MXC_I2C_CLK) / i2c_clk_div[clk_div][0];
169		-}
170		-
171	178	#define ST_BUS_IDLE (0 \| (I2SR_IBB << 8))
172	179	#define ST_BUS_BUSY (I2SR_IBB \| (I2SR_IBB << 8))
173	180	#define ST_IIF (I2SR_IIF \| (I2SR_IIF << 8))
174	181
175	182
...	...	@@ -410,20 +417,30 @@
410	417	*/
411	418	static struct sram_data __attribute__((section(".data"))) srdata;
412	419
413		-void *get_base(void)
414		-{
415		-#ifdef CONFIG_SYS_I2C_BASE
416		-#ifdef CONFIG_I2C_MULTI_BUS
417		- void *ret = srdata.i2c_data[srdata.curr_i2c_bus].base;
418		- if (ret)
419		- return ret;
420		-#endif
421		- return (void *)CONFIG_SYS_I2C_BASE;
422		-#elif defined(CONFIG_I2C_MULTI_BUS)
423		- return srdata.i2c_data[srdata.curr_i2c_bus].base;
	420	+static void * const i2c_bases[] = {
	421	+#if defined(CONFIG_MX25)
	422	+ (void *)IMX_I2C_BASE,
	423	+ (void *)IMX_I2C2_BASE,
	424	+ (void *)IMX_I2C3_BASE
	425	+#elif defined(CONFIG_MX27)
	426	+ (void *)IMX_I2C1_BASE,
	427	+ (void *)IMX_I2C2_BASE
	428	+#elif defined(CONFIG_MX31) \|\| defined(CONFIG_MX35) \|\| \
	429	+ defined(CONFIG_MX51) \|\| defined(CONFIG_MX53) \|\| \
	430	+ defined(CONFIG_MX6)
	431	+ (void *)I2C1_BASE_ADDR,
	432	+ (void *)I2C2_BASE_ADDR,
	433	+ (void *)I2C3_BASE_ADDR
	434	+#elif defined(CONFIG_VF610)
	435	+ (void *)I2C0_BASE_ADDR
424	436	#else
425		- return srdata.i2c_data[0].base;
	437	+#error "architecture not supported"
426	438	#endif
	439	+};
	440	+
	441	+void i2c_get_base(struct i2c_adapter adap)
	442	+{
	443	+ return i2c_bases[adap->hwadapnr];
427	444	}
428	445
429	446	static struct i2c_parms i2c_get_parms(void base)
430	447
431	448
432	449
433	450
434	451
435	452
436	453
...	...	@@ -448,39 +465,26 @@
448	465	return 0;
449	466	}
450	467
451		-#ifdef CONFIG_I2C_MULTI_BUS
452		-unsigned int i2c_get_bus_num(void)
	468	+static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
	469	+ uint addr, int alen, uint8_t *buffer,
	470	+ int len)
453	471	{
454		- return srdata.curr_i2c_bus;
	472	+ return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
455	473	}
456	474
457		-int i2c_set_bus_num(unsigned bus_idx)
	475	+static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
	476	+ uint addr, int alen, uint8_t *buffer,
	477	+ int len)
458	478	{
459		- if (bus_idx >= ARRAY_SIZE(srdata.i2c_data))
460		- return -1;
461		- if (!srdata.i2c_data[bus_idx].base)
462		- return -1;
463		- srdata.curr_i2c_bus = bus_idx;
464		- return 0;
	479	+ return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
465	480	}
466		-#endif
467	481
468		-int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
469		-{
470		- return bus_i2c_read(get_base(), chip, addr, alen, buf, len);
471		-}
472		-
473		-int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
474		-{
475		- return bus_i2c_write(get_base(), chip, addr, alen, buf, len);
476		-}
477		-
478	482	/*
479	483	* Test if a chip at a given address responds (probe the chip)
480	484	*/
481		-int i2c_probe(uchar chip)
	485	+static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
482	486	{
483		- return bus_i2c_write(get_base(), chip, 0, 0, NULL, 0);
	487	+ return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
484	488	}
485	489
486	490	void bus_i2c_init(void *base, int speed, int unused,
487	491
488	492
489	493
490	494
491	495
...	...	@@ -510,24 +514,39 @@
510	514	/*
511	515	* Init I2C Bus
512	516	*/
513		-void i2c_init(int speed, int unused)
	517	+static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
514	518	{
515		- bus_i2c_init(get_base(), speed, unused, NULL, NULL);
	519	+ bus_i2c_init(i2c_get_base(adap), speed, slaveaddr, NULL, NULL);
516	520	}
517	521
518	522	/*
519	523	* Set I2C Speed
520	524	*/
521		-int i2c_set_bus_speed(unsigned int speed)
	525	+static uint mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
522	526	{
523		- return bus_i2c_set_bus_speed(get_base(), speed);
	527	+ return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
524	528	}
525	529
526	530	/*
527		- * Get I2C Speed
	531	+ * Register mxc i2c adapters
528	532	*/
529		-unsigned int i2c_get_bus_speed(void)
530		-{
531		- return bus_i2c_get_bus_speed(get_base());
532		-}
	533	+U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
	534	+ mxc_i2c_read, mxc_i2c_write,
	535	+ mxc_i2c_set_bus_speed,
	536	+ CONFIG_SYS_MXC_I2C1_SPEED,
	537	+ CONFIG_SYS_MXC_I2C1_SLAVE, 0)
	538	+U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
	539	+ mxc_i2c_read, mxc_i2c_write,
	540	+ mxc_i2c_set_bus_speed,
	541	+ CONFIG_SYS_MXC_I2C2_SPEED,
	542	+ CONFIG_SYS_MXC_I2C2_SLAVE, 1)
	543	+#if defined(CONFIG_MX31) \|\| defined(CONFIG_MX35) \|\|\
	544	+ defined(CONFIG_MX51) \|\| defined(CONFIG_MX53) \|\|\
	545	+ defined(CONFIG_MX6)
	546	+U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
	547	+ mxc_i2c_read, mxc_i2c_write,
	548	+ mxc_i2c_set_bus_speed,
	549	+ CONFIG_SYS_MXC_I2C3_SPEED,
	550	+ CONFIG_SYS_MXC_I2C3_SLAVE, 2)
	551	+#endif