ARM: enable ARMv7 virt support for the Arndale board

To enable hypervisors utilizing the ARMv7 virtualization extension on the Arndale board, add the simple SMP pen address writer function and add the required configuration variables to switch all cores to HYP mode before launching the OS. This allows booting KVM and Xen directly from u-boot. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Andre Przywara <andre.przywara@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

ARM: enable ARMv7 virt support for the Arndale board
To enable hypervisors utilizing the ARMv7 virtualization extension on the Arndale board, add the simple SMP pen address writer function and add the required configuration variables to switch all cores to HYP mode before launching the OS. This allows booting KVM and Xen directly from u-boot. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Andre Przywara <andre.przywara@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara · Tom Rini
1 parent 0bf62d7bc4
Showing 2 changed files with 18 additions and 0 deletions Side-by-side Diff
board/samsung/arndale/arndale.c
include/configs/arndale.h
@@ -117,4 +117,14 @@
 	return 0;
 }
 #endif
+
+#ifdef CONFIG_S5P_PA_SYSRAM
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+	writel(addr, CONFIG_S5P_PA_SYSRAM);
+
+	/* make sure this write is really executed */
+	__asm__ volatile ("dsb\n");
+}
+#endif
@@ -250,5 +250,13 @@
 /* Enable Time Command */
 #define CONFIG_CMD_TIME
  
+#define CONFIG_S5P_PA_SYSRAM	0x02020000
+#define CONFIG_SMP_PEN_ADDR	CONFIG_S5P_PA_SYSRAM
+
+/* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */
+#define CONFIG_ARM_GIC_BASE_ADDRESS	0x10480000
+
+#define CONFIG_ARMV7_VIRT
+
 #endif	/* __CONFIG_H */
...	...	@@ -117,4 +117,14 @@
117	117	return 0;
118	118	}
119	119	#endif
	120	+
	121	+#ifdef CONFIG_S5P_PA_SYSRAM
	122	+void smp_set_core_boot_addr(unsigned long addr, int corenr)
	123	+{
	124	+ writel(addr, CONFIG_S5P_PA_SYSRAM);
	125	+
	126	+ /* make sure this write is really executed */
	127	+ __asm__ volatile ("dsb\n");
	128	+}
	129	+#endif
...	...	@@ -250,5 +250,13 @@
250	250	/* Enable Time Command */
251	251	#define CONFIG_CMD_TIME
252	252
	253	+#define CONFIG_S5P_PA_SYSRAM 0x02020000
	254	+#define CONFIG_SMP_PEN_ADDR CONFIG_S5P_PA_SYSRAM
	255	+
	256	+/* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */
	257	+#define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000
	258	+
	259	+#define CONFIG_ARMV7_VIRT
	260	+
253	261	#endif /* __CONFIG_H */