board: axs10x switch serial port and Ethernet to driver model

With this change Synopsys DesignWare SDP board is switched to driver model for both serial port (serial_dw) and Ethernet (Designware GMAC). This simplifies include/configs/axs101.h and allows for reuse of Linux's Device Tree description. For simplicity Linux's .dts files are not blindly copied but only very few extracts of them are really used (those that are supported in U-Boot at the moment). Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>

board: axs10x switch serial port and Ethernet to driver model
With this change Synopsys DesignWare SDP board is switched to driver model for both serial port (serial_dw) and Ethernet (Designware GMAC). This simplifies include/configs/axs101.h and allows for reuse of Linux's Device Tree description. For simplicity Linux's .dts files are not blindly copied but only very few extracts of them are really used (those that are supported in U-Boot at the moment). Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Alexey Brodkin
1 parent db1f17f894
Showing 6 changed files with 72 additions and 39 deletions Side-by-side Diff
arch/arc/dts/Makefile
arch/arc/dts/axs10x.dts
board/synopsys/axs101/axs101.c
configs/axs101_defconfig
configs/axs103_defconfig
include/configs/axs101.h
@@ -2,6 +2,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
  
+dtb-$(CONFIG_TARGET_AXS101) +=  axs10x.dtb
 dtb-$(CONFIG_TARGET_ARCANGEL4) +=  arcangel4.dtb
 dtb-$(CONFIG_TARGET_TB100) +=  abilis_tb100.dtb
  
+/*
+ * Copyright (C) 2015 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+
+#include "skeleton.dtsi"
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		console = &uart0;
+	};
+
+	clocks {
+		apbclk: apbclk {
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+			#clock-cells = <0>;
+		};
+	};
+
+	uart0: serial0@e0022000 {
+		compatible = "snps,dw-apb-uart";
+		reg = <0xe0022000 0x1000>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+	};
+
+	ethernet@e0018000 {
+		#interrupt-cells = <1>;
+		compatible = "altr,socfpga-stmmac";
+		reg = < 0xe0018000 0x2000 >;
+		interrupts = < 25 >;
+		interrupt-names = "macirq";
+		phy-mode = "gmii";
+		snps,pbl = < 32 >;
+		clocks = <&apbclk>;
+		clock-names = "stmmaceth";
+		max-speed = <100>;
+	};
+};
@@ -7,8 +7,6 @@
 #include <common.h>
 #include <dwmmc.h>
 #include <malloc.h>
-#include <netdev.h>
-#include <phy.h>
 #include "axs10x.h"
  
 DECLARE_GLOBAL_DATA_PTR;
@@ -34,16 +32,6 @@
  
 	return 0;
 }
-
-int board_eth_init(bd_t *bis)
-{
-	if (designware_initialize(ARC_DWGMAC_BASE,
-				  PHY_INTERFACE_MODE_RGMII) >= 0)
-		return 1;
-
-	return 0;
-}
-
  
 #define AXS_MB_CREG	0xE0011000
  
 CONFIG_ARC=y
 CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARC_CACHE_LINE_SHIFT=5
+CONFIG_DM_SERIAL=y
 CONFIG_SYS_CLK_FREQ=750000000
 CONFIG_SYS_TEXT_BASE=0x81000000
+CONFIG_DEFAULT_DEVICE_TREE="axs10x"
 CONFIG_SYS_PROMPT="AXS# "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_NETDEVICES=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_ARC=y
 CONFIG_ISA_ARCV2=y
+CONFIG_DM_SERIAL=y
 CONFIG_SYS_CLK_FREQ=50000000
 CONFIG_SYS_TEXT_BASE=0x81000000
+CONFIG_DEFAULT_DEVICE_TREE="axs10x"
 CONFIG_SYS_PROMPT="AXS# "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_NETDEVICES=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USE_PRIVATE_LIBGCC=y
@@ -39,6 +39,8 @@
 #define CONFIG_BOARD_TYPES
 #define CONFIG_BOARD_EARLY_INIT_F
  
+#define CONFIG_OF_LIBFDT
+
 /*
  * NAND Flash configuration
  */
  
  
  
  
@@ -48,28 +50,14 @@
  
 /*
  * UART configuration
- *
- * CONFIG_CONS_INDEX = 1 - Debug UART
- * CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB
  */
-#define CONFIG_CONS_INDEX		4
+#define CONFIG_DW_SERIAL
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	-4
-#if (CONFIG_CONS_INDEX == 1)
-	/* Debug UART */
-#	define CONFIG_SYS_NS16550_CLK		33333000
-#else
-	/* FPGA UARTs use different clock */
-#	define CONFIG_SYS_NS16550_CLK		33333333
-#endif
-#define CONFIG_SYS_NS16550_COM1		(ARC_APB_PERIPHERAL_BASE + 0x5000)
-#define CONFIG_SYS_NS16550_COM2		(ARC_FPGA_PERIPHERAL_BASE + 0x20000)
-#define CONFIG_SYS_NS16550_COM3		(ARC_FPGA_PERIPHERAL_BASE + 0x21000)
-#define CONFIG_SYS_NS16550_COM4		(ARC_FPGA_PERIPHERAL_BASE + 0x22000)
+#define CONFIG_SYS_NS16550_CLK		33333333
 #define CONFIG_SYS_NS16550_MEM32
-
 #define CONFIG_BAUDRATE			115200
+
 /*
  * I2C configuration
  */
  
  
  
@@ -119,18 +107,11 @@
 #define CONFIG_DW_AUTONEG
  
 /*
- * Command line configuration
+ * Commands still not supported in Kconfig
  */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_RARP
-
-#define CONFIG_OF_LIBFDT
  
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_MAXARGS		16
...	...	@@ -2,6 +2,7 @@
2	2	# SPDX-License-Identifier: GPL-2.0+
3	3	#
4	4
	5	+dtb-$(CONFIG_TARGET_AXS101) += axs10x.dtb
5	6	dtb-$(CONFIG_TARGET_ARCANGEL4) += arcangel4.dtb
6	7	dtb-$(CONFIG_TARGET_TB100) += abilis_tb100.dtb
7	8
	1	+/*
	2	+ * Copyright (C) 2015 Synopsys, Inc. All rights reserved.
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ */
	6	+/dts-v1/;
	7	+
	8	+#include "skeleton.dtsi"
	9	+
	10	+/ {
	11	+ #address-cells = <1>;
	12	+ #size-cells = <1>;
	13	+
	14	+ aliases {
	15	+ console = &uart0;
	16	+ };
	17	+
	18	+ clocks {
	19	+ apbclk: apbclk {
	20	+ compatible = "fixed-clock";
	21	+ clock-frequency = <50000000>;
	22	+ #clock-cells = <0>;
	23	+ };
	24	+ };
	25	+
	26	+ uart0: serial0@e0022000 {
	27	+ compatible = "snps,dw-apb-uart";
	28	+ reg = <0xe0022000 0x1000>;
	29	+ reg-shift = <2>;
	30	+ reg-io-width = <4>;
	31	+ };
	32	+
	33	+ ethernet@e0018000 {
	34	+ #interrupt-cells = <1>;
	35	+ compatible = "altr,socfpga-stmmac";
	36	+ reg = < 0xe0018000 0x2000 >;
	37	+ interrupts = < 25 >;
	38	+ interrupt-names = "macirq";
	39	+ phy-mode = "gmii";
	40	+ snps,pbl = < 32 >;
	41	+ clocks = <&apbclk>;
	42	+ clock-names = "stmmaceth";
	43	+ max-speed = <100>;
	44	+ };
	45	+};
...	...	@@ -7,8 +7,6 @@
7	7	#include <common.h>
8	8	#include <dwmmc.h>
9	9	#include <malloc.h>
10		-#include <netdev.h>
11		-#include <phy.h>
12	10	#include "axs10x.h"
13	11
14	12	DECLARE_GLOBAL_DATA_PTR;
...	...	@@ -34,16 +32,6 @@
34	32
35	33	return 0;
36	34	}
37		-
38		-int board_eth_init(bd_t *bis)
39		-{
40		- if (designware_initialize(ARC_DWGMAC_BASE,
41		- PHY_INTERFACE_MODE_RGMII) >= 0)
42		- return 1;
43		-
44		- return 0;
45		-}
46		-
47	35
48	36	#define AXS_MB_CREG 0xE0011000
49	37
1	1	CONFIG_ARC=y
2	2	CONFIG_SYS_DCACHE_OFF=y
3	3	CONFIG_ARC_CACHE_LINE_SHIFT=5
	4	+CONFIG_DM_SERIAL=y
4	5	CONFIG_SYS_CLK_FREQ=750000000
5	6	CONFIG_SYS_TEXT_BASE=0x81000000
	7	+CONFIG_DEFAULT_DEVICE_TREE="axs10x"
6	8	CONFIG_SYS_PROMPT="AXS# "
7	9	# CONFIG_CMD_IMLS is not set
8	10	# CONFIG_CMD_FLASH is not set
9	11	# CONFIG_CMD_SETEXPR is not set
10		-CONFIG_NETDEVICES=y
	12	+CONFIG_CMD_DHCP=y
	13	+CONFIG_CMD_PING=y
	14	+CONFIG_OF_CONTROL=y
	15	+CONFIG_OF_EMBED=y
	16	+CONFIG_NET_RANDOM_ETHADDR=y
	17	+CONFIG_DM=y
	18	+CONFIG_CLK=y
	19	+CONFIG_DM_ETH=y
11	20	CONFIG_ETH_DESIGNWARE=y
12	21	CONFIG_USE_PRIVATE_LIBGCC=y
1	1	CONFIG_ARC=y
2	2	CONFIG_ISA_ARCV2=y
	3	+CONFIG_DM_SERIAL=y
3	4	CONFIG_SYS_CLK_FREQ=50000000
4	5	CONFIG_SYS_TEXT_BASE=0x81000000
	6	+CONFIG_DEFAULT_DEVICE_TREE="axs10x"
5	7	CONFIG_SYS_PROMPT="AXS# "
6	8	# CONFIG_CMD_IMLS is not set
7	9	# CONFIG_CMD_FLASH is not set
8	10	# CONFIG_CMD_SETEXPR is not set
9		-CONFIG_NETDEVICES=y
	11	+CONFIG_CMD_DHCP=y
	12	+CONFIG_CMD_PING=y
	13	+CONFIG_OF_CONTROL=y
	14	+CONFIG_OF_EMBED=y
	15	+CONFIG_NET_RANDOM_ETHADDR=y
	16	+CONFIG_DM=y
	17	+CONFIG_CLK=y
	18	+CONFIG_DM_ETH=y
10	19	CONFIG_ETH_DESIGNWARE=y
11	20	CONFIG_USE_PRIVATE_LIBGCC=y
...	...	@@ -39,6 +39,8 @@
39	39	#define CONFIG_BOARD_TYPES
40	40	#define CONFIG_BOARD_EARLY_INIT_F
41	41
	42	+#define CONFIG_OF_LIBFDT
	43	+
42	44	/*
43	45	* NAND Flash configuration
44	46	*/
45	47
46	48
47	49
48	50
...	...	@@ -48,28 +50,14 @@
48	50
49	51	/*
50	52	* UART configuration
51		- *
52		- * CONFIG_CONS_INDEX = 1 - Debug UART
53		- * CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB
54	53	*/
55		-#define CONFIG_CONS_INDEX 4
	54	+#define CONFIG_DW_SERIAL
56	55	#define CONFIG_SYS_NS16550
57	56	#define CONFIG_SYS_NS16550_SERIAL
58		-#define CONFIG_SYS_NS16550_REG_SIZE -4
59		-#if (CONFIG_CONS_INDEX == 1)
60		- /* Debug UART */
61		-# define CONFIG_SYS_NS16550_CLK 33333000
62		-#else
63		- /* FPGA UARTs use different clock */
64		-# define CONFIG_SYS_NS16550_CLK 33333333
65		-#endif
66		-#define CONFIG_SYS_NS16550_COM1 (ARC_APB_PERIPHERAL_BASE + 0x5000)
67		-#define CONFIG_SYS_NS16550_COM2 (ARC_FPGA_PERIPHERAL_BASE + 0x20000)
68		-#define CONFIG_SYS_NS16550_COM3 (ARC_FPGA_PERIPHERAL_BASE + 0x21000)
69		-#define CONFIG_SYS_NS16550_COM4 (ARC_FPGA_PERIPHERAL_BASE + 0x22000)
	57	+#define CONFIG_SYS_NS16550_CLK 33333333
70	58	#define CONFIG_SYS_NS16550_MEM32
71		-
72	59	#define CONFIG_BAUDRATE 115200
	60	+
73	61	/*
74	62	* I2C configuration
75	63	*/
76	64
77	65
78	66
...	...	@@ -119,18 +107,11 @@
119	107	#define CONFIG_DW_AUTONEG
120	108
121	109	/*
122		- * Command line configuration
	110	+ * Commands still not supported in Kconfig
123	111	*/
124		-#define CONFIG_CMD_DHCP
125		-#define CONFIG_CMD_EEPROM
126	112	#define CONFIG_CMD_FAT
127		-#define CONFIG_CMD_I2C
128	113	#define CONFIG_CMD_MMC
129	114	#define CONFIG_CMD_NAND
130		-#define CONFIG_CMD_PING
131		-#define CONFIG_CMD_RARP
132		-
133		-#define CONFIG_OF_LIBFDT
134	115
135	116	#define CONFIG_AUTO_COMPLETE
136	117	#define CONFIG_SYS_MAXARGS 16