Eric Lee / smarc-uboot

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Commit fb4a2409b46c98672557bb07dec8e873bef1e23c

Authored by Aneesh Bansal
Committed by York Sun
1 parent bea3cbb07f
Exists in v2017.01-smarct4x and in 40 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS 

Changes:
1. L2 cache is being invalidated by Boot ROM code for e6500 core.
   So removing the invalidation from start.S
2. Clear the LAW and corresponding configuration for CPC. Boot ROM
   code uses it as hosekeeping area.
3. For Secure boot, CPC is configured as SRAM and used as house
   keeping area. This configuration is to be disabled once in uboot.
   Earlier this disabling of CPC as SRAM was happening in cpu_init_r.
   As a result cache invalidation function was getting skipped in
   case CPC is configured as SRAM.This was causing random crashes.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

Showing 5 changed files with 35 additions and 6 deletions Side-by-side Diff

... ... @@ -427,6 +427,10 @@
427 427 In this mode, a single differential clock is used to supply
428 428 clocks to the sysclock, ddrclock and usbclock.
429 429  
  430 + CONFIG_SYS_CPC_REINIT_F
  431 + This CONFIG is defined when the CPC is configured as SRAM at the
  432 + time of U-boot entry and is required to be re-initialized.
  433 +
430 434 - Generic CPU options:
431 435 CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
432 436  
arch/powerpc/cpu/mpc85xx/cpu_init.c
Diff comments   View file @ fb4a240
... ... @@ -173,17 +173,14 @@
173 173 #endif
174 174  
175 175 #ifdef CONFIG_SYS_FSL_CPC
176   -static void enable_cpc(void)
  176 +#if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
  177 +static void disable_cpc_sram(void)
177 178 {
178 179 int i;
179   - u32 size = 0;
180 180  
181 181 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
182 182  
183 183 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
184   - u32 cpccfg0 = in_be32(&cpc->cpccfg0);
185   - size += CPC_CFG0_SZ_K(cpccfg0);
186   -#ifdef CONFIG_RAMBOOT_PBL
187 184 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
188 185 /* find and disable LAW of SRAM */
189 186 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
190 187  
... ... @@ -198,8 +195,21 @@
198 195 out_be32(&cpc->cpccsr0, 0);
199 196 out_be32(&cpc->cpcsrcr0, 0);
200 197 }
  198 + }
  199 +}
201 200 #endif
202 201  
  202 +static void enable_cpc(void)
  203 +{
  204 + int i;
  205 + u32 size = 0;
  206 +
  207 + cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
  208 +
  209 + for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
  210 + u32 cpccfg0 = in_be32(&cpc->cpccfg0);
  211 + size += CPC_CFG0_SZ_K(cpccfg0);
  212 +
203 213 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
204 214 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
205 215 #endif
206 216  
... ... @@ -298,7 +308,11 @@
298 308 law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
299 309 if (law.index != -1)
300 310 disable_law(law.index);
  311 +
  312 +#if defined(CONFIG_SYS_CPC_REINIT_F)
  313 + disable_cpc_sram();
301 314 #endif
  315 +#endif
302 316  
303 317 #ifdef CONFIG_CPM2
304 318 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
... ... @@ -598,6 +612,9 @@
598 612 puts("disabled\n");
599 613 #endif
600 614  
  615 +#if defined(CONFIG_RAMBOOT_PBL)
  616 + disable_cpc_sram();
  617 +#endif
601 618 enable_cpc();
602 619  
603 620 #ifndef CONFIG_SYS_FSL_NO_SERDES
arch/powerpc/cpu/mpc85xx/start.S
Diff comments   View file @ fb4a240
... ... @@ -122,7 +122,8 @@
122 122 #endif
123 123  
124 124  
125   -#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
  125 +#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \
  126 + !defined(CONFIG_E6500)
126 127 /* ISBC uses L2 as stack.
127 128 * Disable L2 cache here so that u-boot can enable it later
128 129 * as part of it's normal flow
arch/powerpc/include/asm/fsl_secure_boot.h
Diff comments   View file @ fb4a240
... ... @@ -17,6 +17,12 @@
17 17 #endif
18 18 #define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000
19 19  
  20 +#if defined(CONFIG_B4860QDS)
  21 +#define CONFIG_SYS_CPC_REINIT_F
  22 +#undef CONFIG_SYS_INIT_L3_ADDR
  23 +#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
  24 +#endif
  25 +
20 26 #endif
21 27 #endif
... ... @@ -744,6 +744,7 @@
744 744 Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
745 745 Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
746 746 Active powerpc mpc85xx - freescale b4860qds B4860QDS B4860QDS:PPC_B4860 -
  747 +Active powerpc mpc85xx - freescale b4860qds B4860QDS_SECURE_BOOT B4860QDS:PPC_B4860,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
747 748 Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
748 749 Active powerpc mpc85xx - freescale b4860qds B4860QDS_SPIFLASH B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
749 750 Active powerpc mpc85xx - freescale b4860qds B4860QDS_SRIO_PCIE_BOOT B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -