dts: 820c: Add pinctrl node and uart mux

* Add pinctrl node for TLMM and add mux request for uart node. * Rename uart to the actual board uart port. * Fix indentendation of sdhc2 node. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>

dts: 820c: Add pinctrl node and uart mux
* Add pinctrl node for TLMM and add mux request for uart node. * Rename uart to the actual board uart port. * Fix indentendation of sdhc2 node. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Ramon Fried · Tom Rini
1 parent ea7bf8fb08
Showing 2 changed files with 31 additions and 8 deletions Side-by-side Diff
arch/arm/dts/dragonboard820c-uboot.dtsi
arch/arm/dts/dragonboard820c.dts
@@ -13,14 +13,22 @@
 	soc {
 		u-boot,dm-pre-reloc;
  
+		qcom,tlmm@1010000 {
+			u-boot,dm-pre-reloc;
+
+			uart {
+				u-boot,dm-pre-reloc;
+			};
+		};
+
 		clock-controller@300000 {
 			u-boot,dm-pre-reloc;
 		};
  
 		serial@75b0000 {
 			u-boot,dm-pre-reloc;
-			};
 		};
+	};
 };
  
 &pm8994_pon {
@@ -8,6 +8,7 @@
 /dts-v1/;
  
 #include "skeleton64.dtsi"
+#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
  
 / {
 	model = "Qualcomm Technologies, Inc. DB820c";
@@ -16,7 +17,7 @@
 	#size-cells = <2>;
  
 	aliases {
-		serial0 = &blsp2_uart1;
+		serial0 = &blsp2_uart2;
 	};
  
 	chosen {
  
  
@@ -63,18 +64,32 @@
 			reg = <0x300000 0x90000>;
 		};
  
-		blsp2_uart1: serial@75b0000 {
+		pinctrl: qcom,tlmm@1010000 {
+			compatible = "qcom,tlmm-apq8096";
+			reg = <0x1010000 0x400000>;
+
+			blsp8_uart: uart {
+				function = "blsp_uart8";
+				pins = "GPIO_4", "GPIO_5";
+				drive-strength = <DRIVE_STRENGTH_8MA>;
+				bias-disable;
+			};
+		};
+
+		blsp2_uart2: serial@75b0000 {
 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 			reg = <0x75b0000 0x1000>;
 			clock = <&gcc 4>;
+			pinctrl-names = "uart";
+			pinctrl-0 = <&blsp8_uart>;
 		};
  
 		sdhc2: sdhci@74a4900 {
-			 compatible = "qcom,sdhci-msm-v4";
-			 reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
-			 index = <0x0>;
-			 bus-width = <4>;
-			 clock = <&gcc 0>;
+			compatible = "qcom,sdhci-msm-v4";
+			reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
+			index = <0x0>;
+			bus-width = <4>;
+			clock = <&gcc 0>;
 			clock-frequency = <200000000>;
 		 };
...	...	@@ -13,14 +13,22 @@
13	13	soc {
14	14	u-boot,dm-pre-reloc;
15	15
	16	+ qcom,tlmm@1010000 {
	17	+ u-boot,dm-pre-reloc;
	18	+
	19	+ uart {
	20	+ u-boot,dm-pre-reloc;
	21	+ };
	22	+ };
	23	+
16	24	clock-controller@300000 {
17	25	u-boot,dm-pre-reloc;
18	26	};
19	27
20	28	serial@75b0000 {
21	29	u-boot,dm-pre-reloc;
22		- };
23	30	};
	31	+ };
24	32	};
25	33
26	34	&pm8994_pon {
...	...	@@ -8,6 +8,7 @@
8	8	/dts-v1/;
9	9
10	10	#include "skeleton64.dtsi"
	11	+#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
11	12
12	13	/ {
13	14	model = "Qualcomm Technologies, Inc. DB820c";
...	...	@@ -16,7 +17,7 @@
16	17	#size-cells = <2>;
17	18
18	19	aliases {
19		- serial0 = &blsp2_uart1;
	20	+ serial0 = &blsp2_uart2;
20	21	};
21	22
22	23	chosen {
23	24
24	25
...	...	@@ -63,18 +64,32 @@
63	64	reg = <0x300000 0x90000>;
64	65	};
65	66
66		- blsp2_uart1: serial@75b0000 {
	67	+ pinctrl: qcom,tlmm@1010000 {
	68	+ compatible = "qcom,tlmm-apq8096";
	69	+ reg = <0x1010000 0x400000>;
	70	+
	71	+ blsp8_uart: uart {
	72	+ function = "blsp_uart8";
	73	+ pins = "GPIO_4", "GPIO_5";
	74	+ drive-strength = <DRIVE_STRENGTH_8MA>;
	75	+ bias-disable;
	76	+ };
	77	+ };
	78	+
	79	+ blsp2_uart2: serial@75b0000 {
67	80	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
68	81	reg = <0x75b0000 0x1000>;
69	82	clock = <&gcc 4>;
	83	+ pinctrl-names = "uart";
	84	+ pinctrl-0 = <&blsp8_uart>;
70	85	};
71	86
72	87	sdhc2: sdhci@74a4900 {
73		- compatible = "qcom,sdhci-msm-v4";
74		- reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
75		- index = <0x0>;
76		- bus-width = <4>;
77		- clock = <&gcc 0>;
	88	+ compatible = "qcom,sdhci-msm-v4";
	89	+ reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
	90	+ index = <0x0>;
	91	+ bus-width = <4>;
	92	+ clock = <&gcc 0>;
78	93	clock-frequency = <200000000>;
79	94	};
80	95