Commit fc33705e66cc2c753026f04f92555ad00b709f11
Committed by
Tom Rini
Tom Rini
1 parent
f35034fe16
Exists in
master
and in
53 other branches
Allow AM335x MPU core clock speed to be specified in the board config file
Allow AM335x MPU core clock speed to be specified in the board config file. To use, add the following to the board's config file:- #define CONFIG_SYS_MPUCLK <desired clock freq in MHz> Signed-off-by: Mark Jackson <mpfj@newflow.co.uk> Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
Showing 2 changed files with 9 additions and 2 deletions Side-by-side Diff
README
| ... | ... | @@ -3878,6 +3878,10 @@ |
| 3878 | 3878 | If defined, the x86 reset vector code is included. This is not |
| 3879 | 3879 | needed when U-Boot is running from Coreboot. |
| 3880 | 3880 | |
| 3881 | +- CONFIG_SYS_MPUCLK | |
| 3882 | + Defines the MPU clock speed (in MHz). | |
| 3883 | + | |
| 3884 | + NOTE : currently only supported on AM335x platforms. | |
| 3881 | 3885 | |
| 3882 | 3886 | Freescale QE/FMAN Firmware Support: |
| 3883 | 3887 | ----------------------------------- |
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
| ... | ... | @@ -21,8 +21,11 @@ |
| 21 | 21 | |
| 22 | 22 | #define OSC (V_OSCK/1000000) |
| 23 | 23 | |
| 24 | -/* MAIN PLL Fdll = 550 MHZ, */ | |
| 25 | -#define MPUPLL_M 550 | |
| 24 | +/* MAIN PLL Fdll = 550 MHz, by default */ | |
| 25 | +#ifndef CONFIG_SYS_MPUCLK | |
| 26 | +#define CONFIG_SYS_MPUCLK 550 | |
| 27 | +#endif | |
| 28 | +#define MPUPLL_M CONFIG_SYS_MPUCLK | |
| 26 | 29 | #define MPUPLL_N (OSC-1) |
| 27 | 30 | #define MPUPLL_M2 1 |
| 28 | 31 |