Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit fc54c7fa0addfc0e33b703be0502395920d2926b

Authored by Liu Gang
Committed by Andy Fleming
1 parent 81fa73bab0
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

powerpc/corenet_ds: Update README and README.srio-pcie-boot-corenet 

Added descriptions about boot from PCIE in the files README and
doc/README.srio-pcie-boot-corenet, and changed the name of the
doc/README.srio-boot-corenet to doc/README.srio-pcie-boot-corenet.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

Showing 3 changed files with 118 additions and 105 deletions Side-by-side Diff

... ... @@ -3092,12 +3092,12 @@
3092 3092 These two #defines specify the address and size of the
3093 3093 environment area within the remote memory space. The
3094 3094 local device can get the environment from remote memory
3095   - space by SRIO or other links.
  3095 + space by SRIO or PCIE links.
3096 3096  
3097 3097 BE CAREFUL! For some special cases, the local device can not use
3098 3098 "saveenv" command. For example, the local device will get the
3099   -environment stored in a remote NOR flash by SRIO link, but it can
3100   -not erase, write this NOR flash by SRIO interface.
  3099 +environment stored in a remote NOR flash by SRIO or PCIE link,
  3100 +but it can not erase, write this NOR flash by SRIO or PCIE interface.
3101 3101  
3102 3102 - CONFIG_ENV_IS_IN_NAND:
3103 3103  
... ... @@ -3538,9 +3538,9 @@
3538 3538 - CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
3539 3539 Specifies that QE/FMAN firmware is located in the remote (master)
3540 3540 memory space. CONFIG_SYS_FMAN_FW_ADDR is a virtual address which
3541   - can be mapped from slave TLB->slave LAW->slave SRIO outbound window
3542   - ->master inbound window->master LAW->the ucode address in master's
3543   - NOR flash.
  3541 + can be mapped from slave TLB->slave LAW->slave SRIO or PCIE outbound
  3542 + window->master inbound window->master LAW->the ucode address in
  3543 + master's memory space.
3544 3544  
3545 3545 Building the Software:
3546 3546 ======================
doc/README.srio-boot-corenet
View file @ fc54c7f
1   -------------------------------
2   -SRIO Boot on Corenet Platforms
3   -------------------------------
4   -
5   -For some PowerPC processors with SRIO interface, boot location can be configured
6   -to SRIO by RCW. The processor booting from SRIO can do without flash for u-boot
7   -image, ucode and ENV. All the images can be fetched from another processor's
8   -memory space by SRIO link connected between them.
9   -
10   -This document describes the processes based on an example implemented on P4080DS
11   -platforms and a RCW example with boot from SRIO configuration.
12   -
13   -Environment of the SRIO boot:
14   - a) Master and slave can be SOCs in one board or SOCs in separate boards.
15   - b) They are connected with SRIO links, whether 1x or 4x, and directly or
16   - through switch system.
17   - c) Only Master has NorFlash for booting, and all the Master's and Slave's
18   - U-Boot images, UCodes will be stored in this flash.
19   - d) Slave has its own EEPROM for RCW and PBI.
20   - e) Slave's RCW should configure the SerDes for SRIO boot port, set the boot
21   - location to SRIO, and holdoff all the cores.
22   -
23   - ---------- ----------- -----------
24   - | | | | | |
25   - | | | | | |
26   - | NorFlash|<----->| Master | SRIO | Slave |<---->[EEPROM]
27   - | | | |<===========>| |
28   - | | | | | |
29   - ---------- ----------- -----------
30   -
31   -The example based on P4080DS platform:
32   - Two P4080DS platforms can be used to implement the boot from SRIO. Their SRIO
33   - ports 1 will be connected directly and will be used for the boot from SRIO.
34   -
35   - 1. Slave's RCW example for boot from SRIO port 1 and all cores in holdoff.
36   - 00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000
37   - 00000010: 1818 1818 0000 8888 7440 4000 0000 2000
38   - 00000020: f440 0000 0100 0000 0000 0000 0000 0000
39   - 00000030: 0000 0000 0083 0000 0000 0000 0000 0000
40   - 00000040: 0000 0000 0000 0000 0813 8040 063c 778f
41   -
42   - 2. Sequence in Step by Step.
43   - a) Update RCW for slave with boot from SRIO port 1 configuration.
44   - b) Program slave's U-Boot image, UCode, and ENV parameters into master's
45   - NorFlash.
46   - c) Set environment variable "bootmaster" to "SRIO1" and save environment
47   - for master.
48   - setenv bootmaster SRIO1
49   - saveenv
50   - d) Restart up master and it will boot up normally from its NorFlash.
51   - Then, it will finish necessary configurations for slave's boot from
52   - SRIO port 1.
53   - e) Master will set inbound SRIO windows covered slave's U-Boot image stored
54   - in master's NorFlash.
55   - f) Master will set an inbound SRIO window covered slave's UCode and ENV
56   - stored in master's NorFlash.
57   - g) Master will set outbound SRIO windows in order to configure slave's
58   - registers for the core's releasing.
59   - h) Since all cores of slave in holdoff, slave should be powered on before all
60   - the above master's steps, and wait to be released by master. In the
61   - startup phase of the slave from SRIO, it will finish some necessary
62   - configurations.
63   - i) Slave will set a specific TLB entry for the boot process.
64   - j) Slave will set a LAW entry with the TargetID SRIO port 1 for the boot.
65   - k) Slave will set a specific TLB entry in order to fetch UCode and ENV
66   - from master.
67   - l) Slave will set a LAW entry with the TargetID SRIO port 1 for UCode and ENV.
68   -
69   -How to use this feature:
70   - To use this feature, you need to focus those points.
71   -
72   - 1. Slave's RCW with SRIO boot configurations, and all cores in holdoff
73   - configurations.
74   - Please refer to the examples given above.
75   -
76   - 2. U-Boot image's compilation.
77   - For master, U-Boot image should be generated normally.
78   -
79   - For example, master U-Boot image used on P4080DS should be compiled with
80   -
81   - make P4080DS_config.
82   -
83   - For slave, U-Boot image should be generated specifically by
84   -
85   - make xxxx_SRIOBOOT_SLAVE_config.
86   -
87   - For example, slave U-Boot image used on P4080DS should be compiled with
88   -
89   - make P4080DS_SRIOBOOT_SLAVE_config.
90   -
91   - 3. Necessary modifications based on a specific environment.
92   - For a specific environment, the addresses of the slave's U-Boot image,
93   - UCode, ENV stored in master's NorFlash, and any other configurations
94   - can be modified in the file:
95   - include/configs/corenet_ds.h.
96   -
97   - 4. Set and save the environment variable "bootmaster" with "SRIO1" or "SRIO2"
98   - for master, and then restart it in order to perform the role as a master
99   - for boot from SRIO.
doc/README.srio-pcie-boot-corenet
Diff comments   View file @ fc54c7f
  1 +---------------------------------------
  2 +SRIO and PCIE Boot on Corenet Platforms
  3 +---------------------------------------
  4 +
  5 +For some PowerPC processors with SRIO or PCIE interface, boot location can be
  6 +configured to SRIO or PCIE by RCW. The processor booting from SRIO or PCIE can
  7 +do without flash for u-boot image, ucode and ENV. All the images can be fetched
  8 +from another processor's memory space by SRIO or PCIE link connected between
  9 +them.
  10 +
  11 +This document describes the processes based on an example implemented on P4080DS
  12 +platforms and a RCW example with boot from SRIO or PCIE configuration.
  13 +
  14 +Environment of the SRIO or PCIE boot:
  15 + a) Master and slave can be SOCs in one board or SOCs in separate boards.
  16 + b) They are connected with SRIO or PCIE links, whether 1x, 2x or 4x, and
  17 + directly or through switch system.
  18 + c) Only Master has NorFlash for booting, and all the Master's and Slave's
  19 + U-Boot images, UCodes will be stored in this flash.
  20 + d) Slave has its own EEPROM for RCW and PBI.
  21 + e) Slave's RCW should configure the SerDes for SRIO or PCIE boot port, set
  22 + the boot location to SRIO or PCIE, and holdoff all the cores.
  23 +
  24 + ---------- ----------- -----------
  25 + | | | | | |
  26 + | | | | | |
  27 + | NorFlash|<----->| Master |SRIO or PCIE | Slave |<---->[EEPROM]
  28 + | | | |<===========>| |
  29 + | | | | | |
  30 + ---------- ----------- -----------
  31 +
  32 +The example based on P4080DS platform:
  33 + Two P4080DS platforms can be used to implement the boot from SRIO or PCIE.
  34 + Their SRIO or PCIE ports 1 will be connected directly and will be used for
  35 + the boot from SRIO or PCIE.
  36 +
  37 + 1. Slave's RCW example for boot from SRIO port 1 and all cores in holdoff.
  38 + 00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000
  39 + 00000010: 1818 1818 0000 8888 7440 4000 0000 2000
  40 + 00000020: f440 0000 0100 0000 0000 0000 0000 0000
  41 + 00000030: 0000 0000 0083 0000 0000 0000 0000 0000
  42 + 00000040: 0000 0000 0000 0000 0813 8040 063c 778f
  43 +
  44 + 2. Slave's RCW example for boot from PCIE port 1 and all cores in holdoff.
  45 + 00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000
  46 + 00000010: 1818 1818 0000 8888 1440 4000 0000 2000
  47 + 00000020: f040 0000 0100 0000 0020 0000 0000 0000
  48 + 00000030: 0000 0000 0083 0000 0000 0000 0000 0000
  49 + 00000040: 0000 0000 0000 0000 0813 8040 547e ffc9
  50 +
  51 + 3. Sequence in Step by Step.
  52 + a) Update RCW for slave with boot from SRIO or PCIE port 1 configuration.
  53 + b) Program slave's U-Boot image, UCode, and ENV parameters into master's
  54 + NorFlash.
  55 + c) Set environment variable "bootmaster" to "SRIO1" or "PCIE1" and save
  56 + environment for master.
  57 + setenv bootmaster SRIO1
  58 + or
  59 + setenv bootmaster PCIE1
  60 + saveenv
  61 + d) Restart up master and it will boot up normally from its NorFlash.
  62 + Then, it will finish necessary configurations for slave's boot from
  63 + SRIO or PCIE port 1.
  64 + e) Master will set inbound SRIO or PCIE windows covered slave's U-Boot
  65 + image stored in master's NorFlash.
  66 + f) Master will set an inbound SRIO or PCIE window covered slave's UCode
  67 + and ENV stored in master's NorFlash.
  68 + g) Master will set outbound SRIO or PCIE windows in order to configure
  69 + slave's registers for the core's releasing.
  70 + h) Since all cores of slave in holdoff, slave should be powered on before
  71 + all the above master's steps, and wait to be released by master. In the
  72 + startup phase of the slave from SRIO or PCIE, it will finish some
  73 + necessary configurations.
  74 + i) Slave will set a specific TLB entry for the boot process.
  75 + j) Slave will set a LAW entry with the TargetID SRIO or PCIE port 1 for
  76 + the boot.
  77 + k) Slave will set a specific TLB entry in order to fetch UCode and ENV
  78 + from master.
  79 + l) Slave will set a LAW entry with the TargetID SRIO or PCIE port 1 for
  80 + UCode and ENV.
  81 +
  82 +How to use this feature:
  83 + To use this feature, you need to focus those points.
  84 +
  85 + 1. Slave's RCW with SRIO or PCIE boot configurations, and all cores in holdoff
  86 + configurations.
  87 + Please refer to the examples given above.
  88 +
  89 + 2. U-Boot image's compilation.
  90 + For master, U-Boot image should be generated normally.
  91 +
  92 + For example, master U-Boot image used on P4080DS should be compiled with
  93 +
  94 + make P4080DS_config.
  95 +
  96 + For slave, U-Boot image should be generated specifically by
  97 +
  98 + make xxxx_SRIO_PCIE_BOOT_config.
  99 +
  100 + For example, slave U-Boot image used on P4080DS should be compiled with
  101 +
  102 + make P4080DS_SRIO_PCIE_BOOT_config.
  103 +
  104 + 3. Necessary modifications based on a specific environment.
  105 + For a specific environment, the addresses of the slave's U-Boot image,
  106 + UCode, ENV stored in master's NorFlash, and any other configurations
  107 + can be modified in the file:
  108 + include/configs/corenet_ds.h.
  109 +
  110 + 4. Set and save the environment variable "bootmaster" with "SRIO1", "SRIO2"
  111 + or "PCIE1", "PCIE2", "PCIE3" for master, and then restart it in order to
  112 + perform the role as a master for boot from SRIO or PCIE.