Coding Style cleanup.

Wolfgang Denk
1 parent 3231ea64f4
Showing 3 changed files with 58 additions and 62 deletions Side-by-side Diff
board/v38b/ethaddr.c
doc/README.nand
include/configs/V38B.h
@@ -118,8 +118,8 @@
 	crcval = 0;
  
 	for (i=0; i<NBYTES; i++)
-		
  
+
 	if (!check_device())
 		*perr = ERR_NO_NUMBER;
 	else {
@@ -224,7 +224,7 @@
 			rdat = (rdat >> 1) | 0x80;
 		else
 			rdat = rdat >> 1;
-		
+
 		udelay(60);	/* at least 60 us */
 	}
 	/* copy the return value */
 NAND FLASH commands and notes
  
-
 See NOTE below!!!
  
-
 # (C) Copyright 2003
 # Dave Ellis, SIXNET, dge@sixnetio.com
 #
@@ -207,7 +205,6 @@
 The consequence of this is that the legacy NAND can't be removed  from
 the tree until the DoC is ported to use the new NAND support (or boards
 with DoC will break).
-
  
  
 Additional improvements to the NAND subsystem by Guido Classen, 10-10-2006
@@ -11,7 +11,7 @@
  *
  * This program is distributed in the hope that it will be useful, but WITHOUT
  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.	 See the GNU General Public License
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  * for more details.
  *
  * You should have received a copy of the GNU General Public License along
  
  
  
  
  
  
  
@@ -35,35 +35,35 @@
  * (easy to change)
 */
  
-#define CONFIG_MPC5xxx			1	/* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200			1	/* This is an MPC5200 CPU */
-#define CONFIG_V38B			1	/* ... on V38B board */
-#define CFG_MPC5XXX_CLKIN	33000000	/* ... running at 33.000000MHz */
+#define CONFIG_MPC5xxx			1	/* This is an MPC5xxx CPU	*/
+#define CONFIG_MPC5200			1	/* This is an MPC5200 CPU	*/
+#define CONFIG_V38B			1	/* ... on V38B board		*/
+#define CFG_MPC5XXX_CLKIN	33000000	/* ... running at 33.000000MHz	*/
  
-#define CONFIG_RTC_PCF8563		1	/* has PCF8563 RTC  */
-#define CONFIG_MPC5200_DDR		1	/* has DDR SDRAM    */
-#define CONFIG_HW_WATCHDOG		1	/* has watchdog     */
+#define CONFIG_RTC_PCF8563		1	/* has PCF8563 RTC		*/
+#define CONFIG_MPC5200_DDR		1	/* has DDR SDRAM		*/
+#define CONFIG_HW_WATCHDOG		1	/* has watchdog			*/
  
 #define CONFIG_NETCONSOLE		1
  
-#define CONFIG_BOARD_EARLY_INIT_R	1	/* make flash read/write */
+#define CONFIG_BOARD_EARLY_INIT_R	1	/* make flash read/write	*/
  
-#define CFG_XLB_PIPELINING		1	/* gives better performance */
+#define CFG_XLB_PIPELINING		1	/* gives better performance	*/
  
  
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
-#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
  
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
 #endif
  
 /*
  * Serial console configuration
  */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
-#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps	*/
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
  
  
  
@@ -97,12 +97,12 @@
 #define CONFIG_USB_OHCI
 #define CONFIG_USB_STORAGE
  
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
  
 /*
  * Supported commands
  */
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL	| \
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | \
 				 CFG_CMD_FAT	| \
 				 CFG_CMD_I2C	| \
 				 CFG_CMD_IDE	| \
@@ -112,7 +112,7 @@
 				 CFG_CMD_IRQ	| \
 				 CFG_CMD_JFFS2	| \
 				 CFG_CMD_MII	| \
-				 CFG_CMD_SDRAMi	| \
+				 CFG_CMD_SDRAMi | \
 				 CFG_CMD_DATE	| \
 				 CFG_CMD_USB	| \
 				 CFG_CMD_FAT)
@@ -123,7 +123,7 @@
 /*
  * Boot low with 16 MB Flash
  */
-#   define CFG_LOWBOOT	        1
+#   define CFG_LOWBOOT		1
 #   define CFG_LOWBOOT16	1
  
 /*
  
@@ -131,35 +131,35 @@
  */
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds */
  
-#define CONFIG_PREBOOT	"echo;"	\
+#define CONFIG_PREBOOT	"echo;" \
 	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 	"echo"
  
 #undef	CONFIG_BOOTARGS
  
-#define	CONFIG_EXTRA_ENV_SETTINGS	                            \
-        "netdev=eth0\0"                                             \
-        "devno=5\0"                                                 \
-        "hostname=V38B_$(devno)\0"                                  \
-        "ipaddr=10.100.99.$(devno)\0"                               \
-        "netmask=255.255.0.0\0"                                     \
-        "serverip=10.100.10.90\0"                                   \
-        "gatewayip=10.100.254.254\0"                                \
-        "ramargs=setenv bootargs root=/dev/ram rw\0"                \
-        "rootpath=/opt/eldk/ppc_6xx\0"                              \
-        "bootfile=mpc5200/uImage\0"                                 \
-        "bootcmd=run net_nfs\0"                                     \
-        "addip=setenv bootargs $(bootargs) "                        \
-            "ip=$(ipaddr):$(serverip):$(gatewayip):"                \
-            "$(netmask):$(hostname):$(netdev):off panic=1\0"        \
-        "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0"        \
-        "flash_self=run ramargs addip;bootm $(kernel_addr) "        \
-            "$(ramdisk_addr)\0"                                     \
-        "net_nfs=tftp 200000 $(bootfile);run nfsargs "              \
-            "addip;bootm\0"                                         \
-        "nfsargs=setenv bootargs root=/dev/nfs rw "                 \
-            "nfsroot=$(serverip):$(rootpath)\0"                     \
-        ""
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"devno=5\0"							\
+	"hostname=V38B_$(devno)\0"					\
+	"ipaddr=10.100.99.$(devno)\0"					\
+	"netmask=255.255.0.0\0"						\
+	"serverip=10.100.10.90\0"					\
+	"gatewayip=10.100.254.254\0"					\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"bootfile=mpc5200/uImage\0"					\
+	"bootcmd=run net_nfs\0"						\
+	"addip=setenv bootargs $(bootargs) "				\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):"		\
+		"$(netmask):$(hostname):$(netdev):off panic=1\0"	\
+	"flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0"		\
+	"flash_self=run ramargs addip;bootm $(kernel_addr) "		\
+		"$(ramdisk_addr)\0"					\
+	"net_nfs=tftp 200000 $(bootfile);run nfsargs "			\
+		"addip;bootm\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$(serverip):$(rootpath)\0"			\
+	""
  
 #define CONFIG_BOOTCOMMAND	"run net_nfs"
  
  
@@ -196,13 +196,13 @@
  */
 #define CFG_FLASH_CFI		1		/* Flash is CFI conformant */
 #define CFG_FLASH_CFI_DRIVER	1		/* Use the common driver */
-#define CFG_FLASH_CFI_AMD_RESET	1
+#define CFG_FLASH_CFI_AMD_RESET 1
 #define CFG_FLASH_BASE		0xFF000000
 #define CFG_MAX_FLASH_BANKS	1		/* max num of flash banks */
 #define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
 #define CFG_FLASH_SIZE		0x01000000	/* 16 MiB */
 #define CFG_MAX_FLASH_SECT	256		/* max num of sects on one chip */
-#define CFG_FLASH_USE_BUFFER_WRITE	1	/* flash write speed-up */ 
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* flash write speed-up */
  
 /*
  * Environment settings
@@ -243,7 +243,7 @@
  */
 #define CONFIG_MPC5xxx_FEC	1
 #define CONFIG_PHY_ADDR		0x00
-#define CONFIG_MII              1
+#define CONFIG_MII		1
  
 /*
  * GPIO configuration
  
  
@@ -307,12 +307,12 @@
  *-----------------------------------------------------------------------
  */
  
-#undef  CONFIG_IDE_8xx_PCCARD		/* Don't use IDE with PC Card	Adapter	*/
+#undef	CONFIG_IDE_8xx_PCCARD		/* Don't use IDE with PC Card	Adapter */
  
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
  
-#define	CONFIG_IDE_RESET		/* reset for ide supported	*/
+#define CONFIG_IDE_RESET		/* reset for ide supported	*/
 #define CONFIG_IDE_PREINIT
  
 #define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
  
  
@@ -331,13 +331,13 @@
 /* Offset for alternate registers	*/
 #define CFG_ATA_ALT_OFFSET	(0x005C)
  
-/* Interval between registers                                                */
-#define CFG_ATA_STRIDE          4
+/* Interval between registers						     */
+#define CFG_ATA_STRIDE		4
  
-/* Status LED                                                */
+/* Status LED						     */
  
-#define  CONFIG_STATUS_LED               /* Status LED enabled           */
-#define  CONFIG_BOARD_SPECIFIC_LED       /* version has board specific leds */
+#define	 CONFIG_STATUS_LED		 /* Status LED enabled		 */
+#define	 CONFIG_BOARD_SPECIFIC_LED	 /* version has board specific leds */
  
 #define CFG_LED_BASE	(0xf0000600 + 0x70)	/* Timer 7 GPIO */
...	...	@@ -118,8 +118,8 @@
118	118	crcval = 0;
119	119
120	120	for (i=0; i<NBYTES; i++)
121		-
122	121
	122	+
123	123	if (!check_device())
124	124	*perr = ERR_NO_NUMBER;
125	125	else {
...	...	@@ -224,7 +224,7 @@
224	224	rdat = (rdat >> 1) \| 0x80;
225	225	else
226	226	rdat = rdat >> 1;
227		-
	227	+
228	228	udelay(60); /* at least 60 us */
229	229	}
230	230	/* copy the return value */
1	1	NAND FLASH commands and notes
2	2
3		-
4	3	See NOTE below!!!
5	4
6		-
7	5	# (C) Copyright 2003
8	6	# Dave Ellis, SIXNET, dge@sixnetio.com
9	7	#
...	...	@@ -207,7 +205,6 @@
207	205	The consequence of this is that the legacy NAND can't be removed from
208	206	the tree until the DoC is ported to use the new NAND support (or boards
209	207	with DoC will break).
210		-
211	208
212	209
213	210	Additional improvements to the NAND subsystem by Guido Classen, 10-10-2006
...	...	@@ -11,7 +11,7 @@
11	11	*
12	12	* This program is distributed in the hope that it will be useful, but WITHOUT
13	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14		- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	14	+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15	15	* for more details.
16	16	*
17	17	* You should have received a copy of the GNU General Public License along
18	18
19	19
20	20
21	21
22	22
23	23
24	24
...	...	@@ -35,35 +35,35 @@
35	35	* (easy to change)
36	36	*/
37	37
38		-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
39		-#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
40		-#define CONFIG_V38B 1 /* ... on V38B board */
41		-#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
	38	+#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	39	+#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
	40	+#define CONFIG_V38B 1 /* ... on V38B board */
	41	+#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
42	42
43		-#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */
44		-#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */
45		-#define CONFIG_HW_WATCHDOG 1 /* has watchdog */
	43	+#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */
	44	+#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */
	45	+#define CONFIG_HW_WATCHDOG 1 /* has watchdog */
46	46
47	47	#define CONFIG_NETCONSOLE 1
48	48
49		-#define CONFIG_BOARD_EARLY_INIT_R 1 /* make flash read/write */
	49	+#define CONFIG_BOARD_EARLY_INIT_R 1 /* make flash read/write */
50	50
51		-#define CFG_XLB_PIPELINING 1 /* gives better performance */
	51	+#define CFG_XLB_PIPELINING 1 /* gives better performance */
52	52
53	53
54		-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
55		-#define BOOTFLAG_WARM 0x02 /* Software reboot */
	54	+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	55	+#define BOOTFLAG_WARM 0x02 /* Software reboot */
56	56
57		-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
	57	+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
58	58	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
59		-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	59	+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
60	60	#endif
61	61
62	62	/*
63	63	* Serial console configuration
64	64	*/
65		-#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
66		-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
	65	+#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	66	+#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
67	67	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
68	68
69	69
70	70
...	...	@@ -97,12 +97,12 @@
97	97	#define CONFIG_USB_OHCI
98	98	#define CONFIG_USB_STORAGE
99	99
100		-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	100	+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
101	101
102	102	/*
103	103	* Supported commands
104	104	*/
105		-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
	105	+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
106	106	CFG_CMD_FAT \| \
107	107	CFG_CMD_I2C \| \
108	108	CFG_CMD_IDE \| \
...	...	@@ -112,7 +112,7 @@
112	112	CFG_CMD_IRQ \| \
113	113	CFG_CMD_JFFS2 \| \
114	114	CFG_CMD_MII \| \
115		- CFG_CMD_SDRAMi \| \
	115	+ CFG_CMD_SDRAMi \| \
116	116	CFG_CMD_DATE \| \
117	117	CFG_CMD_USB \| \
118	118	CFG_CMD_FAT)
...	...	@@ -123,7 +123,7 @@
123	123	/*
124	124	* Boot low with 16 MB Flash
125	125	*/
126		-# define CFG_LOWBOOT 1
	126	+# define CFG_LOWBOOT 1
127	127	# define CFG_LOWBOOT16 1
128	128
129	129	/*
130	130
...	...	@@ -131,35 +131,35 @@
131	131	*/
132	132	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
133	133
134		-#define CONFIG_PREBOOT "echo;" \
	134	+#define CONFIG_PREBOOT "echo;" \
135	135	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
136	136	"echo"
137	137
138	138	#undef CONFIG_BOOTARGS
139	139
140		-#define CONFIG_EXTRA_ENV_SETTINGS \
141		- "netdev=eth0\0" \
142		- "devno=5\0" \
143		- "hostname=V38B_$(devno)\0" \
144		- "ipaddr=10.100.99.$(devno)\0" \
145		- "netmask=255.255.0.0\0" \
146		- "serverip=10.100.10.90\0" \
147		- "gatewayip=10.100.254.254\0" \
148		- "ramargs=setenv bootargs root=/dev/ram rw\0" \
149		- "rootpath=/opt/eldk/ppc_6xx\0" \
150		- "bootfile=mpc5200/uImage\0" \
151		- "bootcmd=run net_nfs\0" \
152		- "addip=setenv bootargs $(bootargs) " \
153		- "ip=$(ipaddr):$(serverip):$(gatewayip):" \
154		- "$(netmask):$(hostname):$(netdev):off panic=1\0" \
155		- "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \
156		- "flash_self=run ramargs addip;bootm $(kernel_addr) " \
157		- "$(ramdisk_addr)\0" \
158		- "net_nfs=tftp 200000 $(bootfile);run nfsargs " \
159		- "addip;bootm\0" \
160		- "nfsargs=setenv bootargs root=/dev/nfs rw " \
161		- "nfsroot=$(serverip):$(rootpath)\0" \
162		- ""
	140	+#define CONFIG_EXTRA_ENV_SETTINGS \
	141	+ "netdev=eth0\0" \
	142	+ "devno=5\0" \
	143	+ "hostname=V38B_$(devno)\0" \
	144	+ "ipaddr=10.100.99.$(devno)\0" \
	145	+ "netmask=255.255.0.0\0" \
	146	+ "serverip=10.100.10.90\0" \
	147	+ "gatewayip=10.100.254.254\0" \
	148	+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
	149	+ "rootpath=/opt/eldk/ppc_6xx\0" \
	150	+ "bootfile=mpc5200/uImage\0" \
	151	+ "bootcmd=run net_nfs\0" \
	152	+ "addip=setenv bootargs $(bootargs) " \
	153	+ "ip=$(ipaddr):$(serverip):$(gatewayip):" \
	154	+ "$(netmask):$(hostname):$(netdev):off panic=1\0" \
	155	+ "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \
	156	+ "flash_self=run ramargs addip;bootm $(kernel_addr) " \
	157	+ "$(ramdisk_addr)\0" \
	158	+ "net_nfs=tftp 200000 $(bootfile);run nfsargs " \
	159	+ "addip;bootm\0" \
	160	+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
	161	+ "nfsroot=$(serverip):$(rootpath)\0" \
	162	+ ""
163	163
164	164	#define CONFIG_BOOTCOMMAND "run net_nfs"
165	165
166	166
...	...	@@ -196,13 +196,13 @@
196	196	*/
197	197	#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
198	198	#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
199		-#define CFG_FLASH_CFI_AMD_RESET 1
	199	+#define CFG_FLASH_CFI_AMD_RESET 1
200	200	#define CFG_FLASH_BASE 0xFF000000
201	201	#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
202	202	#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
203	203	#define CFG_FLASH_SIZE 0x01000000 /* 16 MiB */
204	204	#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
205		-#define CFG_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */
	205	+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */
206	206
207	207	/*
208	208	* Environment settings
...	...	@@ -243,7 +243,7 @@
243	243	*/
244	244	#define CONFIG_MPC5xxx_FEC 1
245	245	#define CONFIG_PHY_ADDR 0x00
246		-#define CONFIG_MII 1
	246	+#define CONFIG_MII 1
247	247
248	248	/*
249	249	* GPIO configuration
250	250
251	251
...	...	@@ -307,12 +307,12 @@
307	307	*-----------------------------------------------------------------------
308	308	*/
309	309
310		-#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */
	310	+#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */
311	311
312		-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
313		-#undef CONFIG_IDE_LED /* LED for ide not supported */
	312	+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	313	+#undef CONFIG_IDE_LED /* LED for ide not supported */
314	314
315		-#define CONFIG_IDE_RESET /* reset for ide supported */
	315	+#define CONFIG_IDE_RESET /* reset for ide supported */
316	316	#define CONFIG_IDE_PREINIT
317	317
318	318	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
319	319
320	320
...	...	@@ -331,13 +331,13 @@
331	331	/* Offset for alternate registers */
332	332	#define CFG_ATA_ALT_OFFSET (0x005C)
333	333
334		-/* Interval between registers */
335		-#define CFG_ATA_STRIDE 4
	334	+/* Interval between registers */
	335	+#define CFG_ATA_STRIDE 4
336	336
337		-/* Status LED */
	337	+/* Status LED */
338	338
339		-#define CONFIG_STATUS_LED /* Status LED enabled */
340		-#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
	339	+#define CONFIG_STATUS_LED /* Status LED enabled */
	340	+#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
341	341
342	342	#define CFG_LED_BASE (0xf0000600 + 0x70) /* Timer 7 GPIO */
343	343