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Commit fd2f5658093eca72467f0104659f4826a95f948c

Authored by Eric Benard
Committed by Albert ARIBAUD
1 parent d0a94620a8
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

include/asm/arch-at91: update several .h files to ATMEL_xxx name scheme 

Signed-off-by: Eric Bénard <eric@eukrea.com>

Showing 5 changed files with 28 additions and 28 deletions Inline Diff

arch/arm/include/asm/arch-at91/at91_matrix.h
Diff comments   View file @ fd2f565
1 /* 1 /*
2 * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) 2 * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
3 * 3 *
4 * See file CREDITS for list of people who contributed to this 4 * See file CREDITS for list of people who contributed to this
5 * project. 5 * project.
6 * 6 *
7 * This program is free software; you can redistribute it and/or 7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as 8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of 9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version. 10 * the License, or (at your option) any later version.
11 * 11 *
12 * This program is distributed in the hope that it will be useful, 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 * 16 *
17 * You should have received a copy of the GNU General Public License 17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software 18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA 20 * MA 02111-1307 USA
21 */ 21 */
22 22
23 #ifndef AT91_MATRIX_H 23 #ifndef AT91_MATRIX_H
24 #define AT91_MATRIX_H 24 #define AT91_MATRIX_H
25 25
26 #ifdef __ASSEMBLY__ 26 #ifdef __ASSEMBLY__
27 27
28 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) 28 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
29 #define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x11C) 29 #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x11C)
30 #elif defined(CONFIG_AT91SAM9261) 30 #elif defined(CONFIG_AT91SAM9261)
31 #define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x30) 31 #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x30)
32 #elif defined(CONFIG_AT91SAM9263) 32 #elif defined(CONFIG_AT91SAM9263)
33 #define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x120) 33 #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x120)
34 #elif defined(CONFIG_AT91SAM9G45) 34 #elif defined(CONFIG_AT91SAM9G45)
35 #define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x128) 35 #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x128)
36 #else 36 #else
37 #error AT91_ASM_MATRIX_CSA0 is not definied for current CPU 37 #error AT91_ASM_MATRIX_CSA0 is not definied for current CPU
38 #endif 38 #endif
39 39
40 #define AT91_ASM_MATRIX_MCFG AT91_MATRIX_BASE 40 #define AT91_ASM_MATRIX_MCFG ATMEL_BASE_MATRIX
41 41
42 #else 42 #else
43 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) 43 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
44 #define AT91_MATRIX_MASTERS 6 44 #define AT91_MATRIX_MASTERS 6
45 #define AT91_MATRIX_SLAVES 5 45 #define AT91_MATRIX_SLAVES 5
46 #elif defined(CONFIG_AT91SAM9261) 46 #elif defined(CONFIG_AT91SAM9261)
47 #define AT91_MATRIX_MASTERS 1 47 #define AT91_MATRIX_MASTERS 1
48 #define AT91_MATRIX_SLAVES 5 48 #define AT91_MATRIX_SLAVES 5
49 #elif defined(CONFIG_AT91SAM9263) 49 #elif defined(CONFIG_AT91SAM9263)
50 #define AT91_MATRIX_MASTERS 9 50 #define AT91_MATRIX_MASTERS 9
51 #define AT91_MATRIX_SLAVES 7 51 #define AT91_MATRIX_SLAVES 7
52 #elif defined(CONFIG_AT91SAM9G45) 52 #elif defined(CONFIG_AT91SAM9G45)
53 #define AT91_MATRIX_MASTERS 11 53 #define AT91_MATRIX_MASTERS 11
54 #define AT91_MATRIX_SLAVES 8 54 #define AT91_MATRIX_SLAVES 8
55 #else 55 #else
56 #error CPU not supported. Please update at91_matrix.h 56 #error CPU not supported. Please update at91_matrix.h
57 #endif 57 #endif
58 58
59 typedef struct at91_priority { 59 typedef struct at91_priority {
60 u32 a; 60 u32 a;
61 u32 b; 61 u32 b;
62 } at91_priority_t; 62 } at91_priority_t;
63 63
64 typedef struct at91_matrix { 64 typedef struct at91_matrix {
65 u32 mcfg[AT91_MATRIX_MASTERS]; 65 u32 mcfg[AT91_MATRIX_MASTERS];
66 #if defined(CONFIG_AT91SAM9261) 66 #if defined(CONFIG_AT91SAM9261)
67 u32 scfg[AT91_MATRIX_SLAVES]; 67 u32 scfg[AT91_MATRIX_SLAVES];
68 u32 res61_1[3]; 68 u32 res61_1[3];
69 u32 tcr; 69 u32 tcr;
70 u32 res61_2[2]; 70 u32 res61_2[2];
71 u32 csa; 71 u32 csa;
72 u32 pucr; 72 u32 pucr;
73 u32 res61_3[114]; 73 u32 res61_3[114];
74 #else 74 #else
75 u32 reserve1[16 - AT91_MATRIX_MASTERS]; 75 u32 reserve1[16 - AT91_MATRIX_MASTERS];
76 u32 scfg[AT91_MATRIX_SLAVES]; 76 u32 scfg[AT91_MATRIX_SLAVES];
77 u32 reserve2[16 - AT91_MATRIX_SLAVES]; 77 u32 reserve2[16 - AT91_MATRIX_SLAVES];
78 at91_priority_t pr[AT91_MATRIX_SLAVES]; 78 at91_priority_t pr[AT91_MATRIX_SLAVES];
79 u32 reserve3[32 - (2 * AT91_MATRIX_SLAVES)]; 79 u32 reserve3[32 - (2 * AT91_MATRIX_SLAVES)];
80 u32 mrcr; /* 0x100 Master Remap Control */ 80 u32 mrcr; /* 0x100 Master Remap Control */
81 u32 reserve4[3]; 81 u32 reserve4[3];
82 #if defined(CONFIG_AT91SAM9G45) 82 #if defined(CONFIG_AT91SAM9G45)
83 u32 ccr[52]; /* 0x110 - 0x1E0 Chip Configuration */ 83 u32 ccr[52]; /* 0x110 - 0x1E0 Chip Configuration */
84 u32 womr; /* 0x1E4 Write Protect Mode */ 84 u32 womr; /* 0x1E4 Write Protect Mode */
85 u32 wpsr; /* 0x1E8 Write Protect Status */ 85 u32 wpsr; /* 0x1E8 Write Protect Status */
86 u32 resg45_1[10]; 86 u32 resg45_1[10];
87 #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) 87 #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
88 u32 res60_1[3]; 88 u32 res60_1[3];
89 u32 csa; 89 u32 csa;
90 u32 res60_2[56]; 90 u32 res60_2[56];
91 #elif defined(CONFIG_AT91SAM9263) 91 #elif defined(CONFIG_AT91SAM9263)
92 u32 res63_1; 92 u32 res63_1;
93 u32 tcmr; 93 u32 tcmr;
94 u32 res63_2[2]; 94 u32 res63_2[2];
95 u32 csa[2]; 95 u32 csa[2];
96 u32 res63_3[54]; 96 u32 res63_3[54];
97 #else 97 #else
98 u32 reserve5[60]; 98 u32 reserve5[60];
99 #endif 99 #endif
100 #endif 100 #endif
101 } at91_matrix_t; 101 } at91_matrix_t;
102 102
103 #endif /* __ASSEMBLY__ */ 103 #endif /* __ASSEMBLY__ */
104 104
105 #define AT91_MATRIX_CSA_DBPUC 0x00000100 105 #define AT91_MATRIX_CSA_DBPUC 0x00000100
106 #define AT91_MATRIX_CSA_VDDIOMSEL_1_8V 0x00000000 106 #define AT91_MATRIX_CSA_VDDIOMSEL_1_8V 0x00000000
107 #define AT91_MATRIX_CSA_VDDIOMSEL_3_3V 0x00010000 107 #define AT91_MATRIX_CSA_VDDIOMSEL_3_3V 0x00010000
108 108
109 #define AT91_MATRIX_CSA_EBI_CS1A 0x00000002 109 #define AT91_MATRIX_CSA_EBI_CS1A 0x00000002
110 #define AT91_MATRIX_CSA_EBI_CS3A 0x00000008 110 #define AT91_MATRIX_CSA_EBI_CS3A 0x00000008
111 #define AT91_MATRIX_CSA_EBI_CS4A 0x00000010 111 #define AT91_MATRIX_CSA_EBI_CS4A 0x00000010
112 #define AT91_MATRIX_CSA_EBI_CS5A 0x00000020 112 #define AT91_MATRIX_CSA_EBI_CS5A 0x00000020
113 113
114 #define AT91_MATRIX_CSA_EBI1_CS2A 0x00000008 114 #define AT91_MATRIX_CSA_EBI1_CS2A 0x00000008
115 115
116 #if defined CONFIG_AT91SAM9261 116 #if defined CONFIG_AT91SAM9261
117 /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 117 /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
118 #define AT91_MATRIX_MCFG_RCB0 (1 << 0) 118 #define AT91_MATRIX_MCFG_RCB0 (1 << 0)
119 /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 119 /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
120 #define AT91_MATRIX_MCFG_RCB1 (1 << 1) 120 #define AT91_MATRIX_MCFG_RCB1 (1 << 1)
121 #endif 121 #endif
122 122
123 /* Undefined Length Burst Type */ 123 /* Undefined Length Burst Type */
124 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \ 124 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
125 defined(CONFIG_AT91SAM9G45) 125 defined(CONFIG_AT91SAM9G45)
126 #define AT91_MATRIX_MCFG_ULBT_INFINITE 0x00000000 126 #define AT91_MATRIX_MCFG_ULBT_INFINITE 0x00000000
127 #define AT91_MATRIX_MCFG_ULBT_SINGLE 0x00000001 127 #define AT91_MATRIX_MCFG_ULBT_SINGLE 0x00000001
128 #define AT91_MATRIX_MCFG_ULBT_FOUR 0x00000002 128 #define AT91_MATRIX_MCFG_ULBT_FOUR 0x00000002
129 #define AT91_MATRIX_MCFG_ULBT_EIGHT 0x00000003 129 #define AT91_MATRIX_MCFG_ULBT_EIGHT 0x00000003
130 #define AT91_MATRIX_MCFG_ULBT_SIXTEEN 0x00000004 130 #define AT91_MATRIX_MCFG_ULBT_SIXTEEN 0x00000004
131 #endif 131 #endif
132 #if defined(CONFIG_AT91SAM9G45) 132 #if defined(CONFIG_AT91SAM9G45)
133 #define AT91_MATRIX_MCFG_ULBT_THIRTYTWO 0x00000005 133 #define AT91_MATRIX_MCFG_ULBT_THIRTYTWO 0x00000005
134 #define AT91_MATRIX_MCFG_ULBT_SIXTYFOUR 0x00000006 134 #define AT91_MATRIX_MCFG_ULBT_SIXTYFOUR 0x00000006
135 #define AT91_MATRIX_MCFG_ULBT_128 0x00000007 135 #define AT91_MATRIX_MCFG_ULBT_128 0x00000007
136 #endif 136 #endif
137 137
138 /* Default Master Type */ 138 /* Default Master Type */
139 #define AT91_MATRIX_SCFG_DEFMSTR_TYPE_NONE 0x00000000 139 #define AT91_MATRIX_SCFG_DEFMSTR_TYPE_NONE 0x00000000
140 #define AT91_MATRIX_SCFG_DEFMSTR_TYPE_LAST 0x00010000 140 #define AT91_MATRIX_SCFG_DEFMSTR_TYPE_LAST 0x00010000
141 #define AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED 0x00020000 141 #define AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED 0x00020000
142 142
143 /* Fixed Index of Default Master */ 143 /* Fixed Index of Default Master */
144 #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9263) 144 #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9263)
145 #define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 0xf) << 18) 145 #define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 0xf) << 18)
146 #elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9260) 146 #elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9260)
147 #define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 7) << 18) 147 #define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 7) << 18)
148 #endif 148 #endif
149 149
150 /* Maximum Number of Allowed Cycles for a Burst */ 150 /* Maximum Number of Allowed Cycles for a Burst */
151 #if defined(CONFIG_AT91SAM9G45) 151 #if defined(CONFIG_AT91SAM9G45)
152 #define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0x1ff) << 0) 152 #define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0x1ff) << 0)
153 #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ 153 #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \
154 defined(CONFIG_AT91SAM9263) 154 defined(CONFIG_AT91SAM9263)
155 #define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0xff) << 0) 155 #define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0xff) << 0)
156 #endif 156 #endif
157 157
158 /* Arbitration Type */ 158 /* Arbitration Type */
159 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) 159 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263)
160 #define AT91_MATRIX_SCFG_ARBT_ROUND_ROBIN 0x00000000 160 #define AT91_MATRIX_SCFG_ARBT_ROUND_ROBIN 0x00000000
161 #define AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY 0x01000000 161 #define AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY 0x01000000
162 #endif 162 #endif
163 163
164 /* Master Remap Control Register */ 164 /* Master Remap Control Register */
165 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \ 165 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
166 defined(CONFIG_AT91SAM9G45) 166 defined(CONFIG_AT91SAM9G45)
167 /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 167 /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
168 #define AT91_MATRIX_MRCR_RCB0 (1 << 0) 168 #define AT91_MATRIX_MRCR_RCB0 (1 << 0)
169 /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 169 /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
170 #define AT91_MATRIX_MRCR_RCB1 (1 << 1) 170 #define AT91_MATRIX_MRCR_RCB1 (1 << 1)
171 #endif 171 #endif
172 #if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45) 172 #if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45)
173 #define AT91_MATRIX_MRCR_RCB2 0x00000004 173 #define AT91_MATRIX_MRCR_RCB2 0x00000004
174 #define AT91_MATRIX_MRCR_RCB3 0x00000008 174 #define AT91_MATRIX_MRCR_RCB3 0x00000008
175 #define AT91_MATRIX_MRCR_RCB4 0x00000010 175 #define AT91_MATRIX_MRCR_RCB4 0x00000010
176 #define AT91_MATRIX_MRCR_RCB5 0x00000020 176 #define AT91_MATRIX_MRCR_RCB5 0x00000020
177 #define AT91_MATRIX_MRCR_RCB6 0x00000040 177 #define AT91_MATRIX_MRCR_RCB6 0x00000040
178 #define AT91_MATRIX_MRCR_RCB7 0x00000080 178 #define AT91_MATRIX_MRCR_RCB7 0x00000080
179 #define AT91_MATRIX_MRCR_RCB8 0x00000100 179 #define AT91_MATRIX_MRCR_RCB8 0x00000100
180 #endif 180 #endif
181 #if defined(CONFIG_AT91SAM9G45) 181 #if defined(CONFIG_AT91SAM9G45)
182 #define AT91_MATRIX_MRCR_RCB9 0x00000200 182 #define AT91_MATRIX_MRCR_RCB9 0x00000200
183 #define AT91_MATRIX_MRCR_RCB10 0x00000400 183 #define AT91_MATRIX_MRCR_RCB10 0x00000400
184 #define AT91_MATRIX_MRCR_RCB11 0x00000800 184 #define AT91_MATRIX_MRCR_RCB11 0x00000800
185 #endif 185 #endif
186 186
187 /* TCM Configuration Register */ 187 /* TCM Configuration Register */
188 #if defined(CONFIG_AT91SAM9G45) 188 #if defined(CONFIG_AT91SAM9G45)
189 /* Size of ITCM enabled memory block */ 189 /* Size of ITCM enabled memory block */
190 #define AT91_MATRIX_TCMR_ITCM_0 0x00000000 190 #define AT91_MATRIX_TCMR_ITCM_0 0x00000000
191 #define AT91_MATRIX_TCMR_ITCM_32 0x00000040 191 #define AT91_MATRIX_TCMR_ITCM_32 0x00000040
192 /* Size of DTCM enabled memory block */ 192 /* Size of DTCM enabled memory block */
193 #define AT91_MATRIX_TCMR_DTCM_0 0x00000000 193 #define AT91_MATRIX_TCMR_DTCM_0 0x00000000
194 #define AT91_MATRIX_TCMR_DTCM_32 0x00000060 194 #define AT91_MATRIX_TCMR_DTCM_32 0x00000060
195 #define AT91_MATRIX_TCMR_DTCM_64 0x00000070 195 #define AT91_MATRIX_TCMR_DTCM_64 0x00000070
196 /* Wait state TCM register */ 196 /* Wait state TCM register */
197 #define AT91_MATRIX_TCMR_TCM_NO_WS 0x00000000 197 #define AT91_MATRIX_TCMR_TCM_NO_WS 0x00000000
198 #define AT91_MATRIX_TCMR_TCM_ONE_WS 0x00000800 198 #define AT91_MATRIX_TCMR_TCM_ONE_WS 0x00000800
199 #endif 199 #endif
200 #if defined(CONFIG_AT91SAM9263) 200 #if defined(CONFIG_AT91SAM9263)
201 /* Size of ITCM enabled memory block */ 201 /* Size of ITCM enabled memory block */
202 #define AT91_MATRIX_TCMR_ITCM_0 0x00000000 202 #define AT91_MATRIX_TCMR_ITCM_0 0x00000000
203 #define AT91_MATRIX_TCMR_ITCM_16 0x00000005 203 #define AT91_MATRIX_TCMR_ITCM_16 0x00000005
204 #define AT91_MATRIX_TCMR_ITCM_32 0x00000006 204 #define AT91_MATRIX_TCMR_ITCM_32 0x00000006
205 /* Size of DTCM enabled memory block */ 205 /* Size of DTCM enabled memory block */
206 #define AT91_MATRIX_TCMR_DTCM_0 0x00000000 206 #define AT91_MATRIX_TCMR_DTCM_0 0x00000000
207 #define AT91_MATRIX_TCMR_DTCM_16 0x00000050 207 #define AT91_MATRIX_TCMR_DTCM_16 0x00000050
208 #define AT91_MATRIX_TCMR_DTCM_32 0x00000060 208 #define AT91_MATRIX_TCMR_DTCM_32 0x00000060
209 #endif 209 #endif
210 #if defined(CONFIG_AT91SAM9261) 210 #if defined(CONFIG_AT91SAM9261)
211 /* Size of ITCM enabled memory block */ 211 /* Size of ITCM enabled memory block */
212 #define AT91_MATRIX_TCMR_ITCM_0 0x00000000 212 #define AT91_MATRIX_TCMR_ITCM_0 0x00000000
213 #define AT91_MATRIX_TCMR_ITCM_16 0x00000005 213 #define AT91_MATRIX_TCMR_ITCM_16 0x00000005
214 #define AT91_MATRIX_TCMR_ITCM_32 0x00000006 214 #define AT91_MATRIX_TCMR_ITCM_32 0x00000006
215 #define AT91_MATRIX_TCMR_ITCM_64 0x00000007 215 #define AT91_MATRIX_TCMR_ITCM_64 0x00000007
216 /* Size of DTCM enabled memory block */ 216 /* Size of DTCM enabled memory block */
217 #define AT91_MATRIX_TCMR_DTCM_0 0x00000000 217 #define AT91_MATRIX_TCMR_DTCM_0 0x00000000
218 #define AT91_MATRIX_TCMR_DTCM_16 0x00000050 218 #define AT91_MATRIX_TCMR_DTCM_16 0x00000050
219 #define AT91_MATRIX_TCMR_DTCM_32 0x00000060 219 #define AT91_MATRIX_TCMR_DTCM_32 0x00000060
220 #define AT91_MATRIX_TCMR_DTCM_64 0x00000070 220 #define AT91_MATRIX_TCMR_DTCM_64 0x00000070
221 #endif 221 #endif
222 222
223 #if defined(CONFIG_AT91SAM9G45) 223 #if defined(CONFIG_AT91SAM9G45)
224 /* Video Mode Configuration Register */ 224 /* Video Mode Configuration Register */
225 #define AT91C_MATRIX_VDEC_SEL_OFF 0x00000000 225 #define AT91C_MATRIX_VDEC_SEL_OFF 0x00000000
226 #define AT91C_MATRIX_VDEC_SEL_ON 0x00000001 226 #define AT91C_MATRIX_VDEC_SEL_ON 0x00000001
227 /* Write Protect Mode Register */ 227 /* Write Protect Mode Register */
228 #define AT91_MATRIX_WPMR_WP_WPDIS 0x00000000 228 #define AT91_MATRIX_WPMR_WP_WPDIS 0x00000000
229 #define AT91_MATRIX_WPMR_WP_WPEN 0x00000001 229 #define AT91_MATRIX_WPMR_WP_WPEN 0x00000001
230 #define AT91_MATRIX_WPMR_WPKEY 0xFFFFFF00 /* Write Protect KEY */ 230 #define AT91_MATRIX_WPMR_WPKEY 0xFFFFFF00 /* Write Protect KEY */
231 /* Write Protect Status Register */ 231 /* Write Protect Status Register */
232 #define AT91_MATRIX_WPSR_NO_WPV 0x00000000 232 #define AT91_MATRIX_WPSR_NO_WPV 0x00000000
233 #define AT91_MATRIX_WPSR_WPV 0x00000001 233 #define AT91_MATRIX_WPSR_WPV 0x00000001
234 #define AT91_MATRIX_WPSR_WPVSRC 0x00FFFF00 /* Write Protect Violation Source */ 234 #define AT91_MATRIX_WPSR_WPVSRC 0x00FFFF00 /* Write Protect Violation Source */
235 #endif 235 #endif
236 236
237 /* USB Pad Pull-Up Control Register */ 237 /* USB Pad Pull-Up Control Register */
238 #if defined(CONFIG_AT91SAM9261) 238 #if defined(CONFIG_AT91SAM9261)
239 #define AT91_MATRIX_USBPUCR_PUON 0x40000000 239 #define AT91_MATRIX_USBPUCR_PUON 0x40000000
240 #endif 240 #endif
241 241
242 #define AT91_MATRIX_PRA_M0(x) ((x & 3) << 0) /* Master 0 Priority Reg. A*/ 242 #define AT91_MATRIX_PRA_M0(x) ((x & 3) << 0) /* Master 0 Priority Reg. A*/
243 #define AT91_MATRIX_PRA_M1(x) ((x & 3) << 4) /* Master 1 Priority Reg. A*/ 243 #define AT91_MATRIX_PRA_M1(x) ((x & 3) << 4) /* Master 1 Priority Reg. A*/
244 #define AT91_MATRIX_PRA_M2(x) ((x & 3) << 8) /* Master 2 Priority Reg. A*/ 244 #define AT91_MATRIX_PRA_M2(x) ((x & 3) << 8) /* Master 2 Priority Reg. A*/
245 #define AT91_MATRIX_PRA_M3(x) ((x & 3) << 12) /* Master 3 Priority Reg. A*/ 245 #define AT91_MATRIX_PRA_M3(x) ((x & 3) << 12) /* Master 3 Priority Reg. A*/
246 #define AT91_MATRIX_PRA_M4(x) ((x & 3) << 16) /* Master 4 Priority Reg. A*/ 246 #define AT91_MATRIX_PRA_M4(x) ((x & 3) << 16) /* Master 4 Priority Reg. A*/
247 #define AT91_MATRIX_PRA_M5(x) ((x & 3) << 20) /* Master 5 Priority Reg. A*/ 247 #define AT91_MATRIX_PRA_M5(x) ((x & 3) << 20) /* Master 5 Priority Reg. A*/
248 #define AT91_MATRIX_PRA_M6(x) ((x & 3) << 24) /* Master 6 Priority Reg. A*/ 248 #define AT91_MATRIX_PRA_M6(x) ((x & 3) << 24) /* Master 6 Priority Reg. A*/
249 #define AT91_MATRIX_PRA_M7(x) ((x & 3) << 28) /* Master 7 Priority Reg. A*/ 249 #define AT91_MATRIX_PRA_M7(x) ((x & 3) << 28) /* Master 7 Priority Reg. A*/
250 #define AT91_MATRIX_PRB_M8(x) ((x & 3) << 0) /* Master 8 Priority Reg. B) */ 250 #define AT91_MATRIX_PRB_M8(x) ((x & 3) << 0) /* Master 8 Priority Reg. B) */
251 #define AT91_MATRIX_PRB_M9(x) ((x & 3) << 4) /* Master 9 Priority Reg. B) */ 251 #define AT91_MATRIX_PRB_M9(x) ((x & 3) << 4) /* Master 9 Priority Reg. B) */
252 #define AT91_MATRIX_PRB_M10(x) ((x & 3) << 8) /* Master 10 Priority Reg. B) */ 252 #define AT91_MATRIX_PRB_M10(x) ((x & 3) << 8) /* Master 10 Priority Reg. B) */
253 253
254 #endif 254 #endif
255 255
arch/arm/include/asm/arch-at91/at91_rstc.h
Diff comments   View file @ fd2f565
1 /* 1 /*
2 * [origin: Linux kernel include/asm-arm/arch-at91/at91_rstc.h] 2 * [origin: Linux kernel include/asm-arm/arch-at91/at91_rstc.h]
3 * 3 *
4 * Copyright (C) 2007 Andrew Victor 4 * Copyright (C) 2007 Andrew Victor
5 * Copyright (C) 2007 Atmel Corporation. 5 * Copyright (C) 2007 Atmel Corporation.
6 * 6 *
7 * Reset Controller (RSTC) - System peripherals regsters. 7 * Reset Controller (RSTC) - System peripherals regsters.
8 * Based on AT91SAM9261 datasheet revision D. 8 * Based on AT91SAM9261 datasheet revision D.
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by 11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or 12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version. 13 * (at your option) any later version.
14 */ 14 */
15 15
16 #ifndef AT91_RSTC_H 16 #ifndef AT91_RSTC_H
17 #define AT91_RSTC_H 17 #define AT91_RSTC_H
18 18
19 #define AT91_ASM_RSTC_MR (AT91_RSTC_BASE + 0x08) 19 #define AT91_ASM_RSTC_MR (ATMEL_BASE_RSTC + 0x08)
20 20
21 #ifndef __ASSEMBLY__ 21 #ifndef __ASSEMBLY__
22 22
23 typedef struct at91_rstc { 23 typedef struct at91_rstc {
24 u32 cr; /* Reset Controller Control Register */ 24 u32 cr; /* Reset Controller Control Register */
25 u32 sr; /* Reset Controller Status Register */ 25 u32 sr; /* Reset Controller Status Register */
26 u32 mr; /* Reset Controller Mode Register */ 26 u32 mr; /* Reset Controller Mode Register */
27 } at91_rstc_t; 27 } at91_rstc_t;
28 28
29 #endif /* __ASSEMBLY__ */ 29 #endif /* __ASSEMBLY__ */
30 30
31 #define AT91_RSTC_KEY 0xA5000000 31 #define AT91_RSTC_KEY 0xA5000000
32 32
33 #define AT91_RSTC_CR_PROCRST 0x00000001 33 #define AT91_RSTC_CR_PROCRST 0x00000001
34 #define AT91_RSTC_CR_PERRST 0x00000004 34 #define AT91_RSTC_CR_PERRST 0x00000004
35 #define AT91_RSTC_CR_EXTRST 0x00000008 35 #define AT91_RSTC_CR_EXTRST 0x00000008
36 36
37 #define AT91_RSTC_MR_URSTEN 0x00000001 37 #define AT91_RSTC_MR_URSTEN 0x00000001
38 #define AT91_RSTC_MR_URSTIEN 0x00000010 38 #define AT91_RSTC_MR_URSTIEN 0x00000010
39 #define AT91_RSTC_MR_ERSTL(x) ((x & 0xf) << 8) 39 #define AT91_RSTC_MR_ERSTL(x) ((x & 0xf) << 8)
40 #define AT91_RSTC_MR_ERSTL_MASK 0x0000FF00 40 #define AT91_RSTC_MR_ERSTL_MASK 0x0000FF00
41 41
42 #define AT91_RSTC_SR_NRSTL 0x00010000 42 #define AT91_RSTC_SR_NRSTL 0x00010000
43 43
44 #endif 44 #endif
45 45
arch/arm/include/asm/arch-at91/at91_wdt.h
Diff comments   View file @ fd2f565
1 /* 1 /*
2 * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h] 2 * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h]
3 * 3 *
4 * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 4 * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 * Copyright (C) 2007 Andrew Victor 5 * Copyright (C) 2007 Andrew Victor
6 * Copyright (C) 2007 Atmel Corporation. 6 * Copyright (C) 2007 Atmel Corporation.
7 * 7 *
8 * Watchdog Timer (WDT) - System peripherals regsters. 8 * Watchdog Timer (WDT) - System peripherals regsters.
9 * Based on AT91SAM9261 datasheet revision D. 9 * Based on AT91SAM9261 datasheet revision D.
10 * 10 *
11 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by 12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or 13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version. 14 * (at your option) any later version.
15 */ 15 */
16 16
17 #ifndef AT91_WDT_H 17 #ifndef AT91_WDT_H
18 #define AT91_WDT_H 18 #define AT91_WDT_H
19 19
20 #ifdef __ASSEMBLY__ 20 #ifdef __ASSEMBLY__
21 21
22 #define AT91_ASM_WDT_MR (AT91_WDT_BASE + 0x04) 22 #define AT91_ASM_WDT_MR (ATMEL_BASE_WDT + 0x04)
23 23
24 #else 24 #else
25 25
26 typedef struct at91_wdt { 26 typedef struct at91_wdt {
27 u32 cr; 27 u32 cr;
28 u32 mr; 28 u32 mr;
29 u32 sr; 29 u32 sr;
30 } at91_wdt_t; 30 } at91_wdt_t;
31 31
32 #endif 32 #endif
33 33
34 #define AT91_WDT_CR_WDRSTT 1 34 #define AT91_WDT_CR_WDRSTT 1
35 #define AT91_WDT_CR_KEY 0xa5000000 /* KEY Password */ 35 #define AT91_WDT_CR_KEY 0xa5000000 /* KEY Password */
36 36
37 #define AT91_WDT_MR_WDV(x) (x & 0xfff) 37 #define AT91_WDT_MR_WDV(x) (x & 0xfff)
38 #define AT91_WDT_MR_WDFIEN 0x00001000 38 #define AT91_WDT_MR_WDFIEN 0x00001000
39 #define AT91_WDT_MR_WDRSTEN 0x00002000 39 #define AT91_WDT_MR_WDRSTEN 0x00002000
40 #define AT91_WDT_MR_WDRPROC 0x00004000 40 #define AT91_WDT_MR_WDRPROC 0x00004000
41 #define AT91_WDT_MR_WDDIS 0x00008000 41 #define AT91_WDT_MR_WDDIS 0x00008000
42 #define AT91_WDT_MR_WDD(x) ((x & 0xfff) << 16) 42 #define AT91_WDT_MR_WDD(x) ((x & 0xfff) << 16)
43 #define AT91_WDT_MR_WDDBGHLT 0x10000000 43 #define AT91_WDT_MR_WDDBGHLT 0x10000000
44 #define AT91_WDT_MR_WDIDLEHLT 0x20000000 44 #define AT91_WDT_MR_WDIDLEHLT 0x20000000
45 45
46 #ifdef CONFIG_AT91_LEGACY 46 #ifdef CONFIG_AT91_LEGACY
47 47
48 #define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */ 48 #define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */
49 #define AT91_WDT_WDRSTT (1 << 0) /* Restart */ 49 #define AT91_WDT_WDRSTT (1 << 0) /* Restart */
50 #define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */ 50 #define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */
51 51
52 #define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */ 52 #define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */
53 #define AT91_WDT_WDV (0xfff << 0) /* Counter Value */ 53 #define AT91_WDT_WDV (0xfff << 0) /* Counter Value */
54 #define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */ 54 #define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */
55 #define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */ 55 #define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */
56 #define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */ 56 #define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */
57 #define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */ 57 #define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */
58 #define AT91_WDT_WDD (0xfff << 16) /* Delta Value */ 58 #define AT91_WDT_WDD (0xfff << 16) /* Delta Value */
59 #define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */ 59 #define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */
60 #define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */ 60 #define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */
61 61
62 #define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */ 62 #define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */
63 #define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */ 63 #define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */
64 #define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */ 64 #define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */
65 65
66 #endif /* CONFIG_AT91_LEGACY */ 66 #endif /* CONFIG_AT91_LEGACY */
67 #endif 67 #endif
68 68
arch/arm/include/asm/arch-at91/at91sam9_sdramc.h
Diff comments   View file @ fd2f565
1 /* 1 /*
2 * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h] 2 * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h]
3 * 3 *
4 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 4 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 * Copyright (C) 2007 Andrew Victor 5 * Copyright (C) 2007 Andrew Victor
6 * Copyright (C) 2007 Atmel Corporation. 6 * Copyright (C) 2007 Atmel Corporation.
7 * 7 *
8 * SDRAM Controllers (SDRAMC) - System peripherals registers. 8 * SDRAM Controllers (SDRAMC) - System peripherals registers.
9 * Based on AT91SAM9261 datasheet revision D. 9 * Based on AT91SAM9261 datasheet revision D.
10 * 10 *
11 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by 12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or 13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version. 14 * (at your option) any later version.
15 */ 15 */
16 16
17 #ifndef AT91SAM9_SDRAMC_H 17 #ifndef AT91SAM9_SDRAMC_H
18 #define AT91SAM9_SDRAMC_H 18 #define AT91SAM9_SDRAMC_H
19 19
20 #ifdef __ASSEMBLY__ 20 #ifdef __ASSEMBLY__
21 21
22 #ifndef AT91_SDRAMC_BASE 22 #ifndef ATMEL_BASE_SDRAMC
23 #define AT91_SDRAMC_BASE AT91_SDRAMC0_BASE 23 #define ATMEL_BASE_SDRAMC AT91_SDRAMC0_BASE
24 #endif 24 #endif
25 25
26 #define AT91_ASM_SDRAMC_MR AT91_SDRAMC_BASE 26 #define AT91_ASM_SDRAMC_MR ATMEL_BASE_SDRAMC
27 #define AT91_ASM_SDRAMC_TR (AT91_SDRAMC_BASE + 0x04) 27 #define AT91_ASM_SDRAMC_TR (ATMEL_BASE_SDRAMC + 0x04)
28 #define AT91_ASM_SDRAMC_CR (AT91_SDRAMC_BASE + 0x08) 28 #define AT91_ASM_SDRAMC_CR (ATMEL_BASE_SDRAMC + 0x08)
29 #define AT91_ASM_SDRAMC_MDR (AT91_SDRAMC_BASE + 0x24) 29 #define AT91_ASM_SDRAMC_MDR (ATMEL_BASE_SDRAMC + 0x24)
30 30
31 #endif 31 #endif
32 32
33 /* SDRAM Controller (SDRAMC) registers */ 33 /* SDRAM Controller (SDRAMC) registers */
34 #define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ 34 #define AT91_SDRAMC_MR (ATMEL_BASE_SDRAMC + 0x00) /* SDRAM Controller Mode Register */
35 #define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ 35 #define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
36 #define AT91_SDRAMC_MODE_NORMAL 0 36 #define AT91_SDRAMC_MODE_NORMAL 0
37 #define AT91_SDRAMC_MODE_NOP 1 37 #define AT91_SDRAMC_MODE_NOP 1
38 #define AT91_SDRAMC_MODE_PRECHARGE 2 38 #define AT91_SDRAMC_MODE_PRECHARGE 2
39 #define AT91_SDRAMC_MODE_LMR 3 39 #define AT91_SDRAMC_MODE_LMR 3
40 #define AT91_SDRAMC_MODE_REFRESH 4 40 #define AT91_SDRAMC_MODE_REFRESH 4
41 #define AT91_SDRAMC_MODE_EXT_LMR 5 41 #define AT91_SDRAMC_MODE_EXT_LMR 5
42 #define AT91_SDRAMC_MODE_DEEP 6 42 #define AT91_SDRAMC_MODE_DEEP 6
43 43
44 #define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */ 44 #define AT91_SDRAMC_TR (ATMEL_BASE_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */
45 #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */ 45 #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
46 46
47 #define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */ 47 #define AT91_SDRAMC_CR (ATMEL_BASE_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */
48 #define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ 48 #define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
49 #define AT91_SDRAMC_NC_8 (0 << 0) 49 #define AT91_SDRAMC_NC_8 (0 << 0)
50 #define AT91_SDRAMC_NC_9 (1 << 0) 50 #define AT91_SDRAMC_NC_9 (1 << 0)
51 #define AT91_SDRAMC_NC_10 (2 << 0) 51 #define AT91_SDRAMC_NC_10 (2 << 0)
52 #define AT91_SDRAMC_NC_11 (3 << 0) 52 #define AT91_SDRAMC_NC_11 (3 << 0)
53 #define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ 53 #define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
54 #define AT91_SDRAMC_NR_11 (0 << 2) 54 #define AT91_SDRAMC_NR_11 (0 << 2)
55 #define AT91_SDRAMC_NR_12 (1 << 2) 55 #define AT91_SDRAMC_NR_12 (1 << 2)
56 #define AT91_SDRAMC_NR_13 (2 << 2) 56 #define AT91_SDRAMC_NR_13 (2 << 2)
57 #define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ 57 #define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
58 #define AT91_SDRAMC_NB_2 (0 << 4) 58 #define AT91_SDRAMC_NB_2 (0 << 4)
59 #define AT91_SDRAMC_NB_4 (1 << 4) 59 #define AT91_SDRAMC_NB_4 (1 << 4)
60 #define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ 60 #define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
61 #define AT91_SDRAMC_CAS_1 (1 << 5) 61 #define AT91_SDRAMC_CAS_1 (1 << 5)
62 #define AT91_SDRAMC_CAS_2 (2 << 5) 62 #define AT91_SDRAMC_CAS_2 (2 << 5)
63 #define AT91_SDRAMC_CAS_3 (3 << 5) 63 #define AT91_SDRAMC_CAS_3 (3 << 5)
64 #define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */ 64 #define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */
65 #define AT91_SDRAMC_DBW_32 (0 << 7) 65 #define AT91_SDRAMC_DBW_32 (0 << 7)
66 #define AT91_SDRAMC_DBW_16 (1 << 7) 66 #define AT91_SDRAMC_DBW_16 (1 << 7)
67 #define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */ 67 #define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */
68 #define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */ 68 #define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */
69 #define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */ 69 #define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */
70 #define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */ 70 #define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */
71 #define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */ 71 #define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
72 #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */ 72 #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
73 73
74 #define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */ 74 #define AT91_SDRAMC_LPR (ATMEL_BASE_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */
75 #define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */ 75 #define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
76 #define AT91_SDRAMC_LPCB_DISABLE 0 76 #define AT91_SDRAMC_LPCB_DISABLE 0
77 #define AT91_SDRAMC_LPCB_SELF_REFRESH 1 77 #define AT91_SDRAMC_LPCB_SELF_REFRESH 1
78 #define AT91_SDRAMC_LPCB_POWER_DOWN 2 78 #define AT91_SDRAMC_LPCB_POWER_DOWN 2
79 #define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3 79 #define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
80 #define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */ 80 #define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
81 #define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ 81 #define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
82 #define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */ 82 #define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */
83 #define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ 83 #define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
84 #define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12) 84 #define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12)
85 #define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) 85 #define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
86 #define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12) 86 #define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
87 87
88 #define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */ 88 #define AT91_SDRAMC_IER (ATMEL_BASE_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */
89 #define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */ 89 #define AT91_SDRAMC_IDR (ATMEL_BASE_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */
90 #define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */ 90 #define AT91_SDRAMC_IMR (ATMEL_BASE_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */
91 #define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */ 91 #define AT91_SDRAMC_ISR (ATMEL_BASE_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */
92 #define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */ 92 #define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
93 93
94 #define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */ 94 #define AT91_SDRAMC_MDR (ATMEL_BASE_SDRAMC + 0x24) /* SDRAM Memory Device Register */
95 #define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */ 95 #define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
96 #define AT91_SDRAMC_MD_SDRAM 0 96 #define AT91_SDRAMC_MD_SDRAM 0
97 #define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 97 #define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
98 98
99 99
100 #endif 100 #endif
101 101
arch/arm/include/asm/arch-at91/at91sam9_smc.h
Diff comments   View file @ fd2f565
1 /* 1 /*
2 * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9_smc.h] 2 * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9_smc.h]
3 * 3 *
4 * Copyright (C) 2007 Andrew Victor 4 * Copyright (C) 2007 Andrew Victor
5 * Copyright (C) 2007 Atmel Corporation. 5 * Copyright (C) 2007 Atmel Corporation.
6 * 6 *
7 * Static Memory Controllers (SMC) - System peripherals registers. 7 * Static Memory Controllers (SMC) - System peripherals registers.
8 * Based on AT91SAM9261 datasheet revision D. 8 * Based on AT91SAM9261 datasheet revision D.
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by 11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or 12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version. 13 * (at your option) any later version.
14 */ 14 */
15 15
16 #ifndef AT91SAM9_SMC_H 16 #ifndef AT91SAM9_SMC_H
17 #define AT91SAM9_SMC_H 17 #define AT91SAM9_SMC_H
18 18
19 #ifdef __ASSEMBLY__ 19 #ifdef __ASSEMBLY__
20 20
21 #ifndef AT91_SMC_BASE 21 #ifndef ATMEL_BASE_SMC
22 #define AT91_SMC_BASE AT91_SMC0_BASE 22 #define ATMEL_BASE_SMC ATMEL_BASE_SMC0
23 #endif 23 #endif
24 24
25 #define AT91_ASM_SMC_SETUP0 AT91_SMC_BASE 25 #define AT91_ASM_SMC_SETUP0 ATMEL_BASE_SMC
26 #define AT91_ASM_SMC_PULSE0 (AT91_SMC_BASE + 0x04) 26 #define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x04)
27 #define AT91_ASM_SMC_CYCLE0 (AT91_SMC_BASE + 0x08) 27 #define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x08)
28 #define AT91_ASM_SMC_MODE0 (AT91_SMC_BASE + 0x0C) 28 #define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x0C)
29 29
30 #else 30 #else
31 31
32 typedef struct at91_cs { 32 typedef struct at91_cs {
33 u32 setup; /* 0x00 SMC Setup Register */ 33 u32 setup; /* 0x00 SMC Setup Register */
34 u32 pulse; /* 0x04 SMC Pulse Register */ 34 u32 pulse; /* 0x04 SMC Pulse Register */
35 u32 cycle; /* 0x08 SMC Cycle Register */ 35 u32 cycle; /* 0x08 SMC Cycle Register */
36 u32 mode; /* 0x0C SMC Mode Register */ 36 u32 mode; /* 0x0C SMC Mode Register */
37 } at91_cs_t; 37 } at91_cs_t;
38 38
39 typedef struct at91_smc { 39 typedef struct at91_smc {
40 at91_cs_t cs[8]; 40 at91_cs_t cs[8];
41 } at91_smc_t; 41 } at91_smc_t;
42 42
43 #endif /* __ASSEMBLY__ */ 43 #endif /* __ASSEMBLY__ */
44 44
45 #define AT91_SMC_SETUP_NWE(x) (x & 0x3f) 45 #define AT91_SMC_SETUP_NWE(x) (x & 0x3f)
46 #define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8) 46 #define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8)
47 #define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16) 47 #define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16)
48 #define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24) 48 #define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24)
49 49
50 #define AT91_SMC_PULSE_NWE(x) (x & 0x7f) 50 #define AT91_SMC_PULSE_NWE(x) (x & 0x7f)
51 #define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x7f) << 8) 51 #define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x7f) << 8)
52 #define AT91_SMC_PULSE_NRD(x) ((x & 0x7f) << 16) 52 #define AT91_SMC_PULSE_NRD(x) ((x & 0x7f) << 16)
53 #define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x7f) << 24) 53 #define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x7f) << 24)
54 54
55 #define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff) 55 #define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff)
56 #define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16) 56 #define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16)
57 57
58 #define AT91_SMC_MODE_RM_NCS 0x00000000 58 #define AT91_SMC_MODE_RM_NCS 0x00000000
59 #define AT91_SMC_MODE_RM_NRD 0x00000001 59 #define AT91_SMC_MODE_RM_NRD 0x00000001
60 #define AT91_SMC_MODE_WM_NCS 0x00000000 60 #define AT91_SMC_MODE_WM_NCS 0x00000000
61 #define AT91_SMC_MODE_WM_NWE 0x00000002 61 #define AT91_SMC_MODE_WM_NWE 0x00000002
62 62
63 #define AT91_SMC_MODE_EXNW_DISABLE 0x00000000 63 #define AT91_SMC_MODE_EXNW_DISABLE 0x00000000
64 #define AT91_SMC_MODE_EXNW_FROZEN 0x00000020 64 #define AT91_SMC_MODE_EXNW_FROZEN 0x00000020
65 #define AT91_SMC_MODE_EXNW_READY 0x00000030 65 #define AT91_SMC_MODE_EXNW_READY 0x00000030
66 66
67 #define AT91_SMC_MODE_BAT 0x00000100 67 #define AT91_SMC_MODE_BAT 0x00000100
68 #define AT91_SMC_MODE_DBW_8 0x00000000 68 #define AT91_SMC_MODE_DBW_8 0x00000000
69 #define AT91_SMC_MODE_DBW_16 0x00001000 69 #define AT91_SMC_MODE_DBW_16 0x00001000
70 #define AT91_SMC_MODE_DBW_32 0x00002000 70 #define AT91_SMC_MODE_DBW_32 0x00002000
71 #define AT91_SMC_MODE_TDF_CYCLE(x) ((x & 0xf) << 16) 71 #define AT91_SMC_MODE_TDF_CYCLE(x) ((x & 0xf) << 16)
72 #define AT91_SMC_MODE_TDF 0x00100000 72 #define AT91_SMC_MODE_TDF 0x00100000
73 #define AT91_SMC_MODE_PMEN 0x01000000 73 #define AT91_SMC_MODE_PMEN 0x01000000
74 #define AT91_SMC_MODE_PS_4 0x00000000 74 #define AT91_SMC_MODE_PS_4 0x00000000
75 #define AT91_SMC_MODE_PS_8 0x10000000 75 #define AT91_SMC_MODE_PS_8 0x10000000
76 #define AT91_SMC_MODE_PS_16 0x20000000 76 #define AT91_SMC_MODE_PS_16 0x20000000
77 #define AT91_SMC_MODE_PS_32 0x30000000 77 #define AT91_SMC_MODE_PS_32 0x30000000
78 78
79 #ifdef CONFIG_AT91_LEGACY 79 #ifdef CONFIG_AT91_LEGACY
80 80
81 #define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ 81 #define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
82 #define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ 82 #define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
83 #define AT91_SMC_NWESETUP_(x) ((x) << 0) 83 #define AT91_SMC_NWESETUP_(x) ((x) << 0)
84 #define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ 84 #define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
85 #define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8) 85 #define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
86 #define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */ 86 #define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
87 #define AT91_SMC_NRDSETUP_(x) ((x) << 16) 87 #define AT91_SMC_NRDSETUP_(x) ((x) << 16)
88 #define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ 88 #define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
89 #define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) 89 #define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
90 90
91 #define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ 91 #define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
92 #define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ 92 #define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
93 #define AT91_SMC_NWEPULSE_(x) ((x) << 0) 93 #define AT91_SMC_NWEPULSE_(x) ((x) << 0)
94 #define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ 94 #define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
95 #define AT91_SMC_NCS_WRPULSE_(x)((x) << 8) 95 #define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
96 #define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */ 96 #define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
97 #define AT91_SMC_NRDPULSE_(x) ((x) << 16) 97 #define AT91_SMC_NRDPULSE_(x) ((x) << 16)
98 #define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ 98 #define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
99 #define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) 99 #define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
100 100
101 #define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ 101 #define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
102 #define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ 102 #define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
103 #define AT91_SMC_NWECYCLE_(x) ((x) << 0) 103 #define AT91_SMC_NWECYCLE_(x) ((x) << 0)
104 #define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ 104 #define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
105 #define AT91_SMC_NRDCYCLE_(x) ((x) << 16) 105 #define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
106 106
107 #define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ 107 #define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
108 #define AT91_SMC_READMODE (1 << 0) /* Read Mode */ 108 #define AT91_SMC_READMODE (1 << 0) /* Read Mode */
109 #define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ 109 #define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
110 #define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ 110 #define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
111 #define AT91_SMC_EXNWMODE_DISABLE (0 << 4) 111 #define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
112 #define AT91_SMC_EXNWMODE_FROZEN (2 << 4) 112 #define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
113 #define AT91_SMC_EXNWMODE_READY (3 << 4) 113 #define AT91_SMC_EXNWMODE_READY (3 << 4)
114 #define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ 114 #define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
115 #define AT91_SMC_BAT_SELECT (0 << 8) 115 #define AT91_SMC_BAT_SELECT (0 << 8)
116 #define AT91_SMC_BAT_WRITE (1 << 8) 116 #define AT91_SMC_BAT_WRITE (1 << 8)
117 #define AT91_SMC_DBW (3 << 12) /* Data Bus Width */ 117 #define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
118 #define AT91_SMC_DBW_8 (0 << 12) 118 #define AT91_SMC_DBW_8 (0 << 12)
119 #define AT91_SMC_DBW_16 (1 << 12) 119 #define AT91_SMC_DBW_16 (1 << 12)
120 #define AT91_SMC_DBW_32 (2 << 12) 120 #define AT91_SMC_DBW_32 (2 << 12)
121 #define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */ 121 #define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
122 #define AT91_SMC_TDF_(x) ((x) << 16) 122 #define AT91_SMC_TDF_(x) ((x) << 16)
123 #define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */ 123 #define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
124 #define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */ 124 #define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
125 #define AT91_SMC_PS (3 << 28) /* Page Size */ 125 #define AT91_SMC_PS (3 << 28) /* Page Size */
126 #define AT91_SMC_PS_4 (0 << 28) 126 #define AT91_SMC_PS_4 (0 << 28)
127 #define AT91_SMC_PS_8 (1 << 28) 127 #define AT91_SMC_PS_8 (1 << 28)
128 #define AT91_SMC_PS_16 (2 << 28) 128 #define AT91_SMC_PS_16 (2 << 28)
129 #define AT91_SMC_PS_32 (3 << 28) 129 #define AT91_SMC_PS_32 (3 << 28)
130 130
131 #if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */ 131 #if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */
132 #define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ 132 #define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
133 #define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ 133 #define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
134 #define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ 134 #define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
135 #define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ 135 #define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
136 #endif 136 #endif
137 137
138 #endif 138 #endif
139 #endif 139 #endif
140 140