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Commit fd2f5658093eca72467f0104659f4826a95f948c

Authored by Eric Benard
Committed by Albert ARIBAUD
1 parent d0a94620a8
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

include/asm/arch-at91: update several .h files to ATMEL_xxx name scheme 

Signed-off-by: Eric Bénard <eric@eukrea.com>

Showing 5 changed files with 28 additions and 28 deletions Side-by-side Diff

arch/arm/include/asm/arch-at91/at91_matrix.h
Diff comments   View file @ fd2f565
... ... @@ -26,18 +26,18 @@
26 26 #ifdef __ASSEMBLY__
27 27  
28 28 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
29   -#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x11C)
  29 +#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x11C)
30 30 #elif defined(CONFIG_AT91SAM9261)
31   -#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x30)
  31 +#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x30)
32 32 #elif defined(CONFIG_AT91SAM9263)
33   -#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x120)
  33 +#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x120)
34 34 #elif defined(CONFIG_AT91SAM9G45)
35   -#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x128)
  35 +#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x128)
36 36 #else
37 37 #error AT91_ASM_MATRIX_CSA0 is not definied for current CPU
38 38 #endif
39 39  
40   -#define AT91_ASM_MATRIX_MCFG AT91_MATRIX_BASE
  40 +#define AT91_ASM_MATRIX_MCFG ATMEL_BASE_MATRIX
41 41  
42 42 #else
43 43 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
arch/arm/include/asm/arch-at91/at91_rstc.h
Diff comments   View file @ fd2f565
... ... @@ -16,7 +16,7 @@
16 16 #ifndef AT91_RSTC_H
17 17 #define AT91_RSTC_H
18 18  
19   -#define AT91_ASM_RSTC_MR (AT91_RSTC_BASE + 0x08)
  19 +#define AT91_ASM_RSTC_MR (ATMEL_BASE_RSTC + 0x08)
20 20  
21 21 #ifndef __ASSEMBLY__
22 22  
arch/arm/include/asm/arch-at91/at91_wdt.h
Diff comments   View file @ fd2f565
... ... @@ -19,7 +19,7 @@
19 19  
20 20 #ifdef __ASSEMBLY__
21 21  
22   -#define AT91_ASM_WDT_MR (AT91_WDT_BASE + 0x04)
  22 +#define AT91_ASM_WDT_MR (ATMEL_BASE_WDT + 0x04)
23 23  
24 24 #else
25 25  
arch/arm/include/asm/arch-at91/at91sam9_sdramc.h
Diff comments   View file @ fd2f565
... ... @@ -19,19 +19,19 @@
19 19  
20 20 #ifdef __ASSEMBLY__
21 21  
22   -#ifndef AT91_SDRAMC_BASE
23   -#define AT91_SDRAMC_BASE AT91_SDRAMC0_BASE
  22 +#ifndef ATMEL_BASE_SDRAMC
  23 +#define ATMEL_BASE_SDRAMC AT91_SDRAMC0_BASE
24 24 #endif
25 25  
26   -#define AT91_ASM_SDRAMC_MR AT91_SDRAMC_BASE
27   -#define AT91_ASM_SDRAMC_TR (AT91_SDRAMC_BASE + 0x04)
28   -#define AT91_ASM_SDRAMC_CR (AT91_SDRAMC_BASE + 0x08)
29   -#define AT91_ASM_SDRAMC_MDR (AT91_SDRAMC_BASE + 0x24)
  26 +#define AT91_ASM_SDRAMC_MR ATMEL_BASE_SDRAMC
  27 +#define AT91_ASM_SDRAMC_TR (ATMEL_BASE_SDRAMC + 0x04)
  28 +#define AT91_ASM_SDRAMC_CR (ATMEL_BASE_SDRAMC + 0x08)
  29 +#define AT91_ASM_SDRAMC_MDR (ATMEL_BASE_SDRAMC + 0x24)
30 30  
31 31 #endif
32 32  
33 33 /* SDRAM Controller (SDRAMC) registers */
34   -#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */
  34 +#define AT91_SDRAMC_MR (ATMEL_BASE_SDRAMC + 0x00) /* SDRAM Controller Mode Register */
35 35 #define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
36 36 #define AT91_SDRAMC_MODE_NORMAL 0
37 37 #define AT91_SDRAMC_MODE_NOP 1
38 38  
... ... @@ -41,10 +41,10 @@
41 41 #define AT91_SDRAMC_MODE_EXT_LMR 5
42 42 #define AT91_SDRAMC_MODE_DEEP 6
43 43  
44   -#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */
  44 +#define AT91_SDRAMC_TR (ATMEL_BASE_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */
45 45 #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
46 46  
47   -#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */
  47 +#define AT91_SDRAMC_CR (ATMEL_BASE_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */
48 48 #define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
49 49 #define AT91_SDRAMC_NC_8 (0 << 0)
50 50 #define AT91_SDRAMC_NC_9 (1 << 0)
... ... @@ -71,7 +71,7 @@
71 71 #define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
72 72 #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
73 73  
74   -#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */
  74 +#define AT91_SDRAMC_LPR (ATMEL_BASE_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */
75 75 #define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
76 76 #define AT91_SDRAMC_LPCB_DISABLE 0
77 77 #define AT91_SDRAMC_LPCB_SELF_REFRESH 1
78 78  
... ... @@ -85,13 +85,13 @@
85 85 #define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
86 86 #define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
87 87  
88   -#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */
89   -#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */
90   -#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */
91   -#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */
  88 +#define AT91_SDRAMC_IER (ATMEL_BASE_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */
  89 +#define AT91_SDRAMC_IDR (ATMEL_BASE_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */
  90 +#define AT91_SDRAMC_IMR (ATMEL_BASE_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */
  91 +#define AT91_SDRAMC_ISR (ATMEL_BASE_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */
92 92 #define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
93 93  
94   -#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */
  94 +#define AT91_SDRAMC_MDR (ATMEL_BASE_SDRAMC + 0x24) /* SDRAM Memory Device Register */
95 95 #define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
96 96 #define AT91_SDRAMC_MD_SDRAM 0
97 97 #define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
arch/arm/include/asm/arch-at91/at91sam9_smc.h
Diff comments   View file @ fd2f565
... ... @@ -18,14 +18,14 @@
18 18  
19 19 #ifdef __ASSEMBLY__
20 20  
21   -#ifndef AT91_SMC_BASE
22   -#define AT91_SMC_BASE AT91_SMC0_BASE
  21 +#ifndef ATMEL_BASE_SMC
  22 +#define ATMEL_BASE_SMC ATMEL_BASE_SMC0
23 23 #endif
24 24  
25   -#define AT91_ASM_SMC_SETUP0 AT91_SMC_BASE
26   -#define AT91_ASM_SMC_PULSE0 (AT91_SMC_BASE + 0x04)
27   -#define AT91_ASM_SMC_CYCLE0 (AT91_SMC_BASE + 0x08)
28   -#define AT91_ASM_SMC_MODE0 (AT91_SMC_BASE + 0x0C)
  25 +#define AT91_ASM_SMC_SETUP0 ATMEL_BASE_SMC
  26 +#define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x04)
  27 +#define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x08)
  28 +#define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x0C)
29 29  
30 30 #else
31 31